TW202032720A - 用於3d nand應用中之插塞填充沉積之設備及方法 - Google Patents

用於3d nand應用中之插塞填充沉積之設備及方法 Download PDF

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TW202032720A
TW202032720A TW109104302A TW109104302A TW202032720A TW 202032720 A TW202032720 A TW 202032720A TW 109104302 A TW109104302 A TW 109104302A TW 109104302 A TW109104302 A TW 109104302A TW 202032720 A TW202032720 A TW 202032720A
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福憲 金
大衛 柯亨
亞歷山卓 迪摩斯
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Abstract

揭示一種用於形成一3D NAND裝置之設備及方法。該形成3D NAND裝置之方法可包括形成一插塞填充及一空隙。藉由該設備及方法而得到的優點可包括較低成本、較高產出量、極少量或沒有裝置污染、蝕刻步驟期間極少量或沒有損害、及結構完整性以確保形成氧化物－氮化物雙層之一適當堆疊。

Description

用於3D　NAND應用中之插塞填充沉積之設備及方法
相關申請案之交叉參考
本申請案係2019年2月20日提出申請之發明名稱為「APPARATUS AND METHODS FOR PLUG FILL DEPOSITION IN 3-D NAND APPLICATIONs」之美國臨時專利申請案序號第62/807,989號之非臨時案，並主張該案之優先權及權益，特此將該案以引用方式併入本文中。
本揭露大致上係關於一種用於形成反及(NAND)裝置之設備及方法。更具體地，本揭露係關於用於部分以氧化物－氮化物層堆疊製成之3D NAND裝置之插塞填充的沉積。用於形成NAND裝置之設備及方法可包括使用犧牲材料及製造方案以便以較低成本及較高產出量達成裝置結構之適當形成。
NAND裝置係邏輯閘，例如，可用於諸如快閃記憶體之應用中。製造NAND裝置可包括在設置於基材上之層中形成通道孔。通道孔接著可填以犧牲材料，之後再移除。製造NAND裝置100之製程的一實例係繪示於圖1A至圖1D中。NAND裝置100可包含基材110、氮化物層120、及氧化物層130。氮化物層120及氧化物層130之沉積係依需要重複以形成堆疊。
如圖1A所示，NAND裝置100包含第一堆疊140，其包含交替的兩個氮化物層120及兩個氧化物層130。NAND裝置100亦包含第二堆疊150，其包含交替的兩個氮化物層120及兩個氧化物層130。第一堆疊140及第二堆疊150可包含額外交替的氮化物層120及氧化物層130。
氮化物層120及氧化物層130經受蝕刻製程以形成通道孔，如圖1B所示。蝕刻製程可涉及使用氟基（諸如NF3、CHF、SF6、CF4、及前述之混合物）之氧化物或氮化物乾蝕刻化學。在一些情況下，乾蝕刻化學可涉及氧或臭氧。圖1C繪示在經受用以形成襯墊之第一製程之後、在用以形成所謂的通道孔或記憶孔之乾蝕刻製程、用以形成插塞填充之第二製程、及第三拋光製程之後的NAND裝置100。NAND裝置100接著包含襯墊160及插塞填充170。例如，襯墊160可包含氧化矽(SiOx )。
插塞填充170可包含多晶矽、鎢(W)、氮化鈦(TiN)、氧化鋁(AlOx )、金屬碳化物、碳化鎢(WC)、碳化鎢硼(WBC)、金屬氮化物、或上列任何者之一組合。取決於用於插塞填充170之材料，由於與整合相關，可存在成本增加及導因於故障之更大的不穩定性風險。插塞填充170可包含犧牲材料，其用以保護堆疊140之底部處的通道孔或記憶孔。蓋（未繪示）亦能夠可選地設置在插塞填充170的頂部上。例如，蓋可包含金屬氮化物（諸如氮化鈦、氮化鎢、或氮化鋁）。
第三拋光製程可係化學機械拋光(CMP)。在第三拋光製程之後，可在堆疊150、襯墊160、及插塞填充170的頂部上添加額外的氧化物－氮化物層堆疊。
然而，在通道孔經填以襯墊160及插塞填充170之後的一時間點，襯墊160及插塞填充170必須作為犧牲材料的角色而經移除。插塞填充170可使用下列之至少一者以濕蝕刻製程移除：氫氧化銨(NH4 OH)、過氧化氫(H2 O2 )、水(H2 O)、HNO3 、TDMH、或前述之一組合。插塞填充170可例如使用鹵化物化學（諸如氫氟酸(HF)、鹽酸(HCl)、或氫溴酸(HBr)）藉由乾蝕刻來移除。隨後可係使用HF混合物之濕清潔製程，以移除襯墊(160)。
圖1D繪示發生移除之後的NAND裝置100。然而，化學反應可留下殘留物180及/或藉由用於移除襯墊160及/或插塞填充170之化學反應而導致氮化物層120或氧化物層130之任一者的損害190。殘留物180及損害190可使NAND裝置100無法使用。此外，移除襯墊160及插塞填充170可以緩慢的蝕刻率達成，其意指移除襯墊160及插塞填充170的時間可係非所欲的長。例如，此可係插塞填充170由再結晶矽或處於(111)結晶定向之矽所形成的結果。當形成額外堆疊時，再結晶矽可由於退火製程而產生。
此外，可引發的額外問題係額外堆疊經設置在第一堆疊140及第二堆疊150之頂部上時之堆疊失準。失準可係製造期間施加在不同堆疊、襯墊160、及/或插塞填充170上之應力的結果。
結果，所欲的係實現一種用於以低成本及高產出量形成NAND裝置之設備及方法，其在通道孔中具有經最小化的殘留物及損害或無殘留物及損害以及良好的結構完整性。
提供本發明內容來以簡化形式介紹精選的一系列概念。這些概念將在下文之揭露的實例實施例之詳細描述中進一步詳述。此發明內容並非意欲鑑別所主張之主題的關鍵特徵或基本特徵，亦非意欲用以限制所主張之主題的範疇。
根據本發明之至少一實施例，揭示一種方法，該方法包含在一基材上形成一3D NAND裝置之一方法。在各種實施例中，該方法可包含：在一半導體基材上沉積一雙層結構，其中該雙層結構包含一氧化物層及一氮化物層之交替層；以一第一化學品在該雙層結構中蝕刻一通道孔；在該通道孔內於該雙層結構之一頂部上及/或於該雙層結構之一側邊上沉積一襯墊；在該通道孔中沉積一插塞填充，該插塞填充包含一空隙及下列之至少一者：矽鍺插塞或一漸變鍺插塞；拋光該插塞填充；以一第二化學品蝕刻該插塞填充；及/或移除該襯墊；其中該等上述步驟中之任何者係經重複以形成該3D NAND裝置之一所欲高度。
儘管在下文中揭示某些實施例及實例，但所屬技術領域中具有通常知識者應理解，本發明延伸超出本發明所具體揭示之實施例及/或用途以及其明顯修改及等同物。因此，希望所揭示之本發明之範疇不應受下文所述的特定揭示具體例之限制。
本文呈現之圖示並非意指任何特定材料、結構、或裝置之實際視圖，而僅係用以描述本揭露之實施例的理想化表示。
三維(3D)反及(NAND)裝置可用於記憶體應用中。3D NAND裝置可涉及經設置在彼此之上的雙層之堆疊。例如，雙層可包含氧化物及氮化物。當在其他堆疊上設置具有多個雙層的堆疊時，層及不同特徵上的對準及應力可變得至關重要。
圖2A繪示根據本發明之至少一實施例之3D NAND裝置200。裝置200包含基材210、氮化物層220、及氧化物層230。基材210可包含矽、氧化矽、及/或金屬氧化物。氮化物層220可包含下列之至少一者：氮化矽、氮化鍺、氮化矽鍺(SiGeN)、氮氧化矽(SiON)、氮氧化鍺(GeON)、或前述之組合。氧化物層230可包含下列之至少一者：氧化矽、氧化鍺、氧化矽鍺(SiGeOx)、氮氧化鍺(GeON)、氮氧化矽(SiON)、或前述之組合。
裝置200接著可經歷製程，以藉由濕蝕刻或乾蝕刻製程來形成通道孔或記憶孔，以得出圖2B所示之裝置200。乾蝕刻製程可利用例如使用氟基（諸如NF3、CHF、SF6、CF4、及前述之混合物）之鹵化物化學。例如，乾蝕刻製程可涉及遠端電漿系統。在一些情況下，乾蝕刻化學可涉及氧或臭氧。
其後，可如圖2C所示將襯墊240添加至裝置200。襯墊240可包含下列之至少一者：氧化鍺、鍺(Ge)、矽鍺(SiGe)、氮化鍺(GeN)、或純矽(Si)。襯墊240可覆蓋氧化物層230/氮化物層220雙層堆疊之頂部及/或側邊。襯墊240亦可延伸以覆蓋基材210之暴露部分。例如，襯墊240可經由原子層沉積(ALD)製程、化學氣相沉積(CVD)製程、或磊晶製程來沉積。
圖2D繪示發生3D插塞填充之後的結果。裝置200包含插塞填充250及空隙260。插塞填充250可包含下列之至少一者：矽鍺(SiGe)或漸變鍺。SiGe插塞填充250中的鍺濃度範圍可介於1%與100%之間。例如，可調變鍺含量以用於得到3D NAND之後續製程步驟中所需的所欲材料性質（諸如，蝕刻製程中的移除率及熱穩定性）。
取決於用於3D插塞填充的製程，插塞填充250的形狀可有所不同，空隙260的尺寸也是如此。由於形成空隙260，插塞填充250係經完全填充或未完全填充，導致孔內側之所謂的空隙或夾止。空隙或夾止可導致稍後製程中移除插塞填充250期間的較快速移除，從而減少蝕刻化學帶來的裝置損害以及製造時間並增加產出量。在本發明的某些實施例中，空隙或夾止可不存在。
插塞填充250及空隙260可透過原位製程形成，該原位製程包含沉積步驟、涉及鹵化物化學之回蝕步驟、及夾止步驟。沉積步驟可藉由熱反應、電漿反應、電漿增強反應、或高密度電漿(HDP)化學氣相沉積(CVD)製程而發生。沉積步驟可包括矽前驅物之流動，例如，該矽前驅物係諸如矽烷、二矽烷、三矽烷、氯矽烷、二氯矽烷、三氯矽烷、四氯矽烷、新五矽烷、甲基矽烷、二甲基矽烷、三甲基矽烷、四甲基矽烷、或前述之一組合。沉積步驟亦可包括鍺前驅物之流動，例如，鍺前驅物係諸如鍺烷、二鍺烷、二氯鍺烷、三氯鍺烷、四氯鍺烷、鍺醇鹽、或前述之一組合。例如，沉積步驟亦可包含使含有矽及鍺兩者之前驅物（諸如矽烷基鍺烷前驅物）流動。沉積步驟可涉及鍺之原位摻雜。原位摻雜可以原子（諸如Ga、B、P、As、或Al）達成。
原位製程可包含夾止步驟，其中夾止步驟包含沉積矽、鍺、或前述之一組合以便形成空隙260。
對熱沉積步驟而言，壓力範圍可介於10 Torr與800 Torr之間，而溫度範圍可介於50o C與800o C之間。對電漿增強反應或HDP CVD沉積步驟而言，壓力範圍可介於10 mTorr與100 Torr之間，而溫度範圍可介於10o C與700o C之間。
例如，回蝕步驟中所涉及的鹵化物化學可包含氫氟酸(HF)、鹽酸(HCl)、氫氟酸(HF)、氫溴酸(HBr)、或前述之一組合。例如，乾蝕刻製程可涉及遠端電漿系統。
鍺、矽、或SiGe插塞填充及夾止步驟可包含以減少的沉積率沉積SiGe合金以準確地控制厚度。此步驟亦可在SiGe合金中產生空隙。鍺或矽或SiGe插塞填充及夾止步驟可使用Ma等人於2018年8月6日提出申請之發明名稱為「MULTI-PORT GAS INJECTION SYSTEM AND REACTOR SYSTEM INCLUDING SAME」之美國專利申請案第16/055,532號中所揭示的設備來達成，該申請案特此以引用方式併入本文中。鍺、矽、SiGe插塞填充及夾止步驟可替代地使用Sreeram等人於2018年6月4日提出申請之發明名稱為「GAS DISTRIBUTION SYSTEM AND REACTOR SYSTEM INCLUDING SAME」之美國專利申請案第15/997,445號中所揭示的設備來達成，該申請案特此以引用方式併入本文中。這些專利申請案中所述之設備可允許調整所產生之空隙尺寸。
插塞填充250的過量材料可經由CMP製程移除，如圖2E所示。餘留者形成第一堆疊270。一旦存在水平表面，額外的堆疊可形成在襯墊240及插塞填充250上。
第二堆疊280係顯示於圖2F中。如第一堆疊270，第二堆疊280包含交替配置的氮化物層220及氧化物層230。氮化物層220可包含下列之至少一者：氮化矽、氮化鍺、氮化矽、氮化鍺、氮化矽鍺(SiGeN)、氮氧化矽(SiON)、氮氧化鍺(GeON)、或前述之組合。氧化物層230可包含下列之至少一者：氧化矽、氧化鍺、氧化矽鍺(SiGeOx)、氮氧化鍺(GeON)、氮氧化矽(SiON)、或前述之組合。
接著經由蝕刻製程在第二堆疊280中形成通道孔。蝕刻製程可係乾蝕刻或濕蝕刻製程。例如，蝕刻製程可使用鹵化物化學（諸如，氫氟酸(HF)、鹽酸(HCl)、氫氟酸(HF)、氫溴酸(HBr)、或前述之一組合）。在蝕刻製程之後，襯墊240及插塞填充250維持餘留，如圖2G所示。
接著可經由下列之至少一者的流動在濕蝕刻製程中移除插塞填充250：氫氧化銨、過氧化氫、水、甲狀腺素5-脫碘酶、硝酸(HNO3)、(三甲基矽烷基)二甲基聯胺(TDMH)、或上述之任何者之一組合。該流動以快於移除其他矽插塞的速率剝去插塞填充250。插塞填充250之蝕刻率範圍可介於0.1與10000埃/分鐘之間、介於1與1000埃/分鐘之間、或介於10與100埃/分鐘之間。
在移除插塞填充250之後，圖2H繪示仍留下襯墊240。接著可經由下列之至少一者的流動移除襯墊240：氫氧化銨、過氧化氫、水、甲狀腺素5-脫碘酶、硝酸(HNO3)、(三甲基矽烷基)二甲基聯胺(TDMH)、或上述之任何者之一組合。仍留下者係裝置200，如圖2I所示。此時，可完成裝置200的製造，或者可重複步驟以便在裝置200的頂部上形成額外堆疊。
圖3繪示根據本發明之至少一實施例之用於製造3D NAND裝置之方法300。方法300包含：乾蝕刻步驟310；襯墊沉積步驟320；插塞填充步驟330；拋光步驟340；堆疊沉積步驟350；孔蝕刻步驟360；及可選的剝除步驟370。若孔蝕刻步驟360亦移除了襯墊，則可不需要剝除步驟370。
例如，用於形成3D NAND裝置之方法可發生在ALD反應室、化學氣相沉積(CVD)室、磊晶反應室、批式反應室、微型批式反應室、或單晶圓反應室中。適當的反應室可允許這些製程的全部或大部分作為原位製程而發生。
圖4繪示根據本發明之至少一實施例製成之3D NAND裝置400。3D NAND裝置400包含基材410、氧化物－氮化物層堆疊區段420、源線430、位元線電極區段440。氧化物－氮化物層堆疊區段420亦可包含複數個通道孔。
所顯示及描述之特定實施方案係對本發明及其最佳模式之說明，且並非意欲以任何不同方式限制態樣及實施方案之範疇。實際上，為簡潔起見，系統之習知製造、連接、製備、及其他功能性態樣可能未詳細描述。此外，各種圖式中所示之連接線係意欲表示各種元件之間的例示性功能關係及/或實體耦接。許多替代或額外的功能關係或實體連接可存在於實際系統中及/或在一些實施例中可不存在。
應理解，本文所述之設置及/或方法本質上係例示性的，且這些特定實施例或實例不視為具有限制意義，原因在於可能存在諸多變化。本文所述之特定常式或方法可表示任何數目的處理策略之一或多者。因此，所說明之各種動作可於所說明之順序執行，以其他順序執行，或在一些情況下被省略。
本揭露之主題包括本文中所揭示之各種製程、系統、及設置、以及其他特徵、功能、動作、及/或性質的所有新式及非顯而易見的組合及子組合以及前述之任何及所有等同物。
100,200,400:NAND裝置 110,210,410:基材 120,220:氮化物層 130,230:氧化物層 140,270:第一堆疊 150,280:第二堆疊 160,240:襯墊 170,250:插塞填充 180:殘留物 260:空隙 300:方法 310:乾蝕刻步驟 320:襯墊沉積步驟 330:插塞填充步驟 340:拋光步驟 350:堆疊沉積步驟 360:孔蝕刻步驟 370:剝除步驟 420:氧化物－氮化物層堆疊區段 430:源線 440:位元線電極區段
本文所揭示的本發明之這些及其他特徵、態樣、及優點在下文參照某些實施例之圖式描述，該等實施例係意欲說明而非限制本發明。 圖1A至圖1D係經由先前技術之製程所形成之NAND裝置的截面圖。 圖2A至圖2I係根據本發明之至少一實施例形成之NAND裝置的截面圖。 圖3係根據本發明之至少一實施例之製程流程圖。 圖4係根據本發明之至少一實施例形成之NAND裝置的截面圖。 應理解，圖式中之元件係為了簡單及清楚起見而繪示且未必按比例繪製。例如，圖式中的一些元件之尺寸可相對於其他元件誇大，以幫助提昇對本揭露之說明實施例的理解。
300:方法
310:乾蝕刻步驟
320:襯墊沉積步驟
330:插塞填充步驟
340:拋光步驟
350:堆疊沉積步驟
360:孔蝕刻步驟
370:剝除步驟

Claims (12)

  1. 一種在一基材上形成一3D NAND裝置之方法，該方法包含： 在一半導體基材上沉積一雙層結構，其中該雙層結構包含一氧化物層及一氮化物層之交替層； 以一第一化學品在該雙層結構中蝕刻一通道孔； 在該通道孔內的該雙層結構之一頂部上與該雙層結構之一側邊上沉積一襯墊； 在該通道孔中沉積一插塞填充，且該插塞填充包含下列之至少一者：矽鍺插塞或一漸變鍺插塞； 拋光該插塞填充； 以一第二化學品蝕刻該插塞填充；及 移除該襯墊； 其中該等上述步驟之任何一者係經重複以形成該3D NAND裝置之一所欲高度。
  2. 如請求項1之方法，其中該襯墊包含下列之至少一者：氧化鍺；鍺(Ge)；矽鍺(SiGe)；氮化鍺(GeN)；或純矽(Si)。
  3. 如請求項1之方法，其中該插塞填充包含矽鍺(SiGe)，且其中該插塞填充中之一鍺含量範圍係從1%至100%。
  4. 如請求項1之方法，其中該在該通道孔中以一插塞填充填充之步驟包含： 在該通道孔中沉積一插塞層； 回蝕該插塞層之一部分；及 以下列之至少一者夾擠該插塞層之該頂部：鍺；矽；或矽鍺合金； 其中該插塞層包含矽鍺或漸變鍺；且 其中該夾擠該頂部在該插塞層中產生一空隙，且該空隙的尺寸係可控的。
  5. 如請求項1之方法，其中該第一化學品包含下列之至少一者：氫氟酸(HF)、鹽酸(HCl)、氫氟酸(HF)、氫溴酸(HBr)、或前述之一組合。
  6. 如請求項1之方法，其中該第二化學品包含下列之至少一者：鹽酸(HCl)；氫氟酸(HF)；氫溴酸(HBr)；氫氧化銨；過氧化氫；水；甲狀腺素5-脫碘酶；硝酸(HNO3 )；(三甲基矽烷基)二甲基聯胺(TDMH)；或上述之任何一者之一組合。
  7. 如請求項1之方法，其中該拋光該插塞填充之步驟包含化學機械拋光(CMP)。
  8. 如請求項1之方法，其中該在該通道孔中沉積該插塞填充之步驟進一步包含以一摻雜劑原位摻雜，且該摻雜劑包含下列之至少一者：鍺(Ge)；鎵(Ga)；硼(B)；磷(P)；砷(As)；或鋁(Al)。
  9. 如請求項4之方法，其中該在該通道孔中沉積該插塞層之步驟包含一矽烷前驅物之流動，且該矽烷前驅物包含下列之至少一者：矽烷；二矽烷；三矽烷；氯矽烷；二氯矽烷；三氯矽烷；四氯矽烷；新五矽烷；甲基矽烷；二甲基矽烷；三甲基矽烷；四甲基矽烷；或前述之一組合。
  10. 如請求項4之方法，其中該在該通道孔中沉積該插塞層之步驟包含一鍺前驅物之流動，該鍺前驅物包含下列之至少一者：鍺烷；二鍺烷；二氯鍺烷；三氯鍺烷；四氯鍺烷；鍺醇鹽；或前述之一組合。
  11. 一種用於形成一3D NAND裝置之設備，其中該設備係設置以執行如請求項1之方法。
  12. 如請求項11之設備，其中該設備包含下列之至少一者：一垂直爐系統；一批式反應器系統；或一單晶圓反應器系統。
TW109104302A 2019-02-20 2020-02-12 用於3d nand應用中之插塞填充沉積之設備及方法 TWI838458B (zh)

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