WO2023070847A1 - 一种半导体器件的制造方法及半导体器件 - Google Patents

一种半导体器件的制造方法及半导体器件 Download PDF

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Publication number
WO2023070847A1
WO2023070847A1 PCT/CN2021/136489 CN2021136489W WO2023070847A1 WO 2023070847 A1 WO2023070847 A1 WO 2023070847A1 CN 2021136489 W CN2021136489 W CN 2021136489W WO 2023070847 A1 WO2023070847 A1 WO 2023070847A1
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polysilicon layer
trench
layer
sublayer
annealing process
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PCT/CN2021/136489
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English (en)
French (fr)
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潘凡
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长鑫存储技术有限公司
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Priority to US17/866,688 priority Critical patent/US20230134285A1/en
Publication of WO2023070847A1 publication Critical patent/WO2023070847A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76882—Reflowing or applying of pressure to better fill the contact hole
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76883—Post-treatment or after-treatment of the conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H01L23/5283—Cross-sectional geometry
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53271—Conductive materials containing semiconductor material, e.g. polysilicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices

Definitions

  • the present disclosure relates to the field of semiconductor manufacturing, and in particular, to a method for manufacturing a semiconductor device and the semiconductor device.
  • a semiconductor device such as a dynamic random access memory (DRAM) includes many conductive lines. When the conductive lines are formed, it is usually necessary to fill the trenches with a polysilicon layer.
  • DRAM dynamic random access memory
  • An embodiment of the present disclosure provides a method for manufacturing a semiconductor device.
  • the method includes: providing a substrate, the substrate having at least one groove; forming a first polysilicon layer in the groove, and the first polysilicon layer A polysilicon layer covers the sidewall and bottom of the trench, and does not completely fill the trench; an annealing process is performed on the first polysilicon layer; after the annealing process is performed, in the trench A second polysilicon layer is formed at a region of the trench not filled by the first polysilicon layer.
  • the ratio of the thickness of the first polysilicon layer to the depth of the trench is between 1:5 and 1:4.
  • the region of the trench not filled by the first polysilicon layer forms a first opening, and the first opening has an upper narrow Lower wide cross-sectional shape.
  • the region of the trench not filled by the first polysilicon layer forms a second opening, and the second opening has an upper width of Lower narrow cross-sectional shape.
  • the depth of the second opening is smaller than the depth of the first opening.
  • the temperature range of the annealing process is between 500° C. and 700° C.
  • the pressure range of the annealing process is between 10 Torr and 100 Torr
  • the time range of the annealing process is between 1 h and 2 h.
  • the following steps are completed in the same manufacturing process: the step of forming the first polysilicon layer, the step of performing an annealing process and the step of forming the second polysilicon layer.
  • the device for completing the same process includes a furnace tube.
  • the first polysilicon layer and/or the second polysilicon layer includes doped polysilicon.
  • the doped polysilicon includes at least one of boron-doped polysilicon, phosphorus-doped polysilicon or arsenic-doped polysilicon.
  • the method before forming the first polysilicon layer in the trench, the method further includes: depositing an insulating layer on the sidewall of the trench.
  • the first polysilicon layer includes a first sublayer and a second sublayer; forming the first polysilicon layer in the trench includes:
  • the second sublayer is formed on the first sublayer.
  • the deposition temperature of the first polysilicon layer and/or the second polysilicon layer is between 350° C. and 700° C.
  • the deposition pressure is between 0.2 Torr and 4 Torr.
  • the method further includes: performing an annealing process on the second polysilicon layer.
  • An embodiment of the present disclosure also provides a semiconductor device, and the semiconductor device includes:
  • the second polysilicon layer is located in the second opening.
  • the substrate includes a base material and a plurality of discrete device layers formed on the base material, and the grooves are formed between adjacent device layers.
  • the first polysilicon layer includes a first sublayer and a second sublayer located on the first sublayer, and the first sublayer is a seed layer of the second sublayer.
  • the semiconductor device further includes: an insulating layer, the insulating layer is located between the first polysilicon layer and the sidewall of the trench.
  • the method for manufacturing a semiconductor device and the semiconductor device provided by the embodiments of the present disclosure, wherein the method includes: providing a substrate having at least one groove; forming a first polysilicon layer in the groove , the first polysilicon layer covers the sidewall and bottom of the trench, and does not completely fill the trench; an annealing process is performed on the first polysilicon layer; after performing the annealing process, A second polysilicon layer is formed at regions of the trench not filled by the first polysilicon layer. After the first polysilicon layer is formed in the trench, the annealing process can significantly reduce the lattice defects of the first polysilicon layer, planarize the first polysilicon layer, and improve the hardness of the second polysilicon layer. filling capacity. Therefore, the embodiments of the present disclosure can effectively reduce or even eliminate the voids in the first polysilicon layer and the second polysilicon layer finally filled in the trenches, and improve the electrical performance of the semiconductor device.
  • FIG. 1 is a schematic structural view of an exemplary semiconductor device
  • FIG. 2 is a flowchart of a method for manufacturing a semiconductor device provided by an embodiment of the present disclosure
  • FIG. 3 to FIG. 8 are process flow charts of the manufacturing method of the semiconductor device provided by the embodiments of the present disclosure.
  • FIG. 1 is a schematic structural view of an exemplary semiconductor device. As shown in FIG. 1, the semiconductor device includes: a substrate 10; a plurality of trenches TH1 are provided in the substrate 10, and the plurality of trenches TH1 are filled with polysilicon layer 12 .
  • the polysilicon layer 12 is formed in the trench TH1 by a conventional deposition method. It can be seen that there are pores 13 in the polysilicon layer 12. The existence of the pores 13 will increase the resistance of the polysilicon layer and affect the subsequent formation. The electrical properties of the conductive wire.
  • An embodiment of the present disclosure provides a method for manufacturing a semiconductor device. As shown in FIG. 2, the method includes the following steps:
  • Step 210 providing a substrate having at least one groove
  • Step 220 forming a first polysilicon layer in the trench, the first polysilicon layer covers the sidewall and bottom of the trench, and does not completely fill the trench;
  • Step 230 performing an annealing process on the first polysilicon layer
  • Step 240 After performing the annealing process, forming a second polysilicon layer at a region of the trench not filled by the first polysilicon layer.
  • an annealing process is performed, which can significantly reduce the lattice defects of the first polysilicon layer, planarize the first polysilicon layer, and improve the second polysilicon layer.
  • the filling capacity of the crystalline silicon layer Therefore, the embodiments of the present disclosure can effectively reduce or even eliminate the voids in the first polysilicon layer and the second polysilicon layer finally filled in the trenches, and improve the electrical performance of the semiconductor device.
  • FIG. 3 to FIG. 8 are process flow charts of the manufacturing method of the semiconductor device provided by the embodiments of the present disclosure.
  • step 210 is performed to provide a substrate 20 having at least one trench TH2 .
  • the trench TH2 can be formed in the substrate 20 by a dry etching process or a wet etching process.
  • the substrate 20 includes a base material 201 and a plurality of discrete device layers 202 formed on the base material 201, and the trench TH2 is formed on adjacent device layers 202 between.
  • the substrate 201 may be a semiconductor material, such as silicon.
  • the device layer 202 can be formed of a single layer of material or a multi-layer material; the device layer 202 can include a conductive layer or an insulating layer; the device layer 202 can be retained in the final semiconductor device, or can be It is removed during the fabrication of semiconductor devices.
  • the embodiment of the present disclosure does not limit the material, number of layers, and application of the device layer 202 .
  • the method before forming the first polysilicon layer 21 (see FIG. 6 ) in the trench TH2, the method further includes: depositing an insulating layer on the sidewall of the trench TH2 Layer 23.
  • the insulating layer 23 is used to isolate the device layer 202 from the first polysilicon layer 21 .
  • the material of the insulating layer 23 may include but not limited to oxide, nitride, and oxynitride, such as silicon oxide, silicon nitride, silicon oxynitride, and the like.
  • step 220 is performed to form a first polysilicon layer 21 in the trench TH2, and the first polysilicon layer 21 covers the sidewall and the trench TH2. bottom, and does not completely fill the trench TH2.
  • the first polysilicon layer 21 may include a first sub-layer 211 and a second sub-layer 212 . Forming a first polysilicon layer 21 in the trench TH2 includes:
  • the first sublayer 211 covers the sidewall and bottom of the trench TH2, as shown in FIG. 5 ;
  • the second sub-layer 212 is formed above the first sub-layer 211 , as shown in FIG. 6 .
  • the first sub-layer 211 and the second sub-layer 212 are made of the same material, both being polysilicon layers.
  • the first sub-layer 211 is a seed layer, and the first sub-layer 211 forms many "nuclear centers" on the sidewall and bottom of the trench TH2, and the "nuclear centers" can avoid subsequent deposition
  • the abnormal growth of crystal grains in the second sub-layer 212 reduces the lattice mismatch between the second sub-layer 212 and the trench TH2, and improves the uniformity and growth quality of the second sub-layer 212.
  • the first polysilicon layer 21 may be a doped polysilicon layer, for example, at least one of boron-doped polysilicon, phosphorus-doped polysilicon or arsenic-doped polysilicon.
  • the formation of the first polysilicon layer 21 can be formed using one or more thin film deposition processes; specifically, the thin film deposition processes include but are not limited to chemical vapor deposition (CVD) process, plasma enhanced chemical vapor deposition ( PECVD) process, atomic layer deposition (ALD) process or a combination thereof.
  • CVD chemical vapor deposition
  • PECVD plasma enhanced chemical vapor deposition
  • ALD atomic layer deposition
  • the first polysilicon layer 21 is formed by a low pressure chemical vapor deposition process (LPCVD). Specifically, the deposition temperature of the first polysilicon layer 21 is between 350° C. and 700° C., and the deposition pressure is between 0.2 Torr and 4 Torr.
  • the gas used to form the first polysilicon layer 21 may include, but not limited to, silane (SiH 4 ), disilane (Si 2 H 6 ), dichlorosilane (SiH 2 Cl 2 ), and the like. In the actual process, two or more gases can be mixed or used alternately among silane (SiH 4 ), disilane (Si 2 H 6 ), and dichlorosilane (SiH 2 Cl 2 ).
  • the first polysilicon layer 21 is a doped polysilicon layer
  • the ratio of the thickness of the first polysilicon layer 21 to the depth of the trench TH2 is between 1:5 and 1:4. If the first polysilicon layer 21 is too thick or too thin, it will adversely affect the second polysilicon layer 22 grown subsequently.
  • the area of the trench TH2 not filled by the first polysilicon layer 21 forms a first opening H1
  • the first polysilicon layer 21 forms a first opening H1.
  • the depth of an opening H1 is h1
  • the first opening H1 has a cross-sectional shape with a narrow top and a wide bottom. It can be understood that the first opening H1 having a narrow top and a wide bottom is not conducive to subsequent deposition of the second polysilicon layer 22 (see FIG. 8 ).
  • step 230 is performed to perform an annealing process on the first polysilicon layer 21 .
  • the annealing process can discharge the semi-reactants or impurities in the first polysilicon layer 21, significantly reduce the lattice defects of the first polysilicon layer 21, and at the same time make the first polysilicon layer 21 more Flatness is beneficial for subsequent deposition of the second polysilicon layer 22 (see FIG. 8 ).
  • the half-reactants or impurities include, but are not limited to, hydrogen, hydrogen chloride, and the like.
  • the region of the trench TH2 not filled by the first polysilicon layer 21 forms a second opening H2, and the second opening H2 has a depth h2, so
  • the second opening H2 has a cross-sectional shape that is wide at the top and narrow at the bottom. It can be seen from FIG. 6 that the depth h2 of the second opening H2 is smaller than the depth h1 of the first opening H1 , that is, h2 ⁇ h1.
  • the depth of the opening above the first polysilicon layer 21 becomes shallower, and the cross-sectional shape of the opening changes from narrow at the top and wide at the bottom to wide at the top and narrow at the bottom, which is more conducive to the subsequent second polysilicon layer 21. Filling of layer 22.
  • the annealing process is performed in an annealing furnace; specifically, the annealing furnace may be a furnace tube.
  • the temperature range of the annealing process is between 500° C. and 700° C.
  • the pressure range is between 10 Torr and 100 Torr
  • the time range is between 1 h and 2 h.
  • nitrogen gas is introduced into the annealing furnace.
  • the nitrogen gas is used to stabilize the pressure in the process chamber so that the annealing process can be performed within a set pressure range.
  • step 240 after performing the annealing process, form a second polysilicon layer 22 at a region of the trench TH2 not filled by the first polysilicon layer 21 . That is, the second polysilicon layer 22 is formed in the second opening H2.
  • the trench TH2 is filled with the first polysilicon layer 21 and the second polysilicon layer 22, and the first polysilicon layer 21 and the second polysilicon layer 22
  • the porosity is much smaller than that of the polysilicon layer 12 in the related art.
  • the second polysilicon layer 22 may be a doped polysilicon layer, for example, at least one of boron-doped polysilicon, phosphorus-doped polysilicon or arsenic-doped polysilicon.
  • the doping elements in the second polysilicon layer 22 may be the same as or different from the doping elements in the first polysilicon layer 21 .
  • the formation of the second polysilicon layer 22 can be formed using one or more thin film deposition processes; specifically, the thin film deposition processes include but are not limited to chemical vapor deposition (CVD) process, plasma enhanced chemical vapor deposition ( PECVD) process, atomic layer deposition (ALD) process or a combination thereof.
  • CVD chemical vapor deposition
  • PECVD plasma enhanced chemical vapor deposition
  • ALD atomic layer deposition
  • the second polysilicon layer 22 is formed by a low pressure chemical vapor deposition process (LPCVD). Specifically, the deposition temperature of the second polysilicon layer 22 is between 350° C. and 700° C., and the deposition pressure is between 0.2 Torr and 4 Torr.
  • the gas used to form the second polysilicon layer 22 may include, but not limited to, silane (SiH 4 ), disilane (Si 2 H 6 ), dichlorosilane (SiH 2 Cl 2 ), and the like. In the actual process, two or more gases can be mixed or used alternately among silane (SiH 4 ), disilane (Si 2 H 6 ), and dichlorosilane (SiH 2 Cl 2 ).
  • the second polysilicon layer 22 is a doped polysilicon layer
  • the step of forming the first polysilicon layer 21 , the step of performing an annealing process, and the step of forming the second polysilicon layer 22 are completed in the same process.
  • the surface of the first polysilicon layer 21 can be prevented from being oxidized to form an oxide layer during the conversion of different processes, and the oxide layer will increase the thickness of the first polysilicon layer 21 and the second polysilicon layer. 22 resistors.
  • the device for completing the same process may include but not limited to a furnace tube and the like. That is, the following steps may be successively performed in the furnace tube: forming the first polysilicon layer, performing an annealing process, and forming the second polysilicon layer. During this process, the substrate on which the first polysilicon layer is formed does not need to be removed from the furnace tube, and the first polysilicon layer will not be oxidized.
  • the method further includes: performing an annealing process on the second polysilicon layer.
  • the main purpose of the annealing process is to repair defects in the second polysilicon layer, further reduce the porosity in the second polysilicon layer, and improve the film-forming quality of the second polysilicon layer.
  • the process conditions for the annealing of the second polysilicon layer may be the same as or different from the process conditions for the annealing of the first polysilicon layer, which will not be repeated here.
  • the first polysilicon layer and the second polysilicon layer in the embodiments of the present disclosure can form conductive lines, such as bit lines and word lines in DRAM devices; but they are not limited thereto, and can also form other conductive lines. Structures, such as conductive plugs, such as bit line plugs in DRAM devices, etc.
  • a second polysilicon layer is deposited on the first polysilicon layer. Filling the trench with the polysilicon layer formed by the above method can significantly reduce the porosity in the polysilicon layer, improve the film-forming quality of the polysilicon layer, and further improve the electrical performance of the polysilicon layer.
  • the step of forming the first polysilicon layer 21 , the step of performing an annealing process, and the step of forming the second polysilicon layer 22 are all completed in the same process. It makes little or even no oxide layer between the first polysilicon layer 21 and the second polysilicon layer 22 finally formed in the trench, which is beneficial to reduce the resistance of the finally formed polysilicon layer and form a polysilicon layer with good electrical properties. quality semiconductor devices.
  • the semiconductor device includes: a substrate 20 having at least one trench TH2 therein;
  • the first polysilicon layer 21 covers the sidewall and bottom of the trench TH2, and there is a second opening H2 above the first polysilicon layer 21;
  • the second polysilicon layer 22 is formed on the first polysilicon layer 22.
  • the second opening H2 has a cross-sectional shape with a wide top and a narrow bottom.
  • the reason why the second opening H2 has a cross-section that is wide at the top and narrow at the bottom is that the first polysilicon layer 21 is grown to cover the sidewall and bottom of the trench TH2, and the first polysilicon layer 21 The crystalline silicon layer 21 is annealed after formation.
  • the substrate 20 includes a base material 201 and a plurality of discrete device layers 202 formed on the base material, and the trench TH2 is formed between adjacent device layers 202 .
  • the substrate 201 may be a semiconductor material, such as silicon.
  • the device layer 202 can be formed of a single layer of material or a multi-layer material; the device layer 202 can include a conductive layer or an insulating layer; the device layer 202 can be retained in the final semiconductor device, or can be It is removed during the fabrication of semiconductor devices.
  • the embodiment of the present disclosure does not limit the material, number of layers, and application of the device layer 202 .
  • an insulating layer 23 is further provided between the trench TH2 and the sidewall of the first polysilicon layer 21 .
  • the insulating layer 23 is used to isolate the device layer 202 from the first polysilicon layer 21 ; the material of the insulating layer 23 may include but not limited to silicon oxide, silicon nitride, silicon carbide, silicon oxynitride and the like.
  • the first polysilicon layer 21 may include a first sublayer 211 and a second sublayer 212 , and the first sublayer 211 is a seed layer of the second sublayer 212 .
  • the first sub-layer 211 is a seed layer
  • the first sub-layer 211 forms a plurality of "core centers" on the sidewall and bottom of the trench TH2, and the "core centers" can avoid subsequent deposition
  • the abnormal growth of crystal grains in the second sub-layer 212 reduces the lattice mismatch between the second sub-layer 212 and the trench TH2, and improves the uniformity and growth quality of the second sub-layer 212.
  • the first polysilicon layer 21 and/or the second polysilicon layer 22 may be a doped polysilicon layer.
  • a doped polysilicon layer For example, at least one of boron-doped polysilicon, phosphorus-doped polysilicon or arsenic-doped polysilicon.
  • the formation of the first polysilicon layer 21 and/or the second polysilicon layer 22 can be formed using one or more thin film deposition processes; specifically, the thin film deposition process includes but is not limited to chemical vapor deposition (CVD ) process, plasma enhanced chemical vapor deposition (PECVD) process, atomic layer deposition (ALD) process or a combination thereof.
  • CVD chemical vapor deposition
  • PECVD plasma enhanced chemical vapor deposition
  • ALD atomic layer deposition
  • the first polysilicon layer 21 and/or the second polysilicon layer 22 are formed by a low pressure chemical vapor deposition process (LPCVD).
  • LPCVD low pressure chemical vapor deposition process
  • the deposition temperature of the first polysilicon layer 21 and/or the second polysilicon layer 22 is between 350° C. and 700° C.
  • the deposition pressure is between 0.2 Torr and 4 Torr.
  • the gas used to form the first polysilicon layer 21 and/or the second polysilicon layer 22 may include, but not limited to, silane (SiH 4 ), disilane (Si 2 H 6 ), dichlorosilane (SiH 2 Cl 2 ) etc.
  • two or more gases can be mixed or used alternately among silane (SiH 4 ), disilane (Si 2 H 6 ), and dichlorosilane (SiH 2 Cl 2 ).
  • silane SiH 4
  • disilane Si 2 H 6
  • dichlorosilane SiH 2 Cl 2
  • phosphine PH 3
  • boron trichloride One or more gases in BCl 3
  • borane B 2 H 6
  • arsine AsH 4
  • performing the annealing process on the first polysilicon layer 21 can significantly reduce the lattice defects of the first polysilicon layer 21 and improve the planarization degree of the first polysilicon layer 21, It is beneficial to improve the filling ability of the second polysilicon layer 22 formed subsequently, and greatly reduces the possibility of pores in the polysilicon layer.
  • the function of the annealing process also includes: removing semi-reactants or impurities generated during the formation of the first polysilicon layer 21 from the first polysilicon layer 21, so as to improve the film quality of the formed first polysilicon layer 21.
  • the annealing process is performed in an annealing furnace; specifically, the annealing furnace may be a furnace tube.
  • the temperature range of the annealing process is between 500° C. and 700° C.
  • the pressure range is between 10 Torr and 100 Torr
  • the time range is between 1 h and 2 h.
  • nitrogen gas is introduced into the annealing furnace.
  • the nitrogen gas is used to stabilize the pressure in the process chamber so that the annealing process can be performed within a set pressure range.
  • the first polysilicon layer and the second polysilicon layer in the embodiments of the present disclosure can form conductive lines, such as bit lines and word lines in DRAM devices; but they are not limited thereto, and can also form other conductive lines. Structures, such as conductive plugs, such as bit line plugs in DRAM devices, etc.
  • the semiconductor device of the embodiment of the present disclosure there are almost no pores in the formed polysilicon layer, which reduces the resistance of the polysilicon layer filled in the trench TH2 and helps to form a semiconductor device with good electrical quality. It should be understood that the semiconductor device may be formed by using a method for manufacturing a semiconductor device provided in the foregoing embodiments.
  • the method for manufacturing a semiconductor device provided by the embodiments of the present disclosure can be applied to a DRAM structure or other semiconductor devices, and there is no excessive limitation here.
  • the embodiment of the semiconductor device manufacturing method provided in the present disclosure belongs to the same idea as the embodiment of the semiconductor device; the technical features in the technical solutions recorded in each embodiment can be combined arbitrarily if there is no conflict.
  • the method for manufacturing a semiconductor device and the semiconductor device provided by the embodiments of the present disclosure, wherein the method includes: providing a substrate having at least one groove; forming a first polysilicon layer in the groove , the first polysilicon layer covers the sidewall and bottom of the trench, and does not completely fill the trench; an annealing process is performed on the first polysilicon layer; after performing the annealing process, A second polysilicon layer is formed at regions of the trench not filled by the first polysilicon layer. After the first polysilicon layer is formed in the trench, the annealing process can significantly reduce the lattice defects of the first polysilicon layer, planarize the first polysilicon layer, and improve the hardness of the second polysilicon layer. filling capacity. Therefore, the embodiments of the present disclosure can effectively reduce or even eliminate the voids in the first polysilicon layer and the second polysilicon layer finally filled in the trenches, and improve the electrical performance of the semiconductor device.

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Abstract

本公开实施例公开了一种半导体器件的制造方法，所述方法包括：提供衬底，所述衬底具有至少一个沟槽；在所述沟槽内形成第一多晶硅层，所述第一多晶硅层覆盖所述沟槽的侧壁和底部，且未完全填充所述沟槽；对所述第一多晶硅层执行退火工艺；在执行所述退火工艺后，在所述沟槽未被所述第一多晶硅层填充的区域处形成第二多晶硅层。

Description

一种半导体器件的制造方法及半导体器件
相关的交叉引用
本公开基于申请号为202111266168.3、申请日为2021年10月28日、发明名称为“一种半导体器件的制造方法及半导体器件”的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本公开作为参考。
技术领域
本公开涉及半导体制造领域，尤其涉及一种半导体器件的制造方法及半导体器件。
背景技术
半导体器件，如动态随机存储器(Dynamic Random Access Memory，DRAM)，包括很多导电线，该导电线在形成时，通常需要在沟槽内填充多晶硅层。
然而，由于工艺条件的限制或者是因为沟槽的深宽比过大，填充于沟槽内的多晶硅层中容易存在较大的孔隙，影响所述导电线的电学性能。
发明内容
本公开实施例提供了一种半导体器件的制造方法，所述方法包括：提供衬底，所述衬底具有至少一个沟槽；在所述沟槽内形成第一多晶硅层，所述第一多晶硅层覆盖所述沟槽的侧壁和底部，且未完全填充所述沟槽；对所述第一多晶硅层执行退火工艺；在执行所述退火工艺后，在所述沟槽未被所述第一多晶硅层填充的区域处形成第二多晶硅层。
上述方案中，在执行所述退火工艺之前，所述第一多晶硅层的厚度与所述沟槽的深度的比值在1∶5至1∶4之间。
上述方案中，所述第一多晶硅层在执行所述退火工艺之前，所述沟槽未被所述第一多晶硅层填充的区域构成第一开口，所述第一开口具有上窄下宽的截面形状。
上述方案中，所述第一多晶硅层在执行所述退火工艺后，所述沟槽未被所述第一多晶硅层填充的区域构成第二开口，所述第二开口具有上宽下窄的截面形状。
上述方案中，所述第二开口的深度小于所述第一开口的深度。
上述方案中，所述退火工艺的温度范围在500℃～700℃之间，所述退火工艺的压力范围在10Torr至100Torr之间，所述退火工艺的时间范围在1h至2h之间。
上述方案中，在同一制程中完成如下步骤：所述形成第一多晶硅层的步骤、所述执行退火工艺的步骤及所述形成第二多晶硅层的步骤。
上述方案中，完成所述同一制程的装置包括炉管。
上述方案中，所述第一多晶硅层和/或所述第二多晶硅层包括掺杂的多晶硅。
上述方案中，所述掺杂的多晶硅包括硼掺杂的多晶硅、磷掺杂的多晶硅或砷掺杂的多晶硅中的至少一种。
上述方案中，在所述沟槽内形成第一多晶硅层之前，所述方法还包括：在所述沟槽的侧壁沉积绝缘层。
上述方案中，所述第一多晶硅层包括第一子层和第二子层；在所述沟槽内形成第一多晶硅层，包括：
在所述沟槽内形成所述第一子层，所述第一子层覆盖所述沟槽的侧壁和底部；
在所述第一子层上形成所述第二子层。
上述方案中，所述第一多晶硅层和/或所述第二多晶硅层的沉积温度在350℃至700℃之间，沉积压力在0.2Torr至4Torr之间。
上述方案中，在形成所述第二多晶硅层后，所述方法还包括：对所述第二多晶硅层执行退火工艺。
本公开实施例还提供了一种半导体器件，所述半导体器件包括：
衬底，所述衬底内具有至少一个沟槽；
第一多晶硅层，覆盖所述沟槽的侧壁和底部；所述第一多晶硅层的上方具有第二开口，所述第二开口具有上宽下窄的截面形状；
第二多晶硅层，位于所述第二开口内。
上述方案中，所述衬底包括底材以及形成在所述底材上的多个分立的器件层，所述沟槽形成在相邻所述器件层之间。
上述方案中，所述第一多晶硅层包括第一子层及位于所述第一子层上的第二子层，所述第一子层是所述第二子层的种子层。
上述方案中，所述半导体器件还包括：绝缘层，所述绝缘层位于所述第一多晶硅层和所述沟槽的侧壁之间。
本公开实施例所提供的半导体器件的制造方法及半导体器件，其中，所述方法包括：提供衬底，所述衬底具有至少一个沟槽；在所述沟槽内形成第一多晶硅层，所述第一多晶硅层覆盖所述沟槽的侧壁和底部，且未完全填充所述沟槽；对所述第一多晶硅层执行退火工艺；在执行所述退火工艺后，在所述沟槽未被所述第一多晶硅层填充的区域处形成第二多晶硅层。在沟槽内形成第一多晶硅层之后，执行退火工艺，可显著减少第一多晶硅层的晶格缺陷，并使第一多晶硅层平坦化，提高第二多晶硅层的填充能力。因此，本公开实施例可有效减少甚至消除最终填充在沟槽内的第一多晶硅层和第二多晶硅层中的孔隙，提高半导体器件的电性能。
本公开的一个或多个实施例的细节在下面的附图和描述中提出。本公开的其它特征和优点将从说明书、附图以及权利要求书变得明显。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为示例性半导体器件的结构示意图；
图2为本公开实施例提供的半导体器件的制备方法的流程框图；
图3至图8为本公开实施例提供的半导体器件的制备方法的工艺流程图。
具体实施方式
下面将参照附图更详细地描述本公开的示例性实施方式。虽然附图中显示了本公开的示例性实施方式，然而应当理解，可以以各种形式实现本公开，而不应被这里阐述的具体实施方式所限制。相反，提供这些实施方式是为了能够更透彻地理解本公开，并且能够将本公开的范围完整的传达给本领域的技术人员。
在下文的描述中，给出了大量具体的细节以便提供对本公开更为彻底的理解。然而，对于本领域技术人员而言显而易见的是，本公开可以无需一个或多个这些细节而得以实施。在其他的例子中，为了避免与本公开发生混淆，对于本领域公知的一些技术特征未进行描述；即，这里不描述实际实施例的全部特征，不详细描述公知的功能和结构。
在附图中，为了清楚，层、区、元件的尺寸以及其相对尺寸可能被夸大。自始至终相同附图标记表示相同的元件。
应当明白，当元件或层被称为“在……上”、“与……相邻”、“连接到”或“耦合到”其它元件或层时，其可以直接地在其它元件或层上、与之相邻、连接或耦合到其它元件或层，或者可以存在居间的元件或层。相反，当元件被称为“直接在……上”、“与……直接相邻”、“直接连接到”或“直接耦合到”其它元件或层时，则不存在居间的元件或层。应当明白，尽管可使用术语第一、第二、第三等描述各种元件、部件、区、层和/或部分，这些元件、部件、区、层和/或部分不应当被这些术语限制。这些术语仅仅用来区分一个元件、部件、区、层或部分与另一个元件、部件、区、层或部分。因此，在不脱离本公开教导之下，下面讨论的第一元件、部件、区、层或部分可表示为第二元件、部件、区、层或部分。而当讨论第二元件、部件、区、层或部分时，并不表明本公开必然存在第一元件、部件、区、层或部分。
空间关系术语例如“在……下”、“在……下面”、“下面的”、“在……之下”、“在……之上”、“上面的”等，在这里可为了方便描述而被使用从而描述图中所示的一个元件或特征与其它元件或特征的关系。应当明白，除了图中所示的取向以外，空间关系术语意图还包括使用和操作中的器件的不同取向。例如，如果附图中的器件翻转，然后，描述为“在其它元件下面”或“在其之下”或“在其下”元件或特征将取向为在其它元件或特征“上”。因此，示例性术语“在……下面”和“在……下”可包括上和下两个取向。器件可以另外地取向(旋转90度或其它取向)并且在此使用的空间描述语相应地被解释。
在此使用的术语的目的仅在于描述具体实施例并且不作为本公开的限制。在此使用时，单数形式的“一”、“一个”和“所述/该”也意图包括复数形式，除非上下文清楚指出另外的方式。还应明白术语“组成”和/或“包括”，当在该说明书中使用时，确定所述特征、整数、步骤、操作、元件和/或部件的存在，但不排除一个或更多其它的特征、整数、步骤、操作、元件、 部件和/或组的存在或添加。在此使用时，术语“和/或”包括相关所列项目的任何及所有组合。
在半导体器件，如DRAM中，导电线的质量好坏会关系到最终形成的器件的电性能的好坏。图1为示例性半导体器件的结构示意图，如图1所示，所述半导体器件包括：衬底10；所述衬底10内具有多个沟槽TH1，所述多个沟槽TH1内填充有多晶硅层12。
所述多晶硅层12是通过常规的沉积方式形成在沟槽TH1内的，可以看出，所述多晶硅层12内存在孔隙13，该孔隙13的存在会增加所述多晶硅层的电阻，影响后续形成的导电线的电学性能。
基于此，提出了本公开实施例的以下技术方案：
本公开实施例提供了一种半导体器件的制造方法，如图2所示，所述方法包括了如下步骤：
步骤210：提供衬底，所述衬底具有至少一个沟槽；
步骤220：在所述沟槽内形成第一多晶硅层，所述第一多晶硅层覆盖所述沟槽的侧壁和底部，且未完全填充所述沟槽；
步骤230：对所述第一多晶硅层执行退火工艺；
步骤240：在执行所述退火工艺后，在所述沟槽未被所述第一多晶硅层填充的区域处形成第二多晶硅层。
本公开实施例在沟槽内形成第一多晶硅层之后，执行退火工艺，可显著减少第一多晶硅层的晶格缺陷，并使第一多晶硅层平坦化，提高第二多晶硅层的填充能力。因此，本公开实施例可有效减少甚至消除最终填充在沟槽内的第一多晶硅层和第二多晶硅层中的孔隙，提高半导体器件的电性能。
为使本公开的上述目的、特征和优点能够更加明显易懂，下面结合附图对本公开的具体实施方式做详细的说明。在详述本公开实施例时，为便 于说明，示意图会不依一般比例作局部放大，而且所述示意图只是示例，其在此不应限制本公开的保护范围。
图3至图8为本公开实施例提供的半导体器件的制备方法的工艺流程图。
首先，如图3所示，执行步骤210，提供衬底20，所述衬底20至少具有一个沟槽TH2。
所述沟槽TH2可以采用干法刻蚀工艺或湿法刻蚀工艺形成在所述衬底20内。
在一些具体的实施例中，所述衬底20包括底材201以及形成在所述底材201上的多个分立的器件层202，所述沟槽TH2形成在相邻的所述器件层202之间。具体的，所述底材201可以为半导体材料，如硅。所述器件层202可以由单层的材料形成或者多层的材料形成；所述器件层202可以包括导电层也可以包括绝缘层；所述器件层202可以在最终的半导体器件中保留，也可以在半导体器件的制备过程中被移除。总而言之，本公开实施例不限制所述器件层202的材料、层数、及用途。
根据一些实施例，如图4所示，在所述沟槽TH2内形成第一多晶硅层21(参见图6)之前，所述方法还包括：在所述沟槽TH2的侧壁沉积绝缘层23。所述绝缘层23用于隔离所述器件层202和第一多晶硅层21。所述绝缘层23的材料可以包括但不限于氧化物，氮化物，及氮氧化物，例如氧化硅、氮化硅、氮氧化硅等。
接着，如图5、图6所示，执行步骤220，在所述沟槽TH2内形成第一多晶硅层21，所述第一多晶硅层21覆盖所述沟槽TH2的侧壁和底部，且未完全填充所述沟槽TH2。
根据一些实施例，所述第一多晶硅层21可以包括第一子层211和第二子层212。在所述沟槽TH2内形成第一多晶硅层21，包括：
在所述沟槽TH2内形成所述第一子层211，所述第一子层211覆盖所述沟槽TH2的侧壁和底部，如图5所示；
在所述第一子层211的上方形成所述第二子层212，如图6所示。
所述第一子层211和所述第二子层212的材料相同，都为多晶硅层。其中，所述第一子层211为籽晶层，所述第一子层211在所述沟槽TH2的侧壁和底部形成诸多个“核中心”，所述“核中心”可避免后续沉积的第二子层212中晶粒的异常生长，减少第二子层212和所述沟槽TH2之间的晶格失配，提高第二子层212的均匀性和生长质量。
所述第一多晶硅层21可以为掺杂的多晶硅层，比如，硼掺杂的多晶硅、磷掺杂的多晶硅或砷掺杂的多晶硅中的至少一种。
所述第一多晶硅层21的形成可以使用一种或多种薄膜沉积工艺形成；具体的，所述薄膜沉积工艺包括但不限于化学气相沉积(CVD)工艺、等离子体增强化学气相沉积(PECVD)工艺、原子层沉积(ALD)工艺或其组合。
在一示例性的实施例中，采用低压化学气相沉积工艺(LPCVD)形成所述第一多晶硅层21。具体的，所述第一多晶硅层21的沉积温度在350℃至700℃之间，沉积压力在0.2Torr至4Torr之间。用于形成所述第一多晶硅层21的气体可以包括但不限于硅烷(SiH 4)、乙硅烷(Si 2H 6)、二氯氢硅(SiH 2Cl 2)等。在实际工艺中，可在硅烷(SiH 4)、乙硅烷(Si 2H 6)、二氯氢硅(SiH 2Cl 2)中选取两种以上的气体混和或交替使用。当所述第一多晶硅层21为掺杂的多晶硅层时，在制备时，向腔室内通入磷化氢(PH 3),三氯化硼(BCl 3),硼烷(B 2H 6),砷烷(AsH 4)内的一种或多种气体以形成掺杂的多晶硅层。
在实际的工艺中，所述第一多晶硅层21的厚度与所述沟槽TH2的深度的比值在1∶5至1∶4之间。所述第一多晶硅层21过厚或者过薄都会对后 续生长的第二多晶硅层22产生不利的影响。
继续参考图6，所述第一多晶硅层21在执行后续的退火工艺之前，所述沟槽TH2未被所述第一多晶硅层21填充的区域构成第一开口H1，所述第一开口H1的深度为h1，所述第一开口H1具有上窄下宽的截面形状。可以理解的是，具有上窄下宽的截面形状的第一开口H1不利于后续第二多晶硅层22(参见图8)的沉积。
接下来，如图7所示，执行步骤230，对所述第一多晶硅层21执行退火工艺。所述退火工艺可将第一多晶硅层21内的半反应物或者是杂质排出，显著减少第一多晶硅层21的晶格缺陷，同时能够使所述第一多晶硅层21更加平坦，利于后续第二多晶硅层22(参见图8)的沉积。这里，所述半反应物或杂质包括但不限于氢气、氯化氢等。
在执行所述退火工艺后，如图7所示，所述沟槽TH2未被所述第一多晶硅层21填充的区域构成第二开口H2，所述第二开口H2具有深度h2，所述第二开口H2具有上宽下窄的截面形状。结合图6可以看出，所述第二开口H2的深度h2小于所述第一开口H1的深度h1，即h2<h1。换言之，在执行退火工艺后，所述第一多晶硅层21上方的开口的深度变浅，且开口的截面形状由上窄下宽变为上宽下窄，更利于后续第二多晶硅层22的填充。
所述退火工艺在退火炉内进行；具体的，所述退火炉可以为炉管。在本公开的一个实施例中，所述退火工艺的温度范围在500℃～700℃之间，压力范围在10Torr至100Torr之间，时间范围在1h至2h之间。可选的，在所述退火工艺的过程中，向所述退火炉内通入氮气。这里，所述氮气用于稳定工艺腔室内的压力，以使退火工艺能够在设定的压力范围内进行。
最后，如图8所示，执行步骤240：在执行所述退火工艺后，在所述沟槽TH2未被所述第一多晶硅层21填充的区域处形成第二多晶硅层22。也即，在所述第二开口H2内形成第二多晶硅层22。
至此，所述沟槽TH2被所述第一多晶硅层21和所述第二多晶硅层22填满，所述第一多晶硅层21和所述第二多晶硅层22的孔隙率远小于相关技术中多晶硅层12的孔隙率。
所述第二多晶硅层22可以为掺杂的多晶硅层，比如，硼掺杂的多晶硅、磷掺杂的多晶硅或砷掺杂的多晶硅中的至少一种。所述第二多晶硅层22内的掺杂元素可以与所述第一多晶硅层21内的掺杂元素相同或者不相同。
所述第二多晶硅层22的形成可以使用一种或多种薄膜沉积工艺形成；具体的，所述薄膜沉积工艺包括但不限于化学气相沉积(CVD)工艺、等离子体增强化学气相沉积(PECVD)工艺、原子层沉积(ALD)工艺或其组合。
在一具体的实施例中，采用低压化学气相沉积工艺(LPCVD)形成所述第二多晶硅层22。具体的，所述第二多晶硅层22的沉积温度在350℃至700℃之间，沉积压力在0.2Torr至4Torr之间。用于形成所述第二多晶硅层22的气体可以包括但不限于硅烷(SiH 4)、乙硅烷(Si 2H 6)、二氯氢硅(SiH 2Cl 2)等。在实际工艺中，可在硅烷(SiH 4)、乙硅烷(Si 2H 6)、二氯氢硅(SiH 2Cl 2)中选取两种以上的气体混和或交替使用。当所述第二多晶硅层22为掺杂的多晶硅层时，在制备时，向腔室内通入磷化氢(PH 3),三氯化硼(BCl 3),硼烷(B 2H 6),砷烷(AsH 4)内的一种或多种气体以形成掺杂的多晶硅层。
在本公开的一个实施例中，在同一制程中完成所述第一多晶硅层21的形成步骤、所述执行退火工艺的步骤，以及所述第二多晶硅层22的形成步骤。如此，可以避免所述第一多晶硅层21的表面在不同制程的转换途中被氧化生成氧化层，该氧化层会增加所述第一多晶硅层21和所述第二多晶硅层22的电阻。
具体的，完成所述同一制程的装置可以包括但不限于炉管等。即，可以在炉管内相继的进行如下步骤：形成第一多晶硅层、执行退火工艺、形 成第二多晶硅层。在此过程中，不需要将形成有第一多晶硅层的衬底从炉管内移出，所述第一多晶硅层不会被氧化。
在一实施例中，在形成所述第二多晶硅层之后，所述方法还包括：对所述第二多晶硅层执行退火工艺。该退火工艺主要的目的在于修复所述第二多晶硅层内的缺陷，进一步降低所述第二多晶硅层内的孔隙率，提高所述第二多晶硅层的成膜质量。
所述第二多晶硅层退火的工艺条件可以与对所述第一多晶硅层退火时的工艺条件相同，也可以不同，在此不再赘述。
本公开实施例中的所述第一多晶硅层和所述第二多晶硅层可以构成导电线，如DRAM器件中的位线，字线等；但不限于此，也可以构成其他导电结构，如导电插塞，如DRAM器件中的位线插塞等。
本公开实施例提供的半导体器件的制造方法，在沟槽内形成第一多晶硅层之后，执行退火工艺，再在所述第一多晶硅层上沉积第二多晶硅层。采用上述方法在沟槽内填充形成的多晶硅层，可以显著的减少该多晶硅层内的孔隙率，提高多晶硅层的成膜质量，进而提高该多晶硅层的电学性能。
另外，本公开的一个实施例中，形成第一多晶硅层21的步骤、执行退火工艺的步骤，以及形成第二多晶硅层22的步骤均在同一制程中完成。使得最终形成在沟槽内的第一多晶硅层21和第二多晶硅层22之间极少产生甚至不产生氧化层，有利于降低最终形成的多晶硅层的电阻，形成具有良好电性品质的半导体器件。
本公开实施例还提供了一种半导体器件，如图8所示，所述半导体器件包括：衬底20，所述衬底20内具有至少一个沟槽TH2；第一多晶硅层21，所述第一多晶硅层21覆盖所述沟槽TH2的侧壁和底部，所述第一多晶硅层21的上方具有第二开口H2；第二多晶硅层22，形成在所述第二开口H2内；其中，所述第二开口H2具有上宽下窄的截面形状。所述第二开口 H2之所以具有上宽下窄的截面，是因为所述第一多晶硅层21是以覆盖所述沟槽TH2的侧壁和底面的方式生长，且所述第一多晶硅层21在形成之后进行了退火。
在一些实施例中，所述衬底20包括底材201以及形成在所述底材上的多个分立的器件层202，所述沟槽TH2形成在相邻的所述器件层202之间。具体的，所述底材201可以为半导体材料，如硅。所述器件层202可以由单层的材料形成或者多层的材料形成；所述器件层202可以包括导电层也可以包括绝缘层；所述器件层202可以在最终的半导体器件中保留，也可以在半导体器件的制备过程中被移除。总而言之，本公开实施例不限制所述器件层202的材料、层数、及用途。
在一些实施例中，在所述沟槽TH2和所述第一多晶硅层21的侧壁之间还设有绝缘层23。所述绝缘层23用于隔离所述器件层202和第一多晶硅层21；所述绝缘层23的材料可以包括但不限于氧化硅、氮化硅、碳化硅、硅氧氮化物等。
可选的，所述第一多晶硅层21可以包括第一子层211和第二子层212，所述第一子层211是所述第二子层212的种子层。这里，所述第一子层211为籽晶层，所述第一子层211在所述沟槽TH2的侧壁和底部形成诸多个“核中心”，所述“核中心”可避免后续沉积的第二子层212中晶粒的异常生长，减少第二子层212和所述沟槽TH2之间的晶格失配，提高第二子层212的均匀性和生长质量。
所述第一多晶硅层21和/或第二多晶硅层22可以为掺杂的多晶硅层。比如，硼掺杂的多晶硅、磷掺杂的多晶硅或砷掺杂的多晶硅中的至少一种。
所述第一多晶硅层21和/或第二多晶硅层22的形成可以使用一种或多种薄膜沉积工艺形成；具体的，所述薄膜沉积工艺包括但不限于化学气相沉积(CVD)工艺、等离子体增强化学气相沉积(PECVD)工艺、原子层 沉积(ALD)工艺或其组合。
在一具体的实施例中，采用低压化学气相沉积工艺(LPCVD)形成所述第一多晶硅层21和/或第二多晶硅层22。具体的，所述第一多晶硅层21和/或第二多晶硅层22的沉积温度在350℃至700℃之间，沉积压力在0.2Torr至4Torr之间。用于形成所述第一多晶硅层21和/或第二多晶硅层22的气体可以包括但不限于硅烷(SiH 4)、乙硅烷(Si 2H 6)、二氯氢硅(SiH 2Cl 2)等。在实际工艺中，可在硅烷(SiH 4)、乙硅烷(Si 2H 6)、二氯氢硅(SiH 2Cl 2)中选取两种以上的气体混和或交替使用。当所述第一多晶硅层21和/或第二多晶硅层22为掺杂的多晶硅层时，在制备时，向腔室内通入磷化氢(PH 3),三氯化硼(BCl 3),硼烷(B 2H 6),砷烷(AsH 4)内的一种或多种气体以形成掺杂的多晶硅层。
可以理解的，对所述第一多晶硅层21执行退火工艺，可以显著减少所述第一多晶硅层21的晶格缺陷，提高所述第一多晶硅层21的平坦化程度，有利于提高后续形成的所述第二多晶硅层22的填充能力，极大的减少了在多晶硅层中产生孔隙的可能性。另外，在执行退火工艺的过程中，所述退火工艺的作用还包括：将所述第一多晶硅层21形成过程中产生的半反应物或不纯物从所述第一多晶硅层21中排出，以提高形成的所述第一多晶硅层21的膜层质量。
所述退火工艺在退火炉内进行；具体的，所述退火炉可以为炉管。在本公开的一个实施例中，所述退火工艺的温度范围在500℃～700℃之间，压力范围在10Torr至100Torr之间，时间范围在1h至2h之间。可选的，在所述退火工艺的过程中，向所述退火炉内通入氮气。这里，所述氮气用于稳定工艺腔室内的压力，以使退火工艺能够在设定的压力范围内进行。
本公开实施例中的所述第一多晶硅层和所述第二多晶硅层可以构成导电线，如DRAM器件中的位线，字线等；但不限于此，也可以构成其他导 电结构，如导电插塞，如DRAM器件中的位线插塞等。
本公开实施例的半导体器件中，形成的多晶硅层中几乎没有孔隙存在，降低了填充在沟槽TH2内的多晶硅层的电阻，有助于形成具有良好电性品质的半导体器件。应当理解，所述半导体器件的形成可以采用上述各实施例提供的一种半导体器件的制造方法来形成。
需要说明的是，本公开实施例提供的半导体器件的制备方法可应用于DRAM结构或其他半导体器件中，在此不做过多限定。本公开提供的半导体器件制备方法的实施例与半导体器件的实施例属于同一构思；各实施例所记载的技术方案中各技术特征之间，在不冲突的情况下，可以任意组合。
以上所述，仅为本公开的较佳实施例而已，并非用于限定本公开的保护范围，凡在本公开的精神和原则之内所作的任何修改、等同替换和改进等，均应包含在本公开的保护范围之内。
工业实用性
本公开实施例所提供的半导体器件的制造方法及半导体器件，其中，所述方法包括：提供衬底，所述衬底具有至少一个沟槽；在所述沟槽内形成第一多晶硅层，所述第一多晶硅层覆盖所述沟槽的侧壁和底部，且未完全填充所述沟槽；对所述第一多晶硅层执行退火工艺；在执行所述退火工艺后，在所述沟槽未被所述第一多晶硅层填充的区域处形成第二多晶硅层。在沟槽内形成第一多晶硅层之后，执行退火工艺，可显著减少第一多晶硅层的晶格缺陷，并使第一多晶硅层平坦化，提高第二多晶硅层的填充能力。因此，本公开实施例可有效减少甚至消除最终填充在沟槽内的第一多晶硅层和第二多晶硅层中的孔隙，提高半导体器件的电性能。

Claims (18)

  1. 一种半导体器件的制造方法，所述方法包括：
    提供衬底，所述衬底具有至少一个沟槽；
    在所述沟槽内形成第一多晶硅层，所述第一多晶硅层覆盖所述沟槽的侧壁和底部，且未完全填充所述沟槽；
    对所述第一多晶硅层执行退火工艺；
    在执行所述退火工艺后，在所述沟槽未被所述第一多晶硅层填充的区域处形成第二多晶硅层。
  2. 根据权利要求1所述的方法，其中，在执行所述退火工艺之前，所述第一多晶硅层的厚度与所述沟槽的深度的比值在1∶5至1∶4之间。
  3. 根据权利要求1所述的方法，其中，所述第一多晶硅层在执行所述退火工艺之前，所述沟槽未被所述第一多晶硅层填充的区域构成第一开口，所述第一开口具有上窄下宽的截面形状。
  4. 根据权利要求3所述的方法，其中，所述第一多晶硅层在执行所述退火工艺后，所述沟槽未被所述第一多晶硅层填充的区域构成第二开口，所述第二开口具有上宽下窄的截面形状。
  5. 根据权利要求4所述的方法，其中，所述第二开口的深度小于所述第一开口的深度。
  6. 根据权利要求1所述的方法，其中，所述退火工艺的温度范围在500℃～700℃之间，所述退火工艺的压力范围在10Torr至100Torr之间，所述退火工艺的时间范围在1h至2h之间。
  7. 根据权利要求1所述的方法，其中，在同一制程中完成如下步骤：所述形成第一多晶硅层的步骤、所述执行退火工艺的步骤及所述形成第二多晶硅层的步骤。
  8. 根据权利要求7所述的方法，其中，完成所述同一制程的装置包 括炉管。
  9. 根据权利要求1所述的方法，其中，所述第一多晶硅层和/或所述第二多晶硅层包括掺杂的多晶硅。
  10. 根据权利要求9所述的方法，其中，所述掺杂的多晶硅包括硼掺杂的多晶硅、磷掺杂的多晶硅或砷掺杂的多晶硅中的至少一种。
  11. 根据权利要求1所述的方法，其中，在所述沟槽内形成第一多晶硅层之前，所述方法还包括：在所述沟槽的侧壁沉积绝缘层。
  12. 根据权利要求1所述的方法，其中，所述第一多晶硅层包括第一子层和第二子层；在所述沟槽内形成第一多晶硅层，包括：
    在所述沟槽内形成所述第一子层，所述第一子层覆盖所述沟槽的侧壁和底部；
    在所述第一子层上形成所述第二子层。
  13. 根据权利要求1所述的方法，其中，所述第一多晶硅层和/或所述第二多晶硅层的沉积温度在350℃至700℃之间，沉积压力在0.2Torr至4Torr之间。
  14. 根据权利要求1所述的方法，其中，在形成所述第二多晶硅层后，所述方法还包括：对所述第二多晶硅层执行退火工艺。
  15. 一种半导体器件，包括：
    衬底，所述衬底内具有至少一个沟槽；
    第一多晶硅层，覆盖所述沟槽的侧壁和底部；所述第一多晶硅层的上方具有第二开口，所述第二开口具有上宽下窄的截面形状；
    第二多晶硅层，位于所述第二开口内。
  16. 根据权利要求15所述的半导体器件，其中，所述衬底包括底材以及形成在所述底材上的多个分立的器件层，所述沟槽形成在相邻所述器件层之间。
  17. 根据权利要求15所述的半导体器件，其中，所述第一多晶硅层包括第一子层及位于所述第一子层上的第二子层，所述第一子层是所述第二子层的种子层。
  18. 根据权利要求15所述的半导体器件，其中，所述半导体器件还包括：绝缘层，所述绝缘层位于所述第一多晶硅层和所述沟槽的侧壁之间。
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