TW202027275A - 半導體元件及其製作方法 - Google Patents

半導體元件及其製作方法 Download PDF

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TW202027275A
TW202027275A TW108100160A TW108100160A TW202027275A TW 202027275 A TW202027275 A TW 202027275A TW 108100160 A TW108100160 A TW 108100160A TW 108100160 A TW108100160 A TW 108100160A TW 202027275 A TW202027275 A TW 202027275A
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trench
type well
conductivity type
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TWI772588B (zh
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李志成
陳威任
李凱霖
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聯華電子股份有限公司
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Priority to US16/252,679 priority patent/US10629728B1/en
Priority to US16/812,358 priority patent/US10756209B2/en
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Abstract

一種半導體元件，包含基底，包含鰭狀結構，被溝渠絕緣區域圍繞；溝槽，設於鰭狀結構中；氮化矽填溝層，設於溝槽中；層間介電層，設於氮化矽填溝層上；工作閘極，越過鰭狀結構，於溝槽的第一側；虛設閘極，越過鰭狀結構，虛設閘極設置在溝槽的第二側；源極摻雜區，設於鰭狀結構中；以及汲極摻雜區，設於鰭狀結構中，其中虛設閘極設置在溝槽與汲極摻雜區之間。

Description

半導體元件及其製作方法
本發明係有關於半導體製程技術領域，特別是有關於一種具有橫向雙擴散MOS（LDMOS）結構的鰭式場效應電晶體（finFET），能夠改善汲極端的熱載子注入（Hot Carrier Injection，HCI）問題。
已知，橫向雙擴散MOS（LDMOS）元件廣泛用於不同的高壓應用，例如開關模式電源和功率放大器。在CMOS電晶體中，在靠近閘極和汲極重疊區域的高電場區域處，導通狀態載子通過碰撞電離，會產生熱載子注入（Hot Carrier Injection，HCI）問題。
鰭式場效應電晶體（finFET）是三維（3D）元件結構，常應用於奈米級互補金屬氧化物半導體（CMOS）和高密度記憶體等領域。其中，具有橫向雙擴散MOS（LDMOS）結構的finFET，主要用於RF功率放大器，可以提供高崩潰電壓（例如，汲極和源極端子之間）。
然而，現有的LDMOS元件，特別是針對N型LDMOS元件，其缺點在於汲極端的熱載子注入（HCI）問題仍無法獲得有效的改善。
本發明提供了一種改良的鰭式場效應電晶體元件及其製作方法，以解決上述現有技術的不足與缺點。
本發明一方面提供一種半導體元件，包含：一基底，包含一鰭狀結構，被一溝渠絕緣區域圍繞，其中該鰭狀結構包含一第一導電型井區域與一第二導電型井區域，該第二導電型井區域鄰近該第一導電型井區域，且在該第一導電型井區域與該第二導電型井區域之間具有一井接面；一溝槽，設於該鰭狀結構中，且在該第二導電型井區域內；一氮化矽填溝層，設於該溝槽中；一層間介電層，設於該氮化矽填溝層上；一工作閘極，越過該鰭狀結構，其中該工作閘極設於該溝槽的一第一側，且該工作閘極與該井接面重疊；一虛設閘極，越過該鰭狀結構，其中該虛設閘極係設置在相對該第一側的該溝槽的一第二側；一源極摻雜區，設於該鰭狀結構中，其中該源極摻雜區鄰近該工作閘極；以及一汲極摻雜區，設於該鰭狀結構中，鄰近該虛設閘極，其中該虛設閘極係設置在該溝槽與該汲極摻雜區之間。
本發明另一方面提供一種形成半導體元件的方法。首先提供一基底，包含一鰭狀結構，被一溝渠絕緣區域圍繞，其中該鰭狀結構包含一第一導電型井區域與一第二導電型井區域，該第二導電型井區域鄰近該第一導電型井區域，且在該第一導電型井區域與該第二導電型井區域之間具有一井接面。於該鰭狀結構中形成一溝槽，其中該溝槽被設置在該第二導電型井區域內。於該溝槽中形成一氮化矽填溝層。於該氮化矽填溝層上形成一層間介電層。形成一工作閘極，越過該鰭狀結構，其中該工作閘極設於該溝槽的一第一側，且該工作閘極與該井接面重疊。形成一虛設閘極，越過該鰭狀結構，其中該虛設閘極係設置在相對該第一側的該溝槽的一第二側。於該鰭狀結構中形成一源極摻雜區，其中該源極摻雜區鄰近該工作閘極。於該鰭狀結構中形成一汲極摻雜區，其中該汲極摻雜區鄰近該虛設閘極，且該虛設閘極係設置在該溝槽與該汲極摻雜區之間。
為讓本發明之上述目的、特徵及優點能更明顯易懂，下文特舉較佳實施方式，並配合所附圖式，作詳細說明如下。然而如下之較佳實施方式與圖式僅供參考與說明用，並非用來對本發明加以限制者。
在下文中，將參照附圖說明細節，該些附圖中之內容亦構成說明書細節描述的一部份，並且以可實行該實施例之特例描述方式來繪示。下文實施例已描述足夠的細節俾使該領域之一般技藝人士得以具以實施。
當然，亦可採行其他的實施例，或是在不悖離文中所述實施例的前提下作出任何結構性、邏輯性、及電性上的改變。因此，下文之細節描述不應被視為是限制，反之，其中所包含的實施例將由隨附的申請專利範圍來加以界定。
請參閱第1圖及第2圖。第1圖為依據本發明一實施例所繪示的一種具有橫向雙擴散MOS（LDMOS）結構的鰭式場效應電晶體（finFET）的佈局上視示意圖。第2圖為沿著第1圖中切線I-I’所示的剖面示意圖。如第1圖及第2圖所示，本發明鰭式場效應電晶體1，包含基底100，例如，矽基底，但不限於此。基底100包含多個鰭狀結構101，例如，2～8條鰭狀結構101，被溝渠絕緣區域110圍繞。根據本發明實施例，溝渠絕緣區域110包含氧化矽填溝層112。根據本發明實施例，鰭狀結構101沿著第一方向（例如，第1圖中的參考X軸方向）延伸。溝渠絕緣區域110基本上是帶狀區域，平行於鰭狀結構101，沿著第1圖中的參考X軸方向延伸。
在第2圖中，刻意另以虛線顯示出鰭狀結構101兩側的溝渠絕緣區域110內的氧化矽填溝層112的頂面112a與底面112b。鰭狀結構101凸出於氧化矽填溝層112的頂面112a的部分係用來形成本發明鰭式場效應電晶體1。根據本發明實施例，基底100係為矽基底，鰭狀結構101為矽鰭狀結構，但不限於此。
根據本發明實施例，鰭狀結構101包含第一導電型井區域103與第二導電型井區域105，第二導電型井區域105鄰近第一導電型井區域103，且在第一導電型井區域103與第二導電型井區域105之間具有井接面107。根據本發明實施例，第一導電型井區域103係為P型井，第二導電型井區域105為N型井。
根據本發明實施例，鰭式場效應電晶體1另包含溝槽130，設於鰭狀結構101中，且在第二導電型井區域105內。根據本發明實施例，於溝槽130內填入有氮化矽填溝層132。根據本發明實施例，於氮化矽填溝層132正上方，設有層間介電層140，例如，矽氧層，但不限於此。根據本發明實施例，溝槽130沿著一第二方向（例如，第1圖中的參考Y軸方向）延伸，其中所述第一方向不平行於所述第二方向。根據本發明實施例，所述第一方向係垂直於所述第二方向。
根據本發明實施例，在溝槽130中的氮化矽填溝層132的厚度t2 大於氧化矽填溝層112的厚度t1 ，其中氮化矽填溝層132的底面132b低於氧化矽填溝層112的底面112b。根據本發明實施例，層間介電層140係直接接觸氮化矽填溝層132。氮化矽填溝層132的頂面132a係低於鰭狀結構101的頂面101a。根據本發明實施例，在氮化矽填溝層132與基底100之間，設有氧化矽襯墊層131。根據本發明另一實施例，如第3圖所示，在溝槽130中的氮化矽填溝層132的厚度t2 可以約略等於氧化矽填溝層112的厚度t1 ，其中氮化矽填溝層132的底面132b同樣低於氧化矽填溝層112的底面112b。
根據本發明實施例，鰭式場效應電晶體1另包含工作閘極20，沿著所述第二方向延伸，跨越過鰭狀結構101。根據本發明實施例，工作閘極20設於溝槽130的第一側S1 ，且工作閘極20與井接面107重疊。根據本發明實施例，工作閘極20係為金屬閘極，可以利用替換金屬閘極（replacement metal gate，RMG）製程形成。例如，工作閘極20可以包含閘極介電層201、金屬層202以及上蓋層203。
舉例來說，閘極介電層201可以包含矽氧層及/或高介電常數材料層，金屬層202可以包含鎢、鈦、氮化鈦、功函數層、阻障層等，而上蓋層203可以包含氮化矽等。根據本發明實施例，在工作閘極20側壁上設置有側壁子204，例如，氮化矽側壁子，但不限於此。根據本發明實施例，側壁子204與層間介電層140直接接觸。
根據本發明實施例，鰭式場效應電晶體1另包含虛設閘極40，沿著所述第二方向延伸，跨越過鰭狀結構101。根據本發明實施例，虛設閘極40係設置在相對第一側S1 的溝槽130的第二側S2 。工作閘極20與虛設閘極40之間係以層間介電層140隔開。根據本發明實施例，層間介電層140的頂面140a與工作閘極20的頂面20a和虛設閘極40的頂面40a齊平。
根據本發明實施例，溝槽130在其第一側S1 的氮化矽填溝層132的頂面132a上方具有第一邊緣E1 以及位於相對的第二側S2 的第二邊緣E2 ，其中工作閘極20覆蓋第一邊緣E1 ，虛設閘極40覆蓋第二邊緣E2 。
同樣的，虛設閘極40係為金屬閘極，可以利用替換金屬閘極（RMG）製程與工作閘極20一起形成。例如，虛設閘極40可以包含閘極介電層401、金屬層402以及上蓋層403。舉例來說，閘極介電層401可以包含矽氧層及/或高介電常數材料層，金屬層402可以包含鎢、鈦、氮化鈦、功函數層、阻障層等，而上蓋層403可以包含氮化矽等。根據本發明實施例，在虛設閘極40側壁上設置有側壁子404，例如，氮化矽側壁子，但不限於此。
根據本發明實施例，本發明鰭式場效應電晶體1的工作閘極20在第一方向上的寬度會大於虛設閘極40在第一方向上的寬度。熟習該項技藝者應理解第1圖與第2圖中的工作閘極20與虛設閘極40僅為例示說明，並未按照等比例繪示。
根據本發明實施例，鰭式場效應電晶體1另包含源極摻雜區104，例如，N型重摻雜區，設於鰭狀結構101中且位於第一導電型井區域103內，其中源極摻雜區104鄰近工作閘極20。根據本發明實施例，鰭式場效應電晶體1另包含汲極摻雜區106，設於鰭狀結構101中且位於第二導電型井區域105內，其中汲極摻雜區106鄰近虛設閘極40。虛設閘極40係設置在溝槽130與汲極摻雜區106之間。於源極摻雜區104與井接面107之間的工作閘極20的正下方構成通道區域200。
根據本發明實施例，源極摻雜區104包含源極磊晶層104a，汲極摻雜區106包含汲極磊晶層106a。根據本發明實施例，源極磊晶層104a包含磷化矽（SiP），汲極磊晶層106a包含磷化矽。源極磊晶層104a係設於第一導電型井區域103內，汲極磊晶層106a係設於第二導電型井區域105內。
根據本發明實施例，在源極摻雜區104上另設有源極接觸插塞62，直接接觸源極磊晶層104a，而在汲極摻雜區106上另設有汲極接觸插塞64，直接接觸汲極磊晶層106a。根據本發明實施例，如第1圖所示，源極接觸插塞62與汲極接觸插塞64可以是槽式（slot）接觸插塞結構，沿著所述第二方向延伸。
本發明的特點在於鰭式場效應電晶體1的鰭狀結構101中設置有溝槽130，並且在溝槽130中填入氮化矽填溝層132，藉由氮化矽填溝層132具有較高的停止能力，使得在進行井區域的離子佈植製程過程中，位於溝槽130正下方區域105a的N型摻質的濃度能夠較其他N型井部分的N型摻質濃度更低一些，如此可以明顯降低操作時發生在此區域附近的電場強度，有效降低元件操作時的Isubmax /Id 電流值，改善元件汲極端的熱載子注入（HCI）問題。
第4圖為依據本發明另一實施例所繪示的具有橫向雙擴散MOS結構的鰭式場效應電晶體的佈局示意圖。如第4圖所示，鰭式場效應電晶體1a可以是相對於一對稱線A呈現左右對稱的佈局結構。在對稱線A的左邊的佈局結構與第1圖中的佈局結構相同，而第4圖中對稱線A的右邊的佈局結構與對稱線A的左邊的佈局結構互為鏡像對稱。
根據本發明實施例，鰭式場效應電晶體1a包含多個鰭狀結構101，沿著第一方向延伸。兩條沿著第二方向延伸的工作閘極20、20’，跨越過鰭狀結構101。兩條沿著第二方向延伸的虛設閘極40、40’，跨越過鰭狀結構101。汲極D位於虛設閘極40、40’之間，設置有接觸插塞64。在鰭式場效應電晶體1a兩端是源極S，分別設有接觸插塞62、62’。在工作閘極20與虛設閘極40之間為沿著第二方向延伸的溝槽130，在工作閘極20’與虛設閘極40’之間為沿著第二方向延伸的溝槽130’。
第5圖至第10圖為依據本發明實施例所繪示的形成半導體元件的方法的側視示意圖，其中，相同的區域、材料層或元件仍沿用相同的符號來表示。為簡化說明，第5圖至第10圖中僅顯示出部分的基底上的結構，例如，僅顯示出兩條鰭狀結構。
如第5圖所示，首先提供基底100，包含鰭狀結構101，被溝渠絕緣區域110圍繞而彼此隔離。根據本發明實施例，基底100係為矽基底，鰭狀結構101為矽鰭狀結構。第5圖顯示出在溝渠絕緣區域110填入氧化矽填溝層112之後，並且完成CMP研磨製程之後的情形，其中在鰭狀結構101正上方的氮化矽墊層PN此時可以被顯露出來，並與周圍的氧化矽填溝層112齊平。鰭狀結構101及溝渠絕緣區域110均沿著第一方向（參考X軸方向）延伸。
如第6圖所示，接著進行微影及蝕刻製程，於鰭狀結構101及溝渠絕緣區域110中形成沿著第二方向（參考Y軸方向）延伸，且橫斷鰭狀結構101的溝槽130。上述的微影及蝕刻製程為周知技藝，因此其細節不另贅述。
值得注意的是，溝槽130可以與其他電路區域內的單擴散斷裂（single diffusion break，SDB）製程同時完成，換言之，溝槽130可以與其他區域的SDB製程利用同一光罩完成，故不需要另外增加光罩。根據本發明實施例，溝槽130的深度深於溝渠絕緣區域110的深度。例如，溝槽130的深度可以是約為1200埃左右，但不限於此。
如第7圖所示，接著進行化學氣相沉積（CVD）製程以及回蝕刻製程，於溝槽130中形成氮化矽填溝層132。此時，鰭狀結構101正上方的氮化矽墊層PN可以被蝕除，且氮化矽填溝層132的頂面係低於鰭狀結構101的頂面。另外，在沉積氮化矽填溝層132之前，可以先在溝槽130的基底100表面上形成氧化矽襯墊層131。氧化矽襯墊層131位於氮化矽填溝層132與基底100之間。
如第8圖所示，接著進行在基底100中形成井區域的離子佈植製程，於基底100中形成第一導電型井區域103，例如，P型井，與第二導電型井區域105，例如，N型井。第二導電型井區域105鄰近第一導電型井區域103，且在第一導電型井區域103與第二導電型井區域105之間具有井接面107。根據本發明實施例，溝槽130被設置在第二導電型井區域105內，且距離井接面107一預定距離。
如前所述，在第8圖中的離子佈植製程步驟中，藉由氮化矽填溝層132具有較高的停止能力（相對於鄰近的氧化矽填溝層112），使得在進行井區域的離子佈植製程過程中，位於溝槽130正下方區域105a的N型摻質的濃度能夠較其他N型井部分的N型摻質濃度更低一些，如此可以明顯降低操作時發生在此區域附近的電場強度，有效降低元件操作時的Isubmax /Id 電流值，改善元件汲極端的熱載子注入（HCI）問題。
如第9圖所示，接著選擇性的針對氧化矽填溝層112進行回蝕刻，蝕刻掉部分的氧化矽填溝層112之後，顯露出部分的鰭狀結構101以及部分的氮化矽填溝層132上部側壁。接著，可以進行氧化製程，使顯露出的鰭狀結構101氧化形成閘極介電層201、401，例如，二氧化矽。
隨後，如第10圖所示，可以進行替換金屬閘極（RMG）製程，在基底100上形成工作閘極20及虛設閘極40，越過鰭狀結構101。上述RMG製程為周知技藝，故其細節不另贅述。舉例來說，可以先形成多晶矽閘極，然後進行磊晶製程，形成源極或汲極的磊晶層，接著將多晶矽閘極以金屬閘極取代。
工作閘極20設於溝槽130的第一側S1 ，且工作閘極20與井接面107重疊，虛設閘極40設置在相對第一側S1 的溝槽130的第二側S2 。工作閘極20與虛設閘極40之間係以層間介電層140隔開，其中工作閘極20與虛設閘極40均金屬閘極，沿著第二方向延伸。溝槽130在第一側的氮化矽填溝層132的頂面132a上方具有第一邊緣E1 以及位於相對的第二側S2 的第二邊緣E2 ，其中工作閘極20覆蓋第一邊緣E1 ，虛設閘極覆蓋第二邊緣E2 。層間介電層140的頂面140a與工作閘極20的頂面20a和虛設閘極40的頂面40a齊平。
根據本發明實施例，在形成工作閘極20與虛設閘極40之前，可以先於鰭狀結構101中形成源極摻雜區104，其中源極摻雜區104鄰近工作閘極20。於鰭狀結構中形成汲極摻雜區106，其中汲極摻雜區106鄰近虛設閘極40，且虛設閘極40係設置在溝槽130與汲極摻雜區106之間。於源極摻雜區104與井接面107之間的工作閘極20的正下方形成通道區域。源極摻雜區104包含源極磊晶層104a，汲極摻雜區106包含汲極磊晶層106a。源極磊晶層104a包含磷化矽，汲極磊晶層106a包含磷化矽。源極磊晶層104a係設於第一導電型井區域103內，汲極磊晶層106a係設於第二導電型井區域105內。 以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。
1、1a:鰭式場效應電晶體 20、20’:工作閘極 20a:頂面 40、40’:虛設閘極 40a:頂面 62、62’:源極接觸插塞 64:汲極接觸插塞 100:基底 101:鰭狀結構 101a:頂面 103:第一導電型井區域 104:源極摻雜區 104a:源極磊晶層 105第二導電型井區域 105a:區域 106:汲極摻雜區 106a:汲極磊晶層 107:井接面 110:溝渠絕緣區域 112:氧化矽填溝層 112a:頂面 112b:底面 130、130’:溝槽 131:氧化矽襯墊層 132:氮化矽填溝層 132a:頂面 132b:底面 140:層間介電層 140a:頂面 200:通道區域 201:閘極介電層 202:金屬層 203:上蓋層 204:側壁子 401:閘極介電層 402:金屬層 403:上蓋層 404:側壁子 A:對稱線 D:汲極 E1:第一邊緣 E2:第二邊緣 S:源極 S1:第一側 S2:第二側 t1、t2:厚度
第1圖為依據本發明一實施例所繪示的具有橫向雙擴散MOS結構的鰭式場效應電晶體的佈局示意圖。 第2圖為沿著第1圖中切線I-I’所示的剖面示意圖。 第3圖為依據本發明另一實施例所繪示的具有橫向雙擴散MOS結構的鰭式場效應電晶體的剖面示意圖。 第4圖為依據本發明另一實施例所繪示的具有橫向雙擴散MOS結構的鰭式場效應電晶體的佈局示意圖。 第5圖至第10圖為依據本發明實施例所繪示的形成半導體元件的方法的側視示意圖。
1:鰭式場效應電晶體
20:工作閘極
20a:頂面
40:虛設閘極
40a:頂面
62:源極接觸插塞
64:汲極接觸插塞
100:基底
101:鰭狀結構
101a:頂面
103:第一導電型井區域
104:源極摻雜區
104a:源極磊晶層
105:第二導電型井區域
105a:區域
106:汲極摻雜區
106a:汲極磊晶層
107:井接面
110:溝渠絕緣區域
112a:頂面
112b:底面
130:溝槽
131:氧化矽襯墊層
132:氮化矽填溝層
132a:頂面
132b:底面
140:層間介電層
140a:頂面
200:通道區域
201:閘極介電層
202:金屬層
203:上蓋層
204:側壁子
401:閘極介電層
402:金屬層
403:上蓋層
404:側壁子
D:汲極
E1:第一邊緣
E2:第二邊緣
S:源極
S1:第一側
S2:第二側
t1、t2:厚度

Claims (32)

  1. 一種半導體元件，包含： 一基底，包含一鰭狀結構，被一溝渠絕緣區域圍繞，其中該鰭狀結構包含一第一導電型井區域與一第二導電型井區域，該第二導電型井區域鄰近該第一導電型井區域，且在該第一導電型井區域與該第二導電型井區域之間具有一井接面； 一溝槽，設於該鰭狀結構中，且在該第二導電型井區域內； 一氮化矽填溝層，設於該溝槽中； 一層間介電層，設於該氮化矽填溝層上； 一工作閘極，越過該鰭狀結構，其中該工作閘極設於該溝槽的一第一側，且該工作閘極與該井接面重疊； 一虛設閘極，越過該鰭狀結構，其中該虛設閘極係設置在相對該第一側的該溝槽的一第二側； 一源極摻雜區，設於該鰭狀結構中，其中該源極摻雜區鄰近該工作閘極；以及 一汲極摻雜區，設於該鰭狀結構中，鄰近該虛設閘極，其中該虛設閘極係設置在該溝槽與該汲極摻雜區之間。
  2. 如請求項1所述的半導體元件，其中該鰭狀結構沿著一第一方向延伸，該溝槽沿著一第二方向延伸，其中該第一方向不平行於該第二方向。
  3. 如請求項2所述的半導體元件，其中該第一方向係垂直於該第二方向。
  4. 如請求項2所述的半導體元件，其中該工作閘極與該虛設閘極之間係以該層間介電層隔開，又其中該工作閘極與該虛設閘極沿著該第二方向延伸。
  5. 如請求項1所述的半導體元件，其中另包含： 一通道區域，位於該源極摻雜區與該井接面之間的該工作閘極的正下方。
  6. 如請求項1所述的半導體元件，其中該溝渠絕緣區域包含氧化矽填溝層，又其中在該溝槽中的該氮化矽填溝層的厚度大於或等於該氧化矽填溝層的厚度，又其中該氮化矽填溝層的底面低於該氧化矽填溝層的底面。
  7. 如請求項1所述的半導體元件，其中該層間介電層係直接接觸該氮化矽填溝層。
  8. 如請求項1所述的半導體元件，其中該氮化矽填溝層的頂面係低於該鰭狀結構的頂面。
  9. 如請求項8所述的半導體元件，其中該溝槽在該第一側的該氮化矽填溝層的頂面上方具有一第一邊緣以及位於相對的該第二側的一第二邊緣，又其中該工作閘極覆蓋該第一邊緣，該虛設閘極覆蓋該第二邊緣。
  10. 如請求項1所述的半導體元件，其中該層間介電層的頂面與該工作閘極的頂面和該虛設閘極的頂面齊平。
  11. 如請求項1所述的半導體元件，其中另包含： 氧化矽襯墊層，位於該氮化矽填溝層與該基底之間。
  12. 如請求項1所述的半導體元件，其中該第一導電型井區域係為P型井，該第二導電型井區域為N型井。
  13. 如請求項1所述的半導體元件，其中該源極摻雜區包含一源極磊晶層，該汲極摻雜區包含一汲極磊晶層。
  14. 如請求項13所述的半導體元件，其中該源極磊晶層包含磷化矽，該汲極磊晶層包含磷化矽。
  15. 如請求項13所述的半導體元件，其中該源極磊晶層係設於該第一導電型井區域內，該汲極磊晶層係設於該第二導電型井區域內。
  16. 如請求項1所述的半導體元件，其中該基底係為矽基底，該鰭狀結構為矽鰭狀結構。
  17. 一種形成半導體元件的方法，包含： 提供一基底，包含一鰭狀結構，被一溝渠絕緣區域圍繞，其中該鰭狀結構包含一第一導電型井區域與一第二導電型井區域，該第二導電型井區域鄰近該第一導電型井區域，且在該第一導電型井區域與該第二導電型井區域之間具有一井接面； 於該鰭狀結構中形成一溝槽，其中該溝槽被設置在該第二導電型井區域內； 於該溝槽中形成一氮化矽填溝層； 於該氮化矽填溝層上形成一層間介電層； 形成一工作閘極，越過該鰭狀結構，其中該工作閘極設於該溝槽的一第一側，且該工作閘極與該井接面重疊； 形成一虛設閘極，越過該鰭狀結構，其中該虛設閘極係設置在相對該第一側的該溝槽的一第二側； 於該鰭狀結構中形成一源極摻雜區，其中該源極摻雜區鄰近該工作閘極；以及 於該鰭狀結構中形成一汲極摻雜區，其中該汲極摻雜區鄰近該虛設閘極，且該虛設閘極係設置在該溝槽與該汲極摻雜區之間。
  18. 如請求項17所述的方法，其中該鰭狀結構沿著一第一方向延伸，該溝槽沿著一第二方向延伸，其中該第一方向不平行於該第二方向。
  19. 如請求項18所述的方法，其中該第一方向係垂直於該第二方向。
  20. 如請求項18所述的方法，其中該工作閘極與該虛設閘極之間係以該層間介電層隔開，又其中該工作閘極與該虛設閘極沿著該第二方向延伸。
  21. 如請求項17所述的方法，其中另包含： 形成一通道區域，位於該源極摻雜區與該井接面之間的該工作閘極的正下方。
  22. 如請求項17所述的方法，其中該溝渠絕緣區域包含氧化矽填溝層，又其中在該溝槽中的該氮化矽填溝層的厚度大於或等於該氧化矽填溝層的厚度，又其中該氮化矽填溝層的底面低於該氧化矽填溝層的底面。
  23. 如請求項17所述的方法，其中該層間介電層矽直接接觸該氮化矽填溝層。
  24. 如請求項17所述的方法，其中該氮化矽填溝層的頂面係低於該鰭狀結構的頂面。
  25. 如請求項24所述的方法，其中該溝槽在該第一側的該氮化矽填溝層的頂面上方具有一第一邊緣以及位於相對的該第二側的一第二邊緣，又其中該工作閘極覆蓋該第一邊緣，該虛設閘極覆蓋該第二邊緣。
  26. 如請求項17所述的方法，其中該層間介電層的頂面與該工作閘極的頂面和該虛設閘極的頂面齊平。
  27. 如請求項17所述的方法，其中另包含： 形成氧化矽襯墊層，位於該氮化矽填溝層與該基底之間。
  28. 如請求項17所述的方法，其中該第一導電型井區域係為P型井，該第二導電型井區域為N型井。
  29. 如請求項17所述的方法，其中該源極摻雜區包含一源極磊晶層，該汲極摻雜區包含一汲極磊晶層。
  30. 如請求項29所述的方法，其中該源極磊晶層包含磷化矽，該汲極磊晶層包含磷化矽。
  31. 如請求項29所述的方法，其中該源極磊晶層係設於該第一導電型井區域內，該汲極磊晶層係設於該第二導電型井區域內。
  32. 如請求項17所述的方法，其中該基底係為矽基底，該鰭狀結構為矽鰭狀結構。
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