TW202013625A - Wiring board - Google Patents

Abstract

A wiring board of the present disclosure includes: an insulating base (2) comprised of a first surface (5) having a mounting region (5a) and a second surface (6) to be connected to an exterior substrate; a power source conductor (3P) comprised of a first planar conductor (3PF) located in a single-sided area (5b) around the mounting region and a first linear conductor (3PL) protruding in a comb-shaped form towards the mounting region; a grounded conductor (3G) comprised of a second planar conductor (3GF) located in an opposite side area (5c) around the mounting region and a second linear conductor (3GL) protruding in a comb-shaped form towards the mounting region such that the second linear conductor (3GL) is alternatingly adjacent to the first linear conductor (3PL); a power source terminal (11) electrically connected to the first planar conductor via a first through conductor located in a first region overlapping the first planar conductor in a top perspective view in the second surface; and a grounded terminal (12) electrically connected to the second planar conductor via a second through conductor located in a second region overlapping the second planar conductor.

Description

Wiring board

The present disclosure relates to a wiring substrate.

In recent years, the development of high-performance electronic devices that perform arithmetic processing at high speeds, such as supercomputers, is advancing. Such an electronic device has, for example, as described in Japanese Patent Laid-Open No. 2003-188305, a plurality of wiring boards on which semiconductor integrated circuit elements are mounted. Since a plurality of wiring boards are mounted in the electronic device, the wiring board needs to be miniaturized. Each wiring board includes: an insulating base, on which a plurality of insulating layers are stacked; a wiring conductor, which includes a power supply conductor and a grounding conductor located on the surface of each insulating layer; and a terminal for connecting semiconductor integrated circuit elements, which is located on the insulating base The uppermost surface of the; and the terminal for external substrate connection are located on the lowermost surface of the insulating substrate.

However, the above-mentioned semiconductor integrated circuit element requires a large amount of power in order to perform arithmetic processing at high speed. A wiring board on which such semiconductor integrated circuit elements are mounted requires excellent power supply characteristics. In order to improve the power supply characteristics, for example, it is considered to provide a large number of power supply conductors and ground conductors as power supply paths in the wiring board. However, since it is necessary to provide a plurality of areas of the power supply path for this, it may become difficult to miniaturize the wiring board.

The wiring board of the present disclosure has an insulating substrate having a first surface and a second surface, and a plurality of insulating layers are stacked. The first surface includes a mounting area on which a semiconductor integrated circuit element is mounted, and the second surface is External substrate connection; power supply conductor, having a first planar conductor, and a plurality of first linear conductors, the first planar conductor system is located on the first surface, in a single-sided area around the mounting area, the plural A first linear conductor system protrudes from the first planar conductor to the mounting area in a comb-tooth state, and is respectively connected to a plurality of power supply electrodes of the semiconductor integrated circuit element; a ground conductor, which is a second planar conductor And a plurality of second linear conductors, the second planar conductor system is located on the first surface opposite to the one-sided region around the mounting area, the plurality of second linear conductor systems and the first wire The conductors alternately and adjacently protrude from the second planar conductor in a comb-tooth state toward the mounting area, and are respectively connected to a plurality of ground electrodes of the semiconductor integrated circuit element; a plurality of power supply terminals are located on the second surface A first region overlapping with the first planar conductor in a perspective view from above, electrically connected to the first planar conductor between the first planar conductor and the first region via first through conductors respectively penetrating through a plurality of insulating layers; and The plurality of grounding terminals are located on the second surface in a second region overlapping with the second planar conductor in a plan view, and between the second planar conductor and the second region via a plurality of insulating layers The two through conductors are electrically connected to the second planar conductor.

According to the wiring board of the present disclosure, it is possible to provide small and excellent power supply characteristics.

1‧‧‧Wiring board

2‧‧‧Insulating substrate

2a‧‧‧Core insulating layer

2b‧‧‧Insulation layer for build-up

3‧‧‧Wiring conductor

3G‧‧‧grounding conductor

3GF‧‧‧second surface conductor

3GL‧‧‧second linear conductor

3P‧‧‧Power conductor

3PF‧‧‧The first planar conductor

3PL‧‧‧First linear conductor

3S‧‧‧Signal conductor

4‧‧‧ solder resist

4a, 4b‧‧‧ opening

5‧‧‧First surface

5a‧‧‧deployment area

5b‧‧‧Single side area

5c‧‧‧The area on the opposite side

6‧‧‧Second surface

7‧‧‧Through hole

8‧‧‧Through hole conductor

9‧‧‧Through hole

10‧‧‧Through hole conductor

11‧‧‧Power terminal

12‧‧‧Ground terminal

13‧‧‧Signal terminal

S‧‧‧ Semiconductor integrated circuit components

FIG. 1 is a schematic cross-sectional view for explaining the wiring board of the present disclosure.

FIG. 2 is a schematic plan (upper surface) view for explaining the wiring board of the present disclosure.

FIG. 3 is a schematic plan (lower surface) view for explaining the wiring board of the present disclosure.

FIG. 4 is a schematic plan (lower surface) view for explaining another embodiment of the wiring board of the present disclosure.

Based on FIGS. 1 to 3, a wiring board 1 according to an embodiment of the present disclosure will be described. FIG. 1 shows a schematic cross-sectional view of the wiring board 1. FIG. 2 shows a schematic plan view of the insulating base 2. FIG. 3 shows a schematic bottom view of the insulating base 2.

The wiring board 1 of an embodiment includes an insulating base 2, a wiring conductor 3 and a solder resist 4. The wiring board 1 has a quadrangular shape in plan view, for example. The thickness of the wiring substrate 1 is set to 0.3 to 1.5 mm, for example.

The insulating base 2 has a first surface 5 including a mounting area 5a on which a semiconductor integrated circuit element S is mounted, and a second surface 6 connected to an external substrate. Furthermore, the first surface 5 has a single-side region 5b and an opposite-side region 5c located around the mounting region 5a. The mounting area 5a has, for example, a square shape. The shape of the mounting region 5a may be a rectangular shape consistent with the shape of the semiconductor integrated circuit element S. The one-sided region 5b and the opposite-side region 5c are arranged via a linear boundary located on the outer peripheral edge of the insulating base 2 from a pair of opposite sides of the mounting region 5a. The one-sided region 5b has, for example, a function of ensuring an arrangement region of the power supply conductor 3P described later. The opposite side region 5c has, for example, a function of ensuring an arrangement area of the grounding conductor 3G described later.

In the wiring substrate 1 according to an embodiment, the insulating base 2 has a build-up insulating layer 2b in which one layer of the core insulating layer 2a and the upper and lower surfaces of the core insulating layer 2a are located on one layer. The core insulating layer 2 a has functions such as ensuring the rigidity of the wiring substrate 1 and maintaining the flatness of the wiring substrate 1. The core insulating layer 2a includes glass cloth and insulating materials such as epoxy resin or bismaleimide triazine resin. Such a core insulating layer 2a is formed flat by, for example, pressing a slab in a semi-cured state in which a glass cloth is impregnated with an epoxy resin while being heated.

The core insulating layer 2a has a plurality of through holes 7 penetrating from the upper surface to the lower surface. The through holes 7 adjacent to each other are arranged with a predetermined adjacent interval. The diameter of the through hole 7 is set to, for example, 100 to 300 μm. The adjacent interval of the through holes 7 is set to, for example, 150 to 350 μm. The through hole 7 is formed by, for example, sandblasting or drilling. The through-hole conductor 8 composed of a part of the wiring conductor 3 is located in the through-hole 7. The through-hole conductor 8 electrically connects the wiring conductors 3 located on the upper and lower surfaces of the core insulating layer 2a to each other.

The build-up insulating layers 2b are respectively located on the upper surface and the lower surface of the core insulating layer 2a. The build-up insulating layer 2b has, for example, a function of ensuring the layout area of the wiring conductor 3 described later. The build-up insulating layer 2b includes insulating particles and insulating materials such as epoxy resin and polyimide resin. Such an insulating layer 2b for build-up is formed, for example, by sticking a resin film including an epoxy resin dispersed with silicon dioxide to the surface of the insulating layer 2a for core under vacuum and thermally curing it. Since the insulating layer 2b for build-up has the above-mentioned function, it is thinner than the insulating layer 2a for core.

The build-up insulating layer 2b has a plurality of via holes 9 with the wiring conductor 3 located on the upper or lower surface of the core insulating layer 2a as the bottom. A through-hole conductor 10 composed of a part of the wiring conductor 3 is located in the through-hole 9. The via-hole conductor 10 electrically connects the wiring conductors 3 located on the upper side and the lower side via the build-up insulating layer 2b. The diameter of the through hole 9 is set to 30 to 100 μm, for example. The through hole 9 is formed by laser processing, for example.

The wiring conductor 3 is located on the upper and lower surfaces of the core insulating layer 2a, the upper or lower surface of the build-up insulating layer 2b, inside the through hole 7 and inside the through hole 9. The wiring conductor 3 includes a power supply conductor 3P, a grounding conductor 3G, and a signal conductor 3S. The power supply conductor 3P, the grounding conductor 3G, and the signal conductor 3S are arranged at predetermined intervals so as not to be short-circuited with each other.

The power supply conductor 3P has a function of supplying power from an external power supply to the semiconductor integrated circuit element S mounted on the upper surface of the wiring board 1, for example. In order to suppress the loss from the external power supply and quickly supply power to the semiconductor integrated circuit element S, the power supply conductor 3P needs to be arranged in a state where it occupies a large area including the vicinity of the semiconductor integrated circuit element S immediately below. That is, the power supply conductor 3P connects the external power supply and the semiconductor integrated circuit element S at a short distance, so that the power supply characteristics can be improved.

In the wiring board 1 of one embodiment, the power supply conductor 3P has a first planar conductor 3PF and a first linear conductor 3PL. The first planar conductor 3PF is located in the one-sided region 5b around the mounting region 5a in the first surface 5 closest to the insulating layer 2b of the semiconductor integrated circuit element S. That is, the first planar conductor 3PF has a planar wide path in the one-sided region 5b where the distance from the semiconductor integrated circuit element S is short. In the wiring board 1 of one embodiment, the first planar conductor 3PF occupies approximately half of the area around the mounting area 5a.

The first planar conductor 3PF is electrically connected to the external power supply via the through-hole conductor 8 and the through-hole conductor 10 that are the first through conductors located directly below it, and the power supply terminal 11 (described in detail later) connected to the electrode of the external substrate. connection. In other words, since the first planar conductor 3PF is connected to the external power source via the wiring conductor 3 located directly below it, the wiring board 1 of the embodiment can also shorten the power supply path directly under the first planar conductor 3PF .

The first linear conductor 3PL is arranged on the first surface 5 closest to the insulating layer 2b of the semiconductor integrated circuit element S from the first planar conductor 3PF in a comb-tooth state toward the mounting region 5a. Each first linear conductor 3PL is connected to a plurality of power supply electrodes of the semiconductor integrated circuit element S. That is, the first linear conductor 3PL is connected to the power supply electrode of the semiconductor integrated circuit element S directly above the mounting region 5a, so that the power supply path can be shortened. Furthermore, since the first planar conductor 3PF having a wide path connected to the external power source by a short path protrudes toward the mounting area 5a, power can be efficiently supplied with low resistance.

The first linear conductor 3PL is electrically connected to an external power supply via a through-hole conductor 8 and a through-hole conductor 10 that are the first through-conductors located directly below it, and a power supply terminal 11 (described in detail later) connected to the electrode of the external substrate. In other words, the first linear conductor 3PL is connected to the external power source via the wiring conductor 3 located directly below it. Therefore, the wiring board 1 of the embodiment can shorten the power supply path even under the first linear conductor 3PL.

The first linear conductor 3PL is arranged alternately adjacent to the second linear conductor 3GL described later in the mounting area 5a. In this way, by arranging the power supply conductor 3P and the ground conductor 3G alternately adjacent to each other, the loop inductance of the wiring board 1 can be suppressed, which is advantageous in that the power supply characteristics can be improved. The width of the first linear conductor 3PL is set to, for example, 50 to 100 μm so that the power supply electrode of the semiconductor integrated circuit element S can be connected.

The grounding conductor 3G has a function of supplying electric power to the semiconductor integrated circuit element S together with the power supply conductor 3P by providing a potential difference between the power supply conductor 3P. Therefore, the grounding conductor 3G also connects the external power supply and the semiconductor integrated circuit element S with a short distance and a wide path as in the power supply conductor 3P, so that the power supply characteristics can be improved. In addition, the grounding conductor 3G has a function of suppressing the parasitic capacitance generated between the adjacent signal conductors 3S and absorbing radiated noise generated from the signal conductor 3S.

In the wiring board 1 of one embodiment, the ground conductor 3G has a second planar conductor 3GF and a second linear conductor 3GL. The second planar conductor 3GF is located on the first surface 5 closest to the insulating layer 2b of the semiconductor integrated circuit element S, on the side region 5c opposite to the side region 5b around the mounting region 5a. That is, the second planar conductor 3GF exists in the state of ensuring the planar wide path in the region 5c on the opposite side where the distance from the semiconductor integrated circuit element S is short. In this example, the second planar conductor 3GF occupies approximately half of the area around the mounting area 5a.

The second planar conductor 3GF is electrically connected to an external power source via a through-hole conductor 8 that is a second through-conductor located directly below it, and a through-hole conductor 10 and a ground terminal 12 (described in detail later) connected to an electrode of an external substrate. In other words, the second planar conductor 3GF is connected to the external power source via the wiring conductor 3 located directly below it. Therefore, the wiring board 1 of the embodiment can shorten the second planar conductor even under the second planar conductor 3GF The path length between 3GF and external power supply.

The second linear conductor 3GL is arranged on the first surface 5 closest to the insulating layer 2b of the semiconductor integrated circuit element S from the second planar conductor 3GF in a comb-tooth state toward the mounting region 5a. Each second linear conductor 3GL is connected to a plurality of ground electrodes of the semiconductor integrated circuit element S. That is, the second linear conductor 3GL is directly connected to the ground electrode of the semiconductor integrated circuit element S in the mounting area 5a, and therefore the path length of the second linear conductor 3GL and the semiconductor integrated circuit element S can be shortened . Furthermore, since the second planar conductor 3GF having a wide path connected to the external power source with a short path protrudes toward the mounting area 5a, power can be efficiently supplied with low resistance.

The second linear conductor 3GL is electrically connected to an external power source via a through-hole conductor 8 and a through-hole conductor 10 which are second through-conductors located directly below it, and a grounding terminal 12 (described in detail later) connected to the electrode of the external substrate. The second linear conductor 3GL is arranged alternately adjacent to the first linear conductor 3PL in the mounting area 5a. The power supply conductor 3P and the ground conductor 3G are arranged alternately adjacent to each other. Therefore, as described above, the loop inductance in the wiring substrate 1 can be suppressed, which is advantageous in that the power supply characteristics can be improved.

The width of the second linear conductor 3GL is set to, for example, 50 to 100 μm so that the ground electrode of the semiconductor integrated circuit element S can be connected. The width of the second linear conductor 3GL is set to the same size as the width of the first linear conductor 3PL.

The signal conductor 3S is arranged in the wiring board 1 of one embodiment from the outer peripheral portion of the mounting region 5a to the one-sided region 5b and from the outer peripheral portion of the mounting region 5a to the opposite region 5c. The signal conductor 3S is connected to the signal electrode of the semiconductor integrated circuit element S at the outer periphery of the mounting region 5a. The signal conductor 3S is electrically connected to the external substrate via the through-hole conductor 8 and the through-hole conductor 10 which are the through conductors and the signal terminal 13 (described in detail later) connected to the electrode of the external substrate in the one-side region 5b or the opposite side region 5c . Thus, the signal conductor 3S has a function of transmitting electrical signals between the semiconductor integrated circuit element S and the external substrate. The width of the signal conductor 3S is set to, for example, 5 to 50 μm.

The wiring conductor 3 has a power supply terminal 11, a ground terminal 12, and a signal terminal 13 connected to the electrodes of the external substrate on the second surface 6 of the insulating base 2. The power supply terminal 11 is located on the second surface 6 in a region overlapping the first planar conductor 3PF and a region overlapping the first linear conductor 3PL in a plan view (these regions are referred to as first regions). The power supply terminal 11 is electrically connected to the first planar conductor 3PF and the first linear conductor 3PL via the through-hole conductor 8 and the through-hole conductor 10, respectively.

In other words, the power supply terminal 11 located on the second surface 6 is located at a portion that can be connected by a short path via the first planar conductor 3PF or the first linear conductor 3PL and the wiring conductor 3 directly above it. Thus, the path between the power supply terminal 11 and the power supply conductor 3P can be shortened. The power supply terminal 11 has, for example, a circular shape, and the diameter is set to 500 to 700 μm, for example. Each power supply terminal 11 is provided in each of the circular power supply terminal conductors independently provided.

The grounding terminal 12 is located on the second surface 6 in a region overlapping the second planar conductor 3GF and a region overlapping the second linear conductor 3GL in a plan view (these regions are referred to as second regions). Furthermore, the grounding terminal 12 is electrically connected to the second planar conductor 3GF and the second linear conductor 3GL via the through-hole conductor 8 and the through-hole conductor 10, respectively.

In other words, the grounding terminal 12 located on the second surface 6 is located at a position that can be connected by a short path directly via the second planar conductor 3GF or the second linear conductor 3GL and the wiring conductor 3. Thus, the path between the ground terminal 12 and the ground conductor 3G can be shortened. The grounding terminal 12 is provided with a plurality of, for example, a circle having a diameter of 500 to 700 μm in one grounding terminal conductor arranged in a planar state at predetermined intervals around the power supply terminal 11 and the signal terminal 13.

The signal terminal 13 is located on the second surface 6 and is electrically connected to the signal conductor 3S located on the first surface 5 via the through-hole conductor 8 and the through-hole conductor 10. The signal terminal 13 has a circular shape, for example, and the diameter is set to 500 to 700 μm, for example. Each signal terminal 13 is provided in each of the circular signal terminal conductors independently provided.

Such a wiring conductor 3 is formed of a highly conductive metal such as copper using wiring forming techniques such as a semi-additive method and a subtractive method.

In the wiring board 1 of an embodiment, as shown in FIG. 1, the solder resist 4 is located on the upper surface of the uppermost build-up insulating layer 2 b and the lowermost layer of the buildup insulating layer 2 b. The solder resist 4 is not an essential structural element in the wiring board of the present disclosure. The solder resist 4 has, for example, a function of protecting the wiring conductor 3 from heat when the semiconductor integrated circuit element S is mounted on the wiring board 1. The solder resist 4 on the upper surface has an opening 4a exposing a part of the first linear conductor 3PL and the second linear conductor 3GL. The solder resist 4 on the lower surface has an opening 4b that exposes the terminal 11 for power supply, the terminal 12 for grounding, and the terminal 13 for signal.

Such a solder resist 4 is obtained by, for example, sticking a film of a photosensitive thermosetting resin such as an acrylic-modified epoxy resin to the upper or lower surface of the build-up insulating layer 2b, and exposing and developing into a predetermined pattern. It is formed by ultraviolet curing and thermal curing.

In this way, the wiring substrate 1 of the present disclosure has the insulating base 2 having the first surface 5 and the second surface 6, the first surface 5 including the mounting area 5a, and the second surface 6 connected to the external substrate; A planar conductor 3PF, which is a single-sided region 5b located around the mounting region 5a; and a power supply conductor 3P, which has a plurality of first linear conductors 3PL, the plurality of first linear conductors 3PL extending from the first plane The conductor 3PF protrudes toward the mounting area 5a in a comb-toothed state. The wiring board 1 of the present disclosure further includes a grounding conductor 3G including: a second planar conductor 3GF, which is located on the opposite side region 5c opposite to the one side region 5b around the mounting region 5a; and a plurality of The second linear conductor 3GL protrudes from the second planar conductor 3GF in a comb-toothed state toward the mounting area 5a so as to be alternately adjacent to the first linear conductor 3PL.

The wiring board 1 of the present disclosure is located in the first region overlapping the first planar conductor 3PF in the second surface 6 in a plan view, and has a first through conductor between the first planar conductor 3PF and the first region A plurality of power supply terminals 11 electrically connected to the first planar conductor 3PF. The wiring board 1 of the present disclosure is also located on the second surface 6 in a second region overlapping the second planar conductor 3GF in a top view, and has a second through conductor between the second planar conductor 3GF and the second region A plurality of ground terminals 12 electrically connected to the second planar conductor 3GF.

As described above, the first planar conductor 3PF exists in the one-sided region 5b having a short distance from the semiconductor integrated circuit element S while ensuring a planar wide path. Furthermore, since the first planar conductor 3PF is connected to the external power supply via the first through conductor and the power supply terminal 11 located directly below it, the path between the first planar conductor 3PF and the power supply terminal 11 can be shortened.

The second planar conductor 3GF exists in the region 5c on the opposite side with a short distance from the semiconductor integrated circuit element S while ensuring a planar and wide path. Furthermore, since the second planar conductor 3GF is connected to the external power source via the second through conductor and the ground terminal 12 located directly below it, the path between the second planar conductor 3GF and the ground terminal 12 can be shortened.

Thus, according to the wiring board 1 of the present disclosure, it is possible to quickly supply power to the semiconductor integrated circuit element S while suppressing the loss from the external power source.

In the mounting area 5a, the first linear conductor 3PL and the second linear conductor 3GL are alternately arranged adjacent to each other. Therefore, the loop inductance of the wiring board 1 can be suppressed, which contributes to improving the power supply characteristics.

The present disclosure is not limited to an example of the above-described embodiment, and various changes can be made as long as they do not deviate from the gist of the present disclosure.

For example, in this example, the case where the boundary between the first planar conductor 3PF and the second planar conductor 3GF is linear, but all or part of the boundary may include a curved portion. In such a case, for example, it is advantageous in that the degree of freedom of the arrangement of the signal conductor 3S can be increased.

In the wiring board 1 of the present disclosure, as shown in FIG. 3, the case where the power supply terminal conductor provided with the power supply terminal 11 has an independent circular shape is shown. However, it may have a plurality of elongated terminal conductors for a power supply including a plurality of circular power supply terminals 11.

FIG. 4 shows a case where the power supply terminal 11 has an oblong shape, for example. Such an oblong terminal 11 a is located on the second surface 6 in a state where circular power terminals 11 adjacent to each other in FIG. 3 are connected to each other with a good conductive metal such as copper, for example. Therefore, the oblong terminal 11a can secure a wider conductor area than the state where the circular power terminals 11 exist. Thereby, more first through conductors connecting the power supply terminal 11 (that is, the oblong terminal 11 a ), the first planar conductor 3PF, and the first linear conductor 3PL can be arranged.

As a result, the resistance value between the external power supply and the semiconductor integrated circuit element can be suppressed, which is advantageous in that the power supply characteristics can be improved.

A part of the grounding terminal 12 is located between the above-mentioned oblong terminals 11a. In this way, since the ground terminal 12 is located between the oblong terminals 11 a, the loop inductance in the wiring board 1 is suppressed, which is advantageous in that the power supply characteristics can be improved.

FIG. 4 shows a state where the longitudinal directions of the respective oblong terminals 11a are parallel to each other. However, it is not limited to this. The length direction of each terminal may be determined so that the first through conductor connecting the oblong terminal 11a and the first planar conductor 3PF may be arranged more.

In FIG. 4, the case where the power supply terminal 11 has an oblong shape is shown. However, from the viewpoint of electrical characteristics and productivity, it may be appropriately set to be rectangular or elliptical.

2‧‧‧Insulating substrate

3G‧‧‧grounding conductor

3GF‧‧‧second surface conductor

3GL‧‧‧second linear conductor

3P‧‧‧Power conductor

3PF‧‧‧The first planar conductor

3PL‧‧‧First linear conductor

3S‧‧‧Signal conductor

5a‧‧‧deployment area

5b‧‧‧Single side area

5c‧‧‧The area on the opposite side

9‧‧‧Through hole

Claims (5)

A wiring board with: The insulating substrate has a first surface and a second surface, and a plurality of insulating layers are stacked, the first surface includes a mounting area on which a semiconductor integrated circuit element is mounted, and the second surface is connected to an external substrate; The power supply conductor includes a first planar conductor and a plurality of first linear conductors, the first planar conductor system is located on a single side area around the mounting area on the first surface, and the plurality of first A linear conductor system protruding from the first planar conductor in a comb-tooth state toward the mounting area, and a plurality of power supply electrodes of the semiconductor integrated circuit element are respectively connected; The grounding conductor has a second planar conductor and a plurality of second linear conductors, and the second planar conductor system is located on the first surface and opposite to the one-sided region around the mounting region The plurality of second linear conductor systems and the first linear conductor alternately and adjacently protrude from the second planar conductor in a comb-tooth state toward the mounting area, and are respectively connected to the plurality of semiconductor integrated circuit elements Electrodes for grounding; A plurality of power supply terminals are located on the second surface in a first region that overlaps with the first planar conductor in a plan view, and the plurality of terminals are respectively penetrated between the first planar conductor and the first region A first through conductor of an insulating layer electrically connected to the first planar conductor; and A plurality of grounding terminals are located on the second surface in a second region overlapping the second planar conductor in a plan view, and the plurality of terminals are respectively penetrated between the second planar conductor and the second region The second through conductors of each insulating layer are electrically connected to the second planar conductor. The wiring board according to item 1 of the patent application scope, in which The first linear conductor and the second linear conductor system have the same width and are arranged at the same interval from each other. The wiring board according to item 1 of the patent application scope, in which The boundary between the first planar conductor and the second planar conductor is linear, and the extension of the boundary divides the mounting area into two. The wiring board according to item 1 of the patent application scope, in which The boundary between the first planar conductor and the second planar conductor includes a curved portion. The wiring board according to item 1 of the patent application scope, in which A plurality of terminal conductors for a power supply in a long shape including a plurality of terminals for a power supply on the second surface, A part of the grounding terminal conductor including a plurality of the grounding terminals is located between the adjacent power supply terminal conductors.

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