JP5354394B2 - Component built-in substrate and manufacturing method thereof - Google Patents

Description

  The present invention relates to a component-embedded substrate that incorporates an electronic component and a method for manufacturing the same.

  In recent years, modularization has built-in electronic components such as active components such as semiconductor devices such as IC chips (bare chips: dies) used in electronic devices and passive components such as capacitors (capacitors), inductors, thermistors, resistors, etc. Is progressing. If such electronic components include the function of a heat source such as a power amplifier or a power source, the electronic components may malfunction due to the heat generated by the electronic components. Heat dissipation measures are an issue.

  As a heat dissipation measure, for example, Patent Document 1 proposes a multilayer wiring board in which a heat dissipation plate 44 is attached to the lowermost layer that is the back surface of the IC chip 20. Patent Document 1 proposes a metal plate such as aluminum or copper, or a ceramic plate as the heat radiating plate 44. By attaching the heat radiating plate 44 so as to cover the IC chip 20 with the bottom portion exposed, an IC chip is provided. 20 stability of operation is aimed at.

  Further, for example, in Patent Document 2, the semiconductor element 100 is disposed in the recess 30 formed on the first substrate 10, and the ground metal surface is disposed such that the bottom surface of the semiconductor element 100 covers the bottom surface. There has been proposed a high-frequency module that is connected to the heat radiating portion 40 formed under the first substrate 10 through 70-a and a through hole 50-a formed in the first substrate 10. Patent Document 2 attempts to improve the heat dissipation of the high-frequency module by using a metal material having a higher thermal conductivity than that of the first substrate 10 as the material of the heat dissipation unit 40.

JP 2002-246757 A JP 2003-1000093 A1

  However, according to the structure described in Patent Document 1, a heat sink is attached below the back surface of the semiconductor element so as to cover the entire back surface (the surface opposite to the surface on which the terminals are formed) of the semiconductor element. Despite being the outermost layer, it is necessary to secure a large space for mounting the heat sink. Therefore, it is difficult to form a member for connecting to the outside or to form a wiring. The bottom could not be used effectively. For this reason, the structure described in Patent Document 1 cannot sufficiently meet the demand for downsizing and high density of the substrate.

  Furthermore, according to the structures described in Patent Documents 1 and 2, since the heat radiating plate is attached to the region outside the region where the semiconductor element is formed, or the heat radiating portion is attached to substantially the same region, It was difficult to radiate heat at a pinpoint, and it was not enough to take appropriate and flexible heat dissipation measures.

  Furthermore, the semiconductor element can also be a generation source that generates electromagnetic waves (noise). However, according to the structure described in Patent Document 2, the bottom surface of the semiconductor element is connected to the substrate via the connection point that is electrically conductive. Since it is connected to the outermost layer, the noise component radiated from the semiconductor element tends to be easily combined with the wiring inside the substrate and the external element. For this reason, according to the structure described in Patent Document 2, it is necessary to separately take measures against noise around the semiconductor element.

  Therefore, the present invention has been made in view of such circumstances, and it is possible to take appropriate and flexible heat dissipation measures and noise measures, as well as components that can be reduced in size and increased in density. An object is to provide a built-in substrate and a manufacturing method thereof.

  In order to solve the above-described problems, the component-embedded substrate according to the present invention is a component-embedded substrate that incorporates electronic components, and is provided on the main surface on which pads for electrical connection with the outside are formed. An electronic component having a film formed thereon, a first insulating layer containing the electronic component, and a first via conductor and a second via conductor provided in the first insulating layer, wherein the first via conductor is a first via The insulating layer penetrates from the passivation film to the outside in the thickness direction, contacts the pad, and is electrically connected to a conductor provided on the outside of the first insulating layer. The first insulating layer penetrates in the thickness direction and contacts the passivation film, and at least the first insulating layer penetrates in the thickness direction so that heat generated by the electronic component can be released to the outside of the component-embedded substrate. .

  In the present invention, since the second via conductor is formed in the first insulating layer, the electronic component is built in the first insulating layer and then formed by providing a through hole (via hole) toward the passivation film. it can. Therefore, in the present invention, it is not necessary to secure a large space when radiating heat, and it is possible to effectively utilize the upper or lower area of the electronic component and to radiate heat from the heat source in a pinpoint manner. Further, in the present invention, even after the electronic component is built in the first insulating layer, the formation position and the number of formation of the second via conductor can be adjusted according to the result of the subsequent inspection, It is possible to take appropriate and highly flexible heat dissipation measures without greatly changing the original design. Here, the electronic component can also be a generation source that generates electromagnetic waves (noise). However, according to the present invention, when the component-embedded substrate is connected to a low impedance potential such as GND or a power plane, the second via is provided. The conductor can be low impedance. For this reason, by forming the second via conductor having a low impedance close to the electronic component that can be the source, radiation noise radiated from the electronic component is reduced, and appropriate and flexible noise countermeasures are taken. It becomes possible. Furthermore, since the second via conductor is formed in the first insulating layer together with the first via conductor, it can be formed as a conductor penetrating the first insulating layer in the same process as the first via conductor. Therefore, the second via conductor and the first via conductor can be formed in the same process, which simplifies the manufacturing process of the component-embedded substrate and contributes to cost reduction.

  The component-embedded substrate of the present invention includes a first electrode provided on the side opposite to the main surface of the electronic component, and a third via conductor that electrically connects the second via conductor and the first electrode inside the component-embedded substrate. It is preferable to comprise.

  In this preferable aspect, since the first electrode is provided on the side opposite to the main surface of the electronic component, the first electrode and the third via conductor are formed in the vicinity of the electronic component. Accordingly, noise generated from the electronic component is absorbed on and in the vicinity of the electronic component, so that the shielding effect can be exhibited in a three-dimensional range. Further, since the first electrode is connected to the second via conductor by the third via conductor, the heat generated by the electronic component can be dissipated to the side opposite to the main surface of the electronic component.

  In the component-embedded substrate of the present invention, the first electrode is preferably formed so as to cover at least a part of the electronic component in plan view.

  In this preferable aspect, since the first electrode is formed so as to cover at least a part of the electronic component, a shielding effect for absorbing noise can be exhibited not only in the thickness direction but also in the plane direction. Furthermore, according to the present invention, heat generated from the electronic component can be radiated in the surface direction.

  When a plurality of electronic components are provided in the first insulating layer, the first electrode is preferably formed so as to cover at least a part of the plurality of electronic components in a plan view.

  In this preferable aspect, even after a plurality of electronic components are built in the first insulating layer, appropriate and flexible heat dissipation measures and noise measures can be taken. Further, since the first electrode is formed so as to cover at least a part of the plurality of electronic components in a plan view, heat generated from the plurality of electronic components can be dissipated in the surface direction, and noise can be generated. Absorbing shielding effect can be exhibited in the surface direction.

  The method for manufacturing a component-embedded substrate according to the present invention is a method for manufacturing a component-embedded substrate in which an electronic component is embedded, and a passivation film is formed on a main surface on which pads for electrical connection with the outside are formed. A first step of forming a first insulating layer containing an electronic component; and a first via conductor that penetrates the first insulating layer in the thickness direction from the passivation film to the outside and contacts the pad. A second step of forming a second via conductor that penetrates the first insulating layer in the thickness direction from the passivation film to the outside and contacts the passivation film; and a first via conductor that is formed in the first insulating layer. A third step of electrically connecting to a conductor provided on the outside of the semiconductor device, and a fourth step of configuring the second via conductor so that heat generated by the electronic component can be released to the outside of the component-embedded substrate. Prepare.

  In the present invention, since the second via conductor is formed in the first insulating layer, it is possible to provide a through hole (via hole) toward the passivation film after the electronic component is built in the first insulating layer. Therefore, in the present invention, it is not necessary to secure a large space when radiating heat, and it is possible to effectively utilize the upper or lower area of the electronic component and to radiate heat from the heat source in a pinpoint manner. Further, in the present invention, even after the electronic component is incorporated in the first insulating layer, the formation position and the number of formation of the second via conductor can be adjusted according to the result of the subsequent inspection. Therefore, it is possible to take an appropriate and highly flexible heat dissipation measure without greatly changing the original design. Here, the electronic component can also be a generation source that generates electromagnetic waves (noise). However, according to the present invention, when the component-embedded substrate is connected to a low impedance potential such as GND or a power plane, the second via is provided. The conductor can be low impedance. For this reason, by forming the second via conductor, which has a low impedance, close to the electronic component that can be a generation source, radiation noise radiated from the electronic component is reduced, and appropriate noise countermeasures can be taken. Become. Furthermore, since the second via conductor is formed in the first insulating layer together with the first via conductor in the same process, the manufacturing process of the component built-in substrate can be simplified and the cost can be reduced.

  In the method for manufacturing a component built-in board according to the present invention, the first electrode provided on the side opposite to the main surface of the electronic component is formed inside the component built-in substrate, and the second via conductor and the first electrode are electrically connected. It is preferable to include a fifth step of forming a third via conductor to be connected.

  In this preferable aspect, since the first electrode is provided on the side opposite to the main surface of the electronic component, the first electrode and the third via conductor can be formed on and in the vicinity of the electronic component. Therefore, noise generated from the electronic component is absorbed on and in the vicinity of the electronic component, so that the shielding effect can be exhibited in a three-dimensional range. In a preferred embodiment, since the third via conductor that electrically connects the second via conductor and the first electrode is formed, the heat generated by the electronic component can be dissipated to the side opposite to the main surface of the electronic component. it can.

  In the component-embedded substrate manufacturing method of the present invention, in the fifth step, the first electrode is preferably formed so as to cover at least a part of the electronic component in plan view.

  In this preferable aspect, since the first electrode is formed so as to cover at least a part of the electronic component, a shielding effect for absorbing noise can be exhibited in the surface direction. Furthermore, according to the present invention, heat generated from the electronic component can be radiated in the surface direction.

  According to the component-embedded substrate and the method of manufacturing the same according to the present invention, it is possible to take appropriate and flexible heat dissipation measures and noise measures, so that the component-embedded substrate can be further downsized and densified.

1 is a cross-sectional view schematically showing a component built-in substrate according to a first embodiment of the present invention. It is a top view which follows the II-II line of FIG. It is process drawing which shows an example of the procedure which manufactures the component built-in board | substrate of 1st Embodiment. It is process drawing which shows an example of the procedure which manufactures the component built-in board | substrate of 1st Embodiment. It is process drawing which shows an example of the procedure which manufactures the component built-in board | substrate of 1st Embodiment. It is process drawing which shows an example of the procedure which manufactures the component built-in board | substrate of 1st Embodiment. It is process drawing which shows an example of the procedure which manufactures the component built-in board | substrate of 1st Embodiment. It is process drawing which shows an example of the procedure which manufactures the component built-in board | substrate of 1st Embodiment. It is process drawing which shows an example of the procedure which manufactures the component built-in board | substrate of 1st Embodiment. It is sectional drawing which shows schematically the component built-in board | substrate by 2nd Embodiment of this invention. It is a top view which follows the XI-XI line of FIG. It is sectional drawing which shows schematically the component built-in board | substrate by 3rd Embodiment of this invention. It is a top view which follows the XIII-XIII line | wire of FIG.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the drawings, the same elements are denoted by the same reference numerals, and redundant description is omitted. Further, the positional relationship such as up, down, left and right is based on the positional relationship shown in the drawings unless otherwise specified. Furthermore, the dimensional ratios in the drawings are not limited to the illustrated ratios. Further, the following embodiments are exemplifications for explaining the present invention, and are not intended to limit the present invention only to the embodiments. Furthermore, the present invention can be variously modified without departing from the gist thereof.

(First embodiment)
FIG. 1 is a sectional view schematically showing a component-embedded substrate 1 according to a first embodiment of the present invention, and FIG. 2 is a plan view taken along the line II-II in FIG.

  In the component-embedded substrate 1, the conductor layer 11, the insulating layer 15, the conductor layer 21, the insulating layer 25 (first insulating layer), the conductor layer 31, the insulating layer 35, and the conductor layer 41 are sequentially laminated from the bottom layer. The electronic component 71 is embedded in a predetermined position inside the insulating layer 25.

  On the conductor layer 41, for example, electronic components (not shown) such as inductors and capacitors are placed. On the other hand, an insulating layer (not shown) is further formed on the conductor layer 11 in order to protect the conductor layer 11. In this insulating layer, a signal terminal for transmitting a signal between the component-embedded substrate 1 and the outside, a power supply terminal connected to a low impedance potential, and a ground terminal are formed.

  Each conductor layer 11, 21, 31, 41 has wiring layers 12, 22, 32, 42 and low impedance layers 13, 23. The wiring layers 12, 22, 32, and 42 are formed with wiring patterns (signal lines) for transmitting and receiving signals, and are connected to the above-described predetermined potentials on the input side and output side. The low impedance layers 13 and 23 are connected to a ground and a power plane. The low-impedance layers 13 and 23 have an impedance that suppresses noise emission and / or noise conduction and stabilizes the operation of the electronic circuit.

  The electronic component 71 is formed so as to operate with a predetermined function, and a passivation film 74 is formed on the main surface on which the pad 73 for electrical connection with the outside is formed, avoiding the pad 73. Yes. The electronic component 71 in the present embodiment has, for example, a circuit surface 72 on the main surface side where the pads 73 are formed. The passivation film 74 is formed so as to cover the circuit surface 72 so as to protect the circuit surface 72 and prevent the circuit surface 72 from conducting to the outside. As described above, the electronic component 71 is installed in a so-called face-down manner in which the pad 73 is disposed toward the lowermost layer side of the component-embedded substrate 1.

  Via conductors 26, 27, and 28 are formed in the insulating layer 25. The via conductor 26 (first via conductor) penetrates the insulating layer 25 outward from the passivation film 74 in the thickness direction, contacts the pad 73, and is provided on the outer side of the insulating layer 25 (wiring layer). 22, 12, 32 and via conductors 28, 16, 36). The via conductor 27 (second via conductor) penetrates the insulating layer 25 in the thickness direction, contacts the passivation film 74 and penetrates at least the insulating layer 25 in the thickness direction. The heat generated by the component 71 can be released.

  The conductor layer 21 is formed between the insulating layer 25 and the insulating layer 15 and includes a wiring layer 22 having a wiring pattern and a low impedance layer 23 connected to the ground or a power plane. The wiring layer 22 is formed so as to be connected to the pad 73 through the via conductor 26. The low impedance layer 23 is formed between the insulating layer 15 and the insulating layer 25, and is formed to be connected to the passivation film 74 by the via conductor 27. The low impedance layer 23 is formed so as to cover at least a part of the electronic component 71 in the surface direction, and is preferably formed to be larger than the planar area of the via conductor 27. Further, the low impedance layer 23 is a part of the low impedance conductors 27, 23, and 17. The low impedance conductors 27, 23, and 17 are included in the via conductor 27 connected to the passivation film 74 and the conductor layer 21 provided inside the component-embedded substrate 1, and the low impedance layer 23 connected to the ground or power plane. And a via conductor 17 that electrically connects the low impedance layer 23 and the low impedance layer 13.

  The conductor layer 11 includes a wiring layer 12 having a wiring pattern and a low impedance layer 13 connected to the ground or the power plane. The wiring layer 12 is connected to a predetermined potential on the input side or output side, or is formed so as to be connected to the other wiring layers 22, 32, 42 via the via conductors 16, 28, 36. The low impedance layer 13 is included in the conductor layer 11 facing the outside of the component-embedded substrate 1 and is connected to the ground and the power plane. The low impedance layer 13 is formed outside the passivation film 74, and is formed so as to be connected to the passivation film 74 by the low impedance conductors 27, 23, and 17. Further, the low impedance layer 13 is formed so as to cover at least a part of the electronic component in the plane direction, and is preferably formed to be larger than the planar area of the low impedance layer 23.

  The structure in which the electronic component 71 is connected inside the component-embedded substrate 1 is as follows.

  That is, the pad 73 of the electronic component 71 is formed in the insulating layer 25 and connected to the pad 73 to connect to the outside (input side or output side) having a predetermined potential. To the wiring layer 22, and further to the wiring layer 12 through the via conductor 16 formed in the insulating layer 15. Further, the pad 73 of the electronic component 71 is formed in the insulating layer 25 in order to connect to an electronic component (not shown) formed in the outermost layer, and is connected to the wiring layer 32 via the via conductor 28. Further, it is connected to the wiring layer 42 through a via conductor 36 formed in the insulating layer 35.

  On the other hand, the passivation film 74 of the electronic component 71 is formed on the insulating layer 25 in order to be connected to the outside having a ground or a power plane, and is low through the via conductor 27 connected to the passivation film 74. It is connected to the impedance layer 23 and further connected to the low impedance layer 13 through the via conductor 17.

  FIG. 2 shows an arrangement relationship between the via conductor 27 and the electronic component 71 connected to the ground or the power supply plane when viewed in plan from the insulating layer 15 side. In the drawing, a passivation film 74 is formed to avoid six pads 73 formed so as to face the end of the electronic component 71. The three via conductors 27 connected to the ground and the power supply plane are formed in the formation region where the passivation film 74 is formed. The low impedance layer 23 is formed so as to cover at least a part of the electronic component 71. In the figure, via conductors 26 connected to a predetermined potential are formed on six pads 73. In the figure, the pads 73 are provided at six locations and the via conductors 27 are provided at three locations, but the number of the pads 73 is not particularly limited.

  As the passivation film 74, a known film can be used as appropriate as long as the circuit surface 72 does not conduct to the outside, and is not particularly limited. Specific examples of the passivation film 74 include insulating resins such as polyimide and epoxy, and insulating films such as a silicon nitride film and a silicon oxide film.

  The thickness of the passivation film 74 can be set as appropriate, and is not particularly limited. For example, the thickness of the passivation film 74 between the via conductor 27 and the circuit surface 72 is 0.2 w / m · When using K, it is preferable that it is 1-10 micrometers.

  3 to 9 are process diagrams (process flow diagrams) showing an example of a procedure for manufacturing the component-embedded substrate.

  First, a core substrate 51 made of a double-sided copper-clad glass epoxy, etc., on which a wiring layer 32, an insulating layer 35, and a conductor layer 41 are patterned using a known method is prepared (FIG. 3).

  Next, a resin film to be the uncured insulating layer 25 is laminated on the core substrate 51 (FIG. 4).

  Then, after placing the electronic component 71 on the uncured insulating layer 25 in a so-called face-up state (FIG. 5), the electronic component 71 is covered with the uncured resin again and covered in the insulating layer 25. And the insulating layer 25 is cured. Next, after removing unnecessary portions of the conductor layer 21 formed by a method such as laminating a copper foil on the insulating layer 25 by etching or the like, via holes H1, H2 and H3 are formed, and the pad 73 of the electronic component 71 is exposed at the bottom of the via hole H1, and a part of the passivation film 74 of the electronic component 71 is exposed at the bottom of the via hole H2, or a wiring layer is formed at the bottom of the via hole H3. 32 is exposed (FIG. 6).

  Then, copper or the like is plated on the conductor layer 21 in which the via holes H1, H2, and H3 are formed, and the conductor layer 21 and the pad 73, the conductor layer 21 and the passivation film 74, and the conductor layer 21 and the wiring layer 32 are formed. They are connected by via conductors 26, 27, and 28, respectively (FIG. 7).

  Next, the conductor layer 21 is patterned by etching or the like to form a wiring pattern of the wiring layer 22 (FIG. 7). As a result, the wiring layer 22 and the pad 73 are connected by the via conductor 26, the low impedance layer 23 and the passivation film 74 are connected by the via conductor 27, and the wiring layer 22 and the wiring layer 32 are connected by the via conductor 28. (FIG. 7).

  Next, an uncured insulating layer 15 is formed on the conductor layer 21 and the insulating layer 25. Further, a copper foil or the like is laminated thereon to form the conductor layer 11, and then the entire substrate is pressed by hot pressing or the like. And heat cure.

  Thereafter, unnecessary portions of the conductor layer 11 and the conductor layer 41 which are the outermost layers in that state are removed by etching or the like, and via holes H4, H5 and H6 are formed, and wiring layers are respectively formed at the bottoms thereof. 22, the low impedance 23 and the wiring layer 32 are exposed (FIG. 8).

  Next, copper plating is performed on the inside of the via holes H4, H5, and H6, and on the conductor layer 11 and the conductor layer 41, so that the conductor layer 11 and the wiring layer 22, the conductor layer 11 and the low impedance layer 23, and the wiring layer 32 and the conductor layer 41 are connected to the via conductors 16, 17, and 36, respectively. Next, the conductor layer 11 and the conductor layer 41 are patterned by etching or the like to form a wiring pattern (FIG. 9). As a result, the wiring layer 12 and the wiring layer 22 are connected by the via conductor 16, the low impedance layer 13 and the low impedance layer 23 are connected by the via conductor 17, and the wiring layer 32 and the wiring layer 42 are connected by the via conductor 36. Is done.

  Then, a component-embedded substrate 1 is obtained by forming a solder resist at an appropriate portion (FIG. 9). The component built-in module is completed by placing and connecting an electronic component (not shown) such as an inductor on the component built-in substrate 1 upside down (FIG. 1).

  In the present embodiment, the low impedance layers 13 and 23 are formed on the conductor layer 11 and the conductor layer 21. May be. In this embodiment, the conductor layers 11, 21, 31, and 41 are formed in four layers. However, the number of layers is not limited to this, and the number of layers may be changed as appropriate according to the thickness, performance, wiring route, and the like of the substrate. it can. Depending on the number of conductor layers, the number of insulating layers can be changed as appropriate.

  The “component built-in substrate” includes not only individual substrates (individual pieces, individual items) that are unit substrates in which electronic components are incorporated, but also collective substrates (work boards, worksheets) having a plurality of individual substrates. It is a concept. In addition, the type of “electronic component” is not particularly limited, and is, for example, an active component such as a semiconductor device such as an IC chip used in a normal electronic device, more specifically, for example, a CPU (Central Processing Unit). And digital ICs with a very high operating frequency such as digital signal processors (DSPs), analog ICs such as high-frequency amplifiers, antenna switches, and high-frequency oscillation circuits, and passive components such as inductors, capacitors, resistors, and thermistors. . Further, the “signal line” formed by the wiring pattern is a concept including a signal line that operates at high speed, a transmission line that transmits electromagnetic waves, such as a microstrip line and a coplanar waveguide.

  In the present embodiment, since the via conductor 27 is formed in the insulating layer 25, the electronic component 71 is built in the insulating layer 25, and then the through hole is formed in the formation region of the passivation film 74 toward the passivation film 74. (Via hole) It can be formed by providing H2. Therefore, in the present embodiment, it is not necessary to secure a large space when radiating heat, the area above or below the electronic component 71 can be effectively used, and heat can be radiated from the heat source at a pinpoint. . Further, in the present embodiment, even after the electronic component 71 is built in the insulating layer 25, the formation position and the number of the via conductors 27 can be adjusted according to the result of the subsequent inspection. It is possible to take heat dissipation measures with a higher degree of freedom without greatly changing the original design. Furthermore, since the via conductor 27 is formed in the insulating layer 25 together with the via conductor 26 in contact with the pad, it can be formed in the same process as the via conductor 26 as described above. Therefore, since the via conductor 27 can be formed in the same process as the via conductor 26 so as to be in contact with the passivation film 74, the manufacturing process of the component-embedded substrate 1 can be simplified and the cost can be reduced. Furthermore, for example, when the electronic component 71 operates, the electronic component 71 can be a generation source that generates electromagnetic waves (noise). However, in this embodiment, the component-embedded substrate 1 is a GND or a power plane. Because it is connected to a low impedance potential, the second via conductor can be low impedance. For this reason, by forming the low-impedance via conductor 27 close to the electronic component 71 that can be a generation source, radiation noise radiated from the electronic component 71 is reduced, and an appropriate and flexible noise countermeasure can be taken. It is possible to take.

  In the present embodiment, the low impedance layer 13 is connected to the passivation film 74 by the low impedance conductors 27, 23, and 17 and is formed outside the component-embedded substrate 1. Can function as. Furthermore, after the electronic component 71 is built in the insulating layer 25, the low impedance conductors 27, 23, and 17 can be provided toward the passivation film 74. Therefore, even after the electronic component 71 is built in the insulating layer 25, the shape and size of the low impedance layer 13 or the formation of the low impedance conductors 27, 23, 17 depending on the result of the subsequent inspection. Since the position and the number of formations can be adjusted, it is possible to take heat dissipation measures and noise measures with a higher degree of freedom without greatly changing the initial design. In particular, since the low impedance layer 13 is formed larger (wider) in the plane direction than the low impedance layer 23, the range including the ground and the power plane has a spread in the plane direction. Thereby, in the low impedance layer 13 located in the outermost layer of the conductor layer, heat can be reliably released to the outside, and propagation of noise radiation to the outside can be avoided.

  Furthermore, since the low impedance layer 23 is formed in the vicinity of the electronic component 71 in the thickness direction as compared with the low impedance layer 13, noise can be absorbed in the vicinity of the electronic component 71 and the shielding effect is improved. Can be achieved. Further, since the low impedance layer 23 is formed between the insulating layer 25 and the insulating layer 15 and is connected to the passivation film 74 by the via conductor 27, the heat generated by the electronic component 71 is generated by the low impedance layer 23. And 13 can be released.

(Second Embodiment)
FIG. 10 is a cross-sectional view schematically showing the component built-in substrate 2 according to the second embodiment of the present invention. FIG. 11 is a plan view taken along line XI-XI in FIG. In the component-embedded substrate 2, as shown in the drawing, the conductor layer 31 includes a wiring layer 32 </ b> A and a low impedance layer 33 (first electrode), and a via conductor connecting the low impedance layer 33 and the low impedance layer 23. Except that the (third via conductor) 29 is formed, it is configured in the same manner as the component-embedded substrate 1 of the first embodiment described above.

  The conductor layer 31 is provided on the opposite side of the conductor layer 21 with the electronic component 71 interposed therebetween, and includes a wiring layer 32A having a wiring pattern and a low impedance layer 33 connected to the ground or the power plane.

  The low impedance layer 33 is electrically connected to the low impedance layer 23 through a via conductor 29 provided so as to penetrate the insulating layer 25. The via conductor 29 is provided in the vicinity of the electronic component 71 and is preferably formed on the periphery of the electronic component 71 from the viewpoint of heat dissipation countermeasures and noise countermeasures. In FIG. 11, the via conductors 29 are formed on the periphery of the electronic component 71 (in FIG. 10, only two are shown on the front side of the page, but two are also formed on the back side of the page). This is an example. Although two via conductors 29 are formed in FIG. 11, the number is not particularly limited, and two or more via conductors 29 may be formed.

  The low impedance layer 33 is formed so as to cover at least a part of the electronic component in plan view. In the present embodiment, the low impedance layer 33 is formed so as to cover the surface of the electronic component 71 opposite to the circuit surface 72. Yes.

  In the present embodiment, the low impedance layer 33 is formed so as to cover at least a part of the electronic component in plan view, but the low impedance layer 23 or the low impedance layers 23 and 33 are electronic in plan view. It may be formed so as to cover at least a part of the component. In this case, at least a part of the electronic component is covered with the low impedance layer above and below in the thickness direction. The effect can be maximized.

  In this embodiment, not only has the effect of the first embodiment, but the low impedance 33 is provided on the opposite side of the conductor layer 21 with the electronic component 71 interposed therebetween. It is built in the insulating layer 25 so as to be sandwiched between the low impedance layers 33, and the via conductor 29 is formed in the vicinity of the electronic component 71. Therefore, noise generated from the electronic component 71 is absorbed above and below the electronic component 71 and in the vicinity thereof, so that the shielding effect can be exhibited in a three-dimensional range. Further, since the low impedance layer 33 is connected to the low impedance layer 23 by the via conductor 29, the heat that could not be dispersed by the low impedance layer 23 can be reliably dispersed by the low impedance layer 33.

  In the present embodiment, since at least one of the low impedance layer 23 and the low impedance layer 33 is formed so as to cover at least a part of the electronic component 71, a shielding effect for absorbing noise is provided only in the thickness direction. Instead, it can be exhibited in the surface direction. Furthermore, according to the present embodiment, heat generated from the electronic component can be dispersed in the surface direction.

(Third embodiment)
FIG. 12 is a cross-sectional view schematically showing a component built-in substrate 3 according to the third embodiment of the present invention. 13 is a plan view taken along line XIII-XIII in FIG. It is sectional drawing which shows roughly the component built-in board | substrate 3 by 3rd Embodiment of this invention. The component-embedded substrate 3 shown in FIG. 12 is a schematic cross-sectional view, and therefore has the same configuration as the component-embedded substrate 1 of the first embodiment, and the insulating layers 15 and 35 and the via conductors 16, 17, The detailed configuration of 36 is omitted.

  As shown in the figure, the component-embedded substrate 3 includes a plurality of electronic components 71 and 75 built in the insulating layer 25. The conductor layer 31A includes a wiring layer 32A and a low impedance layer 34 (first impedance) instead of the low impedance layer 33. 1 electrode), the low impedance layer 24 is formed so as to overlap with the low impedance layer 34 in plan view, and via conductors 29A and 29B (third via conductors) connecting the low impedance layer 24 and the low impedance layer 34 are formed. ) Is configured in the same manner as the component-embedded substrate 1 of the first embodiment described above.

  A plurality of electronic components 71 and 75 are provided, and at least one of the low impedance layer 24 and the low impedance layer 34 is formed so as to commonly cover at least a part of the plurality of electronic components 71 and 75 in a plan view. Yes.

  The low impedance layer 24 is provided so as to overlap with the low impedance layer 34 in plan view, and is formed so as to be connected to the low impedance layer 34 via the via conductors 27, 29 </ b> A, 29 </ b> B. The low impedance layer 24 is formed so as to cover the via conductors 27, 29 </ b> A, and 29 </ b> B, but is not limited to the shape shown in the figure. For example, the electronic components 71 and 75 are commonly used like the low impedance layer 34. You may form so that it may cover.

  In the present embodiment, the via conductor 29 </ b> B is formed between the electronic component 71 and the electronic component 75, but the via conductor between the electronic component 71 and the electronic component 75 according to the function and type of the electronic component. 29B may be adjusted. For example, when the electronic component 71 and the electronic component 75 are the same type (or the same function) as an analog device, for example, a via conductor 29B is formed between the electronic component 71 and the electronic component 75. Thus, the ground and the power plane may be shared. On the other hand, when the electronic component 71 and the electronic component 75 are different types (or different functions) such as an analog device and a digital device, for example, the via conductor 29B is provided between the electronic component 71 and the electronic component 75. The ground and the power plane may be separated without forming the gate.

  In any case, the position and number of via conductors 29B formed between the electronic component 71 and the electronic component 75 may be adjusted in the same process as the process of forming the other via conductors 28 and 29A. It can contribute to cost reduction. In any case, since part of the electronic components 71 and 75 are formed so as to be covered with the low impedance layers 24 and 34, it is possible to take measures against heat dissipation and noise.

  According to the present embodiment, not only has the effects of the first and second embodiments, but also after having incorporated a plurality of electronic components 71 and 75 in the insulating layer 25, a flexible heat dissipation measure and Noise countermeasures can be taken. Further, since at least one of the low impedance layer 24 and the low impedance layer 34 is formed so as to cover at least a part of the plurality of electronic components in a plan view, heat generated from the plurality of electronic components 71 and 75 is generated. While being able to disperse | distribute in a surface direction, the shielding effect which absorbs a noise can be exhibited in a surface direction.

  As described above, the component-embedded substrate of the present invention can take a heat dissipation measure with a degree of freedom and can be further reduced in size. It can be widely and effectively used for various devices and the like that are particularly required to be miniaturized and improved in performance, and for production and production thereof.

  1, 2, 3... Component built-in substrate, 11, 21, 21A, 31, 31A, 41... Conductor layer, 12, 22, 32, 32A, 42 .. Wiring layer, 13, 23, 24, 33, 34. Layer, 15, 25, 35 ... insulating layer, 16, 17, 26, 27, 28, 29, 29A, 29B, 36 ... via conductor, 51 ... core substrate, 71, 75 ... electronic component, 72 ... circuit surface, 73 ... Pad, 74 ... Passivation film.

Claims (5)

A component-embedded board containing electronic components,
An electronic component in which a passivation film is formed on a main surface on which pads for electrical connection with the outside are formed;
A first insulating layer containing the electronic component;
A first via conductor and a second via conductor provided in the first insulating layer,
The first via conductor penetrates the first insulating layer in the thickness direction from the passivation film to the outside, contacts the pad, and is electrically connected to a conductor provided outside the first insulating layer. Connected to
The second via conductor penetrates the first insulating layer in the thickness direction from the passivation film to the outside, contacts the passivation film, and releases heat generated by the electronic component to the outside of the component-embedded substrate. Configured as possible ,
A first electrode provided on the opposite side of the main surface of the electronic component inside the component-embedded substrate;
A component-embedded board comprising a third via conductor that electrically connects the second via conductor and the first electrode . The component built-in substrate according to claim 1 , wherein the one electrode is formed so as to cover at least a part of the electronic component in a plan view. The electronic component is provided with a plurality on the first insulating layer, the first electrode, according to claim 2 which is formed so as to cover the common at least a portion of said plurality of electronic components in a plan view Component built-in board. A method of manufacturing a component-embedded substrate that incorporates electronic components,
A first step of forming a first insulating layer containing an electronic component in which a passivation film is formed on a main surface on which a pad for electrical connection with the outside is formed;
A first via conductor is formed in the first insulating layer so as to penetrate the first insulating layer in the thickness direction from the passivation film to the outside, and contact the pad. The first insulating layer is formed on the passivation film. A second step of forming a second via conductor that penetrates in the thickness direction from the outer side to the outer side and contacts the passivation film;
A third step of electrically connecting the first via conductor to a conductor provided outside the first insulating layer;
A fourth step of configuring the second via conductor so that heat generated by the electronic component can be released to the outside of the component-embedded substrate ;
A first electrode provided on the side opposite to the main surface of the electronic component is formed inside the component-embedded substrate, and a third via conductor that electrically connects the second via conductor and the first electrode is formed. A method for manufacturing a component-embedded substrate comprising a fifth step of forming . 5. The component built-in board manufacturing method according to claim 4 , wherein in the fifth step, the first electrode is formed so as to cover at least a part of the electronic component in a plan view.

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