JP2005333079A - Semiconductor device packaging structure - Google Patents

Semiconductor device packaging structure Download PDF

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JP2005333079A
JP2005333079A JP2004152315A JP2004152315A JP2005333079A JP 2005333079 A JP2005333079 A JP 2005333079A JP 2004152315 A JP2004152315 A JP 2004152315A JP 2004152315 A JP2004152315 A JP 2004152315A JP 2005333079 A JP2005333079 A JP 2005333079A
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semiconductor element
heat
mounting structure
element mounting
semiconductor
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Yutaka Kumano
豊 熊野
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Panasonic Holdings Corp
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Matsushita Electric Industrial Co Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144Gold (Au) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item

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  • Structure Of Printed Boards (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Cooling Or The Like Of Electrical Apparatus (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device packaging structure which can efficiently dissipate heat generated from a plurality of semiconductor devices. <P>SOLUTION: The semiconductor device packaging structure (1) comprises electrical insulating substrates (11a-11c), semiconductor devices (12-14) disposed on a surface (111c) of the electrical insulating substrate (11c) and between the electrical insulating substrates (11a-11c), heat dissipating parts (15a-15d) provided on the surfaces (111a, 111c) of the electrical insulating substrates (11a, 11c), and heat conducting paths (16a-16d) for connecting the heat dissipating parts (15a-15d) and the semiconductor devices (12-14). <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

本発明は、半導体パッケージや半導体素子が実装された多層配線基板等の半導体素子実装構造体に関し、特に複数の半導体素子が実装された半導体素子実装構造体に関する。   The present invention relates to a semiconductor element mounting structure such as a semiconductor package or a multilayer wiring board on which semiconductor elements are mounted, and more particularly to a semiconductor element mounting structure on which a plurality of semiconductor elements are mounted.

携帯電話、ノートパソコン、デジタルカメラ等に代表されるモバイル電子機器は、その小型化、薄型化及び軽量化が急速に進んでいる。更に高性能化や多機能化に対する要求も著しく、その要求に対応するため半導体素子及び回路部品の小型化やこれらの電子部品の高密度実装技術は飛躍的に進展している。また、近年の半導体素子分野では、微細加工技術の進展に伴い、半導体素子実装構造体の高集積化や大規模化が進んでいるため、半導体素子実装構造体の消費電力が大きくなり、発生する多量の熱に対する放熱処理が重要な課題となってきている。   Mobile electronic devices typified by mobile phones, notebook computers, digital cameras, and the like are rapidly becoming smaller, thinner and lighter. Further, there are significant demands for higher performance and multi-functionality, and miniaturization of semiconductor elements and circuit parts and high-density mounting technology for these electronic parts are making rapid progress in order to meet such demands. Further, in the recent semiconductor element field, with the progress of microfabrication technology, the semiconductor element mounting structure has been highly integrated and scaled up, so that the power consumption of the semiconductor element mounting structure has increased and is generated. Heat dissipation treatment for a large amount of heat has become an important issue.

従来、半導体素子実装構造体の放熱手段としては、半導体素子実装構造体の表面に高熱伝導性金属で形成された放熱フィンを取り付けて半導体素子が発生する熱を放熱する手段が知られている。   Conventionally, as a heat dissipation means for a semiconductor element mounting structure, a means for dissipating heat generated by the semiconductor element by attaching a heat dissipation fin formed of a highly thermally conductive metal to the surface of the semiconductor element mounting structure is known.

図8に、前述した放熱手段を備えた従来の半導体素子実装構造体の断面図を示す。図8に示すように、半導体素子実装構造体100は、基材101と、基材101の開口部101aに配置された半導体素子102と、基材101の図中上面に熱伝導性接着剤103を介して設けられたアルミニウム等からなるヒートシンク104とを備えている。これにより、半導体素子102から発生する熱がヒートシンク104に伝導され、ヒートシンク104に設けられた放熱フィン104aから空気中に放散される。また、半導体素子実装構造体100は、半導体素子102の回路形成面102aに設けられた電極(図示せず)が、金線105によって基材101に形成された内部配線106aへワイヤーボンディングされ、ビア導体107を介して基材101に形成された外部配線106bに接続されている。更に、外部配線106b上にはバンプ108が形成されている。   FIG. 8 shows a cross-sectional view of a conventional semiconductor element mounting structure provided with the above-described heat radiation means. As shown in FIG. 8, the semiconductor element mounting structure 100 includes a base material 101, a semiconductor element 102 disposed in the opening 101 a of the base material 101, and a heat conductive adhesive 103 on the upper surface of the base material 101 in the drawing. And a heat sink 104 made of aluminum or the like provided through the. As a result, heat generated from the semiconductor element 102 is conducted to the heat sink 104 and is dissipated into the air from the radiation fins 104 a provided on the heat sink 104. Further, in the semiconductor element mounting structure 100, an electrode (not shown) provided on the circuit formation surface 102a of the semiconductor element 102 is wire-bonded to the internal wiring 106a formed on the base material 101 by the gold wire 105, and the via The conductor 107 is connected to the external wiring 106 b formed on the base material 101. Further, bumps 108 are formed on the external wiring 106b.

しかし、このようなヒートシンクによる放熱手段を備えた半導体素子実装構造体は実装空間が大きくならざるを得ず、Multi Chip Package(MCP)やSystem In Package(SIP)等への適用が困難となってきている。このような課題を解決するために、ヒートシンクを用いることなく小型電子機器への搭載が可能な放熱構造を備えた半導体素子実装構造体が最近提案されてきている(特許文献1及び特許文献2参照)。   However, the semiconductor device mounting structure provided with the heat dissipation means using such a heat sink has to have a large mounting space, which makes it difficult to apply to Multi Chip Package (MCP) and System In Package (SIP). ing. In order to solve such a problem, a semiconductor element mounting structure having a heat dissipation structure that can be mounted on a small electronic device without using a heat sink has been recently proposed (see Patent Document 1 and Patent Document 2). ).

上記特許文献に記載の放熱手段は、いずれも回路形成面を上向きにして半導体素子を基板上に実装し、その基板内に形成した放熱用スルーホールに充填した金属材料を半導体素子の回路形成面と反対側の面に接続して、半導体素子からの発生熱を基板外へ放熱させている。   All of the heat dissipation means described in the above-mentioned patent documents are such that a semiconductor element is mounted on a substrate with the circuit formation surface facing upward, and a metal material filled in a heat dissipation through hole formed in the substrate is a circuit formation surface of the semiconductor element. The heat generated from the semiconductor element is dissipated out of the substrate.

また、上記提案と異なる放熱構造を備えた半導体素子実装構造体が特許文献3に提案されている。この放熱手段は、基板上にフェイスダウンで実装された半導体ベアチップの回路形成面にグラウンド電極を設け、このグラウンド電極から絶縁樹脂を介して基板上に形成された放熱用突起電極へ半導体素子からの発生熱を伝達させ、放熱させている。
特開平9−199823号公報 特開平10−313071号公報 特開平10−65072号公報
Further, Patent Document 3 proposes a semiconductor element mounting structure having a heat dissipation structure different from the above proposal. This heat radiation means is provided with a ground electrode on a circuit forming surface of a semiconductor bare chip mounted face down on a substrate, and from the ground electrode to a heat radiation projecting electrode formed on the substrate via an insulating resin. The generated heat is transferred to dissipate heat.
JP-A-9-199823 Japanese Patent Laid-Open No. 10-313071 JP-A-10-65072

しかしながら、上記従来の技術はいずれも単一の半導体素子をパッケージ、又は配線基板上に実装したものについての放熱構造であり、MCPや多層配線基板等の表面又は内部に実装された複数の半導体素子から発生する大容量の熱を放熱させるには未だ不充分である。そのため、半導体素子同士の発生熱による素子特性の劣化等を防ぐのは従来の技術では困難であった。   However, each of the above conventional techniques is a heat dissipation structure for a single semiconductor element mounted on a package or wiring board, and a plurality of semiconductor elements mounted on the surface or inside of an MCP, a multilayer wiring board, etc. Is still not enough to dissipate the large amount of heat generated from the heat. For this reason, it has been difficult for conventional techniques to prevent deterioration of element characteristics due to heat generated between semiconductor elements.

本発明は上記課題を解決するものであり、複数の半導体素子から発生する熱を効率良く放熱させることができる半導体素子実装構造体を提供する。   The present invention solves the above problems and provides a semiconductor element mounting structure capable of efficiently dissipating heat generated from a plurality of semiconductor elements.

本発明の半導体素子実装構造体は、複数層の電気絶縁基材と、前記電気絶縁基材表面及び前記電気絶縁基材間の少なくともいずれか一方に配置された複数の半導体素子とを含む半導体素子実装構造体であって、前記半導体素子は、それぞれ前記電気絶縁基材の厚み方向に互いに対面しない部分を有しており、最外層に配置された前記電気絶縁性基材のうち少なくともいずれか一方の表面に設けられた放熱部と、前記電気絶縁基材内に設けられ、前記放熱部と前記半導体素子とを接続する導熱路とを更に備えていることを特徴とする。   A semiconductor element mounting structure according to the present invention includes a semiconductor element including a plurality of layers of an electrically insulating substrate, and a plurality of semiconductor elements disposed on at least one of the surface of the electrically insulating substrate and the electrically insulating substrate. A mounting structure, wherein each of the semiconductor elements has portions that do not face each other in the thickness direction of the electrically insulating substrate, and is at least one of the electrically insulating substrates disposed in the outermost layer. And a heat conducting path provided in the electrically insulating base material and connecting the heat radiating part and the semiconductor element.

本発明の半導体素子実装構造体によれば、半導体素子が、それぞれ電気絶縁基材の厚み方向に互いに対面しない部分を有しており、更に、最外層に配置された電気絶縁性基材のうち少なくともいずれか一方の表面に設けられた放熱部と、この放熱部と半導体素子とを接続する導熱路とを備えているため、半導体素子同士の発生熱による素子特性の劣化を防ぐことができる上、複数の半導体素子から発生する熱を放熱部から効率良く放熱させることができる。   According to the semiconductor element mounting structure of the present invention, each of the semiconductor elements has portions that do not face each other in the thickness direction of the electrically insulating substrate, and further, among the electrically insulating substrates disposed in the outermost layer Since it has a heat radiating portion provided on at least one surface and a heat conduction path connecting the heat radiating portion and the semiconductor element, deterioration of element characteristics due to heat generated between the semiconductor elements can be prevented. The heat generated from the plurality of semiconductor elements can be efficiently radiated from the heat radiating portion.

本発明の半導体素子実装構造体は、複数層の電気絶縁基材と、電気絶縁基材表面及び電気絶縁基材間の少なくともいずれか一方に配置された複数の半導体素子とを含む。本発明の半導体素子実装構造体に使用できる電気絶縁基材は特に限定されないが、熱硬化性樹脂と無機質フィラーとの混合材料等が好適に使用できる。また、電気絶縁基材の厚みは、10〜600μmが好ましい。また、半導体素子の実装は、公知の方法により行うことができ、例えばフリップチップ接合方式等により実装することができる。なお、本発明の半導体素子実装構造体の作製は、例えば特開2002−261449号公報等に開示されている方法を用いることにより可能である。   The semiconductor element mounting structure of the present invention includes a plurality of layers of electrically insulating base materials and a plurality of semiconductor elements disposed on at least one of the surface of the electrically insulating base material and the electrically insulating base material. Although the electrical insulation base material which can be used for the semiconductor element mounting structure of the present invention is not particularly limited, a mixed material of a thermosetting resin and an inorganic filler can be suitably used. The thickness of the electrically insulating substrate is preferably 10 to 600 μm. The semiconductor element can be mounted by a known method, for example, by a flip chip bonding method. The semiconductor element mounting structure of the present invention can be produced by using a method disclosed in, for example, Japanese Patent Application Laid-Open No. 2002-261449.

そして、本発明の半導体素子実装構造体は、前記構成に加え、最外層に配置された電気絶縁性基材のうち少なくともいずれか一方の表面に設けられた放熱部と、前記電気絶縁基材内に設けられ、放熱部と半導体素子とを接続する導熱路とを更に備えている。これにより、複数の半導体素子から発生する熱を放熱部から効率良く放熱させることができる。本発明の半導体素子実装構造体に使用できる放熱部は、例えば電気絶縁基材の表面に熱プレス等により設けられた銅箔等の金属箔を、公知のフォトリソグラフィー法によりパターニングすることにより形成することができる。また、導熱路は、例えば電気絶縁基材の所望の位置にレーザー等により貫通孔を形成し、この貫通孔内に金属粉末及び熱伝導性樹脂(例えば、エポキシ樹脂等)を含む熱伝導性ペーストを充填した後、熱プレス等により加熱、加圧処理して形成することができる。また、熱伝導性ペーストの替わりに、例えば貫通孔内を金属めっき処理して導熱路を形成してもよい。   And in addition to the said structure, the semiconductor element mounting structure of this invention is a heat-radiation part provided in the surface of at least any one among the electrically insulating base materials arrange | positioned in the outermost layer, The said electrically insulating base material inside And a heat conducting path connecting the heat radiating portion and the semiconductor element. Thereby, the heat generated from the plurality of semiconductor elements can be efficiently radiated from the heat radiating portion. The heat dissipating part that can be used for the semiconductor element mounting structure of the present invention is formed by patterning a metal foil such as a copper foil provided on the surface of the electrically insulating base material by hot pressing or the like by a known photolithography method. be able to. In addition, the heat conduction path has a through hole formed by a laser or the like at a desired position of the electrically insulating substrate, for example, and a heat conductive paste containing a metal powder and a heat conductive resin (for example, an epoxy resin) in the through hole. After being filled, it can be formed by heating and pressurizing with a hot press or the like. Further, instead of the heat conductive paste, for example, the inside of the through hole may be subjected to metal plating to form a heat conduction path.

また、本発明の半導体素子実装構造体は、半導体素子が、それぞれ電気絶縁基材の厚み方向に互いに対面しない部分を有している。これにより、半導体素子同士の発生熱による素子特性の劣化を防ぐことができる。また、本発明の半導体素子実装構造体は、電気絶縁基材のうち、複数の半導体素子間の少なくとも一部に位置する箇所に、空気層を形成するための溝が設けられていることが好ましい。この構成によっても半導体素子同士の発生熱による素子特性の劣化を防ぐことができる。なお、前記溝はレーザー等の加工手段により形成することができる。また、素子特性の劣化をより効果的に防ぐには、前記溝の幅を10μm以上とすることが好ましい。更に、前記構成において、前記溝は、複数の半導体素子間に位置する電気絶縁基材の構成材料を分断していることが好ましい。これにより、半導体素子同士の発生熱による素子特性の劣化を効果的に防ぐことができる。   Moreover, the semiconductor element mounting structure of the present invention has a portion where the semiconductor elements do not face each other in the thickness direction of the electrically insulating substrate. Thereby, deterioration of element characteristics due to heat generated between the semiconductor elements can be prevented. In the semiconductor element mounting structure of the present invention, it is preferable that a groove for forming an air layer is provided at a position located at least in a part between the plurality of semiconductor elements in the electrically insulating substrate. . Also with this configuration, it is possible to prevent deterioration of element characteristics due to heat generated between semiconductor elements. The groove can be formed by a processing means such as a laser. In order to more effectively prevent deterioration of device characteristics, the width of the groove is preferably 10 μm or more. Furthermore, in the said structure, it is preferable that the said groove | channel has divided | segmented the structural material of the electrically insulating base material located between several semiconductor elements. Thereby, deterioration of element characteristics due to heat generated between the semiconductor elements can be effectively prevented.

また、本発明の半導体素子実装構造体は、電気絶縁基材間に導熱路と接続する放熱材層を更に備え、この放熱材層が、接続される半導体素子毎に分断されていることが好ましい。これにより、半導体素子から発生する熱をより効率良く放熱させることができる上、半導体素子同士の発生熱による素子特性の劣化を防ぐことができる。また、前記構成において、放熱材層は、グラウンド層及び電源層の少なくともいずれか一方であることが好ましい。これにより、大きな面積を有するグラウンド層又は電源層を利用して、半導体素子から発生する熱をより効率良く放熱させることができる。なお、グラウンド層及び電源層は、前述した放熱部の形成方法と同様の方法により形成できる。   In addition, the semiconductor element mounting structure of the present invention further includes a heat radiating material layer connected to the heat conducting path between the electrically insulating base materials, and the heat radiating material layer is preferably divided for each semiconductor element to be connected. . Thereby, heat generated from the semiconductor elements can be radiated more efficiently, and deterioration of element characteristics due to heat generated between the semiconductor elements can be prevented. Moreover, in the said structure, it is preferable that a heat radiating material layer is at least any one of a ground layer and a power supply layer. Thereby, the heat generated from the semiconductor element can be radiated more efficiently using the ground layer or the power supply layer having a large area. The ground layer and the power supply layer can be formed by a method similar to the method for forming the heat dissipation portion described above.

また、本発明の半導体素子実装構造体は、半導体素子と導熱路とが、集熱パッド、導熱用バンプ及び集熱ランドのうち少なくとも一つを介して接続されていることが好ましい。これにより、半導体素子から発生する熱をより効率良く放熱させることができる。なお、集熱パッドは、例えば、電気信号が通らない箇所に放熱用に設けた半導体素子上のパッドであり、導熱用バンプは、例えば、集熱パッド上に形成した突起電極であり、集熱ランドは、例えば、導熱用バンプが搭載される基板上のランドである。また、前記構成において、半導体素子と導熱路とが、集熱パッド及び集熱ランドの少なくともいずれか一方を介して接続されている場合は、集熱パッド又は集熱ランドの接続面が凹凸形状に形成されていることが好ましい。これにより、接続面の面積を増大させることができるため、半導体素子から発生する熱をより効率良く放熱させることができる。   In the semiconductor element mounting structure of the present invention, the semiconductor element and the heat conducting path are preferably connected via at least one of a heat collecting pad, a heat conducting bump, and a heat collecting land. Thereby, the heat generated from the semiconductor element can be radiated more efficiently. The heat collection pad is, for example, a pad on a semiconductor element provided for heat dissipation in a place where an electrical signal does not pass, and the heat conduction bump is, for example, a protruding electrode formed on the heat collection pad, and the heat collection pad The land is, for example, a land on the substrate on which the heat conduction bump is mounted. Further, in the above configuration, when the semiconductor element and the heat conducting path are connected via at least one of the heat collecting pad and the heat collecting land, the connection surface of the heat collecting pad or the heat collecting land has an uneven shape. Preferably it is formed. Thereby, since the area of a connection surface can be increased, the heat generated from the semiconductor element can be radiated more efficiently.

また、本発明の半導体素子実装構造体は、半導体素子が、それぞれ複数の導熱路により放熱部に接続されていることが好ましい。これにより、半導体素子から発生する熱をより効率良く放熱させることができる。また、本発明の半導体素子実装構造体は、半導体素子が、それぞれ1つ以上の集熱パッド、複数の導熱用バンプ及び1つ以上の集熱ランドを介して1つ以上の導熱路により放熱部に接続されていることが好ましい。これにより、半導体素子から発生する熱をより一層効率良く放熱させることができる。   Moreover, in the semiconductor element mounting structure of the present invention, it is preferable that the semiconductor elements are connected to the heat radiating portion through a plurality of heat conduction paths. Thereby, the heat generated from the semiconductor element can be radiated more efficiently. Further, the semiconductor element mounting structure of the present invention is a semiconductor element in which the semiconductor element is radiated by one or more heat conducting paths through one or more heat collecting pads, a plurality of heat conducting bumps, and one or more heat collecting lands. It is preferable that it is connected to. Thereby, the heat generated from the semiconductor element can be dissipated more efficiently.

また、本発明の半導体素子実装構造体において、それぞれの半導体素子の単位時間あたりの発熱量が異なる場合は、半導体素子の発熱量が大きくなるにつれ、半導体素子に接続される導熱路の熱抵抗が小さくなるように構成されていることが好ましい。これにより、半導体素子から発生する熱をより効率良く放熱させることができる。なお、導熱路の熱抵抗は、10℃/W以下が好ましい。   Further, in the semiconductor element mounting structure of the present invention, if the heat generation amount per unit time of each semiconductor element is different, the heat resistance of the heat conduction path connected to the semiconductor element increases as the heat generation amount of the semiconductor element increases. It is preferable to be configured to be small. Thereby, the heat generated from the semiconductor element can be radiated more efficiently. The heat resistance of the heat conduction path is preferably 10 ° C./W or less.

また、本発明の半導体素子実装構造体において、それぞれの半導体素子の単位時間あたりの発熱量が異なる場合は、半導体素子の発熱量が大きくなるにつれ、半導体素子に接続される導熱路の幅方向の断面積が大きくなるように構成されていることが好ましい。これにより、半導体素子から発生する熱をより効率良く放熱させることができる。   Further, in the semiconductor element mounting structure of the present invention, when the calorific value per unit time of each semiconductor element is different, as the calorific value of the semiconductor element increases, the width of the heat conduction path connected to the semiconductor element increases. It is preferable that the cross-sectional area is large. Thereby, the heat generated from the semiconductor element can be radiated more efficiently.

また、本発明の半導体素子実装構造体は、半導体素子が実装された多層配線基板であることが好ましい。これにより、他の電子部品、例えばコンデンサ等を高密度に実装しても、半導体素子から発生する熱による電子部品の性能劣化等を抑えることができる。以下、本発明の実施形態を詳細に説明する。   The semiconductor element mounting structure of the present invention is preferably a multilayer wiring board on which a semiconductor element is mounted. As a result, even when other electronic components, such as capacitors, are mounted with high density, it is possible to suppress deterioration in performance of the electronic components due to heat generated from the semiconductor element. Hereinafter, embodiments of the present invention will be described in detail.

[第1実施形態]
まず、本発明の第1実施形態について適宜図面を参照して説明する。参照する図1は、本発明の第1実施形態に係る半導体素子実装構造体の断面図である。
[First Embodiment]
First, a first embodiment of the present invention will be described with reference to the drawings as appropriate. FIG. 1 to be referred to is a cross-sectional view of the semiconductor element mounting structure according to the first embodiment of the present invention.

図1に示すように、第1実施形態に係る半導体素子実装構造体1は、電気絶縁基材11a,11b,11cと、電気絶縁基材11a,11b間に配置された半導体素子12と、電気絶縁基材11b,11c間に配置された半導体素子13と、電気絶縁基材11cの表面111cに配置された半導体素子14と、電気絶縁基材11aの表面111aに設けられた放熱部15a,15b,15cと、電気絶縁基材11cの表面111cに設けられた放熱部15dと、電気絶縁基材11a〜11c内に設けられ、放熱部15a〜15cと半導体素子12〜14とを接続する導熱路16a,16b,16cと、放熱部15dと半導体素子12とを接続する導熱路16dとを備えている。これにより、半導体素子12〜14から発生する熱を放熱部15a〜15dから効率良く放熱させることができる。また、本実施形態において、半導体素子12が、半導体素子13,14に比べ単位時間あたりの発熱量が大きい場合でも、半導体素子12の上下面に接続される2つの導熱路16a,16dを介して、発生する熱を効率良く放熱させることができる。また、導熱路16dは、図1に示すように、半導体素子12の発熱量に応じてその幅方向の断面積を導熱路16a〜16cより大きくしてもよい。   As shown in FIG. 1, the semiconductor element mounting structure 1 according to the first embodiment includes an electrical insulating base material 11a, 11b, 11c, a semiconductor element 12 disposed between the electrical insulating base materials 11a, 11b, and an electrical The semiconductor element 13 disposed between the insulating base materials 11b and 11c, the semiconductor element 14 disposed on the surface 111c of the electrical insulating base material 11c, and the heat radiation portions 15a and 15b provided on the surface 111a of the electrical insulating base material 11a. , 15c, a heat radiating portion 15d provided on the surface 111c of the electrical insulating base material 11c, and a heat conduction path provided in the electrical insulating base materials 11a to 11c and connecting the heat radiating portions 15a to 15c and the semiconductor elements 12 to 14 16a, 16b, and 16c, and a heat conducting path 16d that connects the heat radiating portion 15d and the semiconductor element 12 are provided. Thereby, the heat which generate | occur | produces from the semiconductor elements 12-14 can be efficiently radiated from the thermal radiation parts 15a-15d. Further, in the present embodiment, even when the semiconductor element 12 generates a larger amount of heat per unit time than the semiconductor elements 13 and 14, the two heat conduction paths 16 a and 16 d connected to the upper and lower surfaces of the semiconductor element 12 are used. The generated heat can be efficiently dissipated. Further, as shown in FIG. 1, the heat conduction path 16 d may have a cross-sectional area in the width direction larger than that of the heat conduction paths 16 a to 16 c in accordance with the heat generation amount of the semiconductor element 12.

また、図1に示すように、半導体素子13,14は、それぞれ電気絶縁基材11cの厚み方向に互いに対面しない部分13a,14aを有しており、更に、半導体素子12は、半導体素子13,14に面していない。これにより、半導体素子12〜14で発生した熱は、導熱路16a〜16dを優先的に通過し放熱されるため、例えば半導体素子13で発生した熱が半導体素子14に伝播し、半導体素子14の温度が上昇することによる素子特性の劣化を防ぐことができる。なお、導熱路16a〜16dは、半導体素子12〜14の表面温度が最も高い部分に接続されていることが好ましい。   As shown in FIG. 1, the semiconductor elements 13 and 14 have portions 13 a and 14 a that do not face each other in the thickness direction of the electrical insulating base material 11 c, respectively. It does not face 14. As a result, the heat generated in the semiconductor elements 12 to 14 is preferentially passed through the heat conducting paths 16a to 16d to be dissipated. For example, the heat generated in the semiconductor element 13 propagates to the semiconductor element 14 and It is possible to prevent deterioration of element characteristics due to temperature rise. In addition, it is preferable that the heat-conduction paths 16a-16d are connected to the part with the highest surface temperature of the semiconductor elements 12-14.

[第2実施形態]
次に、本発明の第2実施形態について適宜図面を参照して説明する。参照する図2は、本発明の第2実施形態に係る半導体素子実装構造体の部分断面拡大図である。なお、図2において、前述した第1実施形態に係る半導体素子実装構造体1と同一構成のものには同一の符号を付し、その説明は省略する。
[Second Embodiment]
Next, a second embodiment of the present invention will be described with reference to the drawings as appropriate. FIG. 2 to be referred to is a partial cross-sectional enlarged view of a semiconductor element mounting structure according to the second embodiment of the present invention. In FIG. 2, the same components as those of the semiconductor element mounting structure 1 according to the first embodiment described above are denoted by the same reference numerals, and the description thereof is omitted.

図2に示すように、半導体素子実装構造体20は、半導体素子12が、集熱パッド21、導熱用バンプ22及び集熱ランド23を介して導熱路16aに接続されている。また、半導体素子12と電気絶縁基材11aとは、複数の電極24、パッド25及びランド26を介して接続されている。その他は、半導体素子実装構造体1(図1参照)と同様に形成されている。この構成により、半導体素子12から発生する熱を効率よく放熱させることができる。なお、本実施形態では、半導体素子12と導熱路16aとの接続箇所のみが、集熱パッド21、導熱用バンプ22及び集熱ランド23を介して接続されている例について説明したが、その他の半導体素子と導熱路との接続箇所も、同様に接続されていてもよい。   As shown in FIG. 2, in the semiconductor element mounting structure 20, the semiconductor element 12 is connected to the heat conducting path 16 a through the heat collecting pads 21, the heat conducting bumps 22, and the heat collecting lands 23. Further, the semiconductor element 12 and the electrically insulating base material 11 a are connected via a plurality of electrodes 24, pads 25 and lands 26. Others are formed in the same manner as the semiconductor element mounting structure 1 (see FIG. 1). With this configuration, heat generated from the semiconductor element 12 can be efficiently radiated. In the present embodiment, an example in which only the connection portion between the semiconductor element 12 and the heat conducting path 16a is connected via the heat collecting pad 21, the heat conducting bump 22, and the heat collecting land 23 has been described. The connection location between the semiconductor element and the heat conduction path may be similarly connected.

[第3実施形態]
次に、本発明の第3実施形態について適宜図面を参照して説明する。参照する図3は、本発明の第3実施形態に係る半導体素子実装構造体の部分断面拡大図である。なお、図3において、前述した第2実施形態に係る半導体素子実装構造体20と同一構成のものには同一の符号を付し、その説明は省略する。
[Third Embodiment]
Next, a third embodiment of the present invention will be described with reference to the drawings as appropriate. FIG. 3 to be referred to is an enlarged partial cross-sectional view of the semiconductor element mounting structure according to the third embodiment of the present invention. In FIG. 3, the same components as those of the semiconductor element mounting structure 20 according to the second embodiment described above are denoted by the same reference numerals, and the description thereof is omitted.

図3に示すように、半導体素子実装構造体30は、半導体素子12が、集熱パッド21、2つの導熱用バンプ22及び集熱ランド23を介して2つの導熱路16aに接続されている。その他は、半導体素子実装構造体20(図2参照)と同様に形成されている。この構成により、半導体素子12から発生する熱を更に効率よく放熱させることができる。なお、半導体素子12から発生する熱を効果的に放熱させるために、半導体素子12と放熱部15dとを接続する導熱路16dを複数設けてもよい。   As shown in FIG. 3, in the semiconductor element mounting structure 30, the semiconductor element 12 is connected to the two heat conducting paths 16 a via the heat collecting pads 21, the two heat conducting bumps 22 and the heat collecting lands 23. Others are formed in the same manner as the semiconductor element mounting structure 20 (see FIG. 2). With this configuration, the heat generated from the semiconductor element 12 can be radiated more efficiently. In order to effectively dissipate the heat generated from the semiconductor element 12, a plurality of heat conduction paths 16d connecting the semiconductor element 12 and the heat radiating portion 15d may be provided.

[第4実施形態]
次に、本発明の第4実施形態について適宜図面を参照して説明する。参照する図4は、本発明の第4実施形態に係る半導体素子実装構造体の断面図である。なお、図4において、前述した第1実施形態に係る半導体素子実装構造体1と同一構成のものには同一の符号を付し、その説明は省略する。
[Fourth Embodiment]
Next, a fourth embodiment of the present invention will be described with reference to the drawings as appropriate. FIG. 4 to be referred to is a cross-sectional view of the semiconductor element mounting structure according to the fourth embodiment of the present invention. In FIG. 4, the same components as those of the semiconductor element mounting structure 1 according to the first embodiment described above are denoted by the same reference numerals, and the description thereof is omitted.

図4に示すように、半導体素子実装構造体40は、電気絶縁基材11b,11cのうち、半導体素子12,13間に位置する箇所に、空気層41を形成するための溝42が設けられている。その他の構成は、半導体素子実装構造体1(図1参照)と同様に形成されている。溝42は、図4に示す断面図において、半導体素子12の角部12bと半導体素子13の角部13bとを結ぶ線分と、半導体素子12の角部12cと半導体素子13の角部13cとを結ぶ線分との間に位置する電気絶縁基材11b,11cの構成材料を分断している。また、半導体素子12,13と溝42との位置関係を示す概略上面図である図5において、溝42は、半導体素子12の角部12dと半導体素子13の角部13dとを結ぶ線分と、半導体素子12の角部12eと半導体素子13の角部13eとを結ぶ線分との間に位置する電気絶縁基材11b,11cの構成材料を分断している。これにより、半導体素子12と半導体素子13との間の熱伝導が、溝42内の空気層41で遮断され、半導体素子12,13同士の発生熱による素子特性の劣化を効果的に防ぐことができる。   As shown in FIG. 4, the semiconductor element mounting structure 40 is provided with a groove 42 for forming an air layer 41 at a position located between the semiconductor elements 12 and 13 in the electrically insulating base materials 11 b and 11 c. ing. Other configurations are the same as those of the semiconductor element mounting structure 1 (see FIG. 1). In the cross-sectional view shown in FIG. 4, the groove 42 includes a line segment connecting the corner 12 b of the semiconductor element 12 and the corner 13 b of the semiconductor element 13, the corner 12 c of the semiconductor element 12, and the corner 13 c of the semiconductor element 13. The constituent materials of the electrically insulating base materials 11b and 11c located between the line segments connecting the two are separated. In FIG. 5, which is a schematic top view showing the positional relationship between the semiconductor elements 12, 13 and the groove 42, the groove 42 is a line segment connecting the corner portion 12 d of the semiconductor element 12 and the corner portion 13 d of the semiconductor element 13. The constituent materials of the electrical insulating base materials 11b and 11c located between the line segment connecting the corner portion 12e of the semiconductor element 12 and the corner portion 13e of the semiconductor element 13 are divided. As a result, heat conduction between the semiconductor element 12 and the semiconductor element 13 is blocked by the air layer 41 in the groove 42, and deterioration of element characteristics due to heat generated between the semiconductor elements 12 and 13 can be effectively prevented. it can.

[第5実施形態]
次に、本発明の第5実施形態について図面を参照して説明する。参照する図6は、本発明の第5実施形態に係る半導体素子実装構造体の断面図である。なお、図6において、前述した第1実施形態に係る半導体素子実装構造体1と同一構成のものには同一の符号を付し、その説明は省略する。
[Fifth Embodiment]
Next, a fifth embodiment of the present invention will be described with reference to the drawings. FIG. 6 to be referred to is a cross-sectional view of the semiconductor element mounting structure according to the fifth embodiment of the present invention. In FIG. 6, the same components as those of the semiconductor element mounting structure 1 according to the first embodiment described above are denoted by the same reference numerals, and the description thereof is omitted.

図6に示すように、半導体素子実装構造体60は、5層の電気絶縁基材51a〜51eを備え、電気絶縁基材51b,51c間にグラウンド層52が設けられ、更に、電気絶縁基材51a,51b間に電源層53a,53bが設けられている。グラウンド層52は、導熱路16bに接続され、電源層53a,53bはそれぞれ、導熱路16a,16cに接続されている。そして、グラウンド層52及び電源層53a,53bは、接続される半導体素子12〜14毎に分断されている。また、グラウンド層52及び電源層53a,53bは、半導体素子12〜14と同様、それぞれ電気絶縁基材の厚み方向に互いに対面しない部分を有している。その他の構成は、半導体素子実装構造体1(図1参照)と同様に形成されている。これにより、半導体素子12〜14間の熱伝導が遮断され、半導体素子12〜14同士の発生熱による素子特性の劣化を防ぐことができる。   As shown in FIG. 6, the semiconductor element mounting structure 60 includes five layers of electrically insulating base materials 51a to 51e, a ground layer 52 is provided between the electrically insulating base materials 51b and 51c, and further, the electrically insulating base material. Power supply layers 53a and 53b are provided between 51a and 51b. The ground layer 52 is connected to the heat transfer path 16b, and the power supply layers 53a and 53b are connected to the heat transfer paths 16a and 16c, respectively. The ground layer 52 and the power supply layers 53a and 53b are divided for each of the semiconductor elements 12 to 14 to be connected. In addition, the ground layer 52 and the power supply layers 53a and 53b have portions that do not face each other in the thickness direction of the electrically insulating base material, like the semiconductor elements 12 to 14. Other configurations are the same as those of the semiconductor element mounting structure 1 (see FIG. 1). Thereby, the heat conduction between the semiconductor elements 12 to 14 is blocked, and the deterioration of the element characteristics due to the heat generated between the semiconductor elements 12 to 14 can be prevented.

[第6実施形態]
次に、本発明の第6実施形態について適宜図面を参照して説明する。参照する図7は、本発明の第6実施形態に係る半導体素子が実装された多層配線基板(半導体素子実装構造体)の断面図である。なお、図7において、前述した第1実施形態に係る半導体素子実装構造体1と同一構成のものには同一の符号を付し、その説明は省略する。
[Sixth Embodiment]
Next, a sixth embodiment of the present invention will be described with reference to the drawings as appropriate. FIG. 7 to be referred to is a cross-sectional view of a multilayer wiring board (semiconductor element mounting structure) on which a semiconductor element according to the sixth embodiment of the present invention is mounted. In FIG. 7, the same components as those of the semiconductor element mounting structure 1 according to the first embodiment described above are denoted by the same reference numerals, and the description thereof is omitted.

図7に示すように、多層配線基板70は、半導体素子実装構造体1(図1参照)の構成に加え、電気絶縁基材11a,11cの表面111a,111c及び電気絶縁基材11a〜11c間に形成された回路配線71と、電気絶縁基材11a,11b間及び電気絶縁基材11b,11c間に設けられたコンデンサ等の電子部品72a,72bとを備えている。本実施形態では、半導体素子12〜14から発生する熱が、放熱部15a〜15dから効率良く放熱されるため、半導体素子12〜14から発生する熱による電子部品72a,72bの性能劣化等を抑えることができる。なお、本実施形態において、各々の導熱路及び放熱部を、それぞれ信号伝送路及び電極として併用することも可能である。   As shown in FIG. 7, in addition to the configuration of the semiconductor element mounting structure 1 (see FIG. 1), the multilayer wiring board 70 is formed between the surfaces 111a and 111c of the electrical insulating base materials 11a and 11c and the electrical insulating base materials 11a to 11c. Circuit wiring 71 formed between the electrical insulating bases 11a and 11b and between the electrical insulating bases 11b and 11c, and electronic components 72a and 72b such as capacitors. In the present embodiment, the heat generated from the semiconductor elements 12 to 14 is efficiently radiated from the heat radiating portions 15a to 15d, so that the performance deterioration of the electronic components 72a and 72b due to the heat generated from the semiconductor elements 12 to 14 is suppressed. be able to. In the present embodiment, it is also possible to use each heat conducting path and heat radiating portion together as a signal transmission path and an electrode, respectively.

以上説明したように、本発明における半導体素子実装構造体は、半導体素子が、それぞれ電気絶縁基材の厚み方向に互いに対面しない部分を有しており、更に、最外層に配置された電気絶縁性基材のうち少なくともいずれか一方の表面に設けられた放熱部と、この放熱部と半導体素子とを接続する導熱路とを備えているため、半導体素子同士の発生熱による素子特性の劣化を防ぐことができる上、複数の半導体素子から発生する熱を放熱部から効率良く放熱させることができる。また、本発明における半導体素子実装構造体によれば、半導体素子で発生した熱を優先的に放熱部へと誘導するため、例えば、1つの半導体素子で発生した熱が別の半導体素子へと伝播することによって、前記別の半導体素子に所望の電力を印加できなくなったり、前記別の半導体素子が熱暴走を起こしたりする問題を回避できる。なお、前記第1〜第6実施形態において、導熱路、集熱パッド、導熱用バンプ及び集熱ランドは、電気信号伝送用のビア導体及び電極端子として兼用することも可能であることは言うまでもない。   As described above, in the semiconductor element mounting structure according to the present invention, the semiconductor elements each have a portion that does not face each other in the thickness direction of the electric insulating base material, and further, the electric insulating property disposed in the outermost layer. Since it has a heat dissipating part provided on at least one surface of the base material and a heat conducting path connecting the heat dissipating part and the semiconductor element, deterioration of element characteristics due to heat generated between the semiconductor elements is prevented. In addition, heat generated from a plurality of semiconductor elements can be efficiently radiated from the heat radiating portion. In addition, according to the semiconductor element mounting structure of the present invention, heat generated in one semiconductor element is preferentially guided to the heat radiating portion. For example, heat generated in one semiconductor element propagates to another semiconductor element. By doing so, it is possible to avoid a problem that a desired power cannot be applied to the another semiconductor element or a thermal runaway of the another semiconductor element occurs. In the first to sixth embodiments, it goes without saying that the heat conducting path, the heat collecting pad, the heat conducting bump, and the heat collecting land can also be used as a via conductor and an electrode terminal for electric signal transmission. .

上述したように、本発明における半導体素子実装構造体は、複数の半導体素子から発生する熱を効率良く放熱させることができるため、MCPや多層配線基板等の半導体素子実装構造体の小型化を容易に達成することができる。よって、携帯電話等の小型、薄型化が要求される電子機器に好適に使用できる。   As described above, the semiconductor element mounting structure according to the present invention can efficiently dissipate heat generated from a plurality of semiconductor elements. Therefore, the semiconductor element mounting structure such as an MCP or a multilayer wiring board can be easily downsized. Can be achieved. Therefore, it can be suitably used for electronic devices that are required to be small and thin, such as mobile phones.

本発明の第1実施形態に係る半導体素子実装構造体の断面図である。It is sectional drawing of the semiconductor element mounting structure which concerns on 1st Embodiment of this invention. 本発明の第2実施形態に係る半導体素子実装構造体の部分断面拡大図である。It is a partial cross-section enlarged view of the semiconductor element mounting structure according to the second embodiment of the present invention. 本発明の第3実施形態に係る半導体素子実装構造体の部分断面拡大図である。It is a partial cross-section enlarged view of a semiconductor element mounting structure according to a third embodiment of the present invention. 本発明の第4実施形態に係る半導体素子実装構造体の断面図である。It is sectional drawing of the semiconductor element mounting structure which concerns on 4th Embodiment of this invention. 本発明の第4実施形態に係る半導体素子実装構造体において、半導体素子と溝との位置関係を示す概略上面図である。In the semiconductor element mounting structure concerning a 4th embodiment of the present invention, it is a schematic top view showing the positional relationship of a semiconductor element and a slot. 本発明の第5実施形態に係る半導体素子実装構造体の断面図である。It is sectional drawing of the semiconductor element mounting structure which concerns on 5th Embodiment of this invention. 本発明の第6実施形態に係る半導体素子が実装された多層配線基板(半導体素子実装構造体)の断面図である。It is sectional drawing of the multilayer wiring board (semiconductor element mounting structure) with which the semiconductor element which concerns on 6th Embodiment of this invention was mounted. 従来の放熱手段を備えた半導体素子実装構造体の断面図である。It is sectional drawing of the semiconductor element mounting structure provided with the conventional thermal radiation means.

符号の説明Explanation of symbols

1,20,30,40,50,60 半導体素子実装構造体
11a,11b,11c,51a,51b,51c,51d,51e 電気絶縁基材
12,13,14 半導体素子
15a,15b,15c,15d 放熱部
16a,16b,16c,16d 導熱路
21 集熱パッド
22 導熱用バンプ
23 集熱ランド
41 空気層
42 溝
52 グラウンド層
53a,53b 電源層
70 多層配線基板(半導体素子実装構造体)

1, 20, 30, 40, 50, 60 Semiconductor element mounting structure 11a, 11b, 11c, 51a, 51b, 51c, 51d, 51e Electrical insulating base 12, 13, 14 Semiconductor element 15a, 15b, 15c, 15d Part 16a, 16b, 16c, 16d Heat conduction path 21 Heat collection pad 22 Heat conduction bump 23 Heat collection land 41 Air layer 42 Groove 52 Ground layer 53a, 53b Power supply layer 70 Multilayer wiring board (semiconductor element mounting structure)

Claims (13)

複数層の電気絶縁基材と、前記電気絶縁基材表面及び前記電気絶縁基材間の少なくともいずれか一方に配置された複数の半導体素子とを含む半導体素子実装構造体であって、
前記半導体素子は、それぞれ前記電気絶縁基材の厚み方向に互いに対面しない部分を有しており、
最外層に配置された前記電気絶縁性基材のうち少なくともいずれか一方の表面に設けられた放熱部と、
前記電気絶縁基材内に設けられ、前記放熱部と前記半導体素子とを接続する導熱路とを更に備えていることを特徴とする半導体素子実装構造体。
A semiconductor element mounting structure comprising a plurality of layers of an electrically insulating substrate, and a plurality of semiconductor elements disposed on at least one of the electrically insulating substrate surface and the electrically insulating substrate,
Each of the semiconductor elements has portions that do not face each other in the thickness direction of the electrically insulating substrate,
A heat dissipating part provided on the surface of at least one of the electrically insulating substrates disposed in the outermost layer;
A semiconductor element mounting structure, further comprising a heat conduction path provided in the electrically insulating base material and connecting the heat radiating portion and the semiconductor element.
前記電気絶縁基材のうち、複数の前記半導体素子間の少なくとも一部に位置する箇所に、空気層を形成するための溝が設けられている請求項1に記載の半導体素子実装構造体。   2. The semiconductor element mounting structure according to claim 1, wherein a groove for forming an air layer is provided at a position located in at least a part between the plurality of semiconductor elements in the electrically insulating substrate. 前記溝は、複数の前記半導体素子間に位置する前記電気絶縁基材の構成材料を分断している請求項2に記載の半導体素子実装構造体。   The semiconductor element mounting structure according to claim 2, wherein the groove divides a constituent material of the electrically insulating base located between the plurality of semiconductor elements. 前記半導体素子実装構造体は、前記電気絶縁基材間に前記導熱路と接続する放熱材層を更に備え、
前記放熱材層は、接続される前記半導体素子毎に分断されている請求項1〜3のいずれか1項に記載の半導体素子実装構造体。
The semiconductor element mounting structure further includes a heat dissipation material layer connected to the heat conducting path between the electrically insulating bases,
The semiconductor element mounting structure according to claim 1, wherein the heat dissipation material layer is divided for each of the semiconductor elements to be connected.
前記放熱材層は、グラウンド層及び電源層の少なくともいずれか一方である請求項4に記載の半導体素子実装構造体。   The semiconductor element mounting structure according to claim 4, wherein the heat dissipation material layer is at least one of a ground layer and a power supply layer. 前記半導体素子と前記導熱路とは、集熱パッド、導熱用バンプ及び集熱ランドのうち少なくともいずれか一つを介して接続されている請求項1〜5のいずれか1項に記載の半導体素子実装構造体。   The semiconductor element according to claim 1, wherein the semiconductor element and the heat conducting path are connected via at least one of a heat collecting pad, a heat conducting bump, and a heat collecting land. Mounting structure. 前記半導体素子と前記導熱路とは、集熱パッド及び集熱ランドの少なくともいずれか一方を介して接続され、
前記集熱パッド及び前記集熱ランドの少なくともいずれか一方の接続面は、凹凸形状に形成されている請求項6に記載の半導体素子実装構造体。
The semiconductor element and the heat conducting path are connected via at least one of a heat collecting pad and a heat collecting land,
The semiconductor element mounting structure according to claim 6, wherein at least one connection surface of the heat collecting pad and the heat collecting land is formed in an uneven shape.
前記半導体素子は、1つ以上の集熱パッド、複数の導熱用バンプ及び1つ以上の集熱ランドを介して前記導熱路により前記放熱部に接続されている請求項1に記載の半導体素子実装構造体。   2. The semiconductor element mounting according to claim 1, wherein the semiconductor element is connected to the heat radiating portion by the heat conducting path via one or more heat collecting pads, a plurality of heat conducting bumps, and one or more heat collecting lands. Structure. 前記半導体素子は、それぞれ複数の前記導熱路により前記放熱部に接続されている請求項1〜8のいずれか1項に記載の半導体素子実装構造体。   The semiconductor element mounting structure according to claim 1, wherein each of the semiconductor elements is connected to the heat radiating portion by a plurality of the heat conducting paths. 前記半導体素子は、それぞれの単位時間あたりの発熱量が異なり、
前記半導体素子の発熱量が大きくなるにつれ、前記半導体素子に接続される前記導熱路の熱抵抗が小さくなるように構成されている請求項1〜9のいずれか1項に記載の半導体素子実装構造体。
The semiconductor elements have different calorific values per unit time,
The semiconductor element mounting structure according to any one of claims 1 to 9, wherein a heat resistance of the heat conducting path connected to the semiconductor element is reduced as a calorific value of the semiconductor element is increased. body.
前記半導体素子は、それぞれの単位時間あたりの発熱量が異なり、
前記半導体素子の発熱量が大きくなるにつれ、前記半導体素子に接続される前記導熱路の幅方向の断面積が大きくなるように構成されている請求項1〜10のいずれか1項に記載の半導体素子実装構造体。
The semiconductor elements have different calorific values per unit time,
11. The semiconductor according to claim 1, wherein a cross-sectional area in a width direction of the heat conducting path connected to the semiconductor element is increased as a heat generation amount of the semiconductor element is increased. Element mounting structure.
前記導熱路は、金属粉末と熱伝導性樹脂とを含む熱伝導性ペースト及び金属の少なくともいずれか一方で形成されている請求項1〜11のいずれか1項に記載の半導体素子実装構造体。   The semiconductor element mounting structure according to any one of claims 1 to 11, wherein the heat conduction path is formed by at least one of a heat conductive paste containing metal powder and a heat conductive resin and a metal. 前記半導体素子実装構造体は、前記半導体素子が実装された多層配線基板である請求項1〜12のいずれか1項に記載の半導体素子実装構造体。

The semiconductor element mounting structure according to any one of claims 1 to 12, wherein the semiconductor element mounting structure is a multilayer wiring board on which the semiconductor element is mounted.

JP2004152315A 2004-05-21 2004-05-21 Semiconductor device packaging structure Withdrawn JP2005333079A (en)

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008159682A (en) * 2006-12-21 2008-07-10 Fujikura Ltd Multilayer printed wiring board and its manufacturing method
JP2009164287A (en) * 2007-12-28 2009-07-23 Fujikura Ltd Multilayer printed wiring board and manufacturing method thereof
KR101006063B1 (en) * 2008-09-26 2011-01-06 주식회사 심텍 Printed circuit board for solid state drive
JP2012209527A (en) * 2011-03-30 2012-10-25 Tdk Corp Component built-in substrate and manufacturing method of the same

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008159682A (en) * 2006-12-21 2008-07-10 Fujikura Ltd Multilayer printed wiring board and its manufacturing method
JP2009164287A (en) * 2007-12-28 2009-07-23 Fujikura Ltd Multilayer printed wiring board and manufacturing method thereof
KR101006063B1 (en) * 2008-09-26 2011-01-06 주식회사 심텍 Printed circuit board for solid state drive
JP2012209527A (en) * 2011-03-30 2012-10-25 Tdk Corp Component built-in substrate and manufacturing method of the same

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