CN107068634A - A kind of multi-chip power amplifier architecture for minimizing high-cooling property and preparation method thereof - Google Patents
A kind of multi-chip power amplifier architecture for minimizing high-cooling property and preparation method thereof Download PDFInfo
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- CN107068634A CN107068634A CN201710058821.4A CN201710058821A CN107068634A CN 107068634 A CN107068634 A CN 107068634A CN 201710058821 A CN201710058821 A CN 201710058821A CN 107068634 A CN107068634 A CN 107068634A
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
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- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/27—Manufacturing methods
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
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- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
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- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
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- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
Abstract
The invention discloses a kind of multi-chip linear power amplifier structure and preparation method thereof for minimizing high-cooling property, it is characterized in that a separate functional blocks include the multiple element compositions such as power amplifier chip, CMOS chip, RF switch chip and the passive device that matches.Wherein power amplifier chip is embedded to organic substrate in advance, and the power amplifier chip back side is pasted on the metal level inside substrate；The positive electrode of power amplifier chip carries out signal transmission by the metal printed circuit inside substrate and via, and is ultimately connected to the corresponding pad of substrate extexine；Other element are welded in outer surface of substrate, then overall plastic packaging.The present invention can be such that the heat dissipation path of power amplifier chip shortens as far as possible, while can make full use of substrate inner space again, reduce the area of plane of module, so as to reach high-cooling property and reduce the purpose of device size.
Description
Technical field
The present invention relates to the structure of linear power amplifier, specifically a kind of multi-chip work(for minimizing high-cooling property
Rate amplifier structure and preparation method thereof.
Background technology
Radio-frequency transmissions front-end module is the key componentses that rf terminal device realizes signal transmission.Currently with global nothing
The rapid growth of line communication user and user are to the more high-end demand for experience of radio communication, and market is to the bandwidth of radio communication
Demand rapid growth.In order to solve this market demand, the private radio communication frequency range that global open comes out it is more and more and
It is more and more crowded.The high modulation demodulation system of frequency range utilization rate, for example：3G WCDMA (Wideband Code
Division Multiple Access, WCDMA), band CDMA (Code Division Multiple Access,
), CDMA TD SDMA (Time Division Synchronous Code Division Multiple
Access, TD-SCDMA), and gradually substitution 3G technology turns into the Long term evolution of the 4G technologies of the market mainstream,
LTE includes paired spectrum pattern (Frequency domain duplexing, FDD) and non-paired spectrum mode (Time
domain duplexing,TDD).The high various modulation demodulation systems of these frequency range utilization rates are all proposed to wireless communication terminal
Higher requirement, for example：High-quality voice call, reduces the mistake in data communication, and quick voice data transmission is cut
Change, etc..
For the main force's component radio-frequency power amplifier and its module of radio-frequency transmissions front end, it is meant that new
Under the high modulation demodulation system of frequency range utilization rate, power amplifier must have the higher linearity to ensure that radiofrequency signal can
Amplification transmission and the distorted signals less that can try one's best.The high linearity of general power amplifier means that reducing its power output comes
Reduce the generation of the non-linear harmonic wave of output transistor device.Power amplifier is a core member in wireless communication connection
Part, and be among wireless communication system is appeared in the form of independent module.Existing power amplifier is typically using more
It may be included in integrated one module (MCM) of formation on one substrate of element, its module and be not limited to following multiple element：
Power amplifier chip, power-mode control circuitry is typically CMOS technology, and output matching circuit can use passive discrete member
Part or semiconductor passive device, RF switch are typically to use GaAs pHEMT techniques or SOI technology.Each chip and substrate
Connected mode have two kinds substantially, a kind of is that the pad node on the pad and substrate on chip is connected by fly line technology, separately
A kind of is that flip chip technology (fct) is directly docked by the node on the metal salient point and substrate on chip by scolding tin or copper post.
Big yet with the caloric value of power amplifier chip in itself, the thermal diffusivity of device will directly influence the linearity and amplification efficiency,
So needing the factor that emphasis considers when heat-sinking capability is often Designing power amplifier.Meanwhile, with the size of terminal device
Become to develop to thinner and smaller direction, more and more higher is required to device geometries.Therefore, the size how reduced is also work(
The design of rate amplifier part needs one of factor considered.
In existing product design, the connected mode of general chip and substrate has two kinds substantially, and one kind is by fly line
The pad node on pad and substrate on technology connection chip, another is that flip chip technology (fct) is convex by the metal on chip
Node on point and substrate is directly docked by scolding tin or copper post.Putting for multiple element is typically all placed in substrate side by side
Surface, belongs to two-dimensional structure design.This design of putting is except substrate surface to be ensured has enough areas to put down multiple members
Outside part, often also needing to sacrifice more extra plane spaces is used to ensureing the stabilization of good electrical property and production technology
Property.Therefore two-dimensional structure design necessarily causes the overall dimensions of device to be difficult further reduce.
By taking Common wireless communication power amplifier output-stage connected mode as an example, the existing most of power amplification of in the market
Device is that power amplifier chip is realized with substrate by fly line technology to be connected, as shown in Figure 1.Some earthing modes are also likely to be
TWV is grounded using wafer insertion, as shown in Figure 2.Both connection methods are commonly used to the design of linear amplifier.But no matter
It is that fly line or wafer insertion earthing mode radiating effect are all undesirable, because the emitter stage of business HBT transistors is mostly in crystalline substance
The superiors of body pipe multilayer material, electric current needs to include ground level layer by the multilayer material under fly line or emitter,
Then collector layer, substrate layer is grounded, heat transfer is to substrate pads, then passes through substrate by the coat of metal of wafer rear
Via and multi-layer metal wiring, conduct heat to substrate surface.So a long path can cause inductance and resistance
It is excessive, so that heat transfer efficiency is very poor.On the other hand, in as shown in Figure 1, Figure 2, CMOS chip is positioned over base side by side with power amplifier chip
Plate surface, causes the increase of device integral planar area.
Another common chip connection in market is passed through on the metal salient point and substrate on chip using flip chip technology (fct)
Node is directly docked by scolding tin or copper post.This mode is common in the high-performance processor chip of multi-pipe pin, recent market
On engender that the circuit of power amplifier is realized power amplifier chip with substrate by flip chip technology (fct) and be connected.It is this
Design is as shown in figure 3, flip-chip ground nodes weld ground connection by the scolding tin or copper post of very large area with substrate, and heat can
Directly substrate pads are delivered to from chip surface, then by the via and multi-layer metal wiring of substrate, conduct heat to substrate
Surface.It can conduct to substrate, so being designed compared to fly line mode, radiate because chip heating needs not move through very long path
Effect is better.But it is disadvantageous in that heat still will can just be transferred to base by multilayer wiring inside substrate and via
Plate surface.Therefore, designed for multilager base plate, heat dispersion would is that very big challenge.In addition, as in Fig. 3, CMOS chip is still
So placed side by side with power amplifier chip, cause the increase of device overall dimensions.
The content of the invention
The present invention minimizes many of high-cooling property to solve above-mentioned the shortcomings of the prior art there is provided a kind of
Chips wire power amplifier structure and preparation method thereof, to be made full use of by way of chip is embedded into substrate in advance
Substrate inner space, while shortening the heat dissipation path of device, so as to reach the purpose for reducing size and improving thermal diffusivity.
The present invention adopts the following technical scheme that to solve technical problem：
The present invention it is a kind of minimize high-cooling property multi-chip linear power amplifier structure the characteristics of be：Substrate is set
Structure includes：Upper metal layers, middle substrate core materials and lower metal layer；In the upper metal layers and lower metal layer
Include printed circuit and be correspondingly provided with via；
On the substrate core materials power amplifier chip is provided with by being bonded glue；The back side of the power amplifier chip
For substrate, and towards the upper metal layers, the front of the power amplifier chip includes containing circuit and input and output electrode, and
Towards the lower metal layer；
The surface of the upper metal layers and lower metal layer is provided with several pads, and covered with solder resist material
Layer；
The positive input and output electrode of power amplifier chip is corresponding with lower metal layer surface by corresponding via
Pad is connected, and be welded with metal soldered ball on the pad of the lower metal layer surface draws as the input and output of amplifier element
Pin；
CMOS chip is provided with by being bonded glue in the upper metal layers, and passes through fly line and upper metal layers surface
Respective pad be connected；The respective pad on the upper metal layers surface is welded with passive device；
Plastic packaging layer is provided with the upper metal layers to be used to cover the CMOS chip and passive device.
The characteristics of multi-chip linear power amplifier structure of miniaturization high-cooling property of the present invention, lies also in：Set
Diameter of the opening more than its metal soldered ball of the ground connection GND pin pad of the lower metal layer surface.
A kind of the characteristics of preparation method of multi-chip power amplifier architecture for minimizing high-cooling property of the present invention is by such as
Lower step is carried out：
Step 1, in the upper and lower surfaces of substrate core materials press thin metal layer, form upper metal layers and lower metal
Layer；
Step 2, by being bonded glue the substrate of power amplifier chip and upper metal layers are bonded；
Step 3, multilayer circuit is printed in the upper metal layers and lower metal layer, and get through via by the multilayer
Circuit is connected with the positive input and output electrode of power amplifier chip；
Step 4, it is provided with several pads on the surface of the upper metal layers and lower metal layer, and filled with welding resistance
Material layer carries out insulation processing；
Step 5, the multilayer circuit are by setting corresponding via to be connected with corresponding pad；
Step 6, in the respective pad on the upper metal layers surface it is welded with passive device；
Step 7, by CMOS chip with bonding glue in the upper metal layers, and by way of fly line, by telecommunications
Number it is connected to respective pad；
Step 8, it is provided with the upper metal layers plastic packaging layer and is used to cover the CMOS chip and passive device；
Step 9, to be welded with the pad of the lower metal layer surface metal soldered ball defeated as the input of amplifier element
Go out pin and ground connection GND pin.
Compared with the prior art, the present invention has the beneficial effect that：
1st, compared to the most of multi-chip power amplifiers of in the market, power amplifier chip is connected or wafer insertion using fly line
Ground connection, it is of the invention that power amplifier chip is embedded to substrate in advance for the design that CMOS and other elements are placed side by side, it is other
Element is positioned over the design of substrate surface so that power amplifier chip grounding electrode can be connected directly between on the metal level of substrate,
The application of fly line is not only reduced, while the resistance and inductance of ground connection can be greatly reduced, so as to improve leading for amplifier
The thermal efficiency, while multi-chip is placed by three-dimensional structure, greatlys save substrate surface area, so as to reduce the overall chi of module
It is very little.
2nd, the power amplifier being grounded compared to power amplifier chip upside-down mounting, the present invention places power amplification core inside substrate
The design of piece, not only eliminates the metal salient point required for flip-chip design, and grounding electrode is connected to the gold inside substrate
Belong to layer, closer to the GND pin of substrate surface, shortening heat dissipation path significantly improves the heat transfer efficiency of amplifier.
3rd, Design enlargement device structure of the invention, takes full advantage of the space inside substrate, designs and carry for multi-chip module
More flexibilities are supplied.In addition to power amplifier chip should be positioned over inside substrate to improve heat dispersion, Qi Tayuan
Part can flexibly be placed according to product design demand and processing throughput.
Brief description of the drawings
Fig. 1 is existing fly line technology multi-chip linear power amplifier schematic diagram；
Fig. 2 is that existing wafer insertion is grounded multi-chip linear power amplifier schematic diagram；
Fig. 3 is existing flip-chip grounding technology multi-chip linear power amplifier schematic diagram；
Fig. 4 is flush type three-dimensional structure multi-chip linear power amplifier schematic diagram of the present invention；
Label in figure：100 power amplifier chips；110 input and output electrodes；120CMOS chips；200 bonding glue；300 bases
Plate；310 substrate core materials；320 metal levels；330 pads；340 vias；400 passive devices；500 solder resist materials layer；600 fly lines；
700 plastic packagings layer；800 input and output pins；810 ground connection GND pins.
Embodiment
In the present embodiment, as shown in figure 4, a kind of multi-chip linear power amplifier structure for minimizing high-cooling property, bag
Containing in addition to power amplifier chip 100, should also contain, if but necessarily all comprising CMOS chip 120, RF switch chip,
The elements such as dry passive device；Wherein, power amplifier chip refers to be formed on the backing materials such as including but not limited to silicon, GaAs
There is the functional block of power amplification functional integrated circuit；Power amplifier chip 100 comprising substrate, circuit layer and surface several
Input and output electrode (Bondpad), and it is positioned over that substrate 300 is internal, other elements, the He of passive device 400 of such as part
CMOS chip 120 can be positioned over the surface of substrate 300 or on the premise of the overall planar dimension of element is not influenceed, and can also be bonded in
On metal level 320 inside substrate 300, metal ball bond is in the corresponding input/output pads position in the surface of substrate 300；By work(
The input and output electrode 110 of rate amplification chip 100 carries out signal transmission by the metal printed circuit inside substrate and via, and
The corresponding pad 330 of substrate extexine is ultimately connected to, passive device 400, other elements are welded in outer surface of substrate, and by having
Machine material is filled and insulated, and then overall plastic packaging forms complete current path；Specifically,
Setting the structure of substrate 300 includes：Upper metal layers, middle substrate core materials 310 and lower metal layer；Upper strata
Multilayer printed circuit is included on metal level and lower metal layer and via 340 is correspondingly provided with；The making of multilager base plate circuit can
Using organic printed circuit boards technique, with good quality and reliability.
On substrate core materials 310 power amplifier chip 100 is provided with by being bonded glue 200；Power amplifier chip 100
The back side is substrate, and towards upper metal layers, the front of power amplifier chip 100 includes containing circuit and input and output electrode 110,
And towards lower metal layer；
Several pads 330 are provided with the surface of upper metal layers and lower metal layer, and covered with solder resist material layer
500；
The positive input and output electrode 110 of power amplifier chip 100 passes through corresponding via 340 and lower metal layer surface phase
The pad 330 answered is connected, and it is defeated as the input of amplifier element to be welded with metal soldered ball on the pad 330 of lower metal layer surface
Go out pin 800 and grounding pin 810；Because the radiating of power amplifier chip 100 is main by chip front side ground connection GND electrodes,
Transmitted by the inside via 340 of substrate 300 and ground metal layer to outer surface of substrate grounding pin 810, therefore, of the invention sets
Meter causes chip heating region from grounding pin recently, and radiating efficiency is optimal.
It can be required according to specific product, be provided with CMOS chip 120 by being bonded glue 200 in upper metal layers, and lead to
Cross fly line 600 or be connected using flip-chip with the respective pad 330 on upper metal layers surface；Upper metal layers surface
Respective pad 330 be welded with the grade element of passive device 400；
Plastic packaging layer 700 is provided with upper metal layers to be used to cover CMOS chip 120 and passive device 400, by whole
Body plastic packaging to chip and circuit to protect.
In specific implementation, as shown in figure 4, the ground connection pad of GND pin 810 is different from other pads of input and output pin 800,
Diameter of the opening much larger than its metal soldered ball of the ground connection pad of GND pin 810 of lower metal layer surface is set.Large-area metal
Layer, which is exposed, to be come, so that the heat that chip is produced effectively is distributed.
In summary, a kind of multi-chip linear power amplifier structure for minimizing high-cooling property is using in optimization element
The design philosophy of portion's structure, by the way that power amplifier chip 100 is positioned over inside substrate 300, reduces inside modules element simultaneously
The area needed for placement is arranged, and makes the road between the heating region of power amplifier chip 100 and the ground connection GND pin 810 of device
Footpath be optimized to it is most short so that reached reduce module size and improve heat dispersion effect.
In the present embodiment, a kind of preparation method for the multi-chip power amplifier architecture for minimizing high-cooling property is by as follows
Step is carried out：
Step 1, in the upper and lower surfaces of substrate core materials 310 press thin metal layer, form upper metal layers 320 and lower floor
Metal level；
Step 2, by thermal conductivity good bonding glue 200 substrate of power amplifier chip 100 and upper metal layers 320 are glued
Close；
Step 3, by half addition or additive process method, print multilayer in upper metal layers 320 and lower metal layer
Circuit, and get through via 340 multilayer circuit is connected with the positive input and output electrode of power amplifier chip 100 110；
Step 4, it is provided with several pads 330 on the surface of upper metal layers and lower metal layer, and filled with welding resistance
Material layer 500 carries out insulation processing to pad；
Step 5, multilayer circuit are by setting corresponding via 340 to be connected with corresponding pad 330；
Step 6, in the respective pad 330 on the surface of upper metal layers 320 it is welded with passive device 400；
Step 7, CMOS chip 120 with bonding glue 200 is pasted onto upper metal layers, will and by way of fly line 600
Electric signal is connected to respective pad 330；
After the completion of step 8, fly line connection, being provided with plastic packaging layer 700 on layer metal level on the surface of the substrate is used to cover
CMOS chip 120 and passive device 400 are connected with protection circuit；
Step 9, on the pad 330 of lower metal layer surface metal soldered ball is welded with as the input and output of amplifier element
Pin 600 and ground connection GND pin 610.
All be two-dimensional structure as shown in Figure 1, Figure 2, the existing typical designs of tri- kinds of Fig. 3 with existing design project plan comparison, i.e. institute
There is element to be placed on substrate surface side by side.Technical process is first makes organic substrate, then again all device bonded in base
Plate surface, circuit connection is formed with modes such as fly line or metal salient points, and last chip exterior will also carry out plastic packaging to protect chip
With the reliability of connection.And the structure in the present embodiment is that the power amplifier chip of core is placed on inside substrate, Qi Tayuan
Part is placed on substrate surface, and element is put in the way of three-dimensional structure, reduces footprint.
Mainly application can include being not limited to mobile phone, flat board electricity this amplifier architecture in rf terminal equipment
Brain, notebook computer, the Wireless Telecom Equipment of vehicle electronics, the Wireless Telecom Equipment of Internet of Things etc., it can also apply at it
Among its Wireless Telecom Equipment, including it is not limited to communication base station, satellite wireless communication, military Wireless Telecom Equipment etc..
Any change on physical circuit or chip layout way of realization, is included within the covering scope of this structure.
Claims (3)
1. a kind of multi-chip linear power amplifier structure for minimizing high-cooling property, it is characterized in that：The knot of substrate (300) is set
Structure includes：Upper metal layers, middle substrate core materials (310) and lower metal layer；The upper metal layers and lower metal
Include printed circuit on layer and be correspondingly provided with via (340)；
On the substrate core materials (310) power amplifier chip (100) is provided with by being bonded glue (200)；The power is put
The back side of large chip (100) is substrate, and towards the upper metal layers, the front of the power amplifier chip (100) includes
Containing circuit and input and output electrode (110), and towards the lower metal layer；
Several pads (330) are provided with the surface of the upper metal layers and lower metal layer, and covered with solder resist material
Layer (500)；
The positive input and output electrode of the power amplifier chip (100) (110) passes through corresponding via (340) and lower metal layer
The corresponding pad in surface (330) is connected, and metal soldered ball is welded with the pad (330) of the lower metal layer surface as putting
The input and output pin (800) of big element；
Be provided with CMOS chip (120) by being bonded glue (200) in the upper metal layers, and by fly line (600) with it is upper
The respective pad (330) of layer layer on surface of metal is connected；The respective pad (330) on the upper metal layers surface is welded with passive
Device (400)；
Plastic packaging layer (700) is provided with the upper metal layers to be used to cover the CMOS chip (120) and passive device
(400)。
2. the multi-chip linear power amplifier structure of miniaturization high-cooling property according to claim 1, it is characterized in that：If
Put the diameter of the opening more than its metal soldered ball of ground connection GND pin (810) pad of the lower metal layer surface.
3. a kind of preparation method for the multi-chip power amplifier architecture for minimizing high-cooling property, it is characterized in that entering as follows
OK：
Step 1, in the upper and lower surfaces of substrate core materials (310) press thin metal layer, form upper metal layers (32) 0 and lower floor
Metal level；
Step 2, by being bonded glue (200) substrate of power amplifier chip (100) and upper metal layers (320) are bonded；
Step 3, multilayer circuit is printed in the upper metal layers (320) and lower metal layer, and get through via (340) by institute
Multilayer circuit is stated with power amplifier chip (100) positive input and output electrode (110) to be connected；
Step 4, it is provided with several pads (330) on the surface of the upper metal layers and lower metal layer, and filled with resistance
The wlding bed of material (500) carries out insulation processing；
Step 5, the multilayer circuit are by setting corresponding via (340) to be connected with corresponding pad (330)；
Step 6, in the respective pad (330) on the upper metal layers (320) surface it is welded with passive device (400)；
Step 7, CMOS chip (120) with bonding glue (200) is pasted onto the upper metal layers, and passes through the side of fly line 600
Formula, respective pad (330) is connected to by electric signal；
Step 8, it is provided with the upper metal layers plastic packaging layer (700) and is used to cover the CMOS chip (120) and passive
Device (400)；
Step 9, on the pad (330) of the lower metal layer surface to be welded with metal soldered ball defeated as the input of amplifier element
Go out pin (600) and ground connection GND pin (610).
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