CN206460952U - Multi-chip linear power amplifier structure without substrate high-cooling property - Google Patents
Multi-chip linear power amplifier structure without substrate high-cooling property Download PDFInfo
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- CN206460952U CN206460952U CN201720099827.1U CN201720099827U CN206460952U CN 206460952 U CN206460952 U CN 206460952U CN 201720099827 U CN201720099827 U CN 201720099827U CN 206460952 U CN206460952 U CN 206460952U
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
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- H—ELECTRICITY
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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- H—ELECTRICITY
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/19—Manufacturing methods of high density interconnect preforms
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- H—ELECTRICITY
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
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- H—ELECTRICITY
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
Abstract
The utility model discloses a kind of multi-chip linear power amplifier structure without substrate high-cooling property, it is characterized in that different elements are combined into several power amplifier module physical structures by functional requirement, it is integrated on one piece of common detachable big slide glass, by the first overall plastic packaging of each element in power amplifier module, slide glass needs to dismantle after plastic packaging, element input and output electrode is exposed and multilayer interconnection metallic circuit and outer pin pad and soldered ball formation module outer pin are formed on plastic-sealed body surface, so as to constitute several complete linear prower amplifier modules, finally cutting is separated into the power amplifier module of single complete function.The utility model not only contributes to reduce the coupling of interconnecting parts and radio frequency path, reduce the inductance of grounding electrode interconnection, and higher wiring density can greatly reduce the interconnection circuit number of plies, so as to shorten the path of grounding electrode radiating, optimization module performance and the purpose of high-cooling property are reached.
Description
Technical field
The utility model is related to the structure of linear power amplifier, a kind of specific multi-chip work(without substrate high-cooling property
Rate amplification module.
Background technology
Radio-frequency transmissions front-end module is the key componentses that rf terminal device realizes signal transmission.Currently with global nothing
The rapid growth of line communication user and user are to the more high-end demand for experience of radio communication, and market is to the bandwidth of radio communication
Demand rapid growth.In order to solve this market demand, the private radio communication frequency range that global open comes out it is more and more and
It is more and more crowded.The high modulation demodulation system of frequency range utilization rate, for example：3G WCDMA (Wideband Code
Division Multiple Access, WCDMA), band CDMA (Code Division Multiple Access,
), CDMA TD SDMA (Time Division Synchronous Code Division Multiple
Access, TD-SCDMA), and gradually substitution 3G technology turns into the Long term evolution of the 4G technologies of the market mainstream,
LTE includes paired spectrum pattern (Frequency domain duplexing, FDD) and non-paired spectrum mode (Time
domain duplexing,TDD).The high various modulation demodulation systems of these frequency range utilization rates are all proposed to wireless communication terminal
Higher requirement, for example：High-quality voice call, reduces the mistake in data communication, and quick voice data transmission is cut
Change, etc..
For the main force's component radio-frequency power amplifier and its module of radio-frequency transmissions front end, it is meant that new
Under the high modulation demodulation system of frequency range utilization rate, power amplifier must have the higher linearity to ensure that radiofrequency signal can
Amplification transmission and the distorted signals less that can try one's best.The high linearity of general power amplifier means that reducing its power output comes
Reduce the generation of the non-linear harmonic wave of output transistor device.Power amplifier is a core member in wireless communication connection
Part, and be among wireless communication system is appeared in the form of independent module.Existing power amplifier is typically using more
It may be included in integrated one module (MCM) of formation on one substrate of element, its module and be not limited to following multiple element：
Power amplifier chip, power-mode control circuitry is typically CMOS technology, and output matching circuit can use passive discrete member
Part or semiconductor passive device, RF switch are typically to use GaAs pHEMT techniques or SOI technology.Each chip and substrate
Connected mode have two kinds substantially, a kind of is that the pad node on the pad and substrate on chip is connected by fly line technology, separately
A kind of is that flip chip technology (fct) is directly docked by the node on the metal salient point and substrate on chip by scolding tin or copper post.
Big yet with the caloric value of power amplifier chip in itself, the thermal diffusivity of device will directly influence the linearity and amplification efficiency,
So needing the factor that emphasis considers when heat-sinking capability is often Designing power amplifier.Meanwhile, as the size of chip is to more
Small direction is developed, and influence of the coupling between interconnecting parts and radio circuit to device performance also becomes increasing.
In existing product design, the connected mode of general chip and substrate has two kinds substantially, and one kind is by fly line
The pad node on pad and substrate on technology connection chip, another is that flip chip technology (fct) is convex by the metal on chip
Node on point and substrate is directly docked by scolding tin or copper post.With Common wireless communication power amplifier output-stage connection side
Exemplified by formula, the existing most of power amplifier of in the market is that power amplifier chip and substrate are realized by fly line technology to connect
Connect, as shown in Figure 1.Some earthing modes are also likely to be to be grounded TWV using wafer insertion, as shown in Figure 2.Both connection methods
It is commonly used to the design of linear amplifier.But either fly line or wafer insertion earthing mode radiating effect are all undesirable,
Because the emitter stage of business HBT transistors is mostly in the superiors of transistor multi-layer material, electric current is needed by fly line or crystal
Multilayer material under pipe emitter stage includes ground level layer, and then collector layer, substrate layer is connect by the coat of metal of wafer rear
Ground, heat transfer conducts heat to substrate surface to substrate pads, then by the via and multi-layer metal wiring of substrate.This
One path of sample length can cause inductance and resistance excessive, so that heat transfer efficiency is very poor.
Another common chip connection in market is passed through on the metal salient point and substrate on chip using flip chip technology (fct)
Node is directly docked by scolding tin or copper post.This mode is common in the high-performance processor chip of multi-pipe pin, recent market
On engender that the circuit of power amplifier is realized power amplifier chip with substrate by flip chip technology (fct) and be connected.It is this
Design is as shown in figure 3, flip-chip ground nodes weld ground connection by the scolding tin or copper post of very large area with substrate, and heat can
Directly substrate pads are delivered to from chip surface, then by the via and multi-layer metal wiring of substrate, conduct heat to substrate
Surface.It can conduct to substrate, so being designed compared to fly line mode, radiate because chip heating needs not move through very long path
Effect is better.But it is disadvantageous in that heat still will can just be transferred to base by multilayer wiring inside substrate and via
Plate surface.Therefore, designed for multilager base plate, heat dispersion would is that very big challenge.
Both the above connected mode adds extra interconnection structure all between chip and substrate, not only in production cost
It is affected with terms of efficiency, it is often more important that a series of aspect of performances such as coupling, Insertion Loss for being brought by interconnection structure
Problem, is increasingly paid attention to the reduction of chip size by everybody.
Utility model content
The utility model is for the above-mentioned the shortcomings of the prior art of solution there is provided one kind without substrate high-cooling property
Multi-chip linear power amplifier structure, to which from die terminals interconnection circuit directly can be directly led out, omit fly line or gold
Belong to the interconnection link such as salient point, not only contribute to reduce the coupling of interconnecting parts and radio frequency path, reduce the electricity of grounding electrode interconnection
Sense, and higher wiring density can greatly reduce the interconnection circuit number of plies, so as to shorten the path of grounding electrode radiating,
Reach optimization module performance and improve the purpose of thermal diffusivity.
The utility model adopts the following technical scheme that to solve technical problem：
A kind of the characteristics of multi-chip linear power amplifier structure without substrate high-cooling property of the utility model is to include：Work(
Rate amplification chip, CMOS chip and several passive devices；
The power amplifier chip, the back side of CMOS chip and several passive devices and surrounding are covered by binding agent
There is plastic packaging layer, the front of the power amplifier chip and CMOS chip and several passive devices is covered with dielectric layer；It is described
Multiple layer metal circuit layer is included in dielectric layer, and if the input and output electrode with the power amplifier chip and CMOS chip and
The outer solder joint of dry passive device is connected；The dielectric layer surface set outer pin pad, and with the multiple layer metal
Circuit layer is connected；Metal soldered ball is welded with the outer pin pad；So as to form the power amplification of single complete function
Module；Uniformly arranged by the power amplifier module of several single complete functions, so as to form multi-chip linear power amplifier
Structure.
Compared with the prior art, the utility model has the beneficial effect that：
1st, compared to the most of multi-chip power amplification modules of in the market, the utility model is connected or upside-down mounting connection using fly line
For the design of substrate, interconnection circuit directly is directly led out from die terminals, the interconnection link such as fly line or metal salient point is eliminated,
The coupling of interconnecting parts and radio frequency path is conducive to reducing, has reduced the inductance of grounding electrode interconnection, be conducive to module electrical
The optimization of energy.
2nd, compared to the power amplifier module using fly line connection or upside-down mounting connecting substrate, the utility model is directly from die terminals
Interconnection circuit is directly led out, the technique that can be again connected up using metal on disk or flat board reaches the gold thinner than in substrate manufacture
Belong to line width line-spacing.The density of designing wiring is which thereby enhanced, the circuit number of plies is reduced, so as to shorten the road of grounding electrode radiating
Footpath, has reached optimization module performance and the purpose of high-cooling property.
3rd, the multi-chip power amplification module without substrate of the utility model design, eliminates substrate, fly line or metal convex
The interconnection link such as point, and integrated multiple power amplifier modules using detachable support plate, integrally added using multimode
The assemble method of work, circuit is drawn from one single chip the circuit interconnection to be formed between each element, and be ultimately connected to module
Outer pin, advantageously reduces production cost and improves production efficiency.
Brief description of the drawings
Fig. 1 is existing fly line technology multi-chip linear power amplifier schematic diagram；
Fig. 2 is that existing wafer insertion is grounded multi-chip linear power amplifier schematic diagram；
Fig. 3 is existing flip-chip grounding technology multi-chip linear power amplifier schematic diagram；
Fig. 4 a are the top view of adhering chip in the utility model circular mount；
Fig. 4 b are the top view of adhering chip on the square slide glass of the utility model；
Fig. 5 a are the profile of adhering chip on the utility model slide glass；
Fig. 5 b are the profile after the overall plastic packaging of the utility model slide glass；
Fig. 5 c are the profile after the utility model slide glass is peeled off；
Fig. 5 d are that the profile after multiple layer metal circuit and welding soldered ball is drawn on the utility model plastic-sealed body surface；
Fig. 6 is without substrate power amplifier module profile after the utility model is separated；
Label in figure：100 slide glasses；110 power amplifier chips；120 CMOS chips；130 passive devices；140 input and output
Electrode；200 plastic packagings layer；300 dielectric layers；310 metal circuitries；320 outer pin pads；330 Cutting Roads；400 metal soldered balls；
Embodiment
In the present embodiment, a kind of multi-chip linear power amplifier structure without substrate high-cooling property, except power amplification core
Beyond piece 110, CMOS chip 120, RF switch chip and several passive devices 130 can also be included；Various chip lists
Bread contains front and back, and the face containing circuit and input and output electrode is front, and substrate portions are the back side；Passive device 130 can
To be the discrete components such as inductance, electric capacity, resistance；
As shown in fig. 6, power amplifier chip 110, the back side of CMOS chip 120 and several passive devices 130 and four
Week, the input and output electrode of each chip surface and the outer solder joint of discrete component should be sudden and violent by binding agent covered with plastic packaging layer 200
It is exposed at the same outer surface of plastic-sealed body；Power amplifier chip 110 and CMOS chip 120 and several passive devices 130 are just
Face is covered with dielectric layer 300；In dielectric layer 300 include multiple layer metal circuit layer 310, and with power amplifier chip 110 and CMOS
The input and output electrode 140 of chip 120 and the outer solder joint of several passive devices 130 are connected；Wherein, metal circuitry cloth
Line line width line-spacing is no more than 15um/15um layers；Dielectric layer 300 surface set outer pin pad (320), and with the multilayer
Metal circuitry (310) is connected；Metal soldered ball 400 is welded with outer pin pad 320；So as to form single complete function
Power amplifier module；Uniformly arranged by the power amplifier module of several single complete functions, so that it is linear to form multi-chip
Power amplifier structure.
In the present embodiment, a kind of preparation method of the multi-chip linear power amplifier structure without substrate high-cooling property is
Different elements are combined into several power amplifier module things by the design philosophy assembled using module overall processing by functional requirement
Framework is managed, is integrated on one piece of common detachable big slide glass, by the first overall plastic packaging of each element in power amplifier module,
Slide glass is needed to dismantle after plastic packaging, and element input and output electrode is exposed and multilayer interconnection metallic circuit is formed on plastic-sealed body surface
And outer pin pad and soldered ball formation module outer pin, so as to constitute several complete linear prower amplifier modules, finally
Cutting is separated into the power amplifier module of single complete function, is to carry out as follows specifically：
Step 1, one slide glass of setting (100), can be that material is not limited in the disk of silicon or square piece, such as Fig. 4 a, Fig. 4 b institute
Show, divide and pressed in several zonules, each zonule according to the apparent size size of power amplifier module on a slide glass 100
According to the space layout design of a power amplifier module, by strippable film or binding agent with input and output electrode (140)
Face-down mode pastes a power amplifier chip 110, a CMOS chip 120 and several passive devices 130；And work(
The side of input and output electrode 140 of rate amplification chip 110 and CMOS chip 120 and the outer solder joint of several passive devices 130
Side is pasted on slide glass 100；As shown in profile 5a；
Step 2, by the overall plastic packaging of all components on slide glass 100, shown in the profile 5b after plastic packaging, form plastic packaging layer
200；
Step 3, as shown in profile 5c, slide glass 100 is peeled off from plastic packaging layer 200, and exposes input and output electrode 140
With outer solder joint；Now, each element of power amplifier module is encapsulated among plastic-sealed body, but input and output electrode surface should
Just expose.Wherein, chip and passive device sticking veneer can also be slightly higher or can less be less than with plastic packaging surface same level
Plastic packaging surface, but chip electrode and the outer solder joint of passive device must be enable to expose.
Step 4, on the surface that this exposes, covered using the similar photosensitive organic materials of PI (polyimide resin) or other
Cover on the input and output electrode after stripping 140 and outer solder joint, form dielectric layer 300；
Step 5, the method on dielectric layer 300 by wiring layer again (Redistribution Layer), comprising gluing,
The multiple technical process such as exposure, development, plating make multiple layer metal circuits 310, and with power amplifier chip 110 and CMOS chip
120 input and output electrode 140 and the outer solder joint of several passive devices 130 are connected；
Step 6, dielectric layer surface predeterminated position by exposure, development or other special process output several windows,
Outermost metallic circuit is exposed, and further forms the outer pin pad 320 being connected with multiple layer metal circuit layer 310；
Step 7, the welding metal soldered ball 400 on outer pin pad 320；As shown in profile 5d；
Step 8, according to the different corresponding Cutting Roads 330 of region division, identified according still further to Cutting Road, by whole plastic-sealed body
Cutting separation, so as to form the power amplifier module of single complete function；So as to form the multi-chip linear power uniformly arranged
Amplifier architecture, as shown in Figure 6.
There is provided a kind of power amplifier module design without substrate in the present embodiment.With existing design project plan comparison
Eliminate substrate and chip bump or fly line, multiple modules together overall processing can be assembled, save many costs and
Improve efficiency.It is the surface progress in whole disk or square piece because the making of interconnection circuit is different from general substrate process
The method of wiring layer, can cause the line width line-spacing of interconnection line to be less than 15um, so as to improve wiring density, reduce interconnection again
Length and the wiring number of plies so that chip ground electrode leads to the Distance Shortened of module ground pin, and radiating efficiency is carried
It is high.
The implementation process mentioned in the present embodiment can also realize with other processes, and for example chip electrode is upward
Bonding method.
Mainly application can include being not limited to mobile phone the utility model in rf terminal equipment, tablet personal computer,
Notebook computer, the Wireless Telecom Equipment of vehicle electronics, the Wireless Telecom Equipment of Internet of Things etc., it can also apply in other nothings
Among line communication equipment, including it is not limited to communication base station, satellite wireless communication, military Wireless Telecom Equipment etc..It is any
Change on physical circuit or chip layout way of realization, is included within the covering scope of this patent.
Claims (1)
1. a kind of multi-chip linear power amplifier structure without substrate high-cooling property, it is characterized in that including：Power amplifier chip
(110), CMOS chip (120) and several passive devices (130)；
The power amplifier chip (110), CMOS chip (120) and the back side of several passive devices (130) and surrounding are logical
Binding agent is crossed covered with plastic packaging layer (200), the power amplifier chip (110) and CMOS chip (120) and several are passive
The front of device (130) is covered with dielectric layer (300)；Multiple layer metal circuit layer (310) is included in the dielectric layer (300), and
With the power amplifier chip (110) and the input and output electrode (140) of CMOS chip (120) and several passive devices
(130) outer solder joint is connected；Outer pin pad (320) is set on the surface of the dielectric layer (300), and it is golden with the multilayer
Category circuit layer (310) is connected；Metal soldered ball (400) is welded with the outer pin pad (320)；So as to form single complete
The power amplifier module of whole function；Uniformly arranged by the power amplifier module of several single complete functions, so as to form multicore
Piece linear power amplifier structure.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201720099827.1U CN206460952U (en) | 2017-01-23 | 2017-01-23 | Multi-chip linear power amplifier structure without substrate high-cooling property |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201720099827.1U CN206460952U (en) | 2017-01-23 | 2017-01-23 | Multi-chip linear power amplifier structure without substrate high-cooling property |
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| Publication Number | Publication Date |
|---|---|
| CN206460952U true CN206460952U (en) | 2017-09-01 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106601702A (en) * | 2017-01-23 | 2017-04-26 | 合肥雷诚微电子有限责任公司 | Multi-chip linear power amplification structure without substrate and with high heat dissipation and manufacturing method thereof |
| CN110167316A (en) * | 2018-02-12 | 2019-08-23 | 三星电机株式会社 | The mounting structure of communication module and the communication module |
-
2017
- 2017-01-23 CN CN201720099827.1U patent/CN206460952U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106601702A (en) * | 2017-01-23 | 2017-04-26 | 合肥雷诚微电子有限责任公司 | Multi-chip linear power amplification structure without substrate and with high heat dissipation and manufacturing method thereof |
| CN110167316A (en) * | 2018-02-12 | 2019-08-23 | 三星电机株式会社 | The mounting structure of communication module and the communication module |
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