TW202002018A - Semiconductor structure and method for fabricating the same - Google Patents

Abstract

A method for fabricating a semiconductor structure includes providing a substrate. The method further includes implanting the substrate to form a high-voltage well region having a first conductivity type. The method further includes forming a pair of drain drift regions in the high-voltage well region. The pair of drain drift regions are on the front side of the substrate, and the pair of drain drift regions have a second conductivity type opposite to the first conductivity type. The method further includes forming a gate electrode embedded in the high-voltage well region. The gate electrode is positioned between the pair of drain drift regions and laterally spaced apart from the pair of drain drift regions.

Description

Semiconductor structure and its manufacturing method

The embodiments of the present invention relate to a semiconductor structure, and particularly to a semiconductor structure in which a gate electrode is embedded in a substrate.

High-voltage semiconductor components are widely used in high-voltage and high-power integrated circuits. Traditional high-voltage semiconductor devices include double diffused metal oxide semiconductors (DDMOS), lateral diffused metal oxide semiconductors (LDMOS), and extended-diffused metal oxide semiconductors, EDMOS). High-voltage semiconductor devices are compatible with traditional complementary metal oxide semiconductor (CMOS) processes and are therefore cost-effective. Therefore, high-voltage semiconductor devices are widely used in power supply, power management, display drive integrated circuits, communications, automotive electronics, and industrial control.

With the advancement of technology, the semiconductor industry continues to reduce the size of semiconductor components, and the demand for simple and effective components continues to increase. For high-voltage devices, in addition to cost-effectiveness, the drain-to-source on-resistance (Rdson) may also decrease as the device becomes smaller. However, the breakdown voltage may be reduced as a result.

Therefore, although the existing high-voltage components generally meet the needs, they are not satisfactory in all aspects, especially the smaller high-voltage components still need to be further improved.

An embodiment of the present invention provides a method for manufacturing a semiconductor structure, including: providing a substrate, implanting the substrate to form a high-pressure well region, having a first conductivity type, and forming a pair of drain drift regions in the high-pressure well region, wherein the drain drift regions Located on the front side of the substrate, and the drain drift region has a second conductivity type opposite to the first conductivity type; and forming a gate electrode embedded in the high-voltage well region, wherein the gate electrode is located between the drain drift region and the drain electrode The drift zone is horizontally separated.

Another embodiment of the present invention provides a semiconductor structure, including: a substrate; a high-pressure well region having a first conductivity type; a pair of drain drift regions located in the high-pressure well region, wherein the drain drift regions are located on the front side of the substrate, And the drain drift region has a second conductivity type opposite to the first conductivity type; the gate trench is located between the drain drift regions; and the gate electrode is embedded in the high voltage well region, wherein the gate electrode is located in the drain drift Between the zones, and laterally separated from the drain drift zone.

In order to make the above-mentioned objects, features and advantages of the present invention more obvious and understandable, a few embodiments are given below in conjunction with the accompanying drawings, which are described in detail below.

100, 100a, 200, 300 ‧‧‧ semiconductor structure

102‧‧‧ substrate

104‧‧‧High pressure well area

106‧‧‧ Jiji drift zone

108‧‧‧Gate trench

108B‧‧‧Bottom surface

108S‧‧‧Side wall surface

110‧‧‧Insulation

110a‧‧‧Insulation

112、112a‧‧‧Gate electrode

114‧‧‧Source/Drain

116‧‧‧Contact

206‧‧‧Drift zone

210‧‧‧Insulation

212‧‧‧Gate electrode

218‧‧‧Body area

220‧‧‧ Quarantine

306‧‧‧Drift zone

310‧‧‧Insulation

312‧‧‧Gate electrode

D‧‧‧Depth

θ‧‧‧angle

The embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings. It should be noted that according to standard practices in the industry, various features are not drawn to scale and are used for illustration only. In fact, the size of the element may be arbitrarily enlarged or reduced to clearly show the features of the embodiments of the present invention.

FIGS. 1 to 7 are schematic cross-sectional views illustrating different stages of forming a semiconductor structure according to some embodiments.

FIG. 8 is a schematic cross-sectional view of a semiconductor structure according to some embodiments.

FIG. 9 is a schematic cross-sectional view of a semiconductor structure according to some embodiments.

FIG. 10 is a schematic cross-sectional view of a semiconductor structure according to some embodiments.

Many different implementation methods or examples are disclosed below to implement different features of the embodiments of the present invention. The following describes specific embodiments of the elements and their arrangements to illustrate the embodiments of the present invention. Of course, these embodiments are for illustration only, and should not be used to limit the scope of the embodiments of the present invention. For example, it is mentioned in the specification that the first feature is formed on the second feature, which includes the embodiment where the first feature and the second feature are in direct contact, and also includes between the first feature and the second feature. An embodiment of the feature, that is, the first feature and the second feature are not in direct contact. In addition, repeated reference numerals or marks may be used in different embodiments. These repetitions are merely for describing the embodiments of the present invention simply and clearly, and do not mean that there is a specific relationship between the different embodiments and/or structures in question.

In addition, words that are relative to space may be used, such as "below", "below", "lower", "above", "higher", and similar terms. These spaces are relatively used In order to facilitate the description of the relationship between one (s) element or feature and another (s) element or feature in the illustration, these spatial relative terms include different orientations of the device in use or in operation, as well as in the drawings The described orientation. When the device is turned to different orientations (rotated 90 degrees or other orientations), the relative adjectives used in the space will also be interpreted according to the turned orientation.

Here, the terms “about”, “approximately” and “approximately” generally mean within 20% of a given value or range, preferably within 10%, and more preferably within 5%, or 3 Within %, or within 2%, or within 1%, or within 0.5%. It should be noted that the quantity provided in the description is an approximate quantity, that is, if there is no specific description of "about", "approximate", "approximately", "about", "approximate", "" "Approximately".

An embodiment of the present invention provides a high-voltage element, the gate electrode of which is embedded in a substrate. The embedded gate reduces the high-voltage components to reduce the on-resistance without affecting the breakdown voltage and critical voltage. The embedded gate is compatible with existing processes, and is suitable for various high-voltage devices such as double-diffused metal oxide semiconductor, laterally diffused metal oxide semiconductor, and extended-diffused metal oxide semiconductor.

FIGS. 1 to 7 are schematic cross-sectional views illustrating different stages of forming the semiconductor structure 100 according to some embodiments of the present invention. As shown in FIG. 1, the substrate 102 is provided. The substrate 102 may be a semiconductor substrate such as a Si substrate. In addition, the semiconductor substrate may also include other element semiconductors such as Ge; compound semiconductors such as GaN, SiC, GaAs, GaP, InP, InAs, and/or InSb; alloy semiconductors such as SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and/or Or GaInAsP, or a combination of the above. The substrate 102 may be a single-layer substrate or a multi-layer substrate. In addition, the substrate 102 may also be a semiconductor on insulator (SOI). The semiconductor overlying insulator substrate may be manufactured using a wafer bonding process, a silicon film conversion process, a separation by implantation of oxygen (SIMOX) process, other suitable methods, or a combination of the foregoing. In some embodiments, the substrate 102 has a first conductivity type. In some other embodiments, the substrate 102 has a second conductivity type. The second conductivity type is opposite to the first conductivity type. In some embodiments, the first conductivity type is P-type. For example, the substrate 102 may be a boron-doped substrate. In some other embodiments, the first conductivity type is N-type. For example, the substrate 102 may be a phosphorus-doped or arsenic-doped substrate.

In some embodiments, isolation features (not shown) are formed in the semiconductor substrate 102. The isolation feature is used to define the active area and electrically isolate different component parts in and/or on the semiconductor substrate 102 in the active area. In some embodiments, the isolation features include shallow trench isolation (STI) features, local oxidation of silicon (LOCOS) features, other suitable isolation features, or a combination of the foregoing. In some embodiments, the isolation features are filled with a dielectric material such as silicon oxide or silicon nitride. The isolation features can be formed in the following processes in sequence: forming an insulating layer on the substrate 102; selectively etching the insulating layer and the substrate 102 to form a trench in the substrate 102, and growing a liner layer rich in nitrogen (such as silicon oxynitride) in the trench On the bottom and sidewalls of the trench; filling the gap filling material (such as silicon dioxide or borophosphosilicate glass (BPSG) in the trench with a deposition process such as chemical vapor deposition (CVD)); Applying a thermal process to the gap filling material; and (using a planarization process such as chemical mechanical polishing (CMP) to planarize the substrate 102 to remove excess gap filling material, so the gap filling material in the trench and the substrate 102 The top surface is of equal height. It is worth noting that the above process is only an example, so the embodiments of the present invention are not limited thereto.

Next, doping the first conductivity type into the substrate 102 to form the high-pressure well region 104. The first conductivity type may be P-type dopants such as B, Ga, Al, In, BF ₃ ⁺ ions, or a combination of the foregoing. In addition, the first conductivity type may be N-type dopants such as P, As, N, Sb ions, or a combination thereof. The dopant concentration of the high-pressure well area 104 is in the range of about 1e14/cm ³ to 1e17/cm ³ . In some embodiments, the high-pressure well region 104 may be formed through a patterned mask (not shown) such as a patterned photoresist implant substrate 102. In some other embodiments, the patterned mask is a hard mask.

Next, according to some embodiments, as shown in FIG. 2, a pair of drain drift regions 106 is formed on the front side (or active side) of the substrate 102. In some embodiments, the pair of drain drift regions 106 has the second conductivity type. The dopant concentration of the pair of drain drift regions 106 is in the range of about 5e14/cm ³ to 1e17/cm ³ . The pair of drain drift regions 106 can be formed through a patterned mask with openings (not shown) to expose the implanted area. The pair of drain drift regions 106 can help maintain a high breakdown voltage of the high-voltage device.

Next, according to some embodiments, as shown in FIG. 3, a gate trench 108 is formed in the substrate between the pair of drain drift regions 106. In some embodiments, the gate trench 108 is formed by a lithography and etching process. The lithography process may include photoresist coating (such as spin coating), soft baking, alignment mask, exposure pattern, post-exposure baking, developing photoresist, and cleaning and drying (such as hard baking). The etching process may include a dry etching process (such as reactive ion etching (RIE), anisotropic plasma etching), a wet etching process, or a combination thereof. The depth D of the gate trench 108 as shown in FIG. 3 is between 0.25 μm and 0.75 μm. If the depth D is too shallow, it is difficult to maintain the same breakdown voltage and critical voltage as compared to a general planar device where the channel is approximately in the same geometric plane under the gate. On the other hand, if the depth D is too deep, the step coverage of the subsequent process may be poor.

As shown in FIG. 3, the gate trench 108 tapers toward the bottom surface 108B of the gate trench 108. In some embodiments, the angle θ between the sidewall surface 108S and the bottom surface 108B of the gate trench 108 is between 55 degrees and 85 degrees. If the angle θ is too steep, the step coverage of the subsequent process may be poor. If the angle θ is too gentle, it is difficult to maintain the same breakdown voltage and critical voltage as the planar device.

As shown in FIG. 3, the top edge of the gate trench 108 abuts the side walls of the pair of drain drift regions 106. That is, the top edge of the gate trench 108 is approximately aligned with the sidewalls of the pair of drain drift regions 106. If the top edge of the gate trench 108 is separated from the sidewalls of the pair of drain drift regions 106, the element size may increase, and the on-resistance may increase. If the top edge of the gate trench 108 overlaps the side walls of the pair of drain drift regions 106, the high breakdown voltage may not be maintained.

It is worth noting that the shape of the gate trench 108 is not particularly limited. Depending on the design requirements, it can be any shape such as inverted trapezoid, U-shaped, rectangular, etc.

Next, as shown in FIG. 4, an insulating layer 110 is compliantly formed on the bottom and side surfaces of the gate trench 108. The insulating layer 110 may be a gate dielectric layer. The insulating layer 110 may include silicon oxide. The silicon oxide can be formed by an oxidation process (such as a dry oxidation process or a wet oxidation process), a deposition process (such as a chemical vapor deposition process), other suitable processes, or a combination of the above. In some embodiments, the insulating layer 110 may be formed in a thermal process or an ultraviolet ozone oxidation process in an oxygen-containing environment or a nitrogen-containing environment (eg, NO or N ₂ O). In addition, the insulating layer 110 may include a high dielectric constant dielectric layer (for example, a dielectric constant greater than 3.9) such as hafnium oxide (HfO ₂ ). In addition, the high dielectric constant dielectric layer may include other high dielectric constant dielectric materials such as LaO, AlO, ZrO, TiO, Ta ₂ O ₅ , Y2O ₃ , SrTiO ₃ , BaTiO ₃ , BaZrO, HfZrO, HfLaO, HfTaO, HfSiO, HfSiON, HfTiO, LaSiO, AlSiO, BaTiO ₃ , SrTiO ₃ , Al ₂ O ₃ , other suitable high dielectric constant dielectrics, or a combination of the above. The high dielectric constant dielectric layer can be chemical vapor deposition process (CVD) (such as plasma enhanced chemical vapor deposition (PECVD), metalorganic chemical vapor deposition process (metalorganic chemical vapor deposition, MOCVD), or high-density plasma chemical vapor deposition (HDPCVD)), atomic layer deposition (ALD) (such as plasma-enhanced atomic layer deposition (plasma enhanced atomic layer deposition (PEALD)), physical vapor deposition (PVD) (such as vacuum evaporation process or sputtering process), other suitable processes, or a combination of the above. The thickness of the insulating layer 110 is between 110Å and 700Å.

Next, as shown in FIG. 5, the gate electrode 112 is formed in the gate trench 108. Thus, the gate electrode 112 is embedded in the high-pressure well region 104 interposed between the pair of drain drift regions 106. The gate electrode 112 may include polysilicon, polysilicon germanium, metals (such as tungsten, titanium, aluminum, copper, molybdenum, nickel, platinum, etc., or a combination of the above, metal alloys, metal nitrides (such as tungsten nitride, molybdenum nitride, Titanium nitride, tantalum nitride, etc., or a combination thereof), metal silicides (e.g. tungsten silicide, titanium silicide, cobalt silicide, nickel silicide, titanium silicide, erbium silicide, etc., or a combination of the above), metal oxides ( For example, ruthenium oxide, indium tin oxide, etc., or a combination of the above), other suitable materials, or a combination of the above. In some embodiments, the gate electrode 112 is a single-layer gate electrode material. In some other embodiments, The gate electrode 112 may be a multi-layer stack including two or more gate electrode materials. The gate electrode 112 may be a chemical vapor deposition (CVD) process (such as low-pressure chemical vapor deposition, LPCVD) or plasma enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD) (such as vacuum evaporation process or sputtering process), other suitable processes, or The above combination is formed. After deposition, a chemical mechanical polishing (CMP) process or an etch-back process can be selectively performed to remove excess gate electrode material. In some embodiments, the gate electrode 112 is A pair of drain drift regions 106 are laterally separated. If the gate electrode 112 is too close to the pair of drain drift regions 106, a high breakdown voltage may not be maintained.

As shown in FIG. 5, in some embodiments, the top surface of the gate electrode 112 is coplanar with the top surface of the substrate 102. In some other examples, the gate electrode 112 may overfill the gate trench 108 and protrude beyond the top surface of the substrate 102.

It is worth noting that the order of forming the drain drift region 106 and the gate electrode 112 can be reversed. In some embodiments, a pair of drain drift regions 106 is formed before the gate electrode 112. In other embodiments, the gate electrode 112 is formed before the pair of drain drift regions 106.

Next, as shown in FIG. 6, source/drain regions 114 are formed in the pair of drain drift regions 106. In some embodiments, the source/drain region 114 has a second conductivity type. Compared with a pair of drain drift regions 106, the source/drain regions 114 are shallower and farther away from the gate structure. The dopant concentration of the source/drain region 114 is between about 5e17/cm ³ and 5e20/cm ³ . In some embodiments, the source/drain regions 114 are implanted with a patterned mask (not shown).

Next, as shown in FIG. 7, a contact 116 is formed on the source/drain region 114. In some embodiments, the contact 116 may include Ti, Al, Au, Pd, Cu, W, other suitable materials, metal alloys, polysilicon, other suitable conductive materials, or a combination thereof. In some embodiments, chemical vapor deposition (CVD), physical vapor deposition (PVD) (eg, resistance heating evaporation or sputtering), electroplating, atomic layer deposition Deposition, ALD), other suitable processes, or a combination of the above forms contact materials on the source/drain regions 114. Next, the contact material is patterned by lithography and etching processes to form the contact 116. Then, a chemical mechanical polishing process or an etch-back process is selectively performed to remove excess contact material.

Compared with the planar device, the gate electrode 112 in the embodiment of the present invention is embedded in the high-voltage well region 104. Therefore, when the device size is reduced, the effective channel length can be maintained unchanged. Therefore, having the embedded gate electrode 112 can maintain the breakdown voltage and the threshold voltage unchanged. As the device size decreases, the distance between the source and drain regions 114 also decreases. Therefore, the drain-to-source on-resistance (Rdson) can also be reduced. In some embodiments, the on-resistance of the high-voltage device with embedded gate electrode 112 can be reduced by more than 25% compared to the planar high-voltage device. In addition, as the device size becomes smaller, the overall die size can also be reduced.

The process in the embodiment of the present invention is compatible with the existing high-pressure process. In some embodiments, only an additional patterned mask is needed to form the gate trench 108, so no major modification of the semiconductor capital equipment is required.

Many changes and/or adjustments can be made in the embodiments of the present invention. FIG. 8 is a schematic cross-sectional view of forming a semiconductor structure 100a according to other embodiments. Unless otherwise noted, the materials and methods used to form the parts in these embodiments are the same as those used to form the parts depicted in Figures 1-7. The same reference numbers are generally used to indicate corresponding or similar features in adjustments or different embodiments. As shown in FIG. 8, the gate electrode 112 a and the insulating layer 110 a extend out of the gate trench 108 and cover part of the pair of drain drift regions 106. The processes and materials used to form the semiconductor structure 100a may be similar to or the same as those used to form the semiconductor structure 100, and are not repeated here.

As shown in FIG. 8, according to some embodiments, the gate electrode 112a and the insulating layer 110a extend out of the gate trench and cover a part of the pair of drain drift regions 106. Due to the increased gate area, when the gate electrode 112a and the insulating layer 110a extend out of the gate trench 108, the gate resistance can be reduced.

The embedded gate of the embodiment of the present invention is also applicable to other high-voltage devices such as lateral diffused metal oxide (LDMOS). FIG. 9 is a schematic cross-sectional view of forming a semiconductor structure 200 according to some embodiments regarding laterally diffused metal oxide semiconductors.

As shown in FIG. 9, according to some embodiments, the semiconductor structure 200 includes a substrate 102 having a first or second conductivity type, a drift region 206 having a second conductivity type, a body region 218 having a first conductivity type, including The embedded gate structure of the insulating layer 210 and the gate electrode 212. The embedded gate structure is embedded in the body region 218 and the drift region 206. The semiconductor structure 200 further includes a source/drain region 114 having a second conductivity type, located on both sides of the gate structure. The contact 116 is formed on the source/drain region 114. The isolation region 220 is located on the drift region 206 between the drain region 114 and the gate structure. In addition, the embedded gate electrode 212 extends out of the gate trench and covers a part of the isolation region 220. The processes and materials used to form the semiconductor structure 200 may be similar to or the same as those used to form the semiconductor structure 100, and are not repeated here.

Since the gate electrode 212 is embedded in the body region 218 and the drift region 206, the effective channel length can be maintained when the device size is reduced. Therefore, having the embedded gate electrode 212 can maintain the breakdown voltage and the threshold voltage unchanged. As the device size decreases, the distance between the source and drain regions 114 also decreases. Therefore, the drain-to-source on-resistance (Rdson) can also be reduced. In some embodiments, the on-resistance of the high-voltage device with embedded gate electrode 112 can be reduced by more than 25% compared to the planar high-voltage device. In addition, as the element size becomes smaller, the overall grain size can also be reduced.

FIG. 10 is a schematic cross-sectional view of forming a semiconductor structure 300 according to some embodiments regarding extended-diffused metal oxide semiconductors (EDMOS). The semiconductor structure 300 is an extended diffusion metal oxide semiconductor similar to the semiconductor structure 100 except that a drift region is provided only on one side of the trench gate.

According to some embodiments, as shown in FIG. 10, the semiconductor structure 300 includes a substrate 102 having a first or second conductivity type, a high voltage well region 104 having a first conductivity type, a drift region 306 having a second conductivity type, An embedded gate structure including an insulating layer 310 and a gate electrode 312. The semiconductor structure 300 further includes a source/drain region 114 having a second conductivity type, located on both sides of the gate structure. On one side (the left side of the embodiment in FIG. 10), the top edge of the gate trench abuts the side wall of one of the source/drain regions 114. On the other side (the right side of the embodiment in FIG. 10), the top edge of the gate trench abuts the side wall of the drift region 306. The contact 116 is formed on the source/drain region 114. The manufacturing process and components are only briefly described and not repeated here.

Since the gate electrode 312 is embedded in the high-pressure well region 104, the effective channel length can be maintained when the device size is reduced. Therefore, having the embedded gate electrode 312 can maintain the breakdown voltage and the threshold voltage unchanged. As the device size decreases, the distance between the source and drain regions 114 also decreases. Therefore, the drain-to-source on-resistance (Rdson) can also be reduced. In some embodiments, the on-resistance of the high-voltage device with embedded gate electrode 312 can be reduced by more than 25% compared to the planar high-voltage device. In addition, as the device size becomes smaller, the overall die size can also be reduced.

Therefore, the embedded gate structure described in the embodiments of the invention is widely used in different high-voltage devices, such as extended-diffused metal oxide semiconductors (EDMOS) and double-diffused metal oxide semiconductors (double diffused metal oxide semiconductors (DDMOS) and lateral diffused metal oxide semiconductors (LDMOS). The extended diffusion metal oxide semiconductor has a drain drift region on the drain side to help reduce the hot carrier effect and help improve reliability. The double-diffused metal oxide semiconductor has a drain drift region on the source side and the drain side, and its reliability is higher. Laterally diffused metal oxide semiconductors can withstand higher voltages, so the operating voltage can be higher.

As described above, in the embodiments of the present invention, the gate electrode is embedded in the substrate of the high-voltage element. When the device size shrinks, the effective channel length increases, and the breakdown voltage and threshold voltage can be maintained unchanged. As the component size is reduced, the on-resistance can be reduced by more than 25%. At the same time, as the device size becomes smaller, the overall die size can also be reduced. The embedded gate process is compatible with traditional high-voltage processes, and only requires an additional mask to form the gate trench. The embedded gate can be suitable for different high voltage devices such as double diffused metal oxide semiconductor (DDMOS), lateral diffused metal oxide semiconductor (LDMOS), and extended diffused metal oxide semiconductor (extended-diffused metal oxide semiconductors, EDMOS).

The above description summarizes the features of many embodiments, so anyone with ordinary knowledge in the technical field can more fully understand the aspects of the embodiments of the present invention. Any person with ordinary knowledge in the technical field may design or modify other processes and structures based on the embodiments of the present invention without difficulty to achieve the same purposes and/or advantages as the embodiments of the present invention. Any person with ordinary knowledge in the technical field should also understand that different changes, substitutions, and modifications can be made without departing from the spirit and scope of the embodiments of the present invention. Such an equivalent creation does not exceed the spirit and scope of the embodiments of the present invention.

100‧‧‧Semiconductor structure

102‧‧‧ substrate

104‧‧‧High pressure well area

106‧‧‧ Jiji drift zone

110‧‧‧Insulation

112‧‧‧Gate electrode

114‧‧‧Source/Drain

116‧‧‧Contact

Claims (20)

A method for manufacturing a semiconductor structure includes: providing a substrate; implanting the substrate to form a high-voltage well (HVW) with a first conductivity type; forming a pair of drain drift regions in the high-pressure well In the region, wherein the pair of drain drift regions is located on a front side of the substrate, and the pair of drain drift regions has a second conductivity type opposite to the first conductivity type; and forming a gate electrode embedded in the high-pressure well region In which the gate electrode is located between the pair of drain drift regions and is laterally separated from the pair of drain drift regions. The method for manufacturing a semiconductor structure as described in item 1 of the patent application scope, wherein a top surface of the gate electrode is coplanar with a top surface of the substrate. The method for manufacturing a semiconductor structure as described in item 1 of the patent application scope, wherein the gate electrode is formed before the pair of drain drift regions is formed. The method for manufacturing a semiconductor structure as described in item 1 of the patent application range, wherein the pair of drain drift regions is formed before the gate electrode is formed. The method for manufacturing a semiconductor structure as described in item 1 of the scope of the patent application further includes: etching the substrate between the pair of drain drift regions to form a gate trench. The method for manufacturing a semiconductor structure as described in item 5 of the patent application scope, wherein the top edge of the gate trench is adjacent to the sidewall of the pair of drain drift regions. The method for manufacturing a semiconductor structure as described in item 5 of the patent application scope, wherein the gate electrode extends out of the gate trench and covers a part of the pair of drain drift regions. The method for manufacturing a semiconductor structure as described in item 5 of the patent application range, wherein the gate trench tapers toward a bottom surface of the gate trench. The method for manufacturing a semiconductor structure as described in item 5 of the patent application scope, wherein an angle between a side wall surface and a bottom surface of the gate trench is between 55 degrees and 85 degrees. The method for manufacturing a semiconductor structure as described in item 5 of the patent application range, wherein a depth of the gate trench is between 0.25 μm and 0.75 μm. The method for manufacturing a semiconductor structure as described in item 5 of the scope of the patent application further includes: conformably forming an insulating layer on a bottom and a side wall of the gate trench. The method for manufacturing a semiconductor structure as described in item 11 of the patent application range, wherein the insulating layer is formed by oxidation. The method for manufacturing a semiconductor structure as described in item 11 of the patent application range, wherein the insulating layer has a thickness between 110Å and 700Å. The method for manufacturing a semiconductor structure as described in item 1 of the patent scope further includes: implanting the substrate to form a source/drain region in the pair of drain drift regions, wherein the source/drain region is located at the The front side of the substrate, and the source/drain region has the second conductivity type; and a contact is formed on the source/drain region. A semiconductor structure includes: a substrate; a high-pressure well region with a first conductivity type; a pair of drain drift regions located in the high-pressure well region, wherein the pair of drain drift regions are located on a front side of the substrate, and The pair of drain drift regions has a second conductivity type opposite to the first conductivity type; a gate trench between the pair of drain drift regions; and a gate electrode embedded in the high-pressure well region, The gate electrode is located between the pair of drain drift regions and is laterally separated from the pair of drain drift regions. The semiconductor structure as recited in item 15 of the patent application range, wherein a top surface of the gate electrode is coplanar with a top surface of the substrate. The semiconductor structure as recited in item 15 of the patent application range, wherein the top edge of the gate trench is adjacent to the sidewall of the pair of drain drift regions. The semiconductor structure as described in item 15 of the patent application range, wherein the gate trench tapers toward a bottom surface of the gate trench. The semiconductor structure described in item 15 of the patent application scope further includes: an insulating layer compliantly located on a bottom and a side wall of the gate trench. The semiconductor structure as described in item 15 of the patent application scope further includes: a source/drain region located in the pair of drain drift regions, wherein the source/drain region has the second conductivity type; and a connection Point, located on the source/drain region.

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