TWI575734B - Semiconductor device and method of manufacturing the same - Google Patents

Description

Semiconductor device and method of manufacturing same

The present disclosure relates to semiconductor technology, and in particular to semiconductor devices and methods of fabricating the same.

The high voltage semiconductor device technology is suitable for the field of high voltage and high power integrated circuits. Conventional high voltage semiconductor devices, such as laterally diffused metal oxide semiconductor (LDMOS) devices, are mainly used in component applications above 18V. The advantages of high-voltage device technology are cost-effective and easy to be compatible with other processes, and have been widely used in display driver IC components, power supplies, power management, communications, automotive electronics or industrial control.

Generally, a high voltage semiconductor device uses an N-type metal oxide semiconductor (NMOS) instead of a P-type metal oxide semiconductor (PMOS), and the N-type gold oxide semiconductor is usually provided on a P-type substrate. However, current semiconductor devices such as high voltage semiconductor devices are not satisfactory in all respects. For example, in order to simultaneously provide an N-type MOS and a P-type MOS on a P-type substrate, it is conventional to use one or more epitaxial processes to form a P-type MOS on a P-type substrate. However, this process step is difficult and the process cost is high.

Therefore, the industry still needs a manufacturing method that is simple in process, low in process cost, and can form a P-type MOS on a P-type substrate, so that the invention Those of ordinary skill in the art can simultaneously provide N-type MOS and P-type MOS on a P-type substrate without increasing excessive process cost.

The present disclosure provides a semiconductor device including: a first conductive type substrate; a second conductive type body region disposed in the first conductive type substrate, wherein the first conductive type is different from the second conductive type; the first conductive type first well The region is disposed in the second conductive type body region; the gate structure is disposed on the upper surface of the first conductive type substrate; the source region, wherein the source region includes the first conductive type heavily doped source region, and the system And disposed in the second conductive type body region; and the drain region, wherein the drain region has a heavily doped first conductivity type and is disposed in the first conductivity type first well region.

The present disclosure further provides a method of fabricating a semiconductor device, comprising: providing a first conductive type substrate; forming a second conductive type body region in the first conductive type substrate, wherein the first conductive type is different from the second conductive type; forming the first a conductive first well region is formed in the second conductive type body region; a gate structure is formed on the upper surface of the first conductive type substrate; a source region is formed, wherein the source region includes the first conductive type heavily doped source region And being disposed in the second conductive type body region; and forming a drain region, wherein the drain region has a heavily doped first conductivity type and is disposed in the first conductivity type first well region.

In order to make the features and advantages of the present disclosure more comprehensible, the preferred embodiments are described below, and are described in detail below with reference to the accompanying drawings.

100‧‧‧First Conductive Substrate

100S1‧‧‧ upper surface

100S2‧‧‧ lower surface

102‧‧‧Second conductive body area

104A‧‧‧First Conductive First Well Area

104B‧‧‧First Conductive Second Well Area

104C‧‧‧First Conductive Third Well Area

106A‧‧‧First Conductive Type First Doped Area

106B‧‧‧First Conductive Type Second Doped Area

108‧‧‧Field oxide layer

108A‧‧‧ openings

110‧‧‧ gate structure

110A‧‧‧gate dielectric layer

110B‧‧‧gate electrode

112‧‧‧ source area

112A‧‧‧First Conductive Heavy Doped Source Region

112B‧‧‧Second Conductive Heavy Doped Source Region

114‧‧‧Bungee Area

116‧‧‧First Conductive Channel Area

118‧‧‧Second Conductive Heavy Doped Zone

120‧‧‧First Conductive Heavy Doped Zone

122‧‧‧Interlayer dielectric layer

124D‧‧‧bend contact plug

124S1‧‧‧First source contact plug

124S2‧‧‧Second source contact plug

124A‧‧‧Contact plug

124B‧‧‧ body contact plug

126D‧‧‧ wire

126S‧‧‧ wire

126B‧‧‧Wire

128‧‧‧Protective layer

130D‧‧‧Electrical mat

130S‧‧‧Electrical mat

200‧‧‧Semiconductor device

1 is a cross-sectional view showing a semiconductor device in one step of a method of fabricating a semiconductor device according to some embodiments of the present disclosure.

2 is a cross-sectional view showing a semiconductor device in one step of a method of fabricating a semiconductor device according to some embodiments of the present disclosure.

3 is a cross-sectional view showing a semiconductor device in one step of a method of fabricating a semiconductor device according to some embodiments of the present disclosure.

4 is a cross-sectional view showing a semiconductor device in one step of a method of fabricating a semiconductor device according to some embodiments of the present disclosure.

Hereinafter, the semiconductor device and the method of manufacturing the same will be described in detail. It will be appreciated that the following description provides many different embodiments or examples for implementing the various aspects of the disclosure. The specific elements and arrangements described below are merely illustrative of the disclosure. Of course, these are only used as examples and not as a limitation of the disclosure. Moreover, repeated numbers or labels may be used in different embodiments. These repetitions are merely for the purpose of simplicity and clarity of the disclosure, and are not intended to be a limitation of the various embodiments and/or structures discussed. Furthermore, when a first material layer is on or above a second material layer, the first material layer is in direct contact with the second material layer. Alternatively, it is also possible to have one or more layers of other materials interposed, in which case there may be no direct contact between the first layer of material and the second layer of material.

In addition, relative terms such as "lower" or "bottom" and "higher" or "top" may be used in the embodiments to describe the relative relationship of one element of the drawing to another. It will be understood that if the device of the drawing is flipped upside down, the component described on the "lower" side will become the component on the "higher" side.

Here, the terms "about", "about" and "major" are usually expressed in Within 20% of a given value or range, preferably within 10%, and more preferably within 5%, or within 3%, or within 2%, or within 1%, or 0.5% Within, or within 0.3%. The quantity given here is an approximate quantity, that is, in the absence of specific descriptions of "about", "about" and "major", the meanings of "about", "about" and "major" may still be implied.

It will be understood that the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers, and/or portions, such elements, components, and regions. The layers, and/or portions are not to be limited by the terms, and the terms are used to distinguish different elements, components, regions, layers, and/or parts. Therefore, a first element, component, region, layer, and/or portion discussed below may be referred to as a second element, component, region, layer, and/or without departing from the teachings of the disclosure. section.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning meaning It will be understood that these terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with the relevant art and the context or context of the present disclosure, and should not be in an idealized or overly formal manner. Interpretation, unless specifically defined in this disclosure.

The embodiments of the present disclosure can be understood in conjunction with the drawings, and the drawings of the present disclosure are also considered as part of the disclosure. It should be understood that the drawings of the present disclosure are not shown in the form of actual devices and components. The shapes and thicknesses of the embodiments may be exaggerated in the drawings in order to clearly illustrate the features of the present disclosure. In addition, the structures and devices in the drawings are schematically illustrated in order to clearly illustrate the features of the disclosure.

In this disclosure, relative terms such as "lower", "upper", "horizontal", "vertical", "lower", "above", "top", "bottom", etc. shall be understood as The orientation shown in the paragraph and related schemas. This relative term is used for convenience of description only, and does not mean that the device described therein is to be manufactured or operated in a particular orientation. Terms such as "joining" and "interconnecting", etc., unless otherwise defined, may mean that two structures are in direct contact, or that two structures are not in direct contact, and other structures are provided here. Between the two structures. The term "joining and joining" may also include the case where both structures are movable or both structures are fixed.

It should be noted that the term "substrate" may be used hereinafter to include formed elements on a semiconductor wafer and various film layers overlying the wafer, and any desired semiconductor elements may have been formed thereon, but here Simplified drawing, represented only by a flat substrate. In addition, the "substrate surface" includes the uppermost and exposed film layer on the semiconductor wafer, such as a germanium surface, an insulating layer, and/or metal lines.

The disclosed embodiment utilizes a novel doped region configuration provided in a P-type substrate to form a P-type MOS in a P-type substrate, and cooperates with a conventional technique for forming an N-type MOS in a P-type substrate. N-type MOS and P-type MOS can be simultaneously provided in the P-type substrate.

In addition, since the embodiment of the present disclosure is to form a P-type MOS in the P-type substrate by changing the configuration of the doped region of the semiconductor device, the process steps of the disclosed embodiment are simple, and the reticle can be omitted. In the case of the number and the excessive process cost, even if the cost is not increased, the N-type MOS and the P-type MOS are simultaneously provided in the P-type substrate.

1 is a cross-sectional view showing a semiconductor device in one step of a method of fabricating a semiconductor device according to some embodiments of the present disclosure. As shown in FIG. 1, first, the first conductive type substrate 100 is provided. The first conductive type substrate 100 may be a semiconductor substrate such as a germanium substrate. In addition, the semiconductor substrate may also be an elemental semiconductor, including germanium; a compound semiconductor including gallium nitride (GaN), silicon carbide, gallium arsenide, gallium phosphide ( Gallium phosphide, indium phosphide, indium arsenide and/or indium antimonide; alloy semiconductors including bismuth alloy (SiGe), phosphorus gallium arsenide (GaAsP), arsenic Aluminum indium alloy (AlInAs), arsenic aluminum gallium alloy (AlGaAs), arsenic gallium alloy (GaInAs), indium gallium alloy (GaInP) and/or phosphorus indium gallium alloy (GaInAsP) or a combination thereof. Further, the first conductive type substrate 100 may be a semiconductor on insulator. In some embodiments, the first conductive type substrate 100 can be a lightly doped P-type substrate.

In the embodiment, "lightly doped" means a doping concentration of about 10 ¹¹ -10 ¹³ /cm ³ , for example, a doping concentration of about 10 ¹² /cm ³ . However, it will be appreciated by those of ordinary skill in the art that the definition of "lightly doped" can also be determined by the particular device type, technology generation, minimum component size, and the like. Thus, the definition of "lightly doped" is re-evaluated based on technical content and is not limited by the embodiments presented herein.

Continuing to refer to FIG. 1, a second conductive type body region 102 is formed in the first conductive type substrate 100. This second conductivity type is different from the first conductivity type. For example, in some embodiments of the present disclosure, the second conductivity type is an N type and the first conductivity type is a P type.

The second conductive type body region 102 can be formed by ion implantation step to make. For example, when the second conductivity type is an N-type, phosphorus ions or arsenic ions may be implanted in a region where the second conductivity type body region 102 is to be formed to form the second conductivity type body region 102. In addition, the second conductive type body region 102 can directly contact the upper surface 100S1 of the first conductive type substrate 100.

It should be noted that in the described embodiment, if not specifically referred to as "lightly doped" or "heavily doped", "doping" means a doping concentration of about 10 ¹⁴ -10 ¹⁶ /cm ³ , for example It is a doping concentration of about 10 ¹⁵ /cm ³ . In other words, in some embodiments, the doping concentration of the second conductive type body region 102 may be a doping concentration of about 10 ¹⁴ -10 ¹⁶ /cm ³ , for example, about 10 ¹⁵ /cm ³ . However, it will be appreciated by those of ordinary skill in the art that the definition of "doping" can also be determined by the particular device type, technical generation, minimum component size, and the like. Thus, the definition of "doping" is re-evaluated based on technical content and is not limited by the embodiments presented herein.

2 is a cross-sectional view showing a semiconductor device in one step of a method of fabricating a semiconductor device according to some embodiments of the present disclosure. As shown in FIG. 2, the first conductive type first well region 104A and the first conductive type second well region 104B are formed in the second conductive type body region 102, and the first conductive type substrate 100 is not formed in the first conductive type substrate 100. A first conductivity type third well region 104C is formed in a region of the second conductive type body region 102. In some embodiments of the present disclosure, the first conductive type first well region 104A and the first conductive type third well region 104C are respectively disposed on opposite sides of the first conductive type second well region 104B.

In some embodiments of the present disclosure, the first conductive type first well region 104A, the first conductive type second well region 104B, and the first conductive type third well region 104C may directly contact the upper surface of the first conductive type substrate 100. 100S1. In addition, the first conductive type third well region 104C can directly contact the second conductive type body region 102, such as the second The figure shows.

In some embodiments of the present disclosure, the first conductive type first well region 104A, the first conductive type second well region 104B, and the first conductive type third well region 104C may be formed by an ion implantation step. For example, when the first conductivity type is a P-type, it may be implanted in a region where the first conductivity type first well region 104A, the first conductivity type second well region 104B, and the first conductivity type third well region 104C are formed. Boron ions, indium ions or boron difluoride ions (BF ₂ ⁺ ) to form a first conductivity type first well region 104A, a first conductivity type second well region 104B, and a first conductivity type third well region 104C.

In addition, in some embodiments of the present disclosure, the doping concentration of the first conductive type first well region 104A, the first conductive type second well region 104B, and the first conductive type third well region 104C may be about 10 ¹⁴ - The doping concentration of 10 ¹⁶ /cm ³ is, for example, about 10 ¹⁵ /cm ³ . The doping concentration of the first conductive type first well region 104A, the first conductive type second well region 104B and the first conductive type third well region 104C is greater than the doping concentration of the second conductive type body region 102.

Continuing to refer to FIG. 2, a first conductivity type first doping region 106A and a first conductivity type second doping region 106B are formed in the second conductivity type body region 102. In some embodiments of the present disclosure, as shown in FIG. 2, the first conductive type first doping region 106A is disposed between the first conductive type first well region 104A and the first conductive type second well region 104B. And directly contacting the first conductivity type first well region 104A and the first conductivity type second well region 104B. The first conductive type first well region 104A and the first conductive type second well region 104B are electrically connected by the first conductive type first doping region 106A, and the first conductive type first doping region 106A is not The upper surface 100S1 of the first conductive type substrate 100 and the subsequent field oxide layer are contacted.

Moreover, in some embodiments of the disclosure, the first conductivity type described above The second doped region 106B is disposed between the first conductive type second well region 104B and the first conductive type third well region 104C, and the first conductive type second doped region 106B contacts only the second conductive type body The region 102 is not in contact with the other doped regions shown in FIG. 2 and any subsequent doped regions. In other words, the first conductive type second doped region 106B is not electrically connected to any other doped regions, and forms a reduced surface field (RESURF) structure with the second conductive type body region 102. The disclosed embodiment can further reduce the surface electric field in the device by thereby reducing the surface electric field structure, and thereby further increase the breakdown voltage of the device.

In addition, in some embodiments of the present disclosure, the first conductive type second doping region 106B also does not contact the upper surface 100S1 of the first conductive type substrate 100 and the subsequent field oxide layer.

In addition, in some embodiments of the present disclosure, the first conductive type first doping region 106A and the first conductive type second doping region 106B may have a doping concentration of about 10 ¹⁴ -10 ¹⁶ /cm ³ . concentration, for example from about 10 ¹⁵ / cm ^3. In addition, the doping concentration of the first conductive type first well region 104A, the first conductive type second well region 104B, and the first conductive type third well region 104C is greater than the first conductive type first doped region 106A and the first The doping concentration of the first conductivity type first doping region 106A and the first conductivity type second doping region 106B is greater than the second conductivity type body region 102 Doping concentration.

Next, referring to FIG. 3, a field oxide layer 108 is formed on the upper surface 100S1 of the first conductive type substrate 100. The material of the field oxide layer 108 may include ruthenium oxide. In some embodiments of the present disclosure, the field oxide layer 108 may be formed on the upper surface 100S1 of the first conductive type substrate 100 by thermal oxidation. However, in other embodiments of the present disclosure, the field oxide layer 108 may also be formed by chemical vapor deposition. (CVD) or spin coating and patterning steps are formed.

Next, a gate structure 110 is formed on the upper surface 100S1 of the first conductive type substrate 100. The gate structure 110 includes a gate dielectric layer 110A and a gate electrode 110B formed on the gate dielectric layer 110A. In detail, the gate structure 110 is formed on the first conductive type second well region 104B and the field oxide layer 108 in contact with the first conductive type second well region 104B. Since the field oxide layer 108 has a height difference from the upper surface 100S1 of the first conductive type substrate 100, and the height difference between the field oxide layer 108 and the gate dielectric layer 110A, the gate structure 110 (or the gate) The electrode 110B) has a stepped shape. In addition, the first conductive type second well region 104B is located under the gate structure 110.

The material of the gate dielectric layer 110A may be tantalum oxide, tantalum nitride, hafnium oxynitride, a high-k dielectric material, or any other suitable dielectric material, or a combination thereof. The material of the high-k dielectric material may be a metal oxide, a metal nitride, a metal halide, a transition metal oxide, a transition metal nitride, a transition metal telluride, a metal oxynitride, Metal aluminate, zirconium silicate, zirconium aluminate. For example, the high-k dielectric material may be LaO, AlO, ZrO, TiO, Ta ₂ O ₅ , Y ₂ O ₃ , SrTiO ₃ (STO), BaTiO ₃ (BTO), BaZrO, HfO. ₂ , HfO ₃ , HfZrO, HfLaO, HfSiO, HfSiON, LaSiO, AlSiO, HfTaO, HfTiO, HfTaTiO, HfAlON, (Ba, Sr)TiO ₃ (BST), Al ₂ O ₃ , other high dielectric constants of other suitable materials Dielectric material, or a combination of the above. The gate dielectric layer 110A can be formed by thermal oxidation, chemical vapor deposition (CVD) or spin coating. The chemical vapor deposition method can be, for example, low pressure chemical vapor deposition (LPCVD), low temperature chemical vapor deposition (LTCVD), or rapid temperature chemical vapor deposition (rapid). Thermal chemical vapor deposition (RTCVD), plasma assisted chemical vapor deposition (PECVD), atomic layer chemical vapor deposition (atomic layer deposition (ALD) or other commonly used methods .

The material of the gate electrode 110B may be amorphous germanium, a germanium germanium, one or more metals, a metal nitride, a conductive metal oxide, or a combination thereof. The above metals may include, but are not limited to, molybdenum, tungsten, titanium, tantalum, platinum or hafnium. The above metal nitrides may include, but are not limited to, molybdenum nitride, tungsten nitride, titanium nitride, and tantalum nitride. The above conductive metal oxide may include, but is not limited to, ruthenium oxide and indium tin oxide. The material of the gate electrode 110B can be formed by the aforementioned chemical vapor deposition (CVD), sputtering, resistance heating evaporation, electron beam evaporation, or any other suitable deposition method, for example, in one In an embodiment, an amorphous germanium conductive material layer or a polycrystalline germanium conductive material layer may be deposited by low pressure chemical vapor deposition (LPCVD) at a temperature between 525 and 650 ° C, and may have a thickness ranging from about 1000 Å to about 10,000 Å.

Next, referring to FIG. 3, the source region 112 is formed in the second conductive type body region 102, and the drain region 114 is formed in the first conductive type first well region 104A. The source region 112 and the drain region 114 are respectively disposed on opposite sides of the gate structure 110. In some embodiments of the disclosure, the source region 112 is disposed in the gate structure 110 and the first conductive type second doping region 106B or the first conductive type third well region. Between 104C.

The drain region 114 has a heavily doped first conductivity type, and the source region 112 includes a first conductivity type heavily doped source region 112A and a second conductivity directly contacting the first conductivity type heavily doped source region 112A. Type heavily doped source region 112B. The first conductive type heavily doped source region 112A is closer to the gate structure 110, and the second conductive type heavily doped source region 112B is farther from the gate structure 110.

In some embodiments of the present disclosure, the drain region 114 and the first conductivity type heavily doped source region 112A may be formed by an ion implantation step. For example, when the first conductivity type is a P-type, boron ions, indium ions or boron difluoride ions (BF) may be implanted in a region where the gate region 114 and the first conductivity type heavily doped source region 112A are formed. ₂ ⁺ ) to form the drain region 114 and the first conductivity type heavily doped source region 112A.

Moreover, in some embodiments of the present disclosure, the second conductivity type heavily doped source region 112B may be formed by an ion implantation step. For example, when the second conductivity type is N-type, phosphorus ions or arsenic ions may be implanted in a region where the second conductivity type heavily doped source region 112B is formed to form the second conductivity type heavily doped source region 112B. .

In the illustrated embodiment, "heavily doped" means a doping concentration in excess of about 10 ¹⁹ /cm ³ , such as a doping concentration of from about 10 ¹⁹ /cm ³ to about 10 ²¹ /cm ³ . However, it will be appreciated by those of ordinary skill in the art that the definition of "heavily doped" can also be determined by the particular device type, technical generation, minimum component size, and the like. Thus, the definition of "heavily doped" is re-evaluated based on technical content and is not limited by the embodiments presented herein.

In addition, the gate structure 110 has a first conductive type channel region 116 under it. The first conductive type channel region 116 is located in the first conductive type heavily doped source The first conductive type substrate 100 (or in the second conductive type body region 102) between the polar region 112A and the first conductive type second well region 104B. In some embodiments of the present disclosure, when the first conductivity type is a P type and the second conductivity type is an N type, the first conductive type channel region 116 is a P-type channel, and at this time, the gate structure 110 and the source are The polar region 112 and the drain region 114 together form a P-type MOS, and the first conductive substrate 100 is a P-type substrate.

Therefore, the disclosed embodiment can form a P-type MOS in the P-type substrate by using a novel doped region configuration provided in the P-type substrate, and form a N-type gold oxide in the P-type substrate. In the semiconductor technology, an N-type MOS and a P-type MOS can be simultaneously provided in a P-type substrate.

In addition, since the embodiment of the present disclosure is to form a P-type MOS in the P-type substrate by changing the configuration of the doped region of the semiconductor device, the process steps of the disclosed embodiment are simple, and the reticle can be omitted. In the case of the number and the excessive process cost, even if the cost is not increased, the N-type MOS and the P-type MOS are simultaneously provided in the P-type substrate.

In some embodiments of the present disclosure, with the novel doping region configuration, the breakdown voltage of the semiconductor device of the disclosed embodiment may be greater than or equal to 710V, and the on-resistance may be less than or equal to 570mohm-cm ² . In addition, in some embodiments of the present disclosure, the thickness of the first conductive type substrate 100 of the semiconductor device of the embodiment of the present disclosure may be greater than 100 μm, and thus, the first conductive type second doping region 106B and the second conductive type main body region. The depletion region formed by the reduced surface electric field structure formed by 102 does not contact the lower surface 100S2 of the first conductive type substrate 100 to affect the performance of the device.

Then, referring to FIG. 3, the second conductive type body region 102 can be The second conductivity type heavily doped region 118 is further formed. The second conductive type heavily doped region 118 is formed in the opening 108A of the field oxide layer 108, and the second conductive type heavily doped region 118 is located in the first conductive type second doped region 106B and the second conductive type. Heavy doped source regions 112B. In addition, in some embodiments of the present disclosure, the first conductive type second doped region 106B and the first conductive type heavily doped source region 112A are respectively disposed on opposite sides of the second conductive type heavily doped region 118. .

In some embodiments of the present disclosure, the second conductivity type heavily doped region 118 may be formed by an ion implantation step. For example, when the second conductivity type is N-type, phosphorus ions or arsenic ions may be implanted in a region where the second conductivity type heavily doped region 118 is to be formed to form the second conductivity type heavily doped region 118.

Next, referring to FIG. 3, the first conductivity type heavily doped region 120 may be formed in the first conductivity type third well region 104C. In some embodiments of the present disclosure, the first conductive type heavily doped region 120 may directly contact the second conductive type body region 102.

In some embodiments of the present disclosure, the first conductivity type heavily doped region 120 may be formed by an ion implantation step. For example, when the first conductivity type is a P-type, boron ions, indium ions or boron difluoride ions (BF ₂ ⁺ ) may be implanted in a region where the first conductivity type heavily doped region 120 is to be formed to form a first Conductive type heavily doped region 120.

In addition, in some embodiments of the present disclosure, the doping concentration of the second conductive type heavily doped region 118 and the first conductive type heavily doped region 120 are similar or identical to the doping of the source region 112 and the drain region 114. concentration.

Next, referring to FIG. 4, the figure shows a semiconductor device in one step of the manufacturing method of the semiconductor device 200 according to some embodiments of the present disclosure. Set the cross-section of 200. As shown in FIG. 4, an interlayer dielectric layer (ILD) 122 is formed on the upper surface 100S1 of the first conductive substrate 100. The interlayer dielectric layer 122 may be hafnium oxide, tantalum nitride, hafnium oxynitride, borophosphoquinone glass (BPSG), phosphorous bismuth glass (PSG), spin-on glass (SOG), high density plasma (high density plasma). , HDP) a dielectric material formed by deposition or any other suitable dielectric material, or a combination thereof. The interlayer dielectric layer (ILD) 122 can be formed by the aforementioned chemical vapor deposition (CVD) or spin coating method and patterning step.

Next, referring to FIG. 4, a drain contact plug 124D, a first source contact plug 124S1, a second source contact plug 124S2, a contact plug 124A, and a body contact plug are formed in the interlayer dielectric layer 122. 124B. The drain contact plug 124D is electrically connected to the drain region 114. The first source contact plug 124S1 is electrically connected to the first conductive type heavily doped source region 112A. The second source contact plug 124S2 Electrically connected to the second conductive type heavily doped source region 112B, the contact plug 124A is electrically connected to the second conductive type heavily doped region 118, and the body contact plug 124B is electrically connected to the first conductive type heavy Doped region 120.

In addition, the interlayer dielectric layer 122 is further formed with a wire 126D electrically connected to the drain contact plug 124D, electrically connected to the first source contact plug 124S1, the second source contact plug 124S2 and the contact plug. A wire 126S of 124A, and a wire 126B electrically connected to the body contact plug 124B.

In some embodiments of the present disclosure, the drain contact plug 124D, the first source contact plug 124S1, the second source contact plug 124S2, the contact plug 124A, the body contact plug 124B, and the wires 126D, 126S are The material of 126B may include copper, aluminum, tungsten, gold, chromium, nickel, platinum, titanium, niobium, tantalum, the above alloys, combinations thereof, or other highly conductive metal materials. For other implementations For example, the material of the above-mentioned drain contact plug 124D, the first source contact plug 124S1, the second source contact plug 124S2, the contact plug 124A, the body contact plug 124B, and the wires 126D, 126S and 126B may be A non-metallic material, as long as the material used is electrically conductive. The material of the drain contact plug 124D, the first source contact plug 124S1, the second source contact plug 124S2, the contact plug 124A, the body contact plug 124B, and the wires 126D, 126S and 126B can be made of the foregoing Formed by chemical vapor deposition (CVD), sputtering, resistance heating evaporation, electron beam evaporation, or any other suitable deposition method.

In addition, in some embodiments of the present disclosure, the body contact plug 124B and the wire 126B are electrically connected to the first conductive type substrate 100 through the first conductive type heavily doped region 120 and the first conductive type third well region 104C, and This first conductive type substrate 100 is grounded.

In addition, a protective layer 128 may be further formed on the interlayer dielectric layer 122. The protective layer 128 may be tantalum nitride, hafnium oxide, hafnium oxynitride, borophosphorus glass (BPSG), phosphorous bismuth (PSG), spin coating. A glass (SOG), a high density plasma (HDP) deposited dielectric material or any other suitable dielectric material, or a combination thereof, and formed by the foregoing methods.

This protective layer 128 covers the wires 126D, 126S and 126B and has an opening to expose the wires 126D and the wires 126S. In addition, the conductive pad 130D of the electrical connection wire 126D and the conductive pad 130S of the electrical connection wire 126S may be formed in the opening of the protection layer 128. The conductive pad 130D is disposed on the wire 126D, and the conductive pad 130S is disposed on the wire 126S.

The materials of the conductive pads 130D and 130S may include copper, aluminum, molybdenum, tungsten, gold, chromium, nickel, platinum, titanium, tantalum, niobium, alloys thereof, combinations thereof. Or other conductive metal materials. In other embodiments, the material of the conductive pads 130D and 130S may be a non-metal material as long as the material used has conductivity. The material of the conductive pads 130D and 130S can be formed by the aforementioned chemical vapor deposition (CVD), sputtering, resistance heating evaporation, electron beam evaporation, or any other suitable deposition method. In some embodiments, the materials of the conductive pads 130D and 130S may be the same and may be formed by the same deposition step. However, in other embodiments, the conductive pads 130D and 130S may be formed by different deposition steps, and the materials thereof may be different from each other.

Continuing to refer to FIG. 4, the semiconductor device 200 includes a first conductive type substrate 100 and a second conductive type body region 102 provided in the first conductive type substrate 100. The semiconductor device 200 further includes a first conductive type first well region 104A and a first conductive type second well region 104B disposed in the second conductive type body region 102, and is not formed in the first conductive type substrate 100. The first conductive type third well region 104C in the region of the second conductive type body region 102. The first conductive type first well region 104A and the first conductive type third well region 104C are respectively disposed on opposite sides of the first conductive type second well region 104B.

The semiconductor device 200 further includes a first conductive type first doping region 106A and a first conductive type second doping region 106B disposed in the second conductive type body region 102. The first conductive type first doping region 106A is disposed between the first conductive type first well region 104A and the first conductive type second well region 104B, and directly contacts the first conductive type first well region 104A and the first conductive type The first conductive type first well region 104A and the first conductive type second well region 104B are electrically connected by the first conductive type first doping region 106A.

The first conductive type second doping region 106B is disposed in the first guide The second type well region 104B is electrically connected to the first conductive type third well region 104C, and the first conductive type second doped region 106B contacts only the second conductive type body region 102 without contacting other doped regions. For example, the first conductive type second well region 104B and the first conductive type third well region 104C.

The semiconductor device 200 further includes a gate structure 110 disposed on the upper surface 100S1 of the first conductive type substrate 100, and the gate structure 110 is disposed on the first conductive type second well region 104B. Next, the semiconductor device 200 further includes a source region 112 and a drain region 114. The source region 112 and the drain region 114 are respectively disposed on opposite sides of the gate structure 110. In detail, the source region 112 is disposed in the second conductive type body region 102 and is located in the gate structure 110 and the first conductive type second doping region 106B or the first conductive type third well region 104C. between. The drain region 114 is disposed in the first conductivity type first well region 104A.

In addition, the source region 112 includes a first conductivity type heavily doped source region 112A and a second conductivity type heavily doped source region 112B that directly contacts the first conductivity type heavily doped source region 112A. The first conductive type heavily doped source region 112A is closer to the gate structure 110, and the second conductive type heavily doped source region 112B is farther from the gate structure 110.

The semiconductor device 200 can further include a first conductive type channel region 116 under the gate structure 110 between the first conductive type heavily doped source region 112A and the first conductive type second well region 104B. In some embodiments of the present disclosure, when the first conductivity type is a P-type, the first conductive type channel region 116 is a P-type channel, and the gate structure 110, the source region 112 and the drain region 114 are formed together. A P-type MOS semiconductor, and the first conductive type substrate 100 is a P-type substrate.

The semiconductor device 200 can further include a second conductive type body The second conductive type heavily doped region 118 in the region 102, and the second conductive type heavily doped region 118 is located in the first conductive type second doped region 106B and the second conductive type heavily doped source region 112B. between. The semiconductor device 200 may further include a first conductivity type heavily doped region 120 disposed in the first conductivity type third well region 104C.

Moreover, in some embodiments of the disclosure, the semiconductor device 200 can be a high voltage semiconductor device, such as a laterally diffused metal oxide semiconductor (LDMOS). In some embodiments of the present disclosure, the semiconductor device 200 uses the P-type substrate 100, and in addition to the P-type MOS semiconductor, the semiconductor device 200 may further include another N-type MOS (not shown).

In summary, the disclosed embodiments can form a P-type MOS in a P-type substrate by using a novel doped region configuration provided in a P-type substrate, and form an N-type in a P-type substrate. The technology of the MOS semiconductor can simultaneously provide an N-type MOS semiconductor and a P-type MOS semiconductor in a P-type substrate.

In addition, since the embodiment of the present disclosure is to form a P-type MOS in the P-type substrate by changing the configuration of the doped region of the semiconductor device, the process steps of the disclosed embodiment are simple, and the reticle can be omitted. In the case of the number and the excessive process cost, even if the cost is not increased, the N-type MOS and the P-type MOS are simultaneously provided in the P-type substrate.

In addition, it should be noted that those skilled in the art are well aware that the drains and sources described herein are interchangeable because their definition is related to the voltage level to which they are connected.

It should be noted that the component sizes, component parameters, and component shapes described above are not limitations of the disclosure. In this technical field Those who are knowledgeable can adjust these settings according to different needs. Further, the semiconductor device and the method of manufacturing the same according to the present disclosure are not limited to the state illustrated in FIGS. 1-4. The disclosure may include only any one or more of the features of any one or more of the embodiments of Figures 1-4. In other words, not all illustrated features must be simultaneously implemented in the semiconductor device and method of fabricating the same.

In addition, although the doping concentrations of the various doped regions in some embodiments are set forth above. However, it will be understood by those of ordinary skill in the art that the doping concentration of each doped region can be determined according to a particular device type, technology generation, minimum component size, and the like. Thus, the doping concentration of each doped region can be re-evaluated in accordance with the technical content without being limited to the embodiments presented herein.

In addition, it should be noted that although in the above embodiments, the first conductivity type is P type and the second conductivity type is N type, however, those skilled in the art can understand the first conductivity. The type can also be N-type, while the second conductivity type is P-type.

Although the embodiments of the present disclosure and its advantages are disclosed above, it should be understood that those skilled in the art can make changes, substitutions, and refinements without departing from the spirit and scope of the disclosure. In addition, the scope of the disclosure is not limited to the processes, machines, manufactures, compositions, devices, methods, and steps in the specific embodiments described in the specification, and those of ordinary skill in the art may disclose the disclosure It is understood that the processes, machines, manufactures, compositions, devices, methods, and procedures that are presently or in the future may be used in accordance with the present disclosure as long as they can perform substantially the same function or achieve substantially the same results in the embodiments described herein. Accordingly, the scope of protection of the present disclosure includes the above-described processes, machines, manufacturing, material compositions, devices, methods, and procedures. In addition, each patent application scope constitutes an individual embodiment, and the scope of protection of the disclosure also includes a combination of the scope of the patent application and the embodiments.

100‧‧‧First Conductive Substrate

100S1‧‧‧ upper surface

100S2‧‧‧ lower surface

102‧‧‧Second conductive body area

104A‧‧‧First Conductive First Well Area

104B‧‧‧First Conductive Second Well Area

104C‧‧‧First Conductive Third Well Area

106A‧‧‧First Conductive Type First Doped Area

106B‧‧‧First Conductive Type Second Doped Area

108‧‧‧Field oxide layer

108A‧‧‧ openings

110‧‧‧ gate structure

110A‧‧‧gate dielectric layer

110B‧‧‧gate electrode

112‧‧‧ source area

112A‧‧‧First Conductive Heavy Doped Source Region

112B‧‧‧Second Conductive Heavy Doped Source Region

114‧‧‧Bungee Area

116‧‧‧First Conductive Channel Area

118‧‧‧Second Conductive Heavy Doped Zone

120‧‧‧First Conductive Heavy Doped Zone

122‧‧‧Interlayer dielectric layer

124D‧‧‧bend contact plug

124S1‧‧‧First source contact plug

124S2‧‧‧Second source contact plug

124A‧‧‧Contact plug

124B‧‧‧ body contact plug

126D‧‧‧ wire

126S‧‧‧ wire

126B‧‧‧Wire

128‧‧‧Protective layer

130D‧‧‧Electrical mat

130S‧‧‧Electrical mat

200‧‧‧Semiconductor device

Claims (20)

A semiconductor device comprising: a first conductive type substrate; a second conductive type body region disposed in the first conductive type substrate, wherein the first conductive type is different from the second conductive type; a first conductive type a first well region is disposed in the second conductive type body region; a gate structure is disposed on the upper surface of the first conductive type substrate; and a source region, wherein the source region includes a first conductive type a heavily doped source region is disposed in the second conductive type body region; and a drain region, wherein the drain region has a heavily doped first conductivity type and is disposed in the first conductivity type In a well area. The semiconductor device of claim 1, wherein the first conductivity type is a P type, the second conductivity type is an N type, and the semiconductor device further comprises a P type channel disposed in the source region and the Between the bungee regions and under the gate structure. The semiconductor device of claim 1, further comprising: a first conductivity type second well region disposed in the second conductivity type body region, wherein the first conductivity type second well region is located in the The first conductive type first doped region is disposed in the second conductive type main body region, wherein the first conductive type first well region and the first conductive type second well region are The first doped region of the first conductivity type is electrically connected. The semiconductor device of claim 3, wherein the first conductive type first doped region does not contact the upper surface of the first conductive type substrate. The semiconductor device of claim 1, further comprising: a first conductive type second doped region disposed in the second conductive type body region, The first conductive type second doped region contacts only the second conductive type body region without contacting other doped regions. The semiconductor device of claim 5, wherein the first conductive type second doped region does not contact the upper surface of the first conductive type substrate. The semiconductor device of claim 1, wherein the source region further comprises: a second conductivity type heavily doped source region directly contacting the first conductivity type heavily doped source region. The semiconductor device of claim 5, further comprising: a second conductive type heavily doped region disposed in the second conductive type body region, wherein the first conductive type second doped region and the first A conductive type heavily doped source region is respectively disposed on opposite sides of the second conductive type heavily doped region. The semiconductor device of claim 1, further comprising: a first conductivity type third well region disposed in the first conductivity type substrate in which the second conductivity type body region is not formed. The semiconductor device of claim 9, further comprising: a first conductivity type heavily doped region disposed in the first conductivity type third well region. A method of manufacturing a semiconductor device, comprising: providing a first conductive type substrate; forming a second conductive type body region in the first conductive type substrate, wherein the first conductive type is different from the second conductive type; forming a a first conductive type first well region is disposed in the second conductive type body region; a gate structure is formed on the upper surface of the first conductive type substrate; a source region is formed, wherein the source region includes a first a conductive heavily doped source region and disposed in the second conductive type body region; A drain region is formed, wherein the drain region has a heavily doped first conductivity type and is disposed in the first conductivity type first well region. The method of manufacturing a semiconductor device according to claim 11, wherein the first conductivity type is a P type, the second conductivity type is an N type, and the semiconductor device further comprises a P type channel disposed at the source The region is between the drain region and is disposed under the gate structure. The method for manufacturing a semiconductor device according to claim 11, further comprising: forming a second conductivity type second well region in the second conductivity type body region, and the first conductivity type second well region Located under the gate structure; and forming a first conductive type first doped region in the second conductive type body region, wherein the first conductive type first well region and the first conductive type second well region The first doped region is electrically connected by the first conductivity type. The method of manufacturing a semiconductor device according to claim 13, wherein the first conductive type first doped region does not contact the upper surface of the first conductive type substrate. The method for manufacturing a semiconductor device according to claim 11, further comprising: forming a first conductivity type second doping region in the second conductivity type body region, wherein the first conductivity type second doping The region contacts only the second conductive type body region without contacting other doped regions. The method of fabricating a semiconductor device according to claim 15, wherein the first conductive type second doped region does not contact the upper surface of the first conductive type substrate. A method of manufacturing a semiconductor device according to claim 11, wherein The source region further includes: a second conductivity type heavily doped source region directly contacting the first conductivity type heavily doped source region. The method for fabricating a semiconductor device according to claim 15 further comprising: forming a second conductivity type heavily doped region in the second conductivity type body region, wherein the first conductivity type second doping region The first conductive type heavily doped source regions are respectively disposed on opposite sides of the second conductive type heavily doped region. The method of manufacturing a semiconductor device according to claim 11, further comprising: forming a first conductive type third well region in the first conductive type substrate in which the second conductive type body region is not formed. The method for fabricating a semiconductor device according to claim 19, further comprising: forming a first conductivity type heavily doped region in the first conductivity type third well region.