TW201933542A - 具有較低電阻與改善崩潰之裝置及其製造方法 - Google Patents
具有較低電阻與改善崩潰之裝置及其製造方法 Download PDFInfo
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Abstract
本發明提供用於形成場板下的鐵電材料層而實現增加的Vbr伴隨減少的Rdson之方法及所產生的裝置。各實施例包含:在一p型基材(p-sub)的一部分中形成的矽層的一部分中形成一n型漂移區(N-Drift);在該矽層及該n型漂移區的部分上方形成一氧化物層;在該氧化物層的一部分上方形成一閘極;在該矽層中形成一S/D延伸區;在該閘極的相對側及該氧化物層上形成第一及第二間隔物;在鄰接該S/D延伸區的該矽層中形成一S/D區,且在遠離該矽層的該n型漂移區中形成一S/D區;在接近或鄰接該閘極的該氧化物層及該n型漂移區上方形成一U形鐵電材料層;以及以一金屬填充該U形鐵電材料層而形成一場閘極。
Description
本揭露係有關諸如積體電路(Integrated Circuit;IC)等的半導體裝置的製造。本揭露尤其適用於需要呈現高崩潰電壓(Vbr)及低導通電阻(Rdson)的中等電壓(Medium-Voltage;MV)至高電壓(High-Voltage;HV)IC。
IC正努力實現高Vbr以及低Rdson。數種MV及HV裝置遭遇的一問題是與諸如n型漂移區(N-Drift)中之摻雜等的輕度摻雜區相關聯的寄生電阻(parasitic resistance),這是因為若降低摻雜而減小電場以便實現較高的Vbr,則將增加寄生外部電阻(Rext)。因此,增加的Vbr遭受由於增加的Rdson而造成的性能降低。
因而有對能夠實現MV及HV裝置及所產生的裝置中之增加的Vbr伴隨減少的Rdson之方法的需求。
本揭露的一觀點是一種形成在場板(field plate)下的鐵電材料層而實現增加的Vbr伴隨減少的Rdson
之方法。
本揭露的另一觀點是一種包含在場板下的鐵電材料層之裝置。
在下文的說明中將述及本揭露的額外觀點及其他特徵,且對此項技術具有一般知識者在細閱下文之後將在某種程度上易於得知該等額外觀點及其他特徵,或者可自本揭露的實施而得知該等額外觀點及其他特徵。如隨附的申請專利範圍中特別指出的,可實現且得到本揭露的該等優點。
根據本揭露,一方法可在某種程度上實現某些技術功效,該方法包含:在一p型基材(p-sub)的一部分中形成一矽(Si)層;在該矽層的一部分中形成一n型漂移區;在該矽層及該n型漂移區的鄰接部分上方形成一氧化物層;在該氧化物層的一部分上方形成一閘極;在該矽層中形成一S/D延伸區;在該閘極的相對側上形成一第一間隔物(spacer)及一第二間隔物;在鄰接該S/D延伸區的該矽層中形成一S/D區,且在該n型漂移區中形成一S/D區;在接近或鄰接該閘極的該氧化物層及該n型漂移區上方形成一U形鐵電材料層;以及以一金屬填充該U形鐵電材料層而形成一場閘極。
本揭露的觀點包含以下列步驟形成該閘極:在該氧化物層上方形成一多晶矽層;以及向下移除該n型漂移區及該矽層上方的該多晶矽層的一部分直到該氧化物層,其中該矽層上方的該多晶矽層的一剩餘部分包含
該閘極,且該n型漂移區上方的該多晶矽層的一剩餘部分包含一假性場閘極(dummy field gate)。進一步的觀點包含:在形成該第一間隔物及該第二間隔物之前,形成鄰接該氧化物層上方的該閘極及該假性場閘極的每一側壁的一氧化物襯墊。另一觀點包含:在該閘極與該假性場閘極之間的該等氧化物襯墊之間形成一間隙填充材料。額外的觀點包含以下列步驟形成該U形鐵電材料層:向下移除該等氧化物襯墊之間的該假性場閘極直到該氧化物層而形成一孔穴;在該孔穴的側壁上方及側壁上形成一鐵電材料層。另一觀點包含:藉由應用一原子層沉積(Atomic Layer Deposition;ALD)製程而形成該鐵電材料層。進一步的觀點包含:形成該U形鐵電材料層到7奈米至20奈米的厚度。另一觀點包含:在該假性場閘極下的該n型漂移區中形成一淺溝槽隔離(Shallow Trench Isolation;STI)。額外的觀點包含以下列步驟形成該閘極:在該氧化物層上方形成一多晶矽層。進一步的觀點包含以下列步驟形成該U形鐵電材料層:在該閘極上方形成一遮罩層;藉由化學機械研磨(Chemical Mechanical Polishing;CMP)向下平坦化該遮罩層的一部分直到該n型漂移區上方的該閘極的上表面;向下移除該閘極的一露出部分直到該氧化物層而形成一孔穴;以及在該孔穴的側壁上方及側壁上形成該U形鐵電材料層。額外的觀點包含:形成該U形鐵電材料層到7奈米至20奈米的厚度。
本揭露的另一觀點是一種裝置,該裝置包
含:一p型基材的一部分中之一矽層;該矽層的一部分中之一n型漂移區;該矽層及該n型漂移區的鄰接部分上方的一氧化物層;該氧化物層的一部分上方的一閘極;鄰接該閘極的一側壁及該矽層上方的該氧化物層之一第一氧化物襯墊;接近或鄰接該閘極的該氧化物層及該n型漂移區上方的一U形鐵電材料層;該U形鐵電材料層內之一場閘極,該場閘極的上表面與該U形鐵電材料層的上表面共面;鄰接該第一氧化物襯墊且在該矽層上方的一第一間隔物、以及遠離該矽層的該閘極的一相對側的該n型漂移區上方的一第二間隔物;遠離該第一氧化物襯墊的該n型漂移區上方的該U形鐵電材料層與該第二間隔物之間的一第二氧化物襯墊;該第一間隔物下的該矽層中之一S/D延伸區;以及在鄰接該S/D延伸區的該矽層中之一S/D區、及遠離該矽層的該n型漂移區中之一S/D區。
該裝置的觀點包含接近該閘極的該U形鐵電材料層,該裝置進一步包含:在該氧化物層上方且分別鄰接該閘極的一側壁及該U形鐵電材料層的一第三氧化物襯墊及第四氧化物襯墊;以及該第三氧化物襯墊與該第四氧化物襯墊之間的一間隙填充材料。另一觀點包含該場閘極下的該n型漂移區中之一STI。一進一步的觀點包含:包含氧化矽鉿(HfSiOx)、氧化鋯鉿(HfZrO2)、或鈦酸鋇(BaTiO3)的該U形鐵電材料層。額外的觀點包含具有7奈米至20奈米之厚度的該U形鐵電材料層。另一觀點包含:包含一金屬的該場閘極。
本揭露的一進一步的觀點包含一種裝置,該裝置包含:一p型基材的一部分中之一矽層;該矽層的一部分中之一n型漂移區;該矽層及該n型漂移區的鄰接部分上方的一氧化物層;該氧化物層的一部分及該n型漂移區的一部分上方的一鐵電材料層;該鐵電材料層及該氧化物層上方的一閘極;鄰接該閘極的一側壁及該矽層上方的該氧化物層之一第一氧化物襯墊,以及鄰接該閘極的一側壁、該n型漂移區上方之該鐵電材料層及該氧化物層的一第二氧化物襯墊;鄰接該第一氧化物襯墊且在該矽層上方的一第一間隔物、以及鄰接該第二氧化物襯墊且在該n型漂移區上方的一第二間隔物;該第一間隔物下的該矽層中之一S/D延伸區;以及在鄰接該S/D延伸區的該矽層中之一S/D區、及該n型漂移區中之一S/D區。
本揭露的觀點包含具有7奈米至20奈米之厚度的該鐵電材料層。另一觀點包含:在該鐵電材料層的一部分下的該n型漂移區中形成一STI。
熟悉此項技術者若參閱下文中之詳細說明,將可易於了解本揭露的額外觀點及技術功效,其中只是以舉例說明預期用於實現本揭露的最佳模式之方式說明本揭露的實施例。如將可了解的,在不脫離本揭露之情形下,本揭露能夠有其他不同的實施例,且其數個細節能夠在各明顯的方面上被修改。因此,各圖式及說明在本質上被視為例示性,且不被視為限制性。
101‧‧‧矽層
103‧‧‧p型基材
105‧‧‧n型漂移區
107‧‧‧淺溝槽隔離(STI)
201、601、601'、1001、1001'‧‧‧氧化物層
203、701、1003‧‧‧閘極
205‧‧‧假性場閘極或場閘極
301、803、1103‧‧‧氧化物襯墊
303、801、1101‧‧‧源極/汲極(S/D)延伸區
305、307、309、805、1105‧‧‧間隔物
311、313、807、809、1107、1109‧‧‧源極/汲極區
401、1201‧‧‧U形鐵電材料層
403、1203‧‧‧場閘極
603、603'‧‧‧鐵電材料層
以舉例且非限制的方式示出本揭露,在各附圖中,相像的參考編號參照到類似的元件,且其中:第1圖至第4圖根據一實施例而以示意方式示出用於形成具有一增強場閘極的一HV閘極的一流程之橫斷面圖;第5圖至第8圖根據一實施例而以示意方式示出用於形成具有雙介電質的一共同HV閘極的一流程之橫斷面圖;以及第9圖至第12圖根據一實施例而以示意方式示出用於形成具有一側向取代場閘極(side replacement field gate)的一HV閘極的一流程之橫斷面圖。
在下文的說明中,為了解說,述及了許多特定細節,以便提供對各實施例的徹底了解。然而,顯然可在沒有這些特定細節或利用等效安排的情形下實施該等實施例。在其他的情形中,係以方塊圖的形式示出習知的結構及裝置,以便不會非必要地模糊了各實施例。此外,除非另有指示,否則本說明書及申請專利範圍中使用的表示成分的量、比率、及數值屬性、以及反應條件等的所有數字將被理解為在所有的情況中被術語"大約"修飾。
本揭露處理且解決在實現伴隨著n型漂移區中之減少的摻雜的較高Vbr時的較高Rdson之目前的問題。尤其藉由透過使用鐵電工程技術對表面電場(surface electric field)及電阻的增強調制而形成在一場板下的一U
形鐵電材料層以實現較低Rdson及較高Vbr,而解決該問題。
根據本揭露的實施例的方法包含:在一p型基材的一部分中形成一矽(Si)層。在該矽層的一部分中形成一n型漂移區。在該矽層及該n型漂移區的鄰接部分上方形成一氧化物層。在該氧化物層的一部分上方形成一閘極。在該矽層中形成一S/D延伸區。在該閘極的相對側形成一第一間隔物及一第二間隔物。在該矽層中形成鄰接該S/D延伸區的一S/D區,且在該n型漂移區中形成一S/D區。在接近或鄰接該閘極的該氧化物層及該n型漂移區上方形成一U形鐵電材料層,且以一金屬填充該U形鐵電材料層而形成一場閘極。
熟悉此項技術者若參閱下文中之詳細說明,將可易於了解另外其他的觀點、特徵、及技術功效,其中只是以舉例說明預期的最佳模式之方式示出且說明較佳實施例。本揭露能夠有其他不同的實施例,且其數項細節能夠在各明顯的方面上被修改。因此,該等圖式及說明在本質上被視為例示性,且不被視為限制性。
第1圖至第4圖根據一實施例而以示意方式示出用於形成具有一增強場閘極的一HV閘極的一流程之橫斷面圖。請參閱第1圖,在p型基材103上方形成一矽層101到諸如0.1微米(μm)至5微米的厚度。在一例子中,矽層101是一高電壓p型井區(High-Voltage p-type Well;HVPW)。在另一例子中,也可以氮化鎵(GaN)或任
何高電阻係數材料形成矽層101。在一進一步的例子中,以硼(B)或銦(In)對矽層101執行p型摻雜。然後,在矽層101的一部分中以諸如矽或氮化鎵或任何高電阻係數材料形成一n型漂移區105到0.1微米至5微米的厚度。在一例子中,以磷(P)或砷(As)對n型漂移區105執行一n型摻雜。然後,在n型漂移區105的一部分中形成一STI 107。在一例子中,STI 107是可選的,且可在矽層101之前形成STI 107。然後,如第2圖所示,在矽層101、n型漂移區105、及STI 107上方形成一氧化物層201。在一例子中,氧化物層201是一高電壓氧化物(High Voltage Oxide;HVOX),例如,氧化物層201是範圍係取決於電壓要求而自10奈米至200奈米的的一較厚氧化物。然後,在氧化物層201上方形成一多晶矽層(為了解說的便利而未被示出)。然後,向下移除矽層101及n型漂移區105上方的該多晶矽層的一些部分直到氧化物層201,矽層101及n型漂移區105上方的該多晶矽層的剩餘部分各自地形成一閘極203及一假性場閘極205。在一例子中,閘極203是一HV閘極。因此,在第3圖中,在閘極203及假性場閘極205的該等側壁上以及氧化物層201的一些部分上方,利用一低壓化學氣相沉積(Low Pressure Chemical Vapor Deposition;LPCVD)或一電漿增強式化學氣相沉積(Plasma Enhanced Chemical Vapor Deposition;PECVD)而以諸如高溫氧化物(High-Temperature Oxide;HTO)形成氧化物襯墊301到0.2奈米至5奈米的厚度及0.2奈米至5奈米的寬
度。然後,在氧化物層201下的矽層101中形成一S/D延伸區303。在一例子中,可在形成該等氧化物襯墊301之前形成S/D延伸區303。然後,在氧化物層201、該等氧化物襯墊301、閘極203、及假性場閘極205上方以保形方式形成一氮化矽(SiN)或一氧化物層(為了解說的便利而未被示出)。在一例子中,該氮化矽或氧化物層的厚度至少等於或大於兩個相鄰氧化物襯墊301之間的間隙的一半,而使氮化矽或氧化物層藉由夾斷而完全填充該間隙。然後,以諸如一定向乾式蝕刻製程蝕刻該氮化矽或氧化物層,而在該等氧化物襯墊301的側壁上及氧化物層201上方形成間隔物305、307及309。然後,在矽層101中形成一S/D區311,且在n型漂移區105中形成一S/D區313。在一例子中,間隔物307可包含具有中間的層間介電質(Inter Layer Dielectric;ILD)的兩個間隔物(為了解說的便利而未被示出)。在該例子中,以用於填充該等兩個間隔物之間的間隙的一常見的後段製程(Back-End-Of-Line;BEOL)形成該ILD。然後,執行一CMP製程,而將表面平坦化。在此種情況中,可經由金屬連接而將場閘極205個別地連接到一獨立的偏壓或到HV閘極203或到S/D區311。
請參閱第4圖,移除該等氧化物襯墊301之間的假性場閘極205,而露出氧化物層201,且形成一孔穴(為了解說的便利而未被示出)。然後,在該露出的氧化物層201上方且在該孔穴的側壁上,以諸如氧化矽鉿(HfSiOx)、氧化鋯鉿(HfZrO2)、鈦酸鋇(BaTiO3)、或任何其
他適當的鐵電材料形成一U形鐵電材料層401到7奈米至20奈米的厚度。然後,以金屬填充U形鐵電材料層401,因而形成一場閘極403。在該例子中,由於CMP的結果,而使場閘極403的上表面與U形鐵電材料層401的上表面共面。在一例子中,並不以金屬填充U形鐵電材料層401,而是以多晶矽填充U形鐵電材料層401。在一例子中,藉由閘極203耦合或偏壓而實現減少的表面電場,其中場閘極403被短路到閘極203。當閘極203被導通到一正偏壓時,閘極203被耦合到場閘極403,且U形鐵電材料層401將該電壓放大諸如25%,因而可實現較低的電阻。此外,場閘極403在關閉狀態(off-state)期間可被偏壓到一負電壓,且在開啟狀態(on-state)期間可被偏壓到一正電壓,可藉由U形鐵電材料層401雙向放大該電壓,而在關閉狀態期間進一步減少電場,且在開啟狀態期間積累載子。
第5圖至第8圖根據一實施例而以示意方式示出用於形成具有雙介電質的一共同HV閘極的一流程之橫斷面圖。第5圖的製程步驟與第1圖的該等製程步驟相同。請參閱第6圖,在矽層101、n型漂移區105、及STI 107的一些部分上方形成一氧化物層601。然後,在n型漂移區105上方的氧化物層601的一部分上方,以諸如氧化矽鉿(HfSiOx)、氧化鋯鉿(HfZrO2)、鈦酸鋇(BaTiO3)、或任何其他適當的鐵電材料形成一鐵電材料層603到5奈米至200奈米的厚度。然後,在氧化物層601及鐵電材料層603上方形成一多晶矽層(為了解說的便利而未被示出)。
然後,如第7圖所示,移除該多晶矽層、氧化物層601及鐵電材料層603的一些部分,因而在鐵電材料層603'及氧化物層601'的一部分上方形成一閘極701。在一例子中,閘極701是一HV閘極。如圖所示,在蝕刻之後,使氧化物層601'對齊閘極701的邊緣。然後,在第8圖中,在矽層101中形成一S/D延伸區801。然後,分別在矽層101及n型漂移區105上方的閘極701、氧化物層601'的該等側壁、及鐵電材料層603'的一側壁上,利用LPCVD或PECVD而以諸如高溫氧化物(HTO)形成氧化物襯墊803到0.2奈米至5奈米的厚度及0.2奈米至5奈米的寬度。然後,依照與前文中參照第1圖至第4圖所示的流程類似的一流程,在該等氧化物襯墊803的該等側壁上且在矽層101及n型漂移區105上方形成間隔物805。然後,分別在矽層101及n型漂移區105中形成S/D區807及809。
第9圖至第12圖根據一實施例而以示意方式示出用於形成具有一側向取代場閘極的一HV閘極的一流程之橫斷面圖。第9圖的製程步驟與第1圖及第5圖的該等製程步驟相同。請參閱第10圖,在矽層101、n型漂移區105及STI 107上方形成一氧化物層1001。然後,在氧化物層1001上方形成一多晶矽層(為了解說的便利而未被示出)。然後,移除該多晶矽層及氧化物層1001的一些部分,因而在氧化物層1001'的一部分上方形成一閘極1003。如圖所示,在蝕刻之後,使氧化物層1001'對齊閘極1003的邊緣。然後,如第11圖所示,在矽層101中形
成一S/D延伸區1101。然後,分別在矽層101及n型漂移區105上方的閘極1003及氧化物層1001'的該等側壁上形成氧化物襯墊1103。然後,依照與前文中參照第1圖至第4圖所示的流程類似的一流程,在該等氧化物襯墊1103的該等側壁上且在矽層101及n型漂移區105上方形成間隔物1105。然後,分別在矽層101及n型漂移區105中形成S/D區1107及1109。
請參閱第12圖,在閘極1003上方以諸如ILD形成一遮罩層(為了解說的便利而未被示出)。然後,向下移除該遮罩層的一部分直到n型漂移區105上方的閘極1003的上表面。然後,向下移除閘極1003的露出部分直到氧化物層1001',因而形成一孔穴(為了解說的便利而未被示出)。然後,在該孔穴的側壁上方及側壁上形成一U形鐵電材料層1201到諸如7奈米至20奈米的厚度。然後,以金屬填充U形鐵電材料層1201,因而形成一場閘極1203。在該例子中,藉由諸如CMP,而使場閘極1203的上表面與U形鐵電材料層1201的上表面共面。
本揭露的實施例可實現數項技術功效,這些技術功效包括諸如放大超過25%之被顯著放大的電壓、藉由鐵電材料而減少關閉狀態中之表面電場且減少開啟狀態中之Rdson。此外,本揭露可實現增強的Rdson-Vbr性能。此外,核心邏輯(core logic)可自由地採用該鐵電材料,否則需要將該鐵電材料沉積及退火的最低成本。根據本揭露的實施例而形成的裝置在諸如微處理器、智慧型手機、行
動電話、細胞式手機、機上盒、數位多功能光碟(DVD)錄影機及播放器、汽車導航、印表機及週邊裝置、網路及電信設備、遊戲系統、及數位相機等的各種產業應用中之任何產業應用中都具有實用性。本揭露在各種類型的高度整合之MV至HV半導體裝置之任一者中都具有產業利用性。
在前文的說明中,係參照本發明的特定實施例而說明本揭露。然而,顯然可在不脫離申請專利範圍中述及的本揭露的較寬廣之精神及範圍下對該等特定實施例作出各種修改及改變。因此,本說明書及各圖式將被視為例示性且非限制性。應當理解:本揭露可使用各種其他組合及實施例,且能夠在本說明書中所述的本發明的概念之範圍內作出任何改變或修改。
Claims (20)
- 一種方法,包含:在一p型基材(p-sub)的一部分中形成一矽(Si)層;在該矽層的一部分中形成一n型漂移區(N-Drift);在該矽層及該n型漂移區的鄰接部分上方形成一氧化物層;在該氧化物層的一部分上方形成一閘極;在該矽層中形成一源極/汲極(S/D)延伸區;在該閘極的相對側上形成一第一間隔物及一第二間隔物;在鄰接該S/D延伸區的該矽層中形成一S/D區,且在該n型漂移區中形成一S/D區;在接近或鄰接該閘極的該氧化物層及該n型漂移區上方形成一U形鐵電材料層;以及以一金屬填充該U形鐵電材料層而形成一場閘極。
- 如申請專利範圍第1項所述之方法,其中,形成該閘極包含:在該氧化物層上方形成一多晶矽層;以及向下移除該n型漂移區及該矽層上方的該多晶矽層的一部分直到該氧化物層,其中,該矽層上方的該多晶矽層的一剩餘部分包含該閘極,且該n型漂移區上方的該多晶矽層的一剩餘部分包含一假性場閘極。
- 如申請專利範圍第2項所述之方法,進一步包含:在形成該第一間隔物及該第二間隔物之前,形成鄰接該氧化物層上方的該閘極及該假性場閘極的每一側壁的一氧化物襯墊。
- 如申請專利範圍第3項所述之方法,進一步包含:在該閘極與該假性場閘極之間的該等氧化物襯墊之間形成一間隙填充材料。
- 如申請專利範圍第4項所述之方法,其中,形成該U形鐵電材料層包含:向下移除該等氧化物襯墊之間的該假性場閘極直到該氧化物層而形成一孔穴;以及在該孔穴的側壁上方及側壁上形成一鐵電材料層。
- 如申請專利範圍第5項所述之方法,包含:藉由應用一原子層沉積(ALD)製程而形成該鐵電材料層。
- 如申請專利範圍第5項所述之方法,包含:形成該U形鐵電材料層到7奈米(nm)至20奈米的厚度。
- 如申請專利範圍第2項所述之方法,進一步包含:在該假性場閘極下的該n型漂移區中形成一淺溝槽隔離(STI)。
- 如申請專利範圍第1項所述之方法,其中,形成該閘極包含:在該氧化物層上方形成一多晶矽層。
- 如申請專利範圍第9項所述之方法,其中,形成該U形鐵電材料層包含: 在該閘極上方形成一遮罩層;藉由化學機械研磨(CMP)向下平坦化該遮罩層的一部分直到該n型漂移區上方的該閘極的上表面;向下移除該閘極的一露出部分直到該氧化物層而形成一孔穴;以及在該孔穴的側壁上方及側壁上形成該U形鐵電材料層。
- 如申請專利範圍第10項所述之方法,包含:形成該U形鐵電材料層到7奈米至20奈米的厚度。
- 一種裝置,包含:一p型基材(p-sub)的一部分中之一矽(Si)層;該矽層的一部分中之一n型漂移區(N-Drift);該矽層及該n型漂移區的鄰接部分上方的一氧化物層;該氧化物層的一部分上方的一閘極;鄰接該閘極的一側壁及該矽層上方的該氧化物層之一第一氧化物襯墊;接近或鄰接該閘極的該氧化物層及該n型漂移區上方的一U形鐵電材料層;該U形鐵電材料層內之一場閘極,該場閘極的上表面與該U形鐵電材料層的上表面共面;鄰接該第一氧化物襯墊且在該矽層上方的一第一間隔物、以及遠離該矽層的該閘極的一相對側上的該n型漂移區上方的一第二間隔物; 遠離該第一氧化物襯墊的該n型漂移區上方的該U形鐵電材料層與該第二間隔物之間的一第二氧化物襯墊;該第一間隔物下的該矽層中之一源極/汲極(S/D)延伸區;以及在鄰接該S/D延伸區的該矽層中之一S/D區、及遠離該矽層的該n型漂移區中之一S/D區。
- 如申請專利範圍第12項所述之裝置,其中,該U形鐵電材料層係接近該閘極,該裝置進一步包含:在該氧化物層上方且分別鄰接該閘極的一側壁及該U形鐵電材料層的一第三氧化物襯墊及第四氧化物襯墊;以及該第三氧化物襯墊與該第四氧化物襯墊之間的一間隙填充材料。
- 如申請專利範圍第11項所述之裝置,進一步包含:該場閘極下的該n型漂移區中之一淺溝槽隔離(STI)。
- 如申請專利範圍第12項所述之裝置,其中,該U形鐵電材料層包含氧化矽鉿(HfSiOx)、氧化鋯鉿(HfZrO2)、或鈦酸鋇(BaTiO3)。
- 如申請專利範圍第12項所述之裝置,其中,該U形鐵電材料層具有7奈米至20奈米之厚度。
- 如申請專利範圍第12項所述之裝置,其中,該場閘極包含一金屬。
- 一種裝置,包含:一p型基材(p-sub)的一部分中之一矽層;該矽層的一部分中之一n型漂移區(N-Drift);該矽層及該n型漂移區的鄰接部分上方的一氧化物層;該氧化物層的一部分及該n型漂移區的一部分上方的一鐵電材料層;該鐵電材料層及該氧化物層上方的一閘極;鄰接該閘極的一側壁及該矽層上方的該氧化物層之一第一氧化物襯墊,以及鄰接該閘極的一側壁、該n型漂移區上方之該鐵電材料層及該氧化物層的一第二氧化物襯墊;鄰接該第一氧化物襯墊且在該矽層上方的一第一間隔物、以及鄰接該第二氧化物襯墊且在該n型漂移區上方的一第二間隔物;該第一間隔物下的該矽層中之一源極/汲極(S/D)延伸區;以及在鄰接該S/D延伸區的該矽層中之一S/D區、及該n型漂移區中之一S/D區。
- 如申請專利範圍第18項所述之裝置,其中,該鐵電材料層具有7奈米(nm)至20奈米之厚度。
- 如申請專利範圍第18項所述之裝置,進一步包含:在該鐵電材料層的一部分下的該n型漂移區中形成一淺溝槽隔離(STI)。
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