TW201926581A - Semiconductor device and method of manufacturing thereof - Google Patents

Abstract

A semiconductor device comprises: a semiconductor stack comprising: a first semiconductor layer, a second semiconductor layer and an active layer between the first semiconductor layer and the second semiconductor layer; a semiconductor contact layer on the first semiconductor layer, and a top-view area of the semiconductor contact layer is smaller than a top-view area of the semiconductor stack, wherein the semiconductor contact layer comprises a first area overlap the semiconductor stack and a second area not overlap the semiconductor stack; and a first electrode on the second area of the semiconductor contact layer.

Description

Semiconductor component and method of manufacturing same

The present disclosure relates to a semiconductor device, and more particularly to a semiconductor device including a semiconductor contact layer and a method of fabricating the same.

The semiconductor element comprises a compound semiconductor composed of a group III-V element, such as gallium phosphide (GaP), gallium arsenide (GaAs) or gallium nitride (GaN), and the semiconductor element may be an optoelectronic semiconductor element such as a light emitting diode (LED) ), laser, photodetector, solar cell or power device. The structure of the light emitting diode comprises a p-type semiconductor layer, an n-type semiconductor layer and an active layer, and the active layer is disposed between the p-type semiconductor layer and the n-type semiconductor layer, so that under an applied electric field, n The electrons and holes provided by the type semiconductor layer and the p-type semiconductor layer are respectively combined in the active layer to convert electrical energy into light energy. How to improve the photoelectric conversion efficiency of optoelectronic semiconductor components is one of the key points for R&D personnel.

The present disclosure provides a semiconductor device including a semiconductor stack including: a first semiconductor layer, a second semiconductor layer, and an active structure between the first semiconductor layer and the second semiconductor layer; a semiconductor contact layer is located On the first semiconductor layer, a top view area of the semiconductor contact layer is smaller than an upper view area of the semiconductor stack, and the semiconductor contact layer has a first region overlapping the semiconductor stack and a second region and the semiconductor stack The layers do not overlap; and a first electrode is disposed on the second region of the semiconductor contact layer.

The present disclosure provides a method of fabricating a semiconductor device, comprising: providing a semiconductor stack and a semiconductor contact structure, wherein the semiconductor is laminated on the first semiconductor contact structure, and the semiconductor stack includes a first semiconductor layer, a second semiconductor layer and an active structure are disposed between the first semiconductor layer and the second semiconductor layer; forming a first electrode disposed on the semiconductor contact structure; and performing a removing step to remove a portion of the semiconductor contact Forming a semiconductor contact layer; wherein the semiconductor contact layer has a first region overlapping the semiconductor stack and a second region not overlapping the semiconductor stack; wherein the semiconductor contact layer has a top view area smaller than the semiconductor The top view area of the laminate.

The present invention will be described with reference to the drawings, in which the same or the same reference numerals are used in the drawings or the description, and in the drawings, the shape or thickness of the elements may be enlarged or reduced. It is to be noted that elements not shown or described in the specification may be in a form known to those skilled in the art.

Please refer to FIGS. 1 to 3 , which are respectively a perspective view, a top view and a cross-sectional view of the semiconductor device 100 according to the first embodiment of the present disclosure. The semiconductor component 100 comprises a semiconductor stack 1, a semiconductor contact layer 2 on the semiconductor stack 1, and a first electrode 3 on the semiconductor contact layer 2. Wherein, the semiconductor laminate 1 has a first top view area and the semiconductor contact layer 2 has a second top view area smaller than the first top view area. In addition, the semiconductor contact layer 2 of the semiconductor device 100 of the present embodiment covers a portion of the semiconductor laminate 1, and the other portion of the semiconductor laminate 1 is not covered by the semiconductor contact layer 2. Specifically, in an embodiment, the semiconductor device 100 is an optoelectronic semiconductor component such as a light emitting diode (LED), a laser, a photodetector, or a solar cell, and the semiconductor stack of the semiconductor device 100 according to the application thereof. The layer 1 has a main working surface, and the main working surface may be a main light emitting surface of an LED or a laser, or a main light absorbing surface of a photodetector or a solar cell, wherein the semiconductor contact layer 2 covers a part of a main working surface, and mainly The remainder of the working surface is not covered by the semiconductor contact layer 2.

Referring to FIG. 3, the semiconductor laminate 1 includes a first semiconductor layer 11, a second semiconductor layer 12, and an active structure 13 between the first semiconductor layer 11 and the second semiconductor layer 12. The first semiconductor layer 11 and the second semiconductor layer 12 respectively have different first conductivity and second conductivity to respectively provide electrons and holes, or respectively provide holes and electrons; and the active structure 13 may comprise a single hetero Single heterostructure, double heterostructure or multiple quantum wells. The semiconductor laminate 1 of the first embodiment further includes a third semiconductor layer 14 on the first semiconductor layer 11 and away from the second semiconductor layer 12. The third semiconductor layer 14 can be used to increase the efficiency of the semiconductor device 100, or The process of the semiconductor device 1 can be optimized through the third semiconductor layer 14. For example, the third semiconductor layer 14 can be a current distributing layer, an etching stop layer, and an electron blocking layer. ), a hole reservoir layer or a window layer, and the like. The third semiconductor layer 14 of the present embodiment is an etch barrier to protect the semiconductor stack 1 during the etching process, but the function of the third semiconductor layer 14 is not limited thereto. The materials of the first semiconductor layer 11, the second semiconductor layer 12, the active structure 13, and the third semiconductor layer 14 include a tri-five compound semiconductor, and may be, for example, GaAs, InGaAs, AlGaAs, AlInGaAs, GaP, InGaP, AlInP, AlGaInP, GaN, InGaN, AlGaN, AlInGaN, AlAsSb, InGaAsP, InGaAsN, AlGaAsP, and the like. In the embodiments of the present disclosure, unless otherwise specified, the chemical expressions include "chemically-accepting compounds" and "non-chemically-accepting compounds", wherein "chemically-accepting compounds" are, for example, tri-family elements. The total elemental dose is the same as the total elemental dose of the Group 5 element. Conversely, the "non-stoichiometric compound" such as the total elemental dose of the tri-family elements is different from the total elemental dose of the Group V element. For example, the chemical expression is AlGaAs, which means that the tri-group element aluminum (Al) and/or gallium (Ga), and the five-element element arsenic (As), of which the tri-group elements (aluminum and/or gallium) are total. The elemental dose may be the same as or different from the total elemental dose of the Group V element (arsenic). Further, if each of the compounds represented by the chemical expression is a chemical compound, AlGaAs represents Al _x Ga _(1-x) As, wherein 0 ≦ x ≦ 1; and AlInP represents Al _x In _{(1-x )} P, wherein, 0 ≦ x ≦ 1; AlGaInP representative of _{(Al y Ga (1-y} )) 1-x In x P, wherein, 0 ≦ x ≦ 1,0 ≦ y ≦ 1; AlGaN Representative Al _x Ga _{( 1-x)} N, where 0≦x≦1; AlAsSb represents AlAs _x Sb _(1-x) , where 0≦x≦1; InGaP represents In _x Ga _1-x P, where 0≦x≦1 InGaAsP represents In _x Ga _1-x As _1-y P _y , where 0≦x≦1, 0≦y≦1; InGaAsN represents In _x Ga _1-x As _1-y N _y , where 0≦x ≦1,0≦y≦1; AlGaAsP represents Al _x Ga _1-x As _1-y P _y , where 0≦x≦1,0≦y≦1; InGaAs represents In _x Ga _1-x As, wherein 0≦x≦1.

The semiconductor laminate 1 of the present embodiment is electrically connected to the first electrode 3 through the semiconductor contact layer 2. The semiconductor contact layer 2 has a first region 21 and a second region 22 different from the first region 21, and the semiconductor contact layer 2 overlaps the semiconductor laminate 1 with the first region 21 and is interdigitated with the semiconductor layer 1 with the second region 22. Or not overlapping. In the present embodiment, the first electrode 3 and the semiconductor laminate 1 are located on the same side of the semiconductor contact layer 2, and different regions of the semiconductor contact layer 2 cover the semiconductor laminate 1 and the first electrode 3, respectively, in other words, the semiconductor laminate 1 The semiconductor contact layer 2 is electrically connected to the semiconductor layer 1 through the first region 21 only over the first region 21 of the semiconductor contact layer 2. The second region 22 of the embodiment further includes a first portion 221, a second portion 222 and a third portion 223. The first electrode 3 is located on the second region 22 and covers the first portion 221 of the semiconductor contact layer 2, so that The current can be transmitted from the first electrode 3 through the first portion 221 of the semiconductor contact layer 2 to the semiconductor stack 1, and the second portion 222 and the third portion 223 of the semiconductor contact layer 2 are interleaved with the first electrode 3, that is, the first electrode 3 does not cover the second portion 222 and the third portion 223. Wherein, the resistivity between the semiconductor contact layer 2 and the first electrode 3 is smaller than the resistivity between the first semiconductor layer 11 and the first electrode 3, or the conductivity between the semiconductor contact layer 2 and the first electrode 3 is greater than The conductivity between the first semiconductor layer 11 and the first electrode 3, preferably the semiconductor contact layer 2, may be in ohmic contact with the first electrode 3. In one embodiment, the semiconductor device 100 is exemplified by an optoelectronic semiconductor device such as a light emitting diode or a laser. The active structure 13 has a first energy gap to emit a light, and the first energy gap is emitted by the active structure 13 The energy gap of the dominant wavelength of the light; the semiconductor contact layer 2 has a second energy gap, and the second energy gap can be greater than, less than or equal to the first energy gap. The second energy gap of the semiconductor contact layer 2 in the first embodiment is less than or equal to the first energy gap of the active structure 13, in other words, the semiconductor contact layer 2 may comprise a material capable of absorbing light emitted from the active structure 13. In another embodiment, the semiconductor contact layer 2 of the semiconductor device 100 has an absorption rate for the light emitted by the active structure 13, and the above absorption rate is not equal to zero. For example, the absorption rate is 2% to 95%, or 5% to 70%, or 10% to 50%. Alternatively, in another embodiment, the semiconductor contact layer 2 has a transmittance to light, and the transmittance is less than 100%, such as a transmittance of 5% to 98%, or 30% to 95%, or 50%~90%. The material of the semiconductor contact layer 2 of the first embodiment comprises a tri-five compound semiconductor, and may be GaAs, InGaAs, AlGaAs, GaP, for example. Or gallium nitride (GaN). In addition, the "overlay" and "overlap" referred to in the present disclosure have substantially the same horizontal position, that is, have substantially the same numerical values in the Y coordinates of the first and third figures, and the "interlace" referred to in the disclosure. Or "do not overlap", the horizontal position of the two is different. Specifically, the two have different values on the Y coordinate of the first and third figures.

As shown in FIGS. 1 and 3, in the present embodiment, the first region 21 of the semiconductor contact layer 2 and the first portion 221 are in direct contact with the semiconductor laminate 1 and the first electrode 3, respectively, and as shown in FIG. 2, From the top view, the area of the first area 21 is different from the area of the second area 22, but the disclosure is not limited thereto. The area of the first region 21 of the embodiment is smaller than the area of the second region 22, so that the current can be effectively distributed to the semiconductor laminate 1, and at the same time, the absorption of light by the semiconductor contact layer 2 can be minimized. The area ratio of the first region 21 to the second region 22 of the semiconductor device 100 is 0.1 to 0.95, or 0.3 to 0.78. In addition, the first top view area of the semiconductor laminate 1 is larger than the second top view area of the semiconductor contact layer 2. In detail, referring to FIG. 2, the semiconductor laminate 1 has a first profile P1, and the semiconductor contact layer 2 has a second profile P2, and the first profile is viewed from the top view of the semiconductor device 100. The first upper viewing area enclosed by P1 is larger than the second upper viewing area enclosed by the second contour P2. For example, the second top view area may be 5% to 60% of the first top view area, or may be 10% to 50%, preferably 15% to 40%. In addition, the first region 21 of the semiconductor contact layer 2 has a third top view area, and the third top view area may be 10% to 30% of the first top view area, as viewed from a top view of the semiconductor device 100. Good is 7% to 20%. By partially overlapping the semiconductor contact layer 2 through the semiconductor contact layer 2, the current injected into the semiconductor contact layer 2 of the first electrode 3 can be uniformly dispersed into the semiconductor laminate 1, and at the same time, the semiconductor element 100 can maintain good light-emitting efficiency. A semiconductor element 100 having high luminance and low driving voltage is obtained. In addition, referring to FIG. 3, the thickness t1 of the semiconductor contact layer 2 may be 100 nm to 2 mm, preferably 500 nm to 1 mm, so that a good electric current can be formed between the semiconductor contact layer 2 and the semiconductor laminate 1. The connection is made, and the semiconductor contact layer 2 is prevented from being too thick, resulting in the efficiency of the semiconductor element 100 being lowered due to the occlusion of the light. In another embodiment, the first portion 221 of the second region 22 of the semiconductor contact layer 2 has a fourth top view area that is smaller than the third top view area. In addition, the first contour P1 and the second contour P2 of the present embodiment have a regular shape, for example, a rectangle shown in FIG. 2, and in other embodiments, the first contour P1 and the second contour P2 may also be irregular. Or one of the first contour P1 and the second contour P2 is a regular shape and the other is an irregular shape.

Referring to FIGS. 1 to 3, the first electrode 3 is disposed on the second region 22 of the semiconductor contact layer 2, and is electrically connected to the semiconductor laminate 1 through the first portion 221 of the second region 22, and the semiconductor device 100 further includes a second electrode 4 separated from the first electrode 3 and located on the semiconductor stack 1, and the first electrode 3 and the second electrode 4 can be used to connect an external power source and transfer current into the semiconductor stack 1. In detail, the first electrode 3 and the second electrode 4 are electrically connected to the first semiconductor layer 11 and the second semiconductor layer 12, respectively, and the first electrode 3 and the second electrode 4 are located on the same side of the semiconductor contact layer 2 to form A horizontal semiconductor element, and the first electrode 3 and the second electrode 4 respectively have a first surface 31 and a second surface 41, and the first surface 31 and the second surface 41 are away from the semiconductor contact layer 2. The upper viewing area of the first surface 31 and the second surface 41 may be the same or different. In the present embodiment, the upper viewing area of the first surface 31 is preferably equal to the upper viewing area of the second surface 41. In addition, in the first embodiment, the first surface 31 of the first electrode 1 and the second surface 41 of the second electrode 2 are substantially at the same horizontal plane, so that when the semiconductor device 100 is flip-chip bonded to a circuit structure, The substantially flush first electrode 3 and the second electrode 4 are advantageous for improving the bonding yield of the semiconductor component 100 to a circuit connection structure such as a printed circuit board. In this embodiment, the first electrode 3 and the second electrode 4 are respectively disposed on the semiconductor contact layer 2 and the second semiconductor layer 12. Since the semiconductor contact layer 2 and the second semiconductor layer 12 have a height difference, in order to make The first surface 31 is substantially flush with the second electrode 4, and the thickness of the second electrode 2 and the first electrode 1 may be different. For example, as shown in FIG. 3, the thickness of the first electrode 3 is greater than the thickness of the second electrode 4. In another embodiment (not shown), the first electrode 3 and the second electrode 4 are on opposite sides of the semiconductor contact layer 2 to form a vertical semiconductor structure. In the first embodiment, there is a gap G between the first electrode 3 and the second electrode 4, and the width of the gap G is not more than 200 mm, preferably 50 mm to 150 mm, as viewed in cross section. The material of the first electrode 3 and the second electrode 4 may include gold (Au), silver (Ag), platinum (Pt), copper (Cu), tin (Sn), nickel (Ni), titanium (Ti) or the above metal Alloy. In addition, in the present embodiment, the semiconductor laminate 1 is interdigitated with the first electrode 3 at a horizontal position. In detail, as shown in FIGS. 1 and 3, the semiconductor laminate 1 is different from the first electrode 3. Y coordinate value. It should be noted that the active structure 13 and the second semiconductor layer 12 are formed on the first semiconductor layer 11 in a stacking direction, and the thicknesses of the first electrode 3 and the second electrode 4 are parallel to the stacking direction, that is, the above The thickness of the first electrode 3, the second electrode 4, and the thickness t1 of the semiconductor contact layer 2 extend in the direction along the X-axis of the first and third views.

The semiconductor device 100 of the present disclosure further includes a current spreading structure 5 disposed on the semiconductor stack 1. In the present embodiment, the current spreading structure 5 covers the semiconductor contact layer 2 and extends onto the semiconductor stack 1. The current spreading structure 5 can help to uniformly transfer the current of the semiconductor contact layer 2 into the semiconductor laminate 1. The current spreading structure 5 may completely cover a surface of the semiconductor laminate 1 and the semiconductor contact layer 2, or the current spreading structure 5 may also cover only a portion of the semiconductor contact layer 2 as shown in the first embodiment of the present embodiment. A portion of the semiconductor laminate 1 is exposed such that portions of the semiconductor contact layer 2 and the surface of the semiconductor laminate 1 are exposed without being covered by the current spreading structure 5, so that the current spreading structure 5 has a coverage ratio, thereby reducing the current spreading structure 5 The light-emitting area of the active structure 13 is shielded. For example, the coverage ratio of the current spreading structure 5 of the present embodiment is A4 / (A1 + A2 - A3), wherein A4 is the upper viewing area of the current spreading structure 5, and A1 is the first top viewing area of the semiconductor laminate 1, A2 A second top view area of the semiconductor contact layer 2, A3 is the third top view area of the first region 21 of the semiconductor contact layer 2. The coverage of the current spreading structure 5 is preferably from 5% to 60%, or from 10% to 50%, or from 15% to 30%. The current spreading structure 5 of the present embodiment may include a metal material such as copper (Cu), aluminum (Al), tin (Sn), gold (Au), silver (Ag), lead (Pb), titanium (Ti), nickel. (Ni), platinum (Pt), tungsten (W) or an alloy of the above materials, etc.; further, in another embodiment, the current spreading structure 5 may comprise a material having a high transmittance to light emitted from the active structure 13, Preferred are materials having a transmittance of 80% to 99.99%, such as indium tin oxide (ITO), indium oxide (InO), tin oxide (SnO), cadmium tin oxide (CTO), antimony tin oxide (ATO), and aluminum oxide. Zinc (AZO), zinc tin oxide (ZTO), gallium zinc oxide (GZO), indium tungsten oxide (IWO), zinc oxide (ZnO), gallium phosphide (GaP), indium lanthanum oxide (ICO), indium oxide tungsten ( IWO), indium titanium oxide (ITiO), indium zinc oxide (IZO), indium gallium oxide (IGO), gallium aluminum zinc oxide (GAZO), graphene or a combination of the above materials. In another embodiment, particularly when the semiconductor device 100 has a small size, the current spreading structure 5 may comprise a semiconductor material, and preferably a semiconductor material having a transmittance of 80% to 99.99% for the light emitted from the active region 13. . Referring to FIG. 3, in the first embodiment, the current spreading structure 5 has a thickness t2 of about 500 nm to 3.5 mm, and the thickness t2 of the current spreading structure 5 and the thickness t1 of the semiconductor contact layer 2 are less than 10, For example, it is 0.8 to 7, and preferably 1 to 5. However, in other embodiments of the present disclosure, the semiconductor device 100 may not have the current spreading structure 5, for example, when the semiconductor device 100 has a small size (eg, a single side length of less than 10 mils or further less than 100 nm), The semiconductor element 100 has only the semiconductor contact layer 2 for electrical conduction, and can also achieve a desired current dispersion effect.

Referring to FIGS. 1 and 3, the semiconductor device 100 further includes a support structure 6 for connecting the semiconductor stack 1. The support structure 6 of the present embodiment serves to protect the semiconductor laminate 1 and increase the mechanical strength of the semiconductor device 100, so that the semiconductor laminate 1 is less susceptible to damage and breakage by external forces. The support structure 6 covers the circumferential surface of the semiconductor laminate 1, the semiconductor contact layer 2, the first electrode 3, and the second electrode 4. In detail, the support structure 6 of the embodiment includes a first support portion 61, a first The second support portion 62 and the third support portion 63 are disposed on opposite sides or around the semiconductor device 100, and the first support portion 61 and the semiconductor laminate 1 and the second electrode 4 The second support portion 62 is connected to the first electrode 3 and the third portion 223 of the semiconductor contact layer 2. The third support portion 63 is connected to the second portion 223 of the semiconductor contact layer 2 and is disposed in the gap G between the first electrode 3 and the second electrode 4. In detail, the third supporting portion 63 is disposed between the semiconductor laminate 1, the semiconductor contact layer 2, the first electrode 3, and the second electrode 4 to connect the above members, and the third supporting portion 63 and the second portion 222 are directly contact. The first support portion 61, the second support portion 62, and the third support portion 63 have widths d1, d2, and d3, respectively, and the width d3 of the third support portion 63 of the present embodiment is greater than the width d1 of the remaining two support portions 61, 62. And d2, thereby enhancing the electrical insulation between the first electrode 3 and the second electrode 4 and the structural strength of the semiconductor element 100 here, and preventing the current from passing through the gap or defect of the third support portion 63 to be turned on to cause short-circuit failure. The support structure 6 comprises an insulating material, which may be an organic material or an inorganic material such as Su8, benzocyclobutene (BCB), perfluorocyclobutane (PFCB), epoxy resin (Epoxy), acrylic resin ( Acrylic Resin), cycloolefin polymer (COC), polymethyl methacrylate (PMMA), polyethylene terephthalate (PET), polycarbonate (PC), polyetherimide (Polyetherimide) or Fluorocarbon Polymer; inorganic materials such as Silicone, Glass, Al ₂ O ₃ , SiN _x , SiO ₂ , TiO ₂ ) or magnesium fluoride (MgF ₂ ). In an embodiment, in order to further improve the light extraction efficiency of the semiconductor device 100, the support structure 6 may include a reflective material having a reflectance higher than 85% of the light emitted from the active structure 13, such as titanium dioxide (TiO ₂ ), cerium oxide. (SiO ₂ ) or alumina (Al ₂ O ₃ ).

Please refer to FIG. 4, which is a schematic cross-sectional view of a semiconductor device 200 according to a second embodiment of the present disclosure. The connection relationship of the members and members of the semiconductor device 200 of the second embodiment is similar to that of the first embodiment. The semiconductor device 200 of the present embodiment further includes a protective layer 7 on the semiconductor contact layer 2 to protect the semiconductor contact layer 2. It is not easily damaged by the intervention of an external force, and the mechanical strength of the semiconductor element 100 can also be increased by this. The protective layer 7 and the first electrode 3 of the present embodiment are respectively disposed on opposite sides of the semiconductor contact layer 2 to jointly protect the semiconductor contact layer 2. The protective layer 7 may include a conductive material to have conductivity, whereby the current input from the first electrode 3 is transmitted or dispersed through the semiconductor contact layer 2, the protective layer 7, and the current spreading layer 5 into the semiconductor laminate 1, the protective layer 7 The conductive material contained is, for example, gold (Au), silver (Ag), platinum (Pt), copper (Cu), tin (Sn), nickel (Ni), titanium (Ti) or an alloy of the above metals. Alternatively, the protective layer 7 may comprise an insulating material such as Su8, benzocyclobutene (BCB), perfluorocyclobutane (PFCB), epoxy resin (Epoxy), acrylic resin (Acrylic Resin), cycloolefin polymer ( COC), polymethyl methacrylate (PMMA), polyethylene terephthalate (PET), polycarbonate (PC), polyetherimide, fluorocarbon polymer (Fluorocarbon Polymer), Silicone, glass, alumina (Al ₂ O ₃ ), tantalum nitride (SiN _x ), yttrium oxide (SiO ₂ ), titanium oxide (TiO ₂ ) or magnesium fluoride (MgF ₂ ). The material of the protective layer 7 may be selected to be the same as or different from the first electrode 3, and no limitation is imposed here. The protective layer 7 of the present embodiment is disposed between the semiconductor contact layer 2 and the current spreading structure 5, but the disclosure is not limited thereto. In other embodiments, the protective layer 7 is disposed on the current spreading structure 5 to spread the current. The structure 5 is located between the protective layer 7 and the semiconductor contact layer 2, whereby the protective layer 7 can simultaneously support and protect the semiconductor contact layer 2 and the current spreading structure 5.

5A-5B, which are respectively a top view and a cross-sectional view of a semiconductor device 300 according to a third embodiment of the present disclosure, and the connection relationship between the components and members of the semiconductor device 300 of the third embodiment. In an embodiment, the semiconductor contact layer 2 of the semiconductor device 300 of the present embodiment further includes an extension region 23 connected to the first region 21, and the extension region 23 has a single or a plurality of extension portions 231 extending from the first region 21 along an extending direction. It extends toward the first support portion 61. In the present embodiment, each of the extending portions 231 has a first width W1, and the current spreading structure 5 has a second width W2 smaller than the first width W1, so that the extending portions 231 are convex. Out of the current spreading structure 5. Further, each of the extending portions 231 is conformally formed outside the current spreading structure 5 by the upper viewing direction of the semiconductor element 300, and the first outline P1 of the semiconductor stacked 1 is a regular shape, and the second of the semiconductor contact layer 2 The contour P2 is irregular like a comb shape, an L shape or a T shape. When the material contained in the current spreading structure 5 has a low transmittance to the light emission of the active structure 13, the semiconductor contact layer 2 having the extended region 23 is conformally formed under the current spreading structure 5, on the one hand, the semiconductor contact layer can be enlarged. The area of 2 allows the current to be more effectively and uniformly dispersed in the semiconductor laminate 1, and on the other hand, does not increase the amount of the semiconductor contact layer 2 which shields light. Referring to FIG. 5C, which is a top view of the semiconductor device 400 of the fourth embodiment of the present disclosure, the connection relationship of the members and members of the semiconductor device 400 of the fourth embodiment is similar to that of the first embodiment. In the semiconductor device 400 of the fourth embodiment, the semiconductor contact layer 2 includes a plurality of mutually separated contact portions 2a, and the current spreading structure 5 includes a plurality of separated current dispersion portions 5a, and the contact portions 2a are viewed from above. Each of the current dispersion portions 5a is conformally surrounded. The direction of the first width W1 and the second width W2 is perpendicular to the extending direction of the extending portion 231. In detail, the first width W1 and the second width W2 are parallel to the Z-axis direction of the fifth drawing.

6A-6E are schematic views of an embodiment of a method of manufacturing the semiconductor device 100. First, a semiconductor stacked structure 1' is formed on a growth substrate 8, as shown in FIG. 6A. In this embodiment, a buffer layer 9 and an etch stop layer are sequentially formed on the growth substrate 8 by epitaxial growth. 10. A semiconductor contact structure 2' and a semiconductor stacked structure 1', the semiconductor stacked structure 1' comprising a third semiconductor structure 14', a first semiconductor structure 11', sequentially formed over the semiconductor contact structure 2', An active region 13' and a second semiconductor structure 12'. The growth substrate 8 may comprise a semiconductor material such as gallium arsenide (GaAs), tantalum carbide (SiC), gallium phosphide (GaP), gallium arsenide (GaAsP), zinc selenide (ZnSe), zinc selenide (ZnSe). Indium phosphide (InP) or alumina (sapphire). The semiconductor stacked structure 1' can be grown on a growth substrate by an epitaxial method such as metalorganic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE) or hydride vapor epitaxy (HVPE). The buffer layer 9 may be used to increase the epitaxial growth quality of the semiconductor stacked structure 1', or the buffer layer 9 may be used as an active layer for subsequently removing the growth substrate 8, and the buffer layer 9 may comprise a polycrystalline material or a single crystal material. The material of the buffer layer 9 may include a tri-five compound semiconductor such as gallium arsenide (GaAs), gallium nitride (GaN), aluminum nitride (AlN), or aluminum gallium nitride (AlGaN). The etch stop layer 10 can be used to protect the semiconductor stacked structure 1 ′ from the process damage of the grown growth substrate 8 when the growth substrate 8 is subsequently removed, wherein the etch barrier layer 10 can include a etch rate lower than that of the buffer layer 9 . The tri-five compound semiconductor material can thereby achieve the effect of protecting the semiconductor stacked structure 1', but the above-mentioned epitaxial method and material selection of each layer are not limited thereto.

Referring to FIG. 6B, next, the semiconductor stacked structure 1' is patterned to remove a portion of the semiconductor stacked structure 1' and expose a portion of the semiconductor contact structure 2', and another portion of the semiconductor stacked structure 1' is retained. The semiconductor contact structure 2' is formed on the semiconductor contact structure 2'. The method of removing a portion of the semiconductor stacked structure 1' can be performed by dry etching, wet etching, or the like, but the present disclosure does not limit the removal method. In this embodiment, the semiconductor stack 1 is formed by a two-stage removal method. In detail, the first stage removes portions of the second semiconductor structure 12', the active region 13', and the first semiconductor structure 11' to form a first The semiconductor layer 12, the active structure 13 and the first semiconductor layer 11, at this time, the third semiconductor structure 14' is substantially not removed to protect the underlying semiconductor contact structure 2', avoiding the semiconductor structure stack in the removed portion The semiconductor contact structure 2' is damaged during the layer structure 1'; then, a portion of the third semiconductor structure 14' is removed by a removal condition different from that of the first stage to form the third semiconductor layer 14. In the present embodiment, the above-mentioned "different removal conditions" use different etching liquids for the first stage and the second stage, but are not limited thereto.

Subsequently, as shown in FIG. 6C, the first electrode 3 and the second electrode 4 are respectively formed on the semiconductor contact structure 2 ′ and the semiconductor laminate 1 , wherein the first electrode 3 and the second electrode 4 are located on the semiconductor contact layer 2 . On the same side, the first surface 31 of the first electrode 3 and the second surface 41 of the second electrode 4 are away from the semiconductor contact layer 2, and the first surface 31 and the second surface 41 of the embodiment are substantially flush and are at the same horizontal plane. on. In this embodiment, a metal film layer is formed by plating or plating on the semiconductor contact structure 2' and the semiconductor layer 1, and then through the patterned metal film layer to form the first electrode 3 and the second separated from each other. Electrode 4, but the disclosure is not limited thereto. Next, as shown in Fig. 6D, the support structure 6 is formed and covers the circumferential surface of the semiconductor laminate 1, the first electrode 3 and the second electrode 4, and the surface of the semiconductor contact structure 2', and the growth substrate 8 is successively removed. The support structure 6 is preferably formed before the growth substrate 8 is removed to increase the mechanical strength of the semiconductor laminate 1 by using the support structure 6, thereby preventing the semiconductor laminate 1 from being damaged or broken when the growth substrate 8 is removed. The support structure 6 can be formed by screen printing, coating, spraying, dispensing, sputtering, and molding. In addition, the method for separating the growth substrate 8 includes directly removing the growth substrate 8 by wet etching, or removing the buffer layer 9 between the growth substrate 8 and the semiconductor laminate 1, thereby separating the growth substrate 8 and the semiconductor laminate 1; Further, it is also possible to separate the semiconductor laminate 1 and the growth substrate 8 by using a laser-peeling technique (Laser-Lift), using laser light to penetrate the growth substrate 8 and irradiating the interface between the growth substrate 8 and the semiconductor laminate 1. Alternatively, the buffer layer 9 between the growth substrate 8 and the semiconductor laminate 1 can be directly removed by vapor etching at a high temperature to separate the growth substrate 8 from the semiconductor laminate 1. In this embodiment, the buffer layer 9 is removed to separate the growth substrate 8 from the semiconductor laminate 1, and the semiconductor barrier structure 2' is protected by the etching barrier layer 10 from being damaged by the buffer layer 9 removal process.

Next, the etch stop layer 10 on the semiconductor contact structure 2' is removed, and then a removal step is performed to remove a portion of the semiconductor contact structure 2', thereby forming the semiconductor contact layer 2, and the semiconductor contact layer 2 includes a first The region 21 overlaps with the semiconductor laminate 1 and a second region 22 does not overlap with the semiconductor laminate 1, and in order to increase light extraction efficiency while maintaining current dispersion efficiency, the upper viewing area of the preferred first region 21 occupies the semiconductor laminate. 10% to 30% of the top view area. Finally, as shown in FIG. 6E, the support structure 6, or the semiconductor contact layer 2 and the support structure 6 thereon are diced to form a plurality of semiconductor elements 100 separated from each other. The upper viewing area of the semiconductor contact layer 2 is made smaller than the upper viewing area of the semiconductor laminate 1 by the above removal step, thereby reducing the absorption rate of the light emitted by the active contact structure 13 by the semiconductor contact layer 2, and improving the semiconductor element 100. Overall efficiency.

It is to be understood that the invention is not intended to limit the scope of the invention. Any obvious modifications or variations of the present invention are possible without departing from the spirit and scope of the invention. The same or similar components in different embodiments, or components having the same reference numbers in different embodiments, have the same physical or chemical properties. In addition, the above-described embodiments of the present invention may be combined or substituted with each other as appropriate, and are not limited to the specific embodiments described. The connection between the specific components and the other components described in detail in the embodiments can also be applied to other embodiments, and all fall within the scope of the scope of the invention as described hereinafter.

100, 200, 300, 400‧‧‧ semiconductor components

1‧‧‧Semiconductor laminate

1'‧‧‧Semiconductor laminate structure

11‧‧‧First semiconductor layer

11'‧‧‧First semiconductor structure

12‧‧‧Second semiconductor layer

12'‧‧‧Second semiconductor structure

13‧‧‧Active structure

13'‧‧‧Active area

14‧‧‧ Third semiconductor layer

14'‧‧‧ Third semiconductor structure

2‧‧‧Semiconductor contact layer

2a‧‧‧Contacts

2'‧‧‧Semiconductor Contact Structure

21‧‧‧First area

22‧‧‧Second area

221‧‧‧Part 1

222‧‧‧ Part II

223‧‧‧Part III

23‧‧‧Extended area

231‧‧‧Extension

3‧‧‧First electrode

31‧‧‧ first side

4‧‧‧second electrode

41‧‧‧ second side

5‧‧‧current distribution structure

5a‧‧‧Electrical Dispersion Department

6‧‧‧Support structure

61‧‧‧First Support Department

62‧‧‧Second Support Department

63‧‧‧ Third Support Department

7‧‧‧Protective layer

8‧‧‧ Growth substrate

9‧‧‧ Buffer layer

10‧‧‧ etching barrier

T1, t2‧‧‧ thickness

G‧‧‧ gap

W1‧‧‧ first width

W2‧‧‧ second width

D1, d2, d3‧‧‧ width

Fig. 1 is a perspective view showing a semiconductor device of a first embodiment of the present disclosure.

Fig. 2 is a top plan view showing a semiconductor device of a first embodiment of the present disclosure.

Fig. 3 is a schematic cross-sectional view of the semiconductor device of Fig. 2 taken along line A-A.

Fig. 4 is a schematic cross-sectional view showing a semiconductor device according to a second embodiment of the present disclosure.

Fig. 5A is a top plan view showing a semiconductor device of a third embodiment of the present disclosure.

Fig. 5B is a schematic cross-sectional view of the semiconductor element taken along line B-B' of Fig. 5A.

Fig. 5C is a top plan view showing the semiconductor device of the fourth embodiment of the present disclosure.

6A to 6E are schematic views showing a method of manufacturing a semiconductor device of the present disclosure.

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Claims (20)

A semiconductor device comprising: a semiconductor stack comprising: a first semiconductor layer, a second semiconductor layer, and an active structure between the first semiconductor layer and the second semiconductor layer; a semiconductor contact layer located at the first The semiconductor contact layer has a top view area smaller than an upper view area of the semiconductor stack, and the semiconductor contact layer has a first region overlapping the semiconductor stack and a second region not overlapping the semiconductor stack And a first electrode is disposed on the second region of the semiconductor contact layer. A semiconductor device according to claim 1, wherein a top view area of the first region accounts for 10% to 30% of a top view area of the semiconductor stack. A semiconductor device according to claim 1, further comprising a second electrode on the semiconductor stack, wherein the first electrode and the second electrode are on the same side of the semiconductor contact layer. The semiconductor device of claim 3, wherein the first electrode and the second electrode respectively have a first surface and a second surface away from the semiconductor contact layer, and the first surface and the second surface are substantially Qi Ping. A semiconductor device according to claim 3, wherein the thickness of the first electrode is different from the thickness of the second electrode in a stacking direction of the semiconductor laminate. A semiconductor device according to claim 1 or 3, further comprising a protective layer disposed on the semiconductor contact layer. A semiconductor device according to claim 6, wherein the protective layer and the first electrode are respectively located on opposite sides of the semiconductor contact layer, and the protective layer comprises a conductive material. A semiconductor device according to claim 1, wherein the active structure and the semiconductor contact layer each comprise a tri-five compound semiconductor, and the active structure has a first energy gap, and the semiconductor contact layer has a second energy The gap is smaller than the first energy gap. The semiconductor device of claim 1, wherein the second region of the semiconductor contact layer comprises a first portion and a second portion, the first electrode is disposed on the first portion, and the second portion is disposed Between the first region and the first portion. A semiconductor device according to claim 9, further comprising a support structure connecting the semiconductor stack and the first electrode. A semiconductor device according to claim 10, wherein the support structure is in contact with the second portion of the semiconductor contact layer. A semiconductor device according to claim 1, wherein the semiconductor contact layer contacts the semiconductor stack and the first electrode. A method of fabricating a semiconductor device, comprising: providing a semiconductor stack and a semiconductor contact structure, wherein the semiconductor is laminated on the first semiconductor contact structure, and the semiconductor stack comprises a first semiconductor layer and a second semiconductor a layer and an active structure between the first semiconductor layer and the second semiconductor layer; forming a first electrode disposed on the semiconductor contact structure; and performing a removing step of removing a portion of the semiconductor contact structure to form a a semiconductor contact layer; wherein the semiconductor contact layer has a first region overlapping the semiconductor stack and a second region not overlapping the semiconductor stack; wherein a top view area of the semiconductor contact layer is smaller than an upper surface of the semiconductor stack View area. A method of fabricating a semiconductor device according to claim 13, further comprising providing a growth substrate, the semiconductor contact structure and the semiconductor laminate being sequentially formed on the growth substrate; and separating the growth substrate from the semiconductor contact structure. A method of fabricating a semiconductor device according to claim 13, further comprising forming a semiconductor stacked structure on the semiconductor contact structure, and patterning the semiconductor stacked structure to form the semiconductor stacked. A method of manufacturing a semiconductor device according to claim 15, wherein the semiconductor laminate is formed first, and the removing step is performed. A method of fabricating a semiconductor device according to claim 13, further comprising forming a support structure for interposing the first electrode and the semiconductor laminate. A method of fabricating a semiconductor device according to claim 13, further comprising forming a second electrode on the semiconductor stack, and the first electrode and the second electrode are on the same side of the semiconductor contact layer. The method of manufacturing a semiconductor device according to claim 18, wherein the first electrode and the second electrode respectively have a first surface and a second surface away from the semiconductor contact layer, and the first surface and the first surface The two sides are roughly flush. A method of fabricating a semiconductor device according to claim 13, wherein a top view area of the first region accounts for 10% to 30% of a top view area of the semiconductor stack.