以下實施例將伴隨著圖式說明本發明之概念，在圖式或說明中，相似或相同之部分係使用相同之標號，並且在圖式中，元件之形狀或厚度可擴大或縮小。需特別注意的是，圖中未繪示或說明書未描述之元件，可以是熟習此技藝之人士所知之形式。The following embodiments will illustrate the concept of the present invention along with the drawings. In the drawings or descriptions, similar or identical parts use the same symbols, and in the drawings, the shape or thickness of the elements can be enlarged or reduced. It should be noted that components not shown in the figure or not described in the specification may be in forms known to those skilled in the art.
請參照第1～3圖所示，此分別為本揭露內容第一實施例之半導體元件100的立體示意圖、上視示意圖及剖面示意圖。半導體元件100包含一半導體疊層1、一半導體接觸層2位於半導體疊層1上以及一第一電極3位於半導體接觸層2上。其中，半導體疊層1具有一第一上視面積且半導體接觸層2具有一第二上視面積小於第一上視面積。另外，本實施例之半導體元件100的半導體接觸層2覆蓋於一部分的半導體疊層1，且另一部分的半導體疊層1未被半導體接觸層2覆蓋。具體的，在一實施例中，半導體元件100為一光電半導體元件，如發光二極體(LED)、雷射、光偵測器或太陽能電池等，且根據其應用，半導體元件100的半導體疊層1具有一主要工作表面，主要工作表面可以為LED或雷射的主要發光表面，或者為光偵測器、太陽能電池的主要吸光表面，其中半導體接觸層2覆蓋主要工作表面的一部分，而主要工作表面的其餘部分則未被半導體接觸層2覆蓋。Please refer to FIGS. 1-3 , which are respectively a three-dimensional schematic view, a top view schematic view and a cross-sectional schematic view of the semiconductor device 100 according to the first embodiment of the present disclosure. The semiconductor device 100 includes a semiconductor stack 1 , a semiconductor contact layer 2 on the semiconductor stack 1 , and a first electrode 3 on the semiconductor contact layer 2 . Wherein, the semiconductor stack 1 has a first top view area and the semiconductor contact layer 2 has a second top view area which is smaller than the first top view area. In addition, the semiconductor contact layer 2 of the semiconductor device 100 in this embodiment covers a part of the semiconductor stack 1 , and another part of the semiconductor stack 1 is not covered by the semiconductor contact layer 2 . Specifically, in one embodiment, the semiconductor element 100 is an optoelectronic semiconductor element, such as a light emitting diode (LED), a laser, a photodetector or a solar cell, etc., and according to its application, the semiconductor stack of the semiconductor element 100 Layer 1 has a main working surface, which can be the main light-emitting surface of LED or laser, or the main light-absorbing surface of photodetector or solar cell, wherein the semiconductor contact layer 2 covers a part of the main working surface, and the main working surface The rest of the working surface is not covered by the semiconductor contact layer 2 .
請參照第3圖所示，半導體疊層1包含一第一半導體層11、一第二半導體層12及一活性結構13位於第一半導體層11及第二半導體層12之間。第一半導體層11及第二半導體層12分別具有不同之一第一導電性及一第二導電性，以分別提供電子與電洞，或者分別提供電洞與電子；活性結構13可以包含單異質結構(single heterostructure)、雙異質結構(double heterostructure)或多層量子井(multiple quantum wells)。第一實施例的半導體疊層1另包含一第三半導體層14位於第一半導體層11上且遠離第二半導體層12，第三半導體層14可以用以增加半導體元件100之效率，或者，也可以透過第三半導體層14優化半導體元件1的製程，舉例來說，第三半導體層14可以為電流散佈層(current distributing layer)、蝕刻阻擋層( etching stop layer)、電子阻擋層(electrode blocking layer)、電洞儲存層(hole reservoir layer)或窗戶層(window layer)等等。本實施例的第三半導體層14為一蝕刻阻擋層，以在蝕刻製程過程中保護半導體疊層1，但第三半導體層14的功用並不以此為限。第一半導體層11、第二半導體層12、活性結構13及第三半導體層14之材料包含三五族化合物半導體，例如可以為：GaAs、InGaAs、AlGaAs、AlInGaAs、GaP、InGaP 、AlInP、AlGaInP、GaN、InGaN、AlGaN 、AlInGaN、AlAsSb、InGaAsP 、InGaAsN 、AlGaAsP等。在本揭露內容之實施例中，若無特別說明，上述化學表示式包含「符合化學劑量之化合物」及「非符合化學劑量之化合物」，其中，「符合化學劑量之化合物」例如為三族元素的總元素劑量與五族元素的總元素劑量相同，反之，「非符合化學劑量之化合物」例如為三族元素的總元素劑量與五族元素的總元素劑量不同。舉例而言，化學表示式為AlGaAs即代表包含三族元素鋁(Al)及/或鎵(Ga)，以及包含五族元素砷(As)，其中三族元素(鋁及/或鎵)的總元素劑量可以與五族元素(砷)的總元素劑量相同或相異。另外，若上述由化學表示式表示的各化合物為符合化學劑量之化合物時，AlGaAs 即代表 AlxGa(1-x)As，其中，0≦x≦1；AlInP 代表AlxIn(1-x)P，其中，0≦x≦1；AlGaInP代表(AlyGa(1-y))1-xInxP，其中，0≦x≦1，0≦y≦1；AlGaN 代表AlxGa(1-x)N，其中，0≦x≦1；AlAsSb 代表 AlAsxSb(1-x)，其中，0≦x≦1；InGaP代表InxGa1-xP，其中，0≦x≦1；InGaAsP代表InxGa1-xAs1-yPy，其中，0≦x≦1, 0≦y≦1；InGaAsN 代表 InxGa1-xAs1-yNy，其中，0≦x≦1，0≦y≦1；AlGaAsP代表AlxGa1-xAs1-yPy，其中，0≦x≦1，0≦y≦1；InGaAs代表InxGa1-xAs，其中，0≦x≦1。Please refer to FIG. 3 , the semiconductor stack 1 includes a first semiconductor layer 11 , a second semiconductor layer 12 and an active structure 13 located between the first semiconductor layer 11 and the second semiconductor layer 12 . The first semiconductor layer 11 and the second semiconductor layer 12 have a different first conductivity and a second conductivity, respectively, to provide electrons and holes, or to provide holes and electrons; the active structure 13 can include a single heterogeneous single heterostructure, double heterostructure or multiple quantum wells. The semiconductor stack 1 of the first embodiment further includes a third semiconductor layer 14 located on the first semiconductor layer 11 and away from the second semiconductor layer 12, the third semiconductor layer 14 can be used to increase the efficiency of the semiconductor element 100, or, also The manufacturing process of the semiconductor device 1 can be optimized through the third semiconductor layer 14. For example, the third semiconductor layer 14 can be a current distributing layer, an etching stop layer, an electron blocking layer ), hole reservoir layer (hole reservoir layer) or window layer (window layer) and so on. The third semiconductor layer 14 in this embodiment is an etching barrier layer to protect the semiconductor stack 1 during the etching process, but the function of the third semiconductor layer 14 is not limited thereto. The materials of the first semiconductor layer 11, the second semiconductor layer 12, the active structure 13, and the third semiconductor layer 14 include Group III and V compound semiconductors, such as: GaAs, InGaAs, AlGaAs, AlInGaAs, GaP, InGaP, AlInP, AlGaInP, GaN, InGaN, AlGaN, AlInGaN, AlAsSb, InGaAsP, InGaAsN, AlGaAsP, etc. In the embodiments of the present disclosure, unless otherwise specified, the above chemical expressions include "compounds that meet the stoichiometric dosage" and "compounds that do not meet the stoichiometric dosage", wherein "compounds that meet the stoichiometric dosage" are, for example, group III elements The total element dose of the compound is the same as the total element dose of the five group elements. On the contrary, the "non-stoichiometric compound" is, for example, the total element dose of the three group elements is different from the total element dose of the five group elements. For example, the chemical formula is AlGaAs, which means that it contains aluminum (Al) and/or gallium (Ga) of group three elements, and arsenic (As) of group five elements, wherein the total of group three elements (aluminum and/or gallium) The elemental dosage may be the same as or different from the total elemental dosage of the Group V element (arsenic). In addition, if each compound represented by the above chemical expression is a chemically dosed compound, AlGaAs represents AlxGa(1-x)As, where 0≦x≦1; AlInP represents AlxIn(1-x)P, where , 0≦x≦1; AlGaInP stands for (AlyGa(1-y))1-xInxP, where 0≦x≦1, 0≦y≦1; AlGaN stands for AlxGa(1-x)N, where 0≦x ≦1; AlAsSb stands for AlAsxSb(1-x), where 0≦x≦1; InGaP stands for InxGa1-xP, where 0≦x≦1; InGaAsP stands for InxGa1-xAs1-yPy, where 0≦x≦1, 0≦y≦1; InGaAsN stands for InxGa1-xAs1-yNy, where 0≦x≦1, 0≦y≦1; AlGaAsP stands for AlxGa1-xAs1-yPy, where 0≦x≦1, 0≦y≦1; InGaAs represents InxGa1-xAs, where 0≦x≦1.
本實施例之半導體疊層1透過半導體接觸層2與第一電極3電性連接。半導體接觸層2具有一第一區域21及一第二區域22不同於第一區域21，半導體接觸層2以第一區域21與半導體疊層1重疊，且以第二區域22與半導體層1交錯或不重疊。在本實施例中，第一電極3與半導體疊層1位於半導體接觸層2的同一側，半導體接觸層2的不同區域分別覆蓋於半導體疊層1及第一電極3，換言之，半導體疊層1僅覆蓋在半導體接觸層2的第一區域21上，使半導體接觸層2透過第一區域21與半導體疊層1電性連接。本實施例的第二區域22另包含一第一部分221、一第二部分222及一第三部分223，第一電極3位於第二區域22上且覆蓋於半導體接觸層2的第一部分221，使電流可以自第一電極3透過半導體接觸層2的第一部分221傳遞至半導體疊層1，而半導體接觸層2的第二部分222及第三部分223則與第一電極3交錯，即第一電極3未覆蓋第二部分222及第三部分223。其中，半導體接觸層2與第一電極3之間的電阻率小於第一半導體層11與第一電極3之間的電阻率，或者，半導體接觸層2與第一電極3之間的導電率大於第一半導體層11與第一電極3之間的導電率，半導體接觸層2較佳可以與第一電極3歐姆接觸。在一實施例中，半導體元件100以光電半導體元件如發光二極體或雷射為例，活性結構13係具有一第一能隙可發出一光線，且第一能隙為活性結構13發出之光線之主波長的能隙；半導體接觸層2具有一第二能隙，第二能隙可以大於 、小於或等於第一能隙。第一實施例中的半導體接觸層2之第二能隙小於或等於活性結構13之第一能隙，換言之，半導體接觸層2可以包含能夠吸收從活性結構13所發出光線的材料。在另一實施例中，半導體元件100的半導體接觸層2對於活性結構13發出的光線具有一吸收率，上述吸收率不等於零。例如吸收率為2%～95%，或者為5%～70%，或者為10%～50%。或者，在另一實施例中，半導體接觸層2對光線具有一穿透率，上述穿透率小於100%，例如穿透率為5%~98%，或者為30%~95%，或者為50%~90%。第一實施例的半導體接觸層2之材料包含三五族化合物半導體，舉例可以為砷化鎵(GaAs)、砷化銦鎵(InGaAs)、砷化鋁鎵(AlGaAs)、磷化鎵(GaP)或氮化鎵(GaN)。另外，本揭露內容所指的「覆蓋」、「重疊」為兩者的水平位置大致相同，即在第1、3圖的Y座標上具有大致相同的數值，本揭露內容所指的「交錯」或「不重疊」則為兩者的水平位置不同，具體而言，即兩者在第1、3圖的Y座標上具有不相同的數值。The semiconductor stack 1 of this embodiment is electrically connected to the first electrode 3 through the semiconductor contact layer 2 . The semiconductor contact layer 2 has a first region 21 and a second region 22 different from the first region 21, the semiconductor contact layer 2 overlaps the semiconductor layer 1 with the first region 21, and intersects with the semiconductor layer 1 with the second region 22 or not overlapping. In this embodiment, the first electrode 3 and the semiconductor stack 1 are located on the same side of the semiconductor contact layer 2, and different regions of the semiconductor contact layer 2 cover the semiconductor stack 1 and the first electrode 3 respectively, in other words, the semiconductor stack 1 Covering only the first region 21 of the semiconductor contact layer 2 , the semiconductor contact layer 2 is electrically connected to the semiconductor stack 1 through the first region 21 . The second region 22 of this embodiment further includes a first portion 221, a second portion 222 and a third portion 223, the first electrode 3 is located on the second region 22 and covers the first portion 221 of the semiconductor contact layer 2, so that Current can be transmitted from the first electrode 3 to the semiconductor stack 1 through the first portion 221 of the semiconductor contact layer 2, while the second portion 222 and the third portion 223 of the semiconductor contact layer 2 are intersected with the first electrode 3, that is, the first electrode 3 does not cover the second part 222 and the third part 223. Wherein, the resistivity between the semiconductor contact layer 2 and the first electrode 3 is smaller than the resistivity between the first semiconductor layer 11 and the first electrode 3, or the conductivity between the semiconductor contact layer 2 and the first electrode 3 is greater than For the conductivity between the first semiconductor layer 11 and the first electrode 3 , the semiconductor contact layer 2 is preferably in ohmic contact with the first electrode 3 . In one embodiment, the semiconductor element 100 is an optoelectronic semiconductor element such as a light-emitting diode or a laser. The active structure 13 has a first energy gap to emit a light, and the first energy gap is emitted by the active structure 13. The energy gap of the dominant wavelength of light; the semiconductor contact layer 2 has a second energy gap, and the second energy gap can be greater than, smaller than or equal to the first energy gap. The second energy gap of the semiconductor contact layer 2 in the first embodiment is smaller than or equal to the first energy gap of the active structure 13 , in other words, the semiconductor contact layer 2 may contain a material capable of absorbing light emitted from the active structure 13 . In another embodiment, the semiconductor contact layer 2 of the semiconductor device 100 has an absorptivity for light emitted by the active structure 13 , and the absorptivity is not equal to zero. For example, the absorption rate is 2% to 95%, or 5% to 70%, or 10% to 50%. Alternatively, in another embodiment, the semiconductor contact layer 2 has a transmittance to light, the above-mentioned transmittance is less than 100%, for example, the transmittance is 5% to 98%, or 30% to 95%, or is 50%~90%. The material of the semiconductor contact layer 2 in the first embodiment includes Group III and V compound semiconductors, such as gallium arsenide (GaAs), indium gallium arsenide (InGaAs), aluminum gallium arsenide (AlGaAs), gallium phosphide (GaP) or Gallium Nitride (GaN). In addition, the "covering" and "overlapping" referred to in this disclosure mean that the horizontal positions of the two are approximately the same, that is, they have approximately the same value on the Y coordinates in Figures 1 and 3, and the "staggered" referred to in this disclosure Or "non-overlapping" means that the horizontal positions of the two are different, specifically, the two have different values on the Y coordinates in Figures 1 and 3 .
如第1、3圖所示，在本實施例中，半導體接觸層2的第一區域21與第一部分221分別直接接觸於半導體疊層1與第一電極3，且如第2圖所示，由上視觀之，第一區域21的面積與第二區域22的面積不同，但本揭露內容並不以此為限。本實施例的第一區域21的面積小於第二區域22的面積，以使電流能夠有效分布於半導體疊層1，且同時亦可以盡量減少半導體接觸層2對光線的吸收，較佳的，由半導體元件100的上視方向觀之，第一區域21與第二區域22的面積比值為0.1～0.95，或者為0.3～0.78。另外，半導體疊層1的第一上視面積大於半導體接觸層2的第二上視面積。詳言之，請參照第2圖所示，由半導體元件100的上視方向觀之，半導體疊層1具有一第一輪廓P1，半導體接觸層2具有一第二輪廓P2，且由第一輪廓P1圍設的第一上視面積大於由第二輪廓P2圍設的第二上視面積。舉例而言：第二上視面積可以為第一上視面積的5%～60%，或者可以為10%～50%，較佳為15%～40%。此外，由半導體元件100的上視方向觀之，半導體接觸層2的第一區域21具有一第三上視面積，第三上視面積可以為第一上視面積的10%～30%，較佳為7%～20%。透過半導體接觸層2部分重疊於半導體疊層1，能將第一電極3注入至半導體接觸層2的電流均勻分散至半導體疊層1中，且同時使半導體元件100維持良好的出光效率，藉此獲得高亮度及低驅動電壓的半導體元件100。此外，請參照第3圖，半導體接觸層2的厚度t1可以為100 nm～2µm，較佳為500 nm～1µm，如此可使半導體接觸層2與半導體疊層1之間形成良好的電性連接，並且避免半導體接觸層2過厚而導致半導體元件100的效率因光線被遮蔽而下降。在另一實施例中，半導體接觸層2的第二區域22之第一部分221具有一第四上視面積小於第三上視面積。此外，本實施例的第一輪廓P1及第二輪廓P2為規則形狀，例如為第2圖所示的長方形，在其他實施例中，第一輪廓P1與第二輪廓P2亦可以為不規則形，或者第一輪廓P1與第二輪廓P2之一為規則形狀、另一為不規則形狀。As shown in Figures 1 and 3, in this embodiment, the first region 21 and the first portion 221 of the semiconductor contact layer 2 are in direct contact with the semiconductor stack 1 and the first electrode 3, respectively, and as shown in Figure 2, Viewed from above, the area of the first region 21 is different from that of the second region 22 , but the present disclosure is not limited thereto. In this embodiment, the area of the first region 21 is smaller than the area of the second region 22, so that the current can be effectively distributed in the semiconductor stack 1, and at the same time, the absorption of light by the semiconductor contact layer 2 can be minimized. Preferably, by Viewed from the top view direction of the semiconductor device 100 , the area ratio of the first region 21 to the second region 22 is 0.1˜0.95, or 0.3˜0.78. In addition, the first top view area of the semiconductor stack 1 is larger than the second top view area of the semiconductor contact layer 2 . Specifically, please refer to FIG. 2 , as viewed from the top view direction of the semiconductor element 100, the semiconductor stack 1 has a first profile P1, the semiconductor contact layer 2 has a second profile P2, and from the first profile The first top view area surrounded by P1 is larger than the second top view area surrounded by the second outline P2. For example: the second upper viewing area may be 5% to 60% of the first upper viewing area, or may be 10% to 50%, preferably 15% to 40%. In addition, viewed from the top view direction of the semiconductor element 100, the first region 21 of the semiconductor contact layer 2 has a third top view area, and the third top view area may be 10% to 30% of the first top view area, which is relatively The best is 7% to 20%. By partially overlapping the semiconductor contact layer 2 with the semiconductor stack 1, the current injected into the semiconductor contact layer 2 by the first electrode 3 can be evenly dispersed into the semiconductor stack 1, and at the same time, the semiconductor element 100 can maintain good light extraction efficiency, thereby A semiconductor element 100 with high brightness and low driving voltage is obtained. In addition, please refer to FIG. 3, the thickness t1 of the semiconductor contact layer 2 can be 100 nm to 2 µm, preferably 500 nm to 1 µm, so that a good electrical connection can be formed between the semiconductor contact layer 2 and the semiconductor stack 1 , and prevent the efficiency of the semiconductor element 100 from being reduced due to light being shielded due to the excessive thickness of the semiconductor contact layer 2 . In another embodiment, the first portion 221 of the second region 22 of the semiconductor contact layer 2 has a fourth top view area smaller than the third top view area. In addition, the first profile P1 and the second profile P2 of this embodiment are regular shapes, such as the rectangle shown in FIG. 2 . In other embodiments, the first profile P1 and the second profile P2 can also be irregular shapes. , or one of the first profile P1 and the second profile P2 is a regular shape, and the other is an irregular shape.
請續參照第1～3圖所示，第一電極3設於半導體接觸層2的第二區域22上，且透過第二區域22的第一部分221與半導體疊層1電性連接，且半導體元件100另包含一第二電極4與第一電極3分離且位於半導體疊層1上，第一電極3與第二電極4可用以連接外部電源並將電流傳遞至半導體疊層1中。詳言之，第一電極3與第二電極4分別電性連接於第一半導體層11與第二半導體層12，第一電極3及第二電極4位於半導體接觸層2的同一側，以形成一水平式半導體元件，且第一電極3與第二電極4分別具有一第一面31及一第二面41，且第一面31及第二面41係遠離半導體接觸層2。第一面31與第二面41的上視面積可以相同或不同，在本實施例中，第一面31的上視面積較佳等於第二面41的上視面積。另外，於第一實施例中，第一電極1的第一面31與第二電極2的第二面41基本上係位於同一水平面，使得當半導體元件100以倒裝接合至一電路結構時，大致齊平的的第一電極3與第二電極4有利於提升半導體元件100與電路連接結構(如印刷電路板)的接合良率。在本實施例中，第一電極3及第二電極4分別設於半導體接觸層2及第二半導體層12上，由於半導體接觸層2及第二半導體層12之間具有一高低差，為了使第一面31大致齊平於第二電極4，第二電極2與第一電極1的厚度可以不同，例如第3圖所示，第一電極3之厚度大於第二電極4的厚度。在另一實施例中(圖未示)，第一電極3與第二電極4是位於半導體接觸層2的相反側，以形成一垂直式半導體結構。在第一實施例中，第一電極3與第二電極4之間具有一間隙G，由剖視觀之，間隙G的寬度不超過200µm，較佳為50µm～150µm。第一電極3與第二電極4的材料可以包含金(Au)、銀(Ag)、鉑(Pt)、銅(Cu)、錫(Sn)、鎳(Ni)、鈦(Ti)或上述金屬之合金。此外，於本實施例中，半導體疊層1係與第一電極3在水平位置上互相交錯，詳言之，如第1、3圖所示，半導體疊層1與第一電極3具有不相同的Y座標數值。在此需要說明的是，活性結構13與第二半導體層12係以一堆疊方向形成於第一半導體層11上方，上述之第一電極3及第二電極4的厚度平行於堆疊方向，即上述第一電極3、第二電極4的厚度及半導體接觸層2的厚度t1是沿著第1、3圖X軸的方向延伸。Please continue referring to FIGS. 1-3, the first electrode 3 is disposed on the second region 22 of the semiconductor contact layer 2, and is electrically connected to the semiconductor stack 1 through the first portion 221 of the second region 22, and the semiconductor element The 100 further includes a second electrode 4 separated from the first electrode 3 and located on the semiconductor stack 1 , the first electrode 3 and the second electrode 4 can be used to connect to an external power source and transmit current to the semiconductor stack 1 . Specifically, the first electrode 3 and the second electrode 4 are electrically connected to the first semiconductor layer 11 and the second semiconductor layer 12 respectively, and the first electrode 3 and the second electrode 4 are located on the same side of the semiconductor contact layer 2 to form A horizontal semiconductor device, and the first electrode 3 and the second electrode 4 respectively have a first surface 31 and a second surface 41 , and the first surface 31 and the second surface 41 are away from the semiconductor contact layer 2 . The upper viewing area of the first surface 31 and the second surface 41 may be the same or different. In this embodiment, the upper viewing area of the first surface 31 is preferably equal to the upper viewing area of the second surface 41 . In addition, in the first embodiment, the first surface 31 of the first electrode 1 and the second surface 41 of the second electrode 2 are substantially on the same level, so that when the semiconductor element 100 is flip-chip bonded to a circuit structure, The approximately flush first electrode 3 and second electrode 4 are beneficial to improve the bonding yield between the semiconductor element 100 and the circuit connection structure (such as a printed circuit board). In this embodiment, the first electrode 3 and the second electrode 4 are respectively arranged on the semiconductor contact layer 2 and the second semiconductor layer 12. Since there is a height difference between the semiconductor contact layer 2 and the second semiconductor layer 12, in order to make The first surface 31 is substantially flush with the second electrode 4 , and the thickness of the second electrode 2 and the first electrode 1 can be different. For example, as shown in FIG. 3 , the thickness of the first electrode 3 is greater than that of the second electrode 4 . In another embodiment (not shown), the first electrode 3 and the second electrode 4 are located on opposite sides of the semiconductor contact layer 2 to form a vertical semiconductor structure. In the first embodiment, there is a gap G between the first electrode 3 and the second electrode 4 , and the width of the gap G is not more than 200 μm, preferably 50 μm˜150 μm in cross-sectional view. The materials of the first electrode 3 and the second electrode 4 may include gold (Au), silver (Ag), platinum (Pt), copper (Cu), tin (Sn), nickel (Ni), titanium (Ti) or the above metals alloy. In addition, in this embodiment, the semiconductor stack 1 and the first electrode 3 are staggered horizontally. Specifically, as shown in Figures 1 and 3, the semiconductor stack 1 and the first electrode 3 have different The Y coordinate value of . It should be noted here that the active structure 13 and the second semiconductor layer 12 are formed above the first semiconductor layer 11 in a stacking direction, and the thicknesses of the above-mentioned first electrodes 3 and second electrodes 4 are parallel to the stacking direction, that is, the above-mentioned The thickness of the first electrode 3 and the second electrode 4 and the thickness t1 of the semiconductor contact layer 2 extend along the direction of the X-axis in the first and third figures.
本揭露內容的半導體元件100另包含一電流散佈結構5設於半導體疊層1上，於本實施例中，電流散佈結構5覆蓋於半導體接觸層2，且延伸至半導體疊層1上。電流散佈結構5可以幫助將半導體接觸層2的電流均勻地傳遞至半導體疊層1中。電流散佈結構5可以完全覆蓋於半導體疊層1與半導體接觸層2的一表面，或者，電流散佈結構5亦可以如本實施例第1～2圖所示，僅覆蓋部分的半導體接觸層2及部分的半導體疊層1，而使部分的半導體接觸層2及半導體疊層1的表面因未被電流散佈結構5覆蓋而暴露，使電流散佈結構5具有一覆蓋比例，藉此減少電流散佈結構5遮蔽活性結構13之發光面積。例如本實施例的電流散佈結構5的覆蓋比例為A4/ (A1+A2-A3)，其中，A4為電流散佈結構5的上視面積，A1為半導體疊層1的第一上視面積，A2為半導體接觸層2的第二上視面積，A3為半導體接觸層2的第一區域21的第三上視面積。由俯視觀之，電流散佈結構5的覆蓋比例較佳為5%～60%、或者為10%～50%，或者為15%～30%。本實施例的電流散佈結構5可以包含金屬材料，例如銅(Cu)、鋁(Al)、錫(Sn)、金(Au)、銀(Ag)、鉛(Pb)、鈦(Ti)、鎳(Ni)、鉑(Pt)、鎢(W)或上述材料之合金等；此外，在另一實施例中，電流散佈結構5可以包含對活性結構13發出之光線具有高穿透率的材料，優選為穿透率在80%～99.99%的材料，例如氧化銦錫(ITO)、氧化銦(InO)、氧化錫(SnO)、氧化鎘錫(CTO)、氧化銻錫(ATO)、氧化鋁鋅(AZO)、氧化鋅錫(ZTO)、氧化鎵鋅(GZO)、氧化銦鎢(IWO)、氧化鋅(ZnO)、磷化鎵(GaP)、氧化銦鈰(ICO)、氧化銦鎢(IWO)、氧化銦鈦(ITiO)、氧化銦鋅(IZO)、氧化銦鎵(IGO)、氧化鎵鋁鋅(GAZO)、石墨烯或上述材料之組合等。在另一實施例中，特別是半導體元件100具有較小尺寸時，電流散佈結構5可以包含半導體材料，且較佳為對活性區域13發出之光線具有80%～99.99%穿透率的半導體材料。上述請參照第3圖，在第一實施例中，電流散佈結構5具有一厚度t2約為500 nm～3.5µm，且電流散佈結構5的厚度t2與半導體接觸層2的厚度t1比值小於10，例如為0.8～7，且較佳為1～5。然而，在本揭露內容的其他實施例中，半導體元件100可不具有電流散佈結構5，舉例而言，當半導體元件100具有較小尺寸(例如單邊長度小於10 mil或進一步小於100 nm) 時，半導體元件100僅具有半導體接觸層2進行電性傳導，亦可達到理想的電流分散效果。The semiconductor device 100 of the present disclosure further includes a current spreading structure 5 disposed on the semiconductor stack 1 . In this embodiment, the current spreading structure 5 covers the semiconductor contact layer 2 and extends to the semiconductor stack 1 . The current spreading structure 5 can help to uniformly transfer the current of the semiconductor contact layer 2 into the semiconductor stack 1 . The current spreading structure 5 can completely cover one surface of the semiconductor stack 1 and the semiconductor contact layer 2, or the current spreading structure 5 can also cover only part of the semiconductor contact layer 2 and the semiconductor contact layer 2 as shown in Figures 1-2 of this embodiment. Part of the semiconductor stack 1, so that part of the semiconductor contact layer 2 and the surface of the semiconductor stack 1 are exposed because they are not covered by the current spreading structure 5, so that the current spreading structure 5 has a coverage ratio, thereby reducing the current spreading structure 5 The light-emitting area of the active structure 13 is shielded. For example, the coverage ratio of the current spreading structure 5 in this embodiment is A4/(A1+A2-A3), wherein A4 is the top view area of the current spread structure 5, A1 is the first top view area of the semiconductor laminate 1, and A2 is the second top view area of the semiconductor contact layer 2 , and A3 is the third top view area of the first region 21 of the semiconductor contact layer 2 . Viewed from a top view, the coverage ratio of the current spreading structure 5 is preferably 5%-60%, or 10%-50%, or 15%-30%. The current spreading structure 5 of this embodiment may include metal materials such as copper (Cu), aluminum (Al), tin (Sn), gold (Au), silver (Ag), lead (Pb), titanium (Ti), nickel (Ni), platinum (Pt), tungsten (W) or alloys of the above materials, etc.; in addition, in another embodiment, the current spreading structure 5 may include a material with high transmittance to the light emitted by the active structure 13, It is preferably a material with a transmittance of 80% to 99.99%, such as indium tin oxide (ITO), indium oxide (InO), tin oxide (SnO), cadmium tin oxide (CTO), antimony tin oxide (ATO), aluminum oxide Zinc (AZO), zinc tin oxide (ZTO), gallium zinc oxide (GZO), indium tungsten oxide (IWO), zinc oxide (ZnO), gallium phosphide (GaP), indium cerium oxide (ICO), indium tungsten oxide ( IWO), indium titanium oxide (ITiO), indium zinc oxide (IZO), indium gallium oxide (IGO), gallium aluminum zinc oxide (GAZO), graphene or a combination of the above materials, etc. In another embodiment, especially when the semiconductor element 100 has a small size, the current spreading structure 5 may comprise a semiconductor material, preferably a semiconductor material with a transmittance of 80% to 99.99% for the light emitted by the active region 13 . Please refer to FIG. 3 above. In the first embodiment, the current spreading structure 5 has a thickness t2 of about 500 nm to 3.5 μm, and the ratio of the thickness t2 of the current spreading structure 5 to the thickness t1 of the semiconductor contact layer 2 is less than 10, For example, it is 0.8-7, and preferably it is 1-5. However, in other embodiments of the present disclosure, the semiconductor device 100 may not have the current spreading structure 5. For example, when the semiconductor device 100 has a small size (eg, the length of a single side is less than 10 mil or further less than 100 nm), The semiconductor element 100 only has the semiconductor contact layer 2 for electrical conduction, which can also achieve an ideal current spreading effect.
請續參照第1、3圖所示，半導體元件100另包含一支持結構6連接半導體疊層1。本實施例的支持結構6用以保護半導體疊層1，並增加半導體元件100的機械強度，使半導體疊層1不易受到外界力量而損傷、斷裂。支持結構6覆蓋於半導體疊層1、半導體接觸層2、第一電極3及第二電極4的環周面，詳言之，本實施例的支持結構6包含一第一支持部61、一第二支持部62及一第三支持部63，第一支持部61及第二支持部62設於半導體元件100的相對兩側或周圍，第一支持部61與半導體疊層1及第二電極4相連接，第二支持部62則與第一電極3及半導體接觸層2的第三部分223相連接。第三支持部63連接於半導體接觸層2的第二部分223，且設於第一電極3與第二電極4的間隙G內。詳言之，第三支持部63設於半導體疊層1、半導體接觸層2、第一電極3及第二電極4之間以連接上述各構件，且第三支持部63與第二部分222直接接觸。第一支持部61、第二支持部62及第三支持部63分別具有寬度d1、d2、d3，且本實施例之第三支持部63的寬度d3大於其餘二支持部61、62的寬度d1、d2，藉此強化第一電極3與第二電極4之間的電性絕緣與半導體元件100在此處的結構強度，避免電流透過第三支持部63的縫隙或缺陷而導通造成短路失效。支持結構6包含絕緣材料，絕緣材料可以為有機材料或無機材料，有機材料例如Su8、苯并環丁烯（BCB）、過氟環丁烷（PFCB）、環氧樹脂（Epoxy）、丙烯酸樹脂（Acrylic Resin）、環烯烴聚合物（COC）、聚甲基丙烯酸甲酯（PMMA）、聚對苯二甲酸乙二酯（PET）、聚碳酸酯（PC）、聚醚醯亞胺（Polyetherimide）或氟碳聚合物（Fluorocarbon Polymer）；無機材料例如矽膠（Silicone）、玻璃（Glass）、氧化鋁（Al2O3）、氮化矽（SiNx）、氧化矽（SiO2）、氧化鈦（TiO2）或氟化鎂（MgF2）。在一實施例中，為了進一步提高半導體元件100的出光效率，支持結構6可以包含對活性結構13發出的光線具有高於85%的反射率的反射物質，例如二氧化鈦(TiO2)、二氧化矽(SiO2)或氧化鋁(Al2O3)。Please continue referring to FIGS. 1 and 3 , the semiconductor device 100 further includes a support structure 6 connected to the semiconductor stack 1 . The support structure 6 of this embodiment is used to protect the semiconductor stack 1 and increase the mechanical strength of the semiconductor element 100 so that the semiconductor stack 1 is not easily damaged or broken by external force. The support structure 6 covers the peripheral surfaces of the semiconductor stack 1, the semiconductor contact layer 2, the first electrode 3 and the second electrode 4. Specifically, the support structure 6 of this embodiment includes a first support portion 61, a first Two support portions 62 and a third support portion 63, the first support portion 61 and the second support portion 62 are arranged on opposite sides or surroundings of the semiconductor element 100, the first support portion 61 is connected to the semiconductor stack 1 and the second electrode 4 The second support portion 62 is connected to the first electrode 3 and the third portion 223 of the semiconductor contact layer 2 . The third supporting portion 63 is connected to the second portion 223 of the semiconductor contact layer 2 and is disposed in the gap G between the first electrode 3 and the second electrode 4 . Specifically, the third support portion 63 is disposed between the semiconductor stack 1, the semiconductor contact layer 2, the first electrode 3, and the second electrode 4 to connect the above components, and the third support portion 63 is directly connected to the second portion 222. touch. The first supporting portion 61, the second supporting portion 62 and the third supporting portion 63 have widths d1, d2, and d3 respectively, and the width d3 of the third supporting portion 63 in this embodiment is greater than the width d1 of the remaining two supporting portions 61, 62 , d2, so as to strengthen the electrical insulation between the first electrode 3 and the second electrode 4 and the structural strength of the semiconductor element 100 here, so as to prevent the current from passing through the gap or defect of the third supporting portion 63 and causing short circuit failure. The support structure 6 contains insulating materials, which can be organic materials or inorganic materials, organic materials such as Su8, benzocyclobutene (BCB), perfluorocyclobutane (PFCB), epoxy resin (Epoxy), acrylic resin ( Acrylic Resin), cycloolefin polymer (COC), polymethyl methacrylate (PMMA), polyethylene terephthalate (PET), polycarbonate (PC), polyetherimide (Polyetherimide) or Fluorocarbon Polymer; Inorganic materials such as Silicone, Glass, Aluminum Oxide (Al2O3), Silicon Nitride (SiNx), Silicon Oxide (SiO2), Titanium Oxide (TiO2) or Magnesium Fluoride (MgF2). In one embodiment, in order to further improve the light extraction efficiency of the semiconductor element 100, the support structure 6 may contain a reflective material with a reflectivity higher than 85% for the light emitted by the active structure 13, such as titanium dioxide (TiO2), silicon dioxide ( SiO2) or aluminum oxide (Al2O3).
請參照第4圖所示，此為本揭露內容第二實施例的半導體元件200的剖面示意圖。第二實施例的半導體元件200之各構件及構件的連接關係與第一實施例類似，本實施例的半導體元件200另包含一保護層7位於半導體接觸層2上，以保護半導體接觸層2使其不易受到外界不當力量介入而損傷，也可以藉此增加半導體元件100的機械強度。本實施例的保護層7及第一電極3分別設於半導體接觸層2的相對兩側，以共同保護半導體接觸層2。保護層7可以包含一導電材料以具有導電性，藉此將由第一電極3輸入的電流透過半導體接觸層2、保護層7及電流散佈層5傳遞或分散至半導體疊層1中，保護層7所包含的導電材料例如金(Au)、銀(Ag)、鉑(Pt)、銅(Cu)、錫(Sn)、鎳(Ni)、鈦(Ti)或上述金屬之合金。或者，保護層7可以包含絕緣材料，例如Su8、苯并環丁烯（BCB）、過氟環丁烷（PFCB）、環氧樹脂（Epoxy）、丙烯酸樹脂（Acrylic Resin）、環烯烴聚合物（COC）、聚甲基丙烯酸甲酯（PMMA）、聚對苯二甲酸乙二酯（PET）、聚碳酸酯（PC）、聚醚醯亞胺（Polyetherimide）、氟碳聚合物（Fluorocarbon Polymer）、矽膠（Silicone）、玻璃（Glass）、氧化鋁（Al2O3）、氮化矽（SiNx）、氧化矽（SiO2）、氧化鈦（TiO2）或氟化鎂（MgF2）等。保護層7的材料可以選擇與第一電極3相同或不同，在此不多做限制。本實施例的保護層7設置在半導體接觸層2及電流散佈結構5之間，但本揭露不以此為限，在其他實施例中，保護層7設置於電流散佈結構5上，使電流散佈結構5位於保護層7及半導體接觸層2之間，藉此使保護層7可以同時支持、保護半導體接觸層2及電流散佈結構5。Please refer to FIG. 4 , which is a schematic cross-sectional view of a semiconductor device 200 according to a second embodiment of the present disclosure. The connection relationship between the components and components of the semiconductor element 200 of the second embodiment is similar to that of the first embodiment. The semiconductor element 200 of the present embodiment further includes a protective layer 7 on the semiconductor contact layer 2 to protect the semiconductor contact layer 2 so that It is not easy to be damaged by the intervention of improper external forces, and the mechanical strength of the semiconductor device 100 can also be increased. The protection layer 7 and the first electrode 3 in this embodiment are respectively disposed on opposite sides of the semiconductor contact layer 2 to jointly protect the semiconductor contact layer 2 . The protection layer 7 may include a conductive material to have conductivity, so that the current input by the first electrode 3 is transferred or dispersed to the semiconductor stack 1 through the semiconductor contact layer 2, the protection layer 7 and the current spreading layer 5. The protection layer 7 The conductive materials included are gold (Au), silver (Ag), platinum (Pt), copper (Cu), tin (Sn), nickel (Ni), titanium (Ti) or alloys of the above metals. Alternatively, the protective layer 7 may contain insulating materials such as Su8, benzocyclobutene (BCB), perfluorocyclobutane (PFCB), epoxy resin (Epoxy), acrylic resin (Acrylic Resin), cycloolefin polymer ( COC), polymethyl methacrylate (PMMA), polyethylene terephthalate (PET), polycarbonate (PC), polyetherimide (Polyetherimide), fluorocarbon polymer (Fluorocarbon Polymer), Silicone (Silicone), glass (Glass), aluminum oxide (Al2O3), silicon nitride (SiNx), silicon oxide (SiO2), titanium oxide (TiO2) or magnesium fluoride (MgF2), etc. The material of the protective layer 7 can be selected to be the same as or different from that of the first electrode 3 , and there is no limitation here. The protective layer 7 of this embodiment is arranged between the semiconductor contact layer 2 and the current spreading structure 5, but the present disclosure is not limited thereto. In other embodiments, the protective layer 7 is arranged on the current spreading structure 5, so that the current spreads The structure 5 is located between the protection layer 7 and the semiconductor contact layer 2 , so that the protection layer 7 can support and protect the semiconductor contact layer 2 and the current spreading structure 5 at the same time.
請參照第5A~5B圖所示，此分別為本揭露內容第三實施例的半導體元件300的上視示意圖及剖面示意圖，第三實施例的半導體元件300之各構件及構件的連接關係與第一實施例類似，本實施例的半導體元件300的半導體接觸層2另包含一延伸區域23連接於第一區域21，延伸區域23具有單一或數個延伸部231自第一區域21沿一延伸方向朝向第一支持部61延伸。在本實施例中，由半導體元件300的上視方向觀之，各延伸部231具有一第一寬度W1，電流散佈結構5具有一第二寬度W2小於第一寬度W1，使各延伸部231凸出於電流散佈結構5之外。此外，由半導體元件300的上視方向觀之，各延伸部231適形地形成於電流散佈結構5之外，且半導體疊層1的第一輪廓P1為規則形狀，半導體接觸層2的第二輪廓P2為不規則狀如梳狀、L狀或T狀。當電流散佈結構5包含之材料對活性結構13的發光具有低穿透率時，透過具有延伸區域23的半導體接觸層2適形地形成於電流散佈結構5的下方，一方面可擴大半導體接觸層2的面積，使電流更有效、均勻地分散於半導體疊層1中，另一方面亦不致增加過多會遮蔽光線的半導體接觸層2。請參照第5C圖所示，此為本揭露內容第四實施例的半導體元件400的上視示意圖，第四實施例的半導體元件400之各構件及構件的連接關係與第一實施例類似。在第四實施例的半導體元件400中，半導體接觸層2包含數個互相分離的接觸部2a，電流散佈結構5包含數個分離的電流分散部5a，且由上視觀之，各接觸部2a適形地環繞各電流分散部5a。上述第一寬度W1及第二寬度W2的方向垂直於延伸部231的延伸方向，詳言之，上述第一寬度W1及第二寬度W2平行於第5A圖的Z軸方向。Please refer to Figures 5A-5B, which are respectively a schematic top view and a schematic cross-sectional view of a semiconductor device 300 according to the third embodiment of the present disclosure. Similar to an embodiment, the semiconductor contact layer 2 of the semiconductor element 300 of this embodiment further includes an extension region 23 connected to the first region 21, and the extension region 23 has a single or several extension portions 231 extending from the first region 21 along an extension direction Extends toward the first support portion 61 . In this embodiment, viewed from the top view direction of the semiconductor element 300, each extension 231 has a first width W1, and the current spreading structure 5 has a second width W2 smaller than the first width W1, so that each extension 231 is convex. out of the current spreading structure 5 . In addition, viewed from the top view direction of the semiconductor element 300, each extension portion 231 is conformally formed outside the current spreading structure 5, and the first contour P1 of the semiconductor stack 1 is a regular shape, and the second contour P1 of the semiconductor contact layer 2 The profile P2 is irregular, such as a comb, L or T shape. When the material contained in the current spreading structure 5 has a low transmittance to the light emission of the active structure 13, the semiconductor contact layer 2 with the extension region 23 is conformally formed under the current spreading structure 5, on the one hand, the semiconductor contact layer can be enlarged 2, so that the current is more effectively and uniformly dispersed in the semiconductor stack 1, and on the other hand, the semiconductor contact layer 2 that would block the light will not be added too much. Please refer to FIG. 5C , which is a schematic top view of the semiconductor device 400 according to the fourth embodiment of the present disclosure. The components and connection relationships of the semiconductor device 400 in the fourth embodiment are similar to those in the first embodiment. In the semiconductor element 400 of the fourth embodiment, the semiconductor contact layer 2 includes several contact portions 2a separated from each other, the current spreading structure 5 includes several separate current spreading portions 5a, and each contact portion 2a Each current spreading portion 5a is conformally surrounded. The directions of the first width W1 and the second width W2 are perpendicular to the extending direction of the extension portion 231 , in detail, the first width W1 and the second width W2 are parallel to the Z-axis direction in FIG. 5A .
第6A-6E圖為半導體元件100之製造方法實施例的示意圖。首先於一成長基板8上形成一半導體疊層結構1’，如第6A圖所示，其中本實施例是以磊晶成長方式於成長基板8上依序形成一緩衝層9、一蝕刻阻擋層10、一半導體接觸結構2’及半導體疊層結構1’，半導體疊層結構1’包含依序形成在半導體接觸結構2’上方的一第三半導體結構14’、一第一半導體結構11’、一活性區域13’及一第二半導體結構12’。 成長基板8可以包含半導體材料，例如砷化鎵 (GaAs)、碳化矽(SiC)、磷化鎵(GaP)、磷砷化鎵(GaAsP) 、硒化鋅(ZnSe)、硒化鋅(ZnSe)、磷化銦(InP)或氧化鋁(sapphire)。半導體疊層結構1’可以透過有機金屬化學氣相沉積法(MOCVD) 、分子束磊晶法(MBE) 或氫化物氣相磊晶法 (HVPE) 等磊晶方法成長於成長基板上8。緩衝層9可以用以增加半導體疊層結構1’的磊晶生長品質，或者可以將緩衝層9作為後續移除成長基板8時的作用層，緩衝層9可以包含多晶材料或單晶材料，緩衝層9之材料可包含三五族化合物半導體例如砷化鎵(GaAs)、氮化鎵(GaN)、氮化鋁(AlN)或氮化鋁鎵(AlGaN)。蝕刻阻擋層10可用以在後續移除成長基板8時保護半導體疊層結構1’不受到移除成長基板8的製程損傷，其中，蝕刻阻擋層10可以包含具有被蝕刻速率較緩衝層9低的三五族化合物半導體材料，藉此達到保護半導體疊層結構1’的效果，惟上述的磊晶方法與各層的材料選擇並不以此為限。6A-6E are schematic diagrams of an embodiment of a manufacturing method of the semiconductor device 100 . Firstly, a semiconductor stacked structure 1' is formed on a growth substrate 8, as shown in FIG. 6A, wherein in this embodiment, a buffer layer 9 and an etching stopper layer are sequentially formed on the growth substrate 8 by means of epitaxial growth. 10. A semiconductor contact structure 2' and a semiconductor stacked structure 1', the semiconductor stacked structure 1' comprising a third semiconductor structure 14', a first semiconductor structure 11', An active region 13' and a second semiconductor structure 12'. The growth substrate 8 may include semiconductor materials, such as gallium arsenide (GaAs), silicon carbide (SiC), gallium phosphide (GaP), gallium arsenide phosphide (GaAsP), zinc selenide (ZnSe), zinc selenide (ZnSe) , indium phosphide (InP) or aluminum oxide (sapphire). The semiconductor stacked structure 1' can be grown on the growth substrate 8 by epitaxial methods such as metal organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE) or hydride vapor phase epitaxy (HVPE). The buffer layer 9 can be used to increase the epitaxial growth quality of the semiconductor stacked structure 1 ′, or the buffer layer 9 can be used as an active layer when the growth substrate 8 is subsequently removed, and the buffer layer 9 can include polycrystalline material or single crystal material, The material of the buffer layer 9 may include III-V compound semiconductors such as gallium arsenide (GaAs), gallium nitride (GaN), aluminum nitride (AlN) or aluminum gallium nitride (AlGaN). The etch barrier layer 10 can be used to protect the semiconductor stacked structure 1' from the process damage of removing the growth substrate 8 when the growth substrate 8 is subsequently removed, wherein the etch barrier layer 10 can comprise III-V compound semiconductor materials, so as to achieve the effect of protecting the semiconductor stacked structure 1 ′, but the above-mentioned epitaxial method and the material selection of each layer are not limited thereto.
請參照第6B圖所示，接著，圖形化半導體疊層結構1’而移除部分的半導體疊層結構1’並暴露部分的半導體接觸結構2’，並保留另一部分的半導體疊層結構1’於半導體接觸結構2’上以形成半導體疊層1。移除部分半導體疊層結構1’的方法可以透過乾蝕刻、濕蝕刻等方法，但本揭露內容並不對移除方法多做限制。本實施例係透過兩階段移除法形成半導體疊層1，詳言之，第一階段係移除部分的第二半導體結構12’、活性區域13’及第一半導體結構11’以分別形成第二半導體層12、活性結構13及第一半導體層11，此時，第三半導體結構14’大致上未被移除而能夠保護下方的半導體接觸結構2’，避免在移除部分的半導體結構疊層結構1’的過程中傷害半導體接觸結構2’；接著，再利用與第一階段不同的移除條件移除部分的第三半導體結構14’以形成第三半導體層14。在本實施例中，上述「不同的移除條件」為第一階段與第二階段使用不同的蝕刻液，但並不以此為限。Please refer to FIG. 6B, and then, pattern the semiconductor stack structure 1' to remove part of the semiconductor stack structure 1' and expose part of the semiconductor contact structure 2', and retain another part of the semiconductor stack structure 1' A semiconductor stack 1 is formed on the semiconductor contact structure 2 ′. The method of removing part of the semiconductor stacked structure 1' can be through methods such as dry etching, wet etching, etc., but this disclosure does not limit the removal method. In this embodiment, the semiconductor stack 1 is formed by a two-stage removal method. Specifically, the first stage is to remove part of the second semiconductor structure 12 ′, the active region 13 ′, and the first semiconductor structure 11 ′ to form the second semiconductor structure 11 ′ respectively. The second semiconductor layer 12, the active structure 13, and the first semiconductor layer 11. At this time, the third semiconductor structure 14' has not been substantially removed to protect the underlying semiconductor contact structure 2', avoiding overlapping of the semiconductor structure in the removed part. During the process of the layer structure 1 ′, the semiconductor contact structure 2 ′ is damaged; then, a part of the third semiconductor structure 14 ′ is removed by using a removal condition different from that of the first stage to form the third semiconductor layer 14 . In this embodiment, the above "different removal conditions" means that different etching solutions are used in the first stage and the second stage, but it is not limited thereto.
隨後，如第6C圖所示，第一電極3及第二電極4分別形成於半導體接觸結構2’及半導體疊層1上，其中，第一電極3及第二電極4位於半導體接觸層2的同一側，且第一電極3的第一面31與第二電極4的第二面41係遠離半導體接觸層2，本實施例的第一面31與第二面41大致齊平而位於同一水平面上。在本實施例中，先於半導體接觸結構2’及半導體疊層1上以電鍍或化鍍形成一金屬膜層，接著再透過圖形化金屬膜層以形成互相分離的第一電極3與第二電極4，但本揭露內容並不以此為限。接著，如第6D圖所示，形成支撐結構6並覆蓋半導體疊層1、第一電極3及第二電極4的環周面以及半導體接觸結構2’之表面，並接續移除成長基板8。其中，支撐結構6較佳成形於成長基板8移除之前，以利用支撐結構6增加半導體疊層1的機械強度，避免半導體疊層1在移除成長基板8時產生損傷或破裂。支撐結構6可以透過網板印刷（screen printing）、塗佈（coating）、噴塗（spraying）、點膠（dispensing）、濺鍍（sputtering）、以及鑄模灌膠（molding）等方式形成。另外，分離成長基板8的方法包括利用濕式蝕刻法直接移除成長基板8，或移除成長基板8與半導體疊層1之間的緩衝層9，進而分離成長基板8與半導體疊層1；此外，也可以利用雷射剝離技術（Laser-Lift），使用雷射光穿透成長基板8，照射成長基板8與半導體疊層1之間的界面，來達到分離半導體疊層1與成長基板8的目的；或者，可以於高溫下利用蒸氣蝕刻直接移除位於成長基板8與半導體疊層1之間的緩衝層9，達到分離成長基板8與半導體疊層1之目的。本實施例是透過移除緩衝層9以分離成長基板8與半導體疊層1，並以蝕刻阻擋層10保護半導體接觸結構2’不受到緩衝層9移除過程的影響而損傷。Subsequently, as shown in FIG. 6C, the first electrode 3 and the second electrode 4 are respectively formed on the semiconductor contact structure 2' and the semiconductor stack 1, wherein the first electrode 3 and the second electrode 4 are located on the semiconductor contact layer 2 On the same side, and the first surface 31 of the first electrode 3 and the second surface 41 of the second electrode 4 are far away from the semiconductor contact layer 2, the first surface 31 and the second surface 41 of this embodiment are approximately flush and located on the same horizontal plane superior. In this embodiment, a metal film layer is formed by electroplating or electroless plating on the semiconductor contact structure 2' and the semiconductor stack 1, and then the first electrode 3 and the second electrode 3 separated from each other are formed by patterning the metal film layer. electrode 4, but the present disclosure is not limited thereto. Next, as shown in FIG. 6D, a support structure 6 is formed to cover the semiconductor stack 1, the peripheral surfaces of the first electrode 3 and the second electrode 4, and the surface of the semiconductor contact structure 2', and then the growth substrate 8 is removed. Wherein, the support structure 6 is preferably formed before the growth substrate 8 is removed, so as to increase the mechanical strength of the semiconductor stack 1 by using the support structure 6 , and prevent the semiconductor stack 1 from being damaged or cracked when the growth substrate 8 is removed. The supporting structure 6 can be formed by screen printing, coating, spraying, dispensing, sputtering, and molding. In addition, the method for separating the growth substrate 8 includes directly removing the growth substrate 8 by wet etching, or removing the buffer layer 9 between the growth substrate 8 and the semiconductor stack 1, and then separating the growth substrate 8 and the semiconductor stack 1; In addition, laser lift-off technology (Laser-Lift) can also be used to use laser light to penetrate the growth substrate 8 and irradiate the interface between the growth substrate 8 and the semiconductor stack 1 to separate the semiconductor stack 1 and the growth substrate 8. Purpose; or, the buffer layer 9 located between the growth substrate 8 and the semiconductor stack 1 can be directly removed by steam etching at high temperature, so as to achieve the purpose of separating the growth substrate 8 and the semiconductor stack 1 . In this embodiment, the growth substrate 8 and the semiconductor stack 1 are separated by removing the buffer layer 9, and the semiconductor contact structure 2' is protected from damage by the removal process of the buffer layer 9 with the etch barrier layer 10.
接著，移除半導體接觸結構2’上的蝕刻阻擋層10，然後進行一移除步驟以移除部分的半導體接觸結構2’，藉此形成半導體接觸層2，且半導體接觸層2包含一第一區域21與半導體疊層1重疊以及一第二區域22與半導體疊層1不重疊，且為增加光取出效率並同時維持電流分散效率，較佳的第一區域21的上視面積佔半導體疊層1的上視面積的10%～30%。最後，如第6E圖所示，對支持結構6、或半導體接觸層2及其上之支持結構6進行切割以形成互相分離的數個半導體元件100。藉由上述移除步驟使半導體接觸層2的上視面積小於半導體疊層1的上視面積，藉此降低半導體接觸層2對活性結構13所發射之光線的吸收率，並提高半導體元件100的整體效率。Next, remove the etch barrier layer 10 on the semiconductor contact structure 2', and then perform a removal step to remove part of the semiconductor contact structure 2', thereby forming a semiconductor contact layer 2, and the semiconductor contact layer 2 includes a first The region 21 overlaps with the semiconductor stack 1 and a second region 22 does not overlap with the semiconductor stack 1, and in order to increase the light extraction efficiency while maintaining the current dispersion efficiency, the preferred top view area of the first region 21 occupies 100% of the semiconductor stack 10% to 30% of the upper viewing area of 1. Finally, as shown in FIG. 6E , the supporting structure 6 , or the semiconductor contact layer 2 and the supporting structure 6 thereon are cut to form several semiconductor elements 100 separated from each other. Through the above removal steps, the upper viewing area of the semiconductor contact layer 2 is smaller than the upper viewing area of the semiconductor stack 1, thereby reducing the absorption rate of the semiconductor contact layer 2 to the light emitted by the active structure 13, and improving the semiconductor element 100. overall efficiency.
可理解的是，本發明所列舉之各實施例僅用以說明本發明，並非用以限制本發明之範圍。任何人對本發明所作顯而易見的修飾或變更皆不脫離本發明之精神與範圍。不同實施例中相同或相似的構件，或者不同實施例中具相同標號的構件皆具有相同的物理或化學特性。此外，本發明中上述之實施例在適當的情況下，是可互相組合或替換，而非僅限於所描述之特定實施例。在一實施例中詳細描述之特定構件與其他構件的連接關係亦可以應用於其他實施例中，且均落於如後所述之本發明之權利保護範圍的範疇中。It can be understood that the various embodiments listed in the present invention are only used to illustrate the present invention, and are not intended to limit the scope of the present invention. Any obvious modifications or changes made by anyone to the present invention will not depart from the spirit and scope of the present invention. The same or similar components in different embodiments, or components with the same number in different embodiments have the same physical or chemical properties. In addition, the above-mentioned embodiments of the present invention can be combined or replaced with each other under appropriate circumstances, and are not limited to the specific embodiments described. The connection relationship between specific components and other components described in detail in one embodiment can also be applied in other embodiments, and all fall within the protection scope of the present invention as described later.
