TWI757187B - Semiconductor device - Google Patents

Abstract

A semiconductor device includes a semiconductor stack and an electrode structure. The semiconductor stack includes a surface with a center, a first margin, and a side margin connecting to the first margin and forming a corner; a virtual line is between the nook and the center. The electrode structure includes an electrode pad on the surface, a first extending electrode, and a second extending electrode; the first extending electrode is closer to the side margin than the second extending electrode, and each of the extending electrodes has a first portion and a second portion; the first portion of the first extending electrode is parallel to the first margin, and the first extending electrode and the second extending electrode respectively have a first curve having a first angle θ1 and a second curve having a second angle θ2; wherein, a first distance is between the first curve and the virtual line, and a second distance is between the second curve and the virtual line, the second distance is greater than the first distance, and θ2>θ1.

Description

semiconductor element

The present disclosure relates to a semiconductor device, especially a semiconductor device with extended electrodes.

The semiconductor element includes compound semiconductors composed of III-V group elements, such as gallium phosphide (GaP), gallium arsenide (GaAs) or gallium nitride (GaN), and the semiconductor element can be an optoelectronic semiconductor element such as a light emitting diode (LED). ), lasers, photodetectors, solar cells, or Power Devices. The structure of the light-emitting diode includes a p-type semiconductor layer, an n-type semiconductor layer and an active layer, and the active layer is arranged between the p-type semiconductor layer and the n-type semiconductor layer, so that under the action of an external electric field, n The electrons and holes provided by the p-type semiconductor layer and the p-type semiconductor layer respectively recombine in the active layer to convert electrical energy into light energy. How to improve the photoelectric conversion efficiency of optoelectronic semiconductor components is actually one of the focuses of R&D personnel.

The present disclosure provides a semiconductor device, comprising: a semiconductor stack and an electrode structure; the semiconductor stack has a surface, and the surface has a center, a first side and a side, the side is connected to the first side and forms a The corners have a virtual connection between the corners and the center; the electrode structure includes an electrode pad formed on the surface, a first extension electrode and a second extension electrode, and the first extension electrode is higher than the first extension electrode. The two extension electrodes are close to the sides, and each extension electrode has a first part and a second part; the first part of the first extension electrode is connected to the second part of the first extension electrode and has a first corner with a first angle θ1, The first part of the second extension electrode is connected to the second part of the second extension electrode and has a second corner with a second angle θ2, there is a first distance between the first corner and the virtual connection line, and the second corner and the virtual connection There is a second distance between the connecting lines; wherein, the first part of the first extending electrode is parallel to the first side, the second distance is greater than the first distance, and θ2>θ1.

The present disclosure provides a semiconductor device, comprising: a semiconductor stack and an electrode structure; the semiconductor stack has a surface, and the surface has a center, a first side, a second side opposite to the first side, and one side side, the side is connected to the first side and the second side, and there is a corner between the side and the first side; the electrode structure is formed on the surface, and the electrode structure includes an electrode pad, a first extension electrode and a second extension electrode , the first extension electrode is closer to the side than the second extension electrode, and the first extension electrode and the second extension electrode each have a first part and a second part, the first part of the first extension electrode and the second part of the first extension electrode The part is connected and has a first corner with a first angle θ1, the first part of the second extension electrode is connected with the second part of the second extension electrode and has a second corner with a second angle θ1; from a top view, The first extension electrode has a first end away from the electrode pad, a first virtual connection between the center and the corner, and a second virtual connection between the center and the first end; wherein the first virtual connection The included angle with the second virtual connection line is less than 120 degrees, and θ2>θ1.

100,200,300: Semiconductor components

1: Semiconductor stack

11: Surface

111: the first semiconductor layer

112: the second semiconductor layer

113: Active Structures

12: First side

13: Second side

14: Side

15: Center

16: Corner

2: Electrode structure

2a: Extended electrode set

21: Electrode pads

22: The first extension electrode

221: The first corner

222: First End

22a, 23a, 24a: Part 1

22b, 23b, 24b: Part II

23: The second extension electrode

231: Second Corner

232: Second End

233: Rendezvous Point

24: The third extension electrode

241: The third corner

242: Third End

25: Fourth extension electrode

26: Fifth extension electrode

27: Sixth extension electrode

28: Intermediate extension electrode

30: Substrate

31: Conductive bonding layer

32: Reflective Structure

320: Ohmic Contact Layer

322: Barrier Layer

324: Reflective bonding layer

326: Reflective layer

33: Transparent conductive structure

33a: first contact upper surface

331: the first transparent conductive layer

332: the second transparent conductive layer

34: Window Layer

35: Insulation layer

35a: Second contact upper surface

351: Pore

36: Second electrode structure

θ1: first angle

θ2: second angle

θ3: The third angle

θ4: included angle

d1: first distance

d2: second distance

d3: the third distance

d4: fourth distance

d5: fifth distance

A1: Virtual central line

P: outline

L1: The first virtual link

L2: Second virtual link

D1: The first extension direction

D2: The second extension direction

D3: The third extension direction

D4: Fourth extension direction

P1: first pitch

P2: Second pitch

W1: first width

W3: third width

W5: Fifth width

W7: seventh width

FIG. 1 is a schematic top view of a semiconductor device according to a first embodiment of the present disclosure.

FIG. 2 is a schematic cross-sectional view of the semiconductor device according to the first embodiment of the present disclosure.

FIG. 3 is a schematic top view of a semiconductor device according to a second embodiment of the present disclosure.

FIG. 4 is a schematic top view of a semiconductor device according to a third embodiment of the present disclosure.

Please refer to FIGS. 1 and 2 , which are a schematic top view and a schematic cross-sectional view of the semiconductor device according to the first embodiment of the present disclosure, respectively. The semiconductor device 100 includes a semiconductor stack 1 and an electrode structure 2 . The semiconductor stack 1 has a surface 11 , and the electrode structure 2 is located on the surface 11 . Specifically, from a top view, the surface 11 of the semiconductor stack 1 has an outline P, and the outline P includes a first side 12 , a second side 13 and a side side 14 connecting the first side 12 and the second side 13 , the first side 12 is opposite to the second side 13 , and the electrode structure 2 includes an electrode pad 21 disposed adjacent to the first side 12 , and an extended electrode group 2 a generally extending from the first side 12 toward the second side 13 . . The extension electrode group 2 a includes a first extension electrode 22 , a second extension electrode 23 and a third extension electrode 24 respectively connected to the electrode pads 21 . The electrode structure 2 is electrically connected to the semiconductor stack 1, and the electrode pad 21 can be electrically connected to an external circuit through a metal wire or a conductive adhesive layer (eg, solder or conductive glue), and can be used to connect an external power source and introduce current into it In the semiconductor stack 1 , the above-mentioned extension electrodes 22 , 23 , 24 distribute the current introduced by the electrode pads 21 into different regions of the semiconductor stack 1 . In this embodiment, the first extension electrode 22 is closer to the outline P of the semiconductor stack 1 than the third extension electrode 24 , and the second extension electrode 23 is located between the first extension electrode 22 and the third extension electrode 24 . That is, the first extension electrode 22 is closer to the first side 12 and the side side 14 of the semiconductor stack 1 than the second and third extension electrodes 23 and 24 . In addition, the first extension electrode 22 includes a first corner 221 having a first angle θ1, the second extension electrode 23 includes a second corner 231 having a second angle θ2, and the third extension electrode 24 includes a third corner 241 having a second angle θ2. A third angle θ3, where θ3>θ2>θ1. Through the design of the electrode structure 2 in this embodiment, the current injected by the electrode pad 21 can be uniformly diffused into the semiconductor stack 1 , so that the semiconductor device 100 has better current spreading efficiency than general semiconductor devices. In addition, in this embodiment, the second angle θ2 and the third angle θ3 are obtuse angles greater than 90 degrees. Preferably, the first angle θ1 is about 80 degrees to 110 degrees, and the second angle θ1 The angle θ2 is about 90 degrees to 125 degrees, and the third angle θ3 is about 110 degrees to 145 degrees. In addition, in this embodiment, the distance from the first corner 221 to the electrode pad 21 is greater than the distance from the second corner 231 to the electrode pad 21 , and the distance from the third corner 241 to the electrode pad 21 is smaller than the distance from the second corner 231 to the electrode pad 21 .

Please continue to refer to FIG. 1 , in this embodiment, the first extension electrode 22 , the second extension electrode 23 and the third extension electrode 24 respectively have a first end 222 , a second end 232 and a third end 242 away from The electrode pad 21, and the first end 222, the second end 232 and the third end 242 are aligned with each other, but the present disclosure is not limited thereto. In addition, the first extension electrode 22 has a first portion 22a located between the electrode pad 21 and the first corner 221, and a second portion 22b located between the first corner 221 and the first end 222; the second extension electrode 23 has a The first part 23a is located between the electrode pad 21 and the second corner 231, and a second part 23b is located between the second corner 231 and the second end 232; the third extension electrode 24 has a first part 24a located between the electrode pad 21 and the second end 232; Between the three corners 241 , and a second portion 24 b is located between the third corner 241 and the third end 242 . As shown in FIG. 1, the second portion 22b of the first extension electrode 22, the second portion 23b of the second extension electrode 23 and the second portion 24b of the third extension electrode 24 have substantially the same first extension direction D1 , the first extending direction D1 is substantially parallel to the side 14 , and the first extending direction D1 is substantially parallel to the Y-axis direction in FIG. 1 . In addition, in this embodiment, the first portion 22a of the first extension electrode 22 has a second extension direction D2, the first portion 23a of the second extension electrode 23 has a third extension direction D3, and the first portion 23a of the second extension electrode 23 has a third extension direction D3. The first portion 24a of the three extending electrodes 24 has a fourth extending direction D4, and the second, third, and fourth extending directions D2, D3, and D4 are not substantially parallel to each other, wherein the second extending direction D2 is substantially the same as X in FIG. 1 - The axis directions are parallel, and the first extension direction D1 is substantially perpendicular to the second extension direction D2. In addition, the second portions 22b, 23b, and 24b of the adjacent extension electrodes 22, 23, and 24 have approximately equal intervals. There is a first distance P1 between the parts 23b, and a second distance between the second part 23b of the second extension electrode 23 and the second part 24b of the third extension electrode 24 P2, and P2 is approximately equal to P1, the uniformity of the current spreading of the semiconductor device 100 of the present disclosure can be increased through the above-mentioned equidistant design. In addition, the spacings of the first portions 22a, 23a, 24a of adjacent extension electrodes 22, 23, 24 are substantially unequal. The distance between 23a and 24a increases or decreases in the direction away from the electrode pad 21. The increase or decrease method may include an equal difference method, a proportional method, a stepwise method or a continuous gradient method, but the present disclosure is not limited thereto.

In addition, as shown in FIG. 1 , from a top view, the surface 11 of the semiconductor stack 1 has a center 15 and a corner 16 , the corner 16 is far from the center 15 and is adjacent to the electrode pad 21 , and the first corner 221 is between the center 15 . The distance is greater than the distance between the second corner 231 and the center 15 , and the third corner 241 is closer to the center 15 than the second corner 231 . There is a first dummy connection line L1 between the corner 16 and the center 15, and along the first extending direction D1, there is a first distance between the first corner 221 of the first extension electrode 22 and the first dummy connection line L1 d1, a second distance d2 between the second corner 231 of the second extension electrode 23 and the first dummy connection line L1, a third distance between the third corner 241 of the third extension electrode 24 and the dummy connection line L1 d3, wherein the second distance d2 is greater than the first distance d1, and preferably, the third distance d3 is greater than the second distance d2. The ratio of the third distance d3 to the second distance d2 in this embodiment is about 3 to 6, or about 4.3 to 5.2, but not limited to this; in one embodiment, the first virtual connection L1 is just Through the first corner 221, the first distance d1 is substantially zero. From a top view, the surface 11 of the semiconductor stack 15 of the first embodiment has four corners, wherein the corner 16 is the corner closest to the electrode pad 21 and is located at the intersection of the first side 12 and the side 14 . In addition, the second extension electrode 23 and the first virtual connection line L1 have an intersection point 233 , and the distance between the intersection point 233 and the center 15 is not less than the distance between the intersection point 233 and the corner 16 . The center 15 of the surface 11 of the semiconductor stack 1 in each embodiment of the present disclosure may coincide with the geometric center of the surface 11 or be located close to the geometric center, for example, the center 15 is about 0.5%~8% away from the geometric center of the surface 11 The length of the first side is 12.

As shown in FIG. 1, in the first embodiment, there is a second dummy line L2 between the first end 222 of the first extension electrode 22 and the center 15, and the second dummy line L2 and the first dummy line There is an included angle θ4 between L1, wherein preferably, the included angle θ4 is less than about 120 degrees, or less than about 105 degrees, and not less than 90 degrees. In addition, the first extension electrode 22 generally extends from the first side 12 toward the second side 13 , and there is a shortest distance between the first portion 22 a of the first extension electrode 22 and the first side 12 , which is a fourth distance d4 , and a shortest distance between the first end 222 and the second side 13 is a fifth distance d5, wherein the fifth distance d5 is smaller than the fourth distance d4. In the first embodiment, the surface 11 includes a virtual center line A1 parallel to the first extension direction D1 and passing through the center 15 , and the extension electrode group 2 a further includes a fourth extension electrode 25 , a fifth extension electrode 26 and a sixth extension electrode 26 The extension electrodes 27 are respectively connected to the electrode pads 21 , wherein if the virtual center line A1 is taken as the axis, the fourth extension electrode 25 , the fifth extension electrode 26 and the sixth extension electrode 27 are respectively mirror-symmetrical to the first extension electrode 22 and the second extension electrode 22 . The extension electrode 23 and the third extension electrode 24, but the distribution pattern of the electrode structure 2 of the present disclosure is not limited to this mirror symmetry, for example, it can also be asymmetric or other symmetry. When the semiconductor element 100 is an optoelectronic semiconductor element or a light-emitting element, the surface 11 is a light-emitting surface. Preferably, from a top view, the upper surface area of the electrode pad 21 and the upper surface area of the surface 11 have a percentage not exceeding 5% , or, the above percentage is 1% to 3% to reduce the shielding of the light emitted by the semiconductor stack 1 by the electrode pad 21 . In the first embodiment, between the upper surface area of the electrode pad 21 and the upper surface area of the surface 11 The percentage is 1.5%~2.6%. The above-mentioned virtual center line A1 is parallel to the first extending direction D1 and passes through the center 15. However, in other embodiments, the virtual center line A1 can also be a surface 11 that divides the surface 11 of the semiconductor stack 1 into two regions with equal surface areas. virtual line. In addition, the number of extension electrodes in the extension electrode group 2a is not limited to the above-mentioned 6. For example, when the semiconductor stack 1 has a larger surface 11, the extension electrode group 2a may include a larger number of extension electrodes to make the current flow uniform. diffusion into the semiconductor stack 1, in some embodiments, the extension electrode group 2a may include 3-15 extension electrodes. also, In order to make the semiconductor device 100 have a better balance between light shielding and current spreading, the electrode structure 2 can be further optimized, wherein the upper surface area of the electrode structure 2 and the upper surface area of the surface 11 of the semiconductor stack 1 have a percentage of 6%. ~15%. The semiconductor device 100 is connected to the external circuit through the electrode pads 21, for example, metal wire bonding or flip-chip bonding is used to form an electrical connection between the electrode pads 21 and the external circuit. The size and current distribution of the surface 11 of the device 100 need to be selected as one or more. Preferably, in the first embodiment of the present disclosure, only a single electrode pad 21 is provided on the surface 11 of the electrode structure 2, so that the It is further prevented that the metal wires straddle the surface 11 after wire bonding will shield the light emitted from the semiconductor stack 1 , thereby optimizing the photoelectric conversion efficiency of the semiconductor element 100 after the package is formed.

Please refer to FIG. 2 , which is a schematic cross-sectional view of the semiconductor device according to the first embodiment of the disclosure along the line A-A' of FIG. 1 . In addition to the above-mentioned semiconductor stack 1 and the electrode structure 2 located on the semiconductor stack 1 , the semiconductor device 100 may further include a substrate 30 and a conductive adhesive layer 31 between the substrate 30 and the semiconductor stack 1 in this embodiment. , a reflective structure 32 is located between the conductive adhesive layer 31 and the semiconductor stack 1, a transparent conductive structure 33 is located between the reflective structure 32 and the semiconductor stack 1, a window layer 34 is located between the transparent conductive structure 33 and the semiconductor stack 1 and an insulating layer 35 is located between the transparent conductive structure 33 and the window layer 34, but the present disclosure is not limited to this. For example, in another implementation, the semiconductor device 100 has the substrate 30 and the semiconductor stack 1 is located between the substrate 30. and the electrode structure 2 is positioned over the semiconductor stack 1 and may optionally include one or more of the other elements described in the first embodiment. The semiconductor device 100 further includes a second electrode structure 36 located on the substrate 30 and away from the semiconductor stack 1 , wherein the electrode structure 2 and the second electrode structure 36 are located on opposite sides of the semiconductor stack 1 , and the electrode structure 2 and the second electrode The electrical properties of the structures 36 are different to form a vertical semiconductor device 100 . The structure of the semiconductor device 100 of the first embodiment is only an example and not intended to be limiting. For example, in some embodiments of the present disclosure, the electrode junction The structure 2 and the second electrode structure 36 can also be located on the same side of the semiconductor stack 1 to form a horizontal semiconductor device 100 .

Both the electrode structure 2 and the second electrode structure 36 can be used to connect an external power source and spread the current evenly into the semiconductor stack 1 . In the first embodiment, the second electrode structure 36 is a conductive film layer formed on the backside of the substrate 30 . The material of the second electrode structure 36 can be the same or different from that of the electrode structure 2 . The electrode structure 2 and the second electrode The material of the structure 36 may include metal material or transparent conductive material. In the first embodiment, the material of the electrode structure 2 and the second electrode structure 36 may include metal, and the metal material may include but not limited to aluminum (Al), chromium (Cr) ), copper (Cu), tin (Sn), gold (Au), nickel (Ni), titanium (Ti), platinum (Pt), lead (Pb), zinc (Zn), cadmium (Cd), antimony (Sb) ), cobalt (Co) or alloys of the above materials, etc.; transparent conductive materials may include, but are not limited to, such as indium tin oxide (ITO), indium oxide (InO), tin oxide (SnO), cadmium tin oxide (CTO), antimony oxide Tin (ATO), Aluminum Zinc Oxide (AZO), Zinc Tin Oxide (ZTO), Gallium Zinc Oxide (GZO), Indium Tungsten Oxide (IWO), Zinc Oxide (ZnO), Aluminum Gallium Arsenide (AlGaAs), Gallium Nitride (GaN), gallium phosphide (GaP), gallium arsenide (GaAs), gallium arsenide phosphide (GaAsP), indium zinc oxide (IZO), diamond-like carbon film (DLC) or graphene.

The semiconductor stack 1 includes a first semiconductor layer 111 , an active structure 113 and a second semiconductor layer 112 sequentially formed on the first semiconductor layer 111 . The first semiconductor layer 111 and the second semiconductor layer 112 have a different first conductivity and a second conductivity respectively, so as to provide electrons and holes, or respectively provide holes and electrons; the active structure 113 may include a single heterogeneity single heterostructure, double heterostructure or multiple quantum wells. The materials of the first semiconductor layer 111, the second semiconductor layer 112 and the active structure 113 are group III and V compound semiconductors, such as: GaAs, InGaAs, AlGaAs, AlInGaAs, GaP, InGaP, AlInP, AlGaInP, GaN, InGaN, AlGaN, AlInGaN, AlAsSb, InGaAsP, InGaAsN, AlGaAsP, etc. In the embodiments of the present invention, unless otherwise specified, the above chemical expressions include “compounds that meet stoichiometric doses” and “compounds that do not meet stoichiometric doses”, wherein, “compounds that meet stoichiometric doses” are, for example, the total of the three groups of elements. The element dosage is the same as the total element dosage of the Group V elements. On the contrary, the "non-stoichiometric compound" is, for example, the total element dosage of the Group III element is different from the total element dosage of the Group V element. For example, the chemical expression is AlGaAs, which means that the group 3 elements include aluminum (Al) and/or gallium (Ga), and the group 5 element arsenic (As), wherein the total of the group 3 elements (aluminum and/or gallium) The elemental dose may be the same or different from the total elemental dose of the Group V element (arsenic). In addition, if each compound represented by the above chemical formula is a compound that meets the chemical dose, AlGaAs represents Al _x Ga _(1-x) As, where 0≦x≦1; AlInP represents Al _x In _{(1-x )} P, where 0≦x≦1; AlGaInP represents (Aly Ga _{(1-y) ) 1-x} In _x P, where 0≦x≦1, 0≦y≦1; AlGaN represents Al _x Ga _{( 1-x)} N, where 0≦x≦1; AlAsSb represents AlAs _x Sb _(1-x) , where 0≦x≦1; InGaP represents In _x Ga _1-x P, where 0≦x≦1 ; InGaAsP represents In _x Ga _1-x As _1-y P _y , where 0≦x≦1, 0≦y≦1; InGaAsN represents In _x Ga _1-x As _1-y N _y , where 0≦x ≦1, 0≦y≦1; AlGaAsP represents Al _x Ga _1-x As _1-y P _y , where 0≦x≦1, 0≦y≦1; InGaAs represents In _x Ga _1-x As, where, 0≦x≦1. When the semiconductor device of the present disclosure is a light-emitting device, the semiconductor stack 1 can emit a light having a dominant wavelength of about 200 nm to 1800 nm; in the first embodiment, the semiconductor stack 1 can emit light The light is infrared light, and the dominant wavelength of the light is about 750nm~1500nm. In addition, the conductivity of the window layer 34 can be the same as the conductivity of the first semiconductor layer 111 , such as n-type or p-type. The window layer 34 is transparent to the light emitted by the semiconductor stack 1 , and its material can include transparent conductive materials. Materials such as Indium Tin Oxide (ITO), Indium Oxide (InO), Tin Oxide (SnO), Cadmium Tin Oxide (CTO), Antimony Tin Oxide (ATO), Aluminum Zinc Oxide (AZO), Zinc Tin Oxide (ZTO), Oxide Gallium Zinc Oxide (GZO), Indium Tungsten Oxide (IWO), Zinc Oxide (ZnO), Magnesium Oxide (MgO), Gallium Arsenide (GaAs), Aluminum Gallium Arsenide (AlGaAs), Gallium Nitride (GaN), Gallium Phosphide (GaP) or indium zinc oxide (IZO).

The transparent conductive structure 33 is transparent to the light emitted by the semiconductor stack 1 to increase the ohmic contact between the window layer 34 and the reflective structure 32 as well as current conduction and diffusion. In some embodiments, the transparent conductive structure 33 can also be combined with The reflective structures 32 together form an omni-directional mirror (Omni-Directional Mirror) Reflector, ODR). The material of the transparent conductive structure 33 may include transparent conductive materials such as indium tin oxide (ITO), indium oxide (InO), tin oxide (SnO), cadmium tin oxide (CTO), antimony tin oxide (ATO), aluminum oxide zinc (AZO) ), zinc tin oxide (ZTO), gallium zinc oxide (GZO), indium tungsten oxide (IWO), zinc oxide (ZnO), gallium phosphide (GaP), indium cerium oxide (ICO), indium tungsten oxide (IWO), Indium titanium oxide (ITIO), indium zinc oxide (IZO), indium gallium oxide (IGO), gallium aluminum zinc oxide (GAZO), graphene or a combination of the above materials. As shown in FIG. 2, in the first embodiment, the transparent conductive structure 33 has a first transparent conductive layer 331 located under the insulating layer 35, and a second transparent conductive layer 332 located between the semiconductor stack 1 and the first transparent conductive layer 332. between the transparent conductive layers 331 . The materials of the first transparent conductive layer 331 and the second transparent conductive layer 332 are different. In another embodiment, the materials of the first transparent conductive layer 331 and the second transparent conductive layer 332 are different in at least one element. For example, the material of the first transparent conductive layer 331 is indium zinc oxide (IZO), the second transparent conductive layer is The material of the conductive layer 332 is indium tin oxide (ITO). The second transparent conductive layer 332 can be in direct contact with the insulating layer 35 and the window layer 34 and cover at least one surface of the insulating layer 35 .

As shown in FIG. 2 , in the first embodiment, the insulating layer 35 is provided on the other surface with respect to the surface 11 of the semiconductor stack 1 , and the material of the insulating layer 35 can be selected to be suitable for the light emitted by the semiconductor stack 1 . The penetration rate is greater than 90%, the material of the insulating layer 35 can be selected to include oxide insulating material or non-oxide insulating material, the oxide insulating material is silicon oxide (SiO _x ), for example, the non-oxide insulating material is benzo ring Butene (BCB), Cyclic Olefin Polymer (COC), Fluorocarbon Polymer or Silicon Nitride (SiN _x ). In another embodiment, the material of the insulating layer 35 may include halides or compounds of groups IIA and VII, such as calcium fluoride (CaF ₂ ) or magnesium fluoride (MgF ₂ ). In the first embodiment, the refractive index of the insulating layer 35 is smaller than the refractive index of the window layer 34 and the transparent conductive structure 33 , and the critical angle of the interface between the window layer 34 and the insulating layer 35 is smaller than the interface between the window layer 34 and the transparent conductive structure 33 The critical angle of , after the light emitted from the semiconductor stack 1 is directed to the insulating layer 35 , the probability of forming total reflection at the interface between the window layer 34 and the insulating layer 35 increases, and between the window layer 34 and the transparent conductive structure 33 The interface between the transparent conductive structures 33 and the light entering the transparent conductive structure 33 does not form total reflection. Since the insulating layer 35 has a low refractive index, total reflection may also occur at the interface between the transparent conductive structure 33 and the insulating layer 35, thereby improving the semiconductor device 100. For example, the refractive index of the insulating layer 35 can be selected to be less than 1.4, preferably 1.3 to 1.4. The transparent conductive structure 33 has a first contact upper surface 33a in contact with the window layer 34, the insulating layer 35 has a second contact upper surface 35a in contact with the window layer 34, and the first contact upper surface 33a and the second contact upper surface 35a are approximately located at the same level. In one embodiment, the percentage of the surface area of the first contact upper surface 33a relative to the sum of the surface areas of the first contact upper surface 33a and the second contact upper surface 35a is about 10%˜50%, so that the semiconductor device 100 has a higher surface area. Excellent luminous efficiency. In another embodiment, the second contact upper surface 35 a can be a rough surface, so as to scatter the light emitted by the semiconductor stack 1 and improve the light extraction efficiency of the semiconductor device 100 . The insulating layer 35 may have a patterned distribution, for example, the distribution of the insulating layer 35 may exhibit regularity or irregularity in a plan view, thereby improving the current diffusion of the semiconductor device 100 . The insulating layer 35 of the first embodiment roughly corresponds to the extension electrode group 2a. On the one hand, the current is uniformly diffused in the semiconductor stack 1, and on the other hand, the light under the extension electrode group 2a can be extracted through total reflection. In one embodiment, the thickness of the insulating layer 35 is less than a half thickness of the transparent conductive structure 33; in another embodiment, the thickness of the insulating layer 35 is less than 1/5 of the thickness of the transparent conductive structure 33, so that the transparent conductive structure can be avoided or reduced The surface planarization process after the formation of 33 destroys the structure of the insulating layer 35 . In the first embodiment, at least one surface of the insulating layer 35 is covered by the transparent conductive structure 33, which can increase the bonding area of the transparent conductive structure 33, strengthen the bonding between the insulating layer 35 and the window layer 34, and improve the mechanical strength of the structure . In the first embodiment, the insulating layer 35 further includes a plurality of pores 351 passing through the insulating layer 35 , wherein the transparent conductive structure 33 is filled in the plurality of pores 351 to form ohmic contact with the window layer 34 .

In the first embodiment, the reflective structure 32 can be used to reflect the light from the semiconductor stack 1 to increase the light extraction efficiency of the semiconductor device 100 . The material of the reflective structure 32 may include, but is not limited to, metal materials, such as copper (Cu), aluminum (Al), tin (Sn), gold (Au), silver (Ag), lead (Pb), titanium (Ti), Nickel (Ni), platinum (Pt), tungsten (W) or alloys of the above materials, etc. As shown in FIG. 2, in this embodiment, the reflective structure 32 includes a reflective layer 326, a reflective adhesive layer 324 under the reflective layer 326, a barrier layer 322 under the reflective adhesive layer 324, and an ohmic contact Layer 320 is below barrier layer 322 . Reflective layer 326 The light from the semiconductor stack 1 can be reflected; the reflective adhesive layer 324 can be used to connect the reflective layer 326 and the barrier layer 322; the barrier layer 322 can be used to prevent the material of the conductive adhesive layer 31 from diffusing to the reflective layer 326 during the process to destroy the reflection The structure of the layer 326 maintains the reflectivity of the reflective layer 326 ; the ohmic contact layer 320 forms an ohmic contact with the underlying conductive adhesive layer 31 . The conductive adhesive layer 31 can connect the connection substrate 20 to the reflective structure 32 and can have a plurality of subordinate layers (not shown). The material of the conductive bonding layer 31 may include transparent conductive materials or metal materials, and the transparent conductive materials include but are not limited to indium tin oxide (ITO), indium oxide (InO), tin oxide (SnO), cadmium tin oxide (CTO), antimony oxide Tin (ATO), Aluminum Zinc Oxide (AZO), Zinc Tin Oxide (ZTO), Gallium Zinc Oxide (GZO), Zinc Oxide (ZnO), Gallium Phosphide (GaP), Indium Cerium Oxide (ICO), Indium Tungsten Oxide ( IWO), indium titanium oxide (ITiO), indium zinc oxide (IZO), indium gallium oxide (IGO), gallium aluminum zinc oxide (GAZO), graphene, or a combination thereof. Metal materials include but are not limited to copper (Cu), aluminum (Al), tin (Sn), gold (Au), silver (Ag), lead (Pb), titanium (Ti), nickel (Ni), platinum (Pt) , Tungsten (W) or alloys of the above materials, etc.

The substrate 30 may be used to support the semiconductor stack 1 and other layers or structures located thereon, which may be transparent, conductive, semiconducting or insulating. The semiconductor stack 1 can be grown on the substrate 30 or another growth substrate by epitaxial methods such as metal-organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), or hydride vapor phase epitaxy (HVPE). If the semiconductor stack 1 is formed on the growth substrate, the semiconductor stack 1 can be bonded to the substrate 30 by the substrate transfer technique, and the growth substrate can be selectively removed or retained. In the first embodiment, the semiconductor stack 1 is grown on the growth substrate, and then bonded to the substrate 30 through the conductive adhesive layer 31 through the substrate transfer technique. Specifically, the material of the substrate 30 may include, but is not limited to, transparent insulating materials such as sapphire, diamond, glass, quartz, acrylic, epoxy ), Aluminum Nitride (AlN), or may include, but are not limited to, Transparent Conductive Oxides (TCO) such as Zinc Oxide (ZnO), Indium Tin Oxide (ITO), Indium Zinc Oxide (IZO), Gallium Oxide (Ga ₂ O _{3 )} ), lithium gallate (LiGaO ₂ ), lithium aluminate (LiAlO ₂ ) or magnesium aluminate (MgAl ₂ O ₄ ), etc., or may include but not limited to semiconductor materials such as silicon carbide (SiC), gallium arsenide (GaAs) , gallium phosphide (GaP), gallium arsenide phosphide (GaAsP), zinc selenide (ZnSe) or indium phosphide (InP), or may include but not limited to metallic materials such as aluminum (Al), copper (Cu), molybdenum Elements such as (Mo) or tungsten (W) or a combination of the above elements.

Please refer to FIG. 3 , which is a schematic top view of the semiconductor device 200 according to the second embodiment of the disclosure, wherein the connection relationship between the components of the semiconductor device 200 of the second embodiment is substantially the same as that of the first embodiment. or similar. In the second embodiment, the electrode structure 2 further includes a middle extension electrode 28 connected to the electrode pad 21 . From a plan view, the middle extension electrode 28 is farther from the side 14 of the outline P of the semiconductor stack 1 than the third extension electrode 24 is. , and the middle extension electrode 28 is located between the third extension electrode 24 and the sixth extension electrode 27 . Specifically, the middle extension electrode 28 is substantially parallel to the virtual center line A1 of the surface 11, or the middle extension electrode 28 is substantially coincident with the virtual center line A1, and is directed along the first extension direction D1 from the place where the electrode pad 21 is connected. The second side 13 extends. In this embodiment, the shape of the middle extension electrode 28 is different from or not similar to the first, second and third extension electrodes 22 , 23 and 24 , for example, the middle extension electrode 28 does not have a corner. In the second embodiment, the number of the middle extension electrodes 28 is one, but in some embodiments, the number of the middle extension electrodes 28 may also be multiple, which can increase the current spreading ability, which is not limited herein.

Please refer to FIG. 4 , which is a schematic top view of the third embodiment of the disclosure, wherein the connection relationship between the components of the semiconductor device 300 of the third embodiment is substantially the same or similar to that of the second embodiment. In the third embodiment, the first extension electrodes 22 of the semiconductor device 300 have varying widths, that is, the widths of the first extension electrodes 22 are non-uniform, wherein the first portion 22a of the first extension electrodes 22 has an average width, and the second extension electrodes 22 have an average width. The portion 22b has another average width different from that of the first portion 22a, and the average width of the first portion 22a is greater than the average width of the second portion 22b. Specifically, the width of the first portion 22a of the first extension electrode 22 is the first width W1, the width of the second portion 22b is gradually narrowed toward the first end 222, and the first end 222 has a second width When the width is smaller than the first width W1, the first extension electrode 22 has a wider width at a portion close to the electrode pad 21 and a narrower width at a portion far from the electrode pad 21, so that the electrode structure 2 can operate at a high current density. (For example, the current density is greater than 1A/mm ² ), it can have the ability to quickly and uniformly spread current, and can also reduce shading and achieve a balance between shading light and current spreading. Similarly, the width of the first portion 23a of the second extension electrode 23 is the third width W3, the width of the second portion 23b is tapered toward the second end 232, and the second end 232 has a fourth width less than The third width W3; the width of the first portion 24a of the third extension electrode 24 is the fifth width W5, the width of the second portion 24b is tapered toward the third end 242, and the third end 242 has a sixth width W5 The width is smaller than the fifth width W5. In this embodiment, the first width W1 , the third width W3 and the fifth width W5 are approximately the same, and the second width, the fourth width and the sixth width are approximately the same, but the present disclosure is not limited thereto. In another embodiment, the first width W1 is greater than the third width W3, and the third width W3 is greater than the fifth width W5. In addition, in yet another embodiment, the end of the middle extension electrode 28 connected to the electrode pad 21 has a seventh width W7, and the end close to the second side 13 has an eighth width smaller than the seventh width W7, wherein the first The first, third and fifth widths W1, W3 and W5 are all larger than the seventh width W7, or in another embodiment, the first, third and fifth widths W1, W3 and W5 are the same as the seventh width W7. In the third embodiment, the ratio of the first width W1 to the second width is 1.5-8, preferably 2-6, so as to achieve better current dispersion capability, thereby improving the reliability and service life of the semiconductor device 300 . The first width W1, the third width W3 and the fifth width W5 in the above embodiment are the average widths of the first portions 22a, 23a and 25a, respectively, but in other embodiments, the widths W1, W3 and W5 may also be the first portions 22a. , 23a, 25a maximum width or minimum width.

In addition, in one embodiment, from a top view, the characteristic length of the electrode pad 21 is larger than the width of the extension electrodes 22-27, and the characteristic length of the electrode pad 21 is preferably the average width of the extension electrodes 22-27. 1.5 times or more, where the characteristic length refers to the longest distance between any two points on the outline of an element. For example, the characteristic length of a circular element is the diameter, and the characteristic length of a square element is the diagonal String.

It should be understood that, the embodiments listed in the present invention are only used to illustrate the present invention, but not to limit the scope of the present invention. Obvious modifications or changes made by anyone to the present invention will not depart from the spirit and scope of the present invention. The same or similar components in different embodiments, or Components with the same number all have the same physical or chemical properties. In addition, the above-mentioned embodiments of the present invention may be combined or replaced with each other under appropriate circumstances, and are not limited to the specific embodiments described. The connection relationship between a specific component and other components described in detail in one embodiment can also be applied to other embodiments, and all fall within the scope of the protection scope of the present invention as described later.

242: Third End

100: Semiconductor Components

25: Fourth extension electrode

1: Semiconductor stack

26: Fifth extension electrode

11: Surface

27: Sixth extension electrode

12: First side

θ 1: first angle

13: Second side

θ 2: second angle

14: Side

θ 3: The third angle

15: Center

θ 4: included angle

16: Corner

d1: first distance

2: Electrode structure

d2: second distance

2a: Extended electrode set

d3: the third distance

21: Electrode pads

d4: fourth distance

22: The first extension electrode

d5: fifth distance

221: The first corner

A1: Virtual central line

222: First End

P: outline

22a, 23a, 24a: Part 1

L1: The first virtual link

22b, 23b, 24b: Part II

L2: Second virtual link

23: The second extension electrode

P1: first pitch

231: Second Corner

P2: Second pitch

232: Second End

D1: The first extension direction

233: Rendezvous Point

D2: The second extension direction

24: The third extension electrode

D3: The third extension direction

241: The third corner

D4: Fourth extension direction

Claims (10)

A semiconductor device, comprising: a semiconductor stack, having a surface, and the surface has a center, a first side and a side, the side connects the first side and forms a corner, the corner and the center are having a dummy connection line; and an electrode structure including an electrode pad formed on the surface, a first extension electrode and a second extension electrode, the first extension electrode is closer to the side than the second extension electrode, and Each of the extension electrodes has a first portion and a second portion; wherein, the first portion of the first extension electrode is parallel to the first side, and the first portion of the first extension electrode and the first portion of the first extension electrode are The two parts are connected and have a first corner with a first angle θ1; wherein the first part of the second extension electrode is connected with the second part of the second extension electrode and has a second angle with a second angle θ2 corner, and θ2>θ1; and wherein, there is a first distance between the first corner and the virtual connection line, there is a second distance between the second corner and the virtual connection line, and the second distance is greater than the first distance. A semiconductor device, comprising: a semiconductor stack having a surface, and the surface has a center, a first side, a second side opposite to the first side, and a side, the side connecting the first side side and the second side, and there is a corner between the side side and the first side; and an electrode structure formed on the surface, the electrode structure comprising an electrode pad, a first extension electrode and a second extension electrode, the first extension electrode is closer to the side than the second extension electrode, and the first extension electrode and the second extension electrode each have a first part and a second part; wherein, the first extension electrode The first part is connected to the second part of the first extension electrode and has a first corner with a first angle θ1; Wherein, the first part of the second extension electrode is connected to the second part of the second extension electrode and has a second angle of a second angle θ2, and θ2>θ1; and wherein, from a top view, the The first extension electrode has a first end away from the electrode pad, a first virtual connection is formed between the center and the corner, and a second virtual connection is formed between the center and the first end. The included angle between a virtual connection line and the second virtual connection line is less than 120 degrees. The semiconductor element according to claim 1 or 2, wherein 80 degrees≦θ1≦110 degrees, and 90 degrees≦θ2≦125 degrees. The semiconductor device of claim 1 or 2, further comprising a third extension electrode having a first portion and a second portion, and the first portion of the third extension electrode and the second portion of the third extension electrode The part is connected and has a third corner, the third corner has a third angle θ3, and θ3 is an obtuse angle. The semiconductor device according to claim 4, wherein, in the third angle θ3, 110 degrees≦θ3≦145 degrees. The semiconductor device of claim 1 or 2, further comprising a third extension electrode having a first portion and a second portion, and the first portion of the third extension electrode and the second portion of the third extension electrode The part is connected and has a third angle, the third angle has a third angle θ3, and θ3>θ2>θ1. The semiconductor device of claim 1 or 2, wherein the second portion of the first extension electrode or the second extension electrode is parallel to the side. The semiconductor device of claim 2, wherein the first portion of the first extension electrode is parallel to the first side, and the shortest distance between the first side and the first portion of the first extension electrode is greater than the second side The shortest distance to the first end. The semiconductor device of claim 1 or 2, wherein the first portion of the first extension electrode and the first portion of the second extension electrode are directly connected to the electrode pad. The semiconductor device according to claim 1 or 2, wherein the electrode structure has an upper surface, and the upper surface has an upper surface area, the surface of the semiconductor stack has a surface area, and the upper surface area is 6% to 15% % of this surface area.

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