TWI823136B - Semiconductor device - Google Patents

Abstract

A semiconductor device is provided. The semiconductor device includes an epitaxial stack, an insulating layer, and a first conductive oxide layer. The insulating layer is disposed on the epitaxial stack, and includes a plurality of openings and a surface away from the epitaxial stack. The first conductive oxide layer is disposed on the epitaxial stack and the insulating layer, and a plurality of first conductive oxide portions separated from each other are provided in the plurality of openings. The surface includes a first portion and a second portion, and the first conductive oxide layer covers the first portion and does not cover the second portion.

Description

Semiconductor components

The present invention relates to a semiconductor element, specifically, to an optoelectronic semiconductor element.

Optoelectronic semiconductor components are components that can convert optical signals and electrical signals. They can use the interaction of photons and electrons to absorb energy and stimulate radiation. Among them, light emitting diodes (LEDs), which are optoelectronic semiconductor components, are often used in Various lighting fixtures, traffic warning signs, etc. in daily life.

However, in order to meet the demand for energy saving, how to make the light emitting diodes in optoelectronic semiconductor components have better light extraction efficiency is an issue that the industry urgently needs to solve.

In order to solve the above technical problems, the present invention is implemented as follows:

Embodiments of the present invention provide a semiconductor device including an epitaxial stack, an insulating layer and a first conductive oxide layer. The insulating layer is located on the epitaxial layer and has a plurality of openings and a surface away from the epitaxial layer. The first conductive oxide layer is located on the epitaxial stack and the insulating layer, and has a plurality of mutually separated first conductive oxide portions located in a plurality of openings. The surface has a first part and a second part, and the first conductive oxide layer covers the first part but does not cover the second part.

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the scope of protection of the present invention.

Unless otherwise specified, the general formula InGaP represents In _x0 Ga _1-x0 P, where 0 < x0 <1; the general formula AlInP represents Al _x1 In _1-x1 P, where 0 < x1 <1; the general formula AlGaInP represents Al _x2 Ga _x3 In _1-x2-x3 P, where 0＜x2＜1 and 0＜x3＜1; the general formula InGaAsP represents In _x4 Ga _1-x4 As _x5 P _1-x5 , where 0＜x4＜1, 0 ＜x5＜1; the general formula AlGaInAs represents Al _x6 Ga _x7 In _1-x6-x7 As, where 0＜x6＜1, 0＜x7＜1; the general formula InGaNAs represents In _x8 Ga _1-x8 N _x9 As _1-x9 , where 0<x8<1, 0<x9<1; the general formula InGaAs represents In _x10 Ga _1-x10 As, where 0<x10<1; the general formula AlGaAs represents Al _x11 Ga _1-x11 As, where 0<x11< 1. The content of each element can be adjusted according to different purposes, such as but not limited to adjusting the energy gap size, or when the semiconductor element is a light-emitting element, the dominant wavelength or peak wavelength of the light-emitting element can be adjusted. .

Semiconductor components of the present disclosure are, for example, light-emitting components (e.g., light-emitting diodes, laser diodes), and light-absorbing components (e.g., photo-detectors). or non-luminous components. The composition and dopant of each layer contained in the semiconductor device of the present disclosure can be analyzed by any suitable method, such as secondary ion mass spectrometer (SIMS), and the thickness of each layer can also be obtained by any suitable method. It is obtained by analysis, such as transmission electron microscopy (TEM) or scanning electron microscope (SEM).

Those with ordinary skill in the art should understand that other components can be added on the basis of each embodiment described below. For example, unless otherwise specified, a similar description of "a first layer (or structure) located on a second layer (or structure)" may include the first layer (or structure) and the second layer (or structure) Embodiments of direct contact may also include embodiments in which the first layer (or structure) and the second layer (or structure) have other structures but are not in direct contact with each other. In addition, it should be understood that the upper and lower position relationships of each layer (or structure) may change due to observation from different directions.

In addition, in this disclosure, the statement that a layer or structure "substantially consists of M" means that the above-mentioned layer or structure is mainly composed of M, but it does not exclude that the above-mentioned layer or structure contains dopants or unavoidable impurities. ).

FIG. 1A is a schematic cross-sectional view of a semiconductor device 100 according to an embodiment of the present disclosure. Figure 1B is an enlarged view of the framed area in Figure 1A. The semiconductor device 100 includes an epitaxial layer 1 , a conductive structure 4 and an insulating layer 8 located between the epitaxial layer 1 and the conductive structure 4 . The semiconductor device 100 further includes a first electrode 2 and a second electrode 3 located on the upper and lower sides of the epitaxial layer 1 respectively, and optionally includes a reflective layer 5, a bonding structure 6 and a substrate 7. The conductive structure 4 is located between the epitaxial layer 1 and the reflective layer 5 , and the bonding structure 6 is located between the substrate 7 and the reflective layer 5 .

As shown in Figure 1B, in this embodiment, the insulating layer 8 has a plurality of first openings 8a, and from a cross-sectional view, the insulating layer 8 includes a plurality of insulating portions 81 that are separated from each other, and the first openings 8a are located in adjacent Between two adjacent insulating portions 81 , each insulating portion 81 includes a surface 811 away from the epitaxial stack 1 and a side wall 812 . The surface 811 has a first portion 811a close to the first opening 8a and a second portion 811b farther away from the first opening 8a than the first portion 811a. The sidewalls 812 connect the epitaxial stack 1 and the surface 811 , and each first opening 8 a is defined by two sidewalls 812 adjacent to the insulating portion 81 .

As shown in Figure 1A, in this embodiment, the first electrode 2 includes a first electrode pad 21 and a plurality of extended electrodes 22, and the plurality of first openings 8a of the insulating layer 8 are in contact with the first electrode pad 21 and/or Or the plurality of extended electrodes 22 do not overlap in the stacking direction of the epitaxial layer 1 (such as the Y direction shown in FIG. 1A ), thereby increasing the effect of current dispersion in the epitaxial layer 1 . The conductive structure 4 includes a first conductive oxide layer 41 contacting the insulating layer 8 . In detail, the first conductive oxide layer 41 is patterned and has a plurality of first conductive oxide portions 411 contacting the plurality of insulating portions 81, and the plurality of first conductive oxide portions 411 are filled in the plurality of first openings 8a. The crystal stack 1 is in direct contact and forms an electrical connection. As shown in FIG. 1B , the first conductive oxide portion 411 contacts the first portion 811 a of the insulating portion 81 and does not contact the second portion 811 b of the insulating portion 81 . The first conductive oxide portion 411 contacts the first portion 811a and the side wall 812 at the same time. Since the first conductive oxide layer 41 will absorb the light emitted from the active area 13, it passes through the patterned first conductive oxide layer 41 (that is, the first conductive oxide layer 41 is provided in the first opening 8a and part of the insulating layer 8) , which can help reduce the absorption of light by the first conductive oxide layer 41, thereby improving the luminous efficiency of the semiconductor device 100. In another embodiment, the first conductive oxide portion 411 only fills the first opening 8 a and is in direct contact with the epitaxial layer 1 and does not contact the first portion 811 a and the second portion 811 b of the insulating portion 81 , thereby further The absorption of light by the first conductive oxide layer 41 can be avoided, and the luminous efficiency of the semiconductor element 100 can be further improved.

In this embodiment, the first electrode pad 21 and the first conductive oxide layer 41 do not overlap in the stacking direction of the epitaxial layer 1 (such as the Y direction shown in FIG. 1A), that is, the first electrode pad 21 The first conductive oxide layer 41 is not formed below. The conductive structure 4 optionally further includes a second conductive oxide layer 42 in contact with the first conductive oxide layer 41 and the insulating layer 8, and the second conductive oxide layer 42 directly contacts the electrode located under the first electrode pad 21 through the first opening 8a. Crystal stack 1. In one embodiment, as shown in Figure 1B, the first conductive oxide layer 41 has a first thickness T1, and the second conductive oxide layer 42 has a second thickness T2 that is greater than the first thickness T1, for example: the first thickness T1 is 5 nm to 500 nm, and the second thickness T2 is 1000 nm to 8000 nm. The above-mentioned first thickness T1 and second thickness T2 are measured parallel to the stacking direction of the epitaxial layer 1 (such as the Y direction shown in Figure 1A).

In the first direction (such as the X direction in FIG. 1B), the first opening 8a has a first width W1, and the first conductive oxide portion 411 has a second width W2 that is greater than the first width W1. In one embodiment, the first width W1 is greater than 4 μm, such as 4 μm to 15 μm, 6 μm to 12 μm, 8 μm to 10 μm; the second width W2 is greater than 6 μm, such as 6 μm to 18 μm, 8 μm to 15 μm, 10 μm to 12 μm. In another embodiment, the difference between the second width W2 and the first width W1 is 1 μm to 5 μm, such as 2 μm to 4 μm. The above-mentioned first direction is perpendicular to the stacking direction of each layer of the epitaxial stack 1 .

The epitaxial stack 1 includes a first semiconductor structure 11, a second semiconductor structure 12, an active region 13 located between the first semiconductor structure 11 and the second semiconductor structure 12, a first confinement layer 14 located in the active region 13 and between the first semiconductor structure 11 and a second confinement layer 15 between the active region 13 and the second semiconductor structure 12 . In this embodiment, the upper surface S of the epitaxial layer 1 (ie, the surface of the second semiconductor structure 12 ) has a roughened structure, and the first electrode 2 is in direct contact with the second semiconductor structure 12 . The first semiconductor structure 11 and the second semiconductor structure 12 may have different conductive types. For example, the first semiconductor structure 11 is N-type and the second semiconductor structure 12 is P-type; or the first semiconductor structure 11 is P-type and the second semiconductor structure 12 is N-type. Therefore, when the semiconductor device 100 is a light-emitting device, the first semiconductor structure 11 and the second semiconductor structure 12 can respectively provide electrons and holes, or holes and electrons. The first semiconductor structure 11 has a first dopant, and the second semiconductor structure 12 has a second dopant, so that the first semiconductor structure 11 and the second semiconductor structure 12 have different conductivities. The first dopant and the second dopant may be carbon (C), zinc (Zn), silicon (Si), germanium (Ge), tin (Sn), selenium (Se), magnesium (Mg) or tellurium (Te) respectively. ). In this embodiment, the first semiconductor structure 11 is P-type, the second semiconductor structure 12 is N-type, and the doping concentration of the first semiconductor structure 11 and the second semiconductor structure 12 is 5 10 ¹⁷ /cm ³ to 1 10 ²⁰ /cm ³ . The energy gaps of the first semiconductor structure 11 and the second semiconductor structure 12 are respectively larger than the first confinement layer 14 and the second confinement layer 15 , thereby further confining carriers (electrons and holes) in the active region 13 .

The active area 13 is located between the first localization layer 14 and the second localization layer 15. In this embodiment, the active area 13 is directly connected to the first localization layer 14, and the active area 13 is directly connected to the second localization layer 15. catch. In this embodiment, the active region 13 includes a plurality of well layers and barrier layers (not shown) stacked on each other. In the active region 13 of the semiconductor device 100 in this embodiment, the thickness of the well layer is smaller than the thickness of the barrier layer. The well layer and/or barrier layer may or may not include dopants.

Viewed from the cross-section of the semiconductor device 100 , the epitaxial stack 1 may optionally include a contact layer 111 between the first semiconductor structure 11 and the conductive structure 4 . The contact layer 111 has a first dopant, and the first dopant concentration in the contact layer 111 is greater than the first dopant concentration of the first semiconductor structure 11 . The material of the contact layer 111 may include III-V semiconductor materials, such as binary III-V semiconductor materials such as GaAs, GaP, GaN, etc. The contact layer 111 helps reduce the contact resistance between the epitaxial layer 1 and the conductive structure 4 and improves the electrical performance of the semiconductor device 100 .

The first semiconductor structure 11 , the second semiconductor structure 12 , the active region 13 , the first confinement layer 14 and the second confinement layer 15 may respectively include III-V semiconductor materials. The above-mentioned Group III and V semiconductor materials may include Al, Ga, As, P or In. In one embodiment, the first semiconductor structure 11 , the second semiconductor structure 12 , the active region 13 , the first confinement layer 14 and the second confinement layer 15 do not contain N. Specifically, the above-mentioned III-V semiconductor materials can be binary compound semiconductors (such as GaAs or GaP), ternary compound semiconductors (such as InGaAs, AlGaAs, InGaP or AlInP) or quaternary compound semiconductors (such as AlGaInAs, AlGaInP, InGaAsP, InGaAsN or AlGaAsP). In one embodiment, the active region 13 is essentially composed of a ternary compound semiconductor (such as InGaAs, AlGaAs, InGaP or AlInP) or a quaternary compound semiconductor (such as AlGaInAs, AlGaInP, InGaAsP or AlGaAsP).

The semiconductor device 100 may include a double heterostructure (DH), a double-side double heterostructure (DDH), or a multiple quantum wells (MQW) structure. According to an embodiment, when the semiconductor device 100 is a light-emitting device, the active region 13 can emit light from the first semiconductor structure 11 toward the second semiconductor structure 12 . The light includes visible light or invisible light. The wavelength of the light emitted by the semiconductor device 100 is determined by the material of the active region 13 . The material of the active region 13 may include InGaAs, AlGaAsP or GaAsP, InGaAsP, AlGaAs, AlGaInAs, InGaP or AlGaInP. For example, the active area 13 can emit infrared light with a peak wavelength of 700 to 1700 nm, red light with a peak wavelength of 610 nm to 700 nm, or yellow light with a peak wavelength of 530 nm to 600 nm. In this embodiment, the active area 13 emits infrared light with a peak wavelength of 730 nm to 1100 nm.

The substrate 7 contains electrically conductive or insulating material. Conductive materials such as gallium arsenide (GaAs), indium phosphide (InP), silicon carbide (SiC), gallium phosphide (GaP), zinc oxide (ZnO), gallium nitride (GaN), aluminum nitride (AlN), Germanium (Ge) or silicon (Si). Insulating materials such as sapphire. In other embodiments, the substrate 7 is a growth substrate, that is, the epitaxial layer 1 can be formed on the substrate 7 through, for example, metal-organic chemical vapor deposition (MOCVD) epitaxy. In one embodiment, the substrate 7 is a bonding substrate rather than a growth substrate, which can be bonded to the epitaxial stack 1 through the bonding structure 6 , as shown in FIG. 1A .

The first electrode 2 and the second electrode 3 are used for electrical connection with an external power supply. The materials of the first electrode 2 and the second electrode 3 may be the same or different, for example, they may respectively include metal oxide materials, metals or alloys. Metal oxide materials include indium tin oxide (ITO), indium oxide (InO), tin oxide (SnO), cadmium tin oxide (CTO), antimony tin oxide (ATO), aluminum zinc oxide (AZO), zinc tin oxide (ZTO) , Gallium zinc oxide (GZO), indium tungsten oxide (IWO), zinc oxide (ZnO) or indium zinc oxide (IZO), etc. The metal may include germanium (Ge), beryllium (Be), zinc (Zn), gold (Au), platinum (Pt), titanium (Ti), aluminum (Al), nickel (Ni) or copper (Cu), etc. The alloy may include at least two selected from the group consisting of the above metals, such as germanium gold nickel (GeAuNi), beryllium gold (BeAu), germanium gold (GeAu) or zinc gold (ZnAu).

The insulating layer 8 includes insulating materials, such as silicon nitride (SiN _x ), aluminum oxide (AlO _x ), silicon oxide (SiO _x ), magnesium fluoride (MgF _x ), titanium oxide (TiO ₂ ), niobium oxide (Nb ₂ O ₅ ) or a combination thereof, the insulating layer 8 may be selected to be an insulating material with a refractive index less than or equal to 2, in particular. In one embodiment, the insulating layer 8 may also include a first Distributed Bragg Reflector structure (DBR), for example, formed by alternately stacking two or more of the above-mentioned insulating materials. The conductive structure 4 may include metal oxide materials, such as indium tin oxide (ITO), indium oxide (InO), tin oxide (SnO), cadmium tin oxide (CTO), antimony tin oxide (ATO), aluminum zinc oxide (AZO) , zinc tin oxide (ZTO), gallium zinc oxide (GZO), indium tungsten oxide (IWO), zinc oxide (ZnO), indium zinc oxide (IZO) or a combination of the above materials.

The reflective layer 5 can reflect the light emitted from the active area 13 so as to be emitted out of the semiconductor element 100 toward the first electrode 2 . Reflective layer 5 may comprise semiconductor material, metal or alloy. The semiconductor material may include a III-V semiconductor material, such as a binary, ternary or quaternary III-V semiconductor material. Metals include but are not limited to copper (Cu), aluminum (Al), tin (Sn), gold (Au) or silver (Ag), etc. The alloy may include at least two selected from the group consisting of the above metals. In an embodiment, the reflective layer 5 may include a second Distributed Bragg Reflector structure (DBR). The second Bragg reflective structure is conductive and is formed by alternately stacking two or more semiconductor materials with different refractive indexes, such as AlAs/GaAs, AlGaAs/GaAs or InGaP/GaAs.

The bonding structure 6 connects the substrate 7 and the reflective layer 5 . In one embodiment, the bonding structure 6 can be a single layer or multiple layers (not shown). The material of the joint structure 6 may include transparent conductive materials, transparent insulating materials, metals or alloys. Transparent conductive materials include indium tin oxide (ITO), indium oxide (InO), tin oxide (SnO), cadmium tin oxide (CTO), antimony tin oxide (ATO), aluminum zinc oxide (AZO), zinc tin oxide (ZTO) , Gallium zinc oxide (GZO), zinc oxide (ZnO), gallium phosphide (GaP), indium cerium oxide (ICO), indium tungsten oxide (IWO), indium titanium oxide (ITiO), indium zinc oxide (IZO), oxide Indium gallium (IGO), gallium aluminum zinc oxide (GAZO), graphene or a combination of the above materials. Transparent insulating materials include aluminum oxide (AlO _x ), silicon oxide (SiO2), silicon nitride (SiN), etc. Metals include copper (Cu), aluminum (Al), tin (Sn), indium (In), gold (Au), silver (Ag), titanium (Ti), nickel (Ni), platinum (Pt) or tungsten (W) )wait. The alloy may include at least two selected from the group consisting of the above metals.

FIG. 2 is a partial cross-sectional view of a semiconductor device 200 according to an embodiment of the present disclosure. The structure of the semiconductor device 200 is generally similar to the semiconductor device 100 shown in FIGS. 1A and 1B. The difference is that the contact layer 111 of this embodiment includes a plurality of contact portions 111a that are separated from each other. There is a second opening 111b, the insulating portion 81 fills the second opening 111b and is in direct contact with the first semiconductor structure 11, and the extended electrode 22 and the contact portion 111a are misaligned with each other, thereby increasing the current dispersion effect of the semiconductor element 200.

FIG. 3 is a partial cross-sectional view of a semiconductor device 300 according to an embodiment of the present disclosure. The structure of the semiconductor device 300 is generally similar to the semiconductor device 100 shown in Figures 1A and 1B. The difference is that the second conductive oxide layer 42 of this embodiment includes a plurality of second conductive oxide portions 421 that are separated from each other, and a plurality of adjacent conductive oxide portions 421. There is a third opening 421a between the second conductive oxide parts 421. The reflective layer 5 fills the third opening 421a and is in direct contact with the insulating layer 8 (the plurality of insulating parts 81). The plurality of second conductive oxidation parts 421 roughly correspond to each other. The positions of the plurality of first conductive oxide portions 411.

FIG. 4 is a partial cross-sectional view of a semiconductor device 400 according to an embodiment of the present disclosure. The structure of the semiconductor device 400 is generally similar to the semiconductor device 300 shown in FIG. 3. The difference is that the contact layer 111 of this embodiment includes a plurality of contact portions 111a that are separated from each other, and each of the adjacent contact portions 111a has a contact layer 111a. In the second opening 111b, the insulating portion 81 fills the second opening 111b and is in direct contact with the first semiconductor structure 11, and the extended electrode 22 and the contact portion 111a are misaligned with each other.

Figures 5 and 6 are partial cross-sectional schematic diagrams of semiconductor devices 500 and 600 according to other embodiments of the present disclosure. The structures of the semiconductor devices 500 and 600 are generally similar to the semiconductor device 100 shown in Figure 1A . The difference lies in the semiconductor devices in these embodiments. The components 500 and 600 do not have the second conductive oxide layer 42 , and the reflective layer 5 is in direct contact with the first conductive oxide layer 41 and the insulating layer 8 (the plurality of insulating portions 81 ). The contact layer 111 of the semiconductor device 600 shown in FIG. 6 includes a plurality of contact portions 111a that are separated from each other. Each of the adjacent contact portions 111a has a second opening 111b. The insulating portion 81 fills the second opening 111b. And is in direct contact with the first semiconductor structure 11, and the extended electrode 22 and the contact portion 111a are misaligned with each other.

FIG. 7 is a partial cross-sectional view of a semiconductor device 700 according to other embodiments of the present disclosure. The structure of the semiconductor device 700 is generally similar to the semiconductor device 100 shown in FIG. 1A . The difference is that the semiconductor device 700 in these embodiments does not have an insulating layer 8 . . The contact layer 111 of the semiconductor device 700 shown in FIG. 7 includes a plurality of contact portions 111a that are separated from each other. Each of the adjacent contact portions 111a has a second opening 111b. The second conductive oxide layer 42 is filled with the second opening 111b. The two openings 111b are in direct contact with the first semiconductor structure 11, and the extended electrode 22 and the contact portion 111a are offset from each other. The plurality of first conductive oxide portions 411 are respectively located under the plurality of contact portions 111a.

The semiconductor device 800 shown in FIG. 8 is generally similar to that of FIG. 7 . The difference is that the second conductive oxide layer 42 in this embodiment includes a plurality of second conductive oxide portions 421 that are separated from each other. Each of the portions 421 has a third opening 421a. The reflective layer 5 directly contacts the first semiconductor structure 11 through the third opening 421a and the second opening 111b. The plurality of second conductive oxide portions 421 generally correspond to the plurality of first conductive oxide portions. The location of part 411.

The semiconductor element 900 shown in Figure 9 is generally similar to Figure 8. The difference is that the semiconductor element in this embodiment does not have the second conductive oxide layer 42. The reflective layer 5 directly contacts the plurality of first conductive oxide portions 411 and also passes through it. The second opening 111 b is in direct contact with the first semiconductor structure 11 .

FIG. 10 is a partial cross-sectional view of a semiconductor device 1000 according to another embodiment of the present disclosure. The structure of the semiconductor device 1000 is generally similar to the semiconductor device shown in FIG. 1A . The difference is that the semiconductor device 1000 in this embodiment does not have an insulating layer 8 , the first conductive oxide layer 41 is completely located under the contact layer 111 and includes a plurality of first conductive oxide portions 411 separated from each other.

FIG. 11 is a partial cross-sectional view of a semiconductor device 1100 according to another embodiment of the present disclosure. The structure of the semiconductor device 1100 is generally similar to the semiconductor device 100 shown in FIG. 1A . The difference is that the semiconductor device 1100 in this embodiment does not have an insulating layer. 8, and the second conductive oxide layer 42 includes a plurality of second conductive oxide portions 421 that are separated from each other. There is a third opening 421a between the adjacent second conductive oxide portions 421, and the reflective layer 5 passes through the third opening. 421a is in direct contact with the contact layer 111, and the plurality of second conductive oxide portions 421 roughly correspond to the positions of the plurality of first conductive oxide portions 411.

Figure 12 is a partial cross-sectional view of a semiconductor device 1200 according to another embodiment of the present disclosure. The structure of the semiconductor device 1200 is generally similar to the semiconductor device 1000 shown in Figure 10 . The difference is that the semiconductor device 1200 in this embodiment does not have a second The conductive oxide layer 42 directly connects the reflective layer 5 to the first conductive oxide portion 411 and the contact layer 111 .

Figure 13 is a partial cross-sectional schematic diagram of a semiconductor device 1300 according to another embodiment of the present disclosure. The structure of the semiconductor device 1300 is generally similar to the semiconductor device 200 shown in Figure 2 . The difference lies in the contact portion 111a of the semiconductor device in this embodiment. The insulating portion 81 has substantially the same thickness, and the contact portion 111a and the surface of the insulating portion 81 away from the epitaxial layer 1 are coplanar. In detail, each contact portion 111a has a third thickness T3, each insulating portion 81 has a fourth thickness T4 that is substantially equal to the third thickness T3, each contact portion 111a has a first surface 1111a away from the epitaxial layer 1, and One surface 1111 a is coplanar with the surface 811 of each insulating part 81 , and the first conductive oxidation part 411 does not contact the sidewall 812 of the insulating part 81 . The contact portion 111a has a third width W3, and the third width W3 is substantially equal to the second width W2 of the first conductive oxide portion 411. In an embodiment, the third width W3 may be greater than or less than the second width W2 of the first conductive oxide portion 411 .

FIG. 14 is a partial cross-sectional structural diagram of a semiconductor package structure 2000 according to an embodiment of the disclosure. The semiconductor package structure 2000 includes a carrier 220, a first semiconductor element 211 and a second semiconductor element 231. The first semiconductor element 211 and/or the second semiconductor element 231 may be the semiconductor elements shown in the above-mentioned FIGS. 1A to 13 . The carrier 220 includes a first retaining wall 221, a second retaining wall 222, a third retaining wall 223, a carrier plate 224, a first space 225 and a second space 226. The first semiconductor element 211 is located between the first retaining wall 221 and the second retaining wall 223. In the first space 225 between the two blocking walls 222 , the second semiconductor element 231 is located in the second space 226 between the second blocking wall 222 and the third blocking wall 223 . The first semiconductor element 211 and/or the second semiconductor element 231 may be a vertical wafer as shown in Figure 1A. The first semiconductor element 211 and the second semiconductor element 231 are located on the carrier board 224 and are electrically connected to the circuit connection structure (not shown) on the carrier board 224 . In this implementation, the first semiconductor element 211 is a light-emitting element, the second semiconductor element 231 is a light-receiving element, and the semiconductor package structure 2000 can be placed in a wearable device (eg, watch, earphone). The first semiconductor element 211 The emitted light passes through the skin and irradiates the body cells and blood, and then absorbs the light scattered/reflected from the body cells and blood through the second semiconductor element 231. Based on the changes in the reflected and scattered light, it is used to detect the physiology of the human body. Signals, such as: heart rate, blood sugar, blood pressure, blood oxygen concentration, etc.

FIG. 15 is a schematic cross-sectional structural diagram of a semiconductor packaging structure 3000 according to an embodiment of the present disclosure. The semiconductor packaging structure 3000 includes a semiconductor element 100 , a packaging substrate 31 , a carrier 33 , bonding wires 35 , contact structures 36 and packaging layers 38 . The packaging substrate 31 may include ceramic or glass materials. The package substrate 31 has a plurality of through holes 32 therein. The through hole 32 may be filled with conductive material such as metal to facilitate conduction and/or heat dissipation. The carrier 33 is located on the surface of one side of the packaging substrate 31 and also includes conductive material, such as metal. Contact structure 36 is located on the surface of the other side of package substrate 31 . In this embodiment, the contact structure 36 includes a first contact pad 36 a and a second contact pad 36 b, and the first contact pad 36 a and the second contact pad 36 b can be electrically connected to the carrier 33 through the through hole 32 . In one embodiment, the contact structure 36 may further include a thermal pad (not shown), for example, located between the first contact pad 36a and the second contact pad 36b.

Semiconductor component 100 is located on carrier 33 . In this embodiment, the carrier 33 includes a first part 33 a and a second part 33 b, and the semiconductor device 100 is electrically connected to the second part 33 b of the carrier 33 through the bonding wire 35 . The material of the bonding wire 35 may include metal, such as gold, silver, copper, aluminum or an alloy containing at least any of the above elements. The encapsulation layer 38 covers the semiconductor element 100 and has the effect of protecting the semiconductor element 100 . Specifically, the encapsulation layer 38 may include resin materials such as epoxy, silicone, etc. The encapsulation layer 38 may optionally include a plurality of wavelength conversion particles (not shown) to convert the first light emitted by the semiconductor device 100 into a second light. The wavelength of the second light is greater than the wavelength of the first light.

Specifically, the semiconductor components and semiconductor packaging structures disclosed in the present disclosure can be applied to products in the fields of lighting, medical care, display, communication, sensing, power supply systems, etc., such as lamps, monitors, mobile phones, tablet computers, and automotive instrument panels. , TVs, computers, wearable devices (such as watches, bracelets, necklaces, etc.), traffic signals, outdoor displays, medical equipment, etc.

Although the present invention has been disclosed above through embodiments, they are not intended to limit the present invention. Those of ordinary skill in the art will understand that slight modifications or changes may be made without departing from the spirit and scope of the present invention. Therefore, the present invention is The protection scope of the invention shall be determined by the appended patent application scope. In addition, the above-described embodiments may be combined or replaced with each other under appropriate circumstances and are not limited to the specific embodiments described. For example, the relevant parameters of a specific component or the connection relationship between a specific component and other components disclosed in one embodiment can also be applied to other embodiments, and all fall within the scope of the present invention.

100, 200, 300, 400, 500, 600, 700, 800, 900, 1000, 1100, 1200, 1300: semiconductor components 211: First semiconductor element 220:Bearer 221:The first retaining wall 222:Second retaining wall 223:The third retaining wall 224: Carrier board 225:First space 226:Second Space 231: Second semiconductor element 31:Package substrate 32:Through hole 33: Carrier 33a:Part 1 33b:Part 2 35:Joining wire 36:Contact structure 36a: First contact pad 36b: Second contact pad 38: Encapsulation layer 1: Epitaxial layer 11: First semiconductor structure 111:Contact layer 111a: Contact Department 1111a: First surface 111b: Second opening 12: Second semiconductor structure 13:Active area 14: The first localization layer 15: The second localization layer 2: First electrode 21: First electrode pad 22:Extended electrode 3: Second electrode 4: Conductive structure 41: First conductive oxide layer 411: First conductive oxidation part 42: Second conductive oxide layer 421: Second conductive oxidation part 421a: The third opening 5: Reflective layer 6: Joint structure 7: Base 8: Insulation layer 8a: First opening 81:Insulation Department 811:Surface 811a:Part 1 811b:Part 2 812:Side wall S: upper surface T1: first thickness T2: second thickness T3: The third thickness T4: The fourth thickness W1: first width W2: second width W3: third width 2000, 3000: Semiconductor packaging structure

The drawings described here are used to provide a further understanding of the present invention and constitute a part of the present invention. The schematic embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the attached picture: FIG. 1A is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present disclosure. Figure 1B is an enlarged view of the framed area in Figure 1A. FIG. 2 is a partial cross-sectional view of a semiconductor device according to an embodiment of the present disclosure. FIG. 3 is a partial cross-sectional view of a semiconductor device according to an embodiment of the present disclosure. FIG. 4 is a partial cross-sectional view of a semiconductor device according to an embodiment of the present disclosure. FIG. 5 is a partial cross-sectional view of a semiconductor device according to an embodiment of the present disclosure. FIG. 6 is a partial cross-sectional view of a semiconductor device according to an embodiment of the present disclosure. FIG. 7 is a partial cross-sectional view of a semiconductor device according to an embodiment of the present disclosure. FIG. 8 is a partial cross-sectional view of a semiconductor device according to an embodiment of the present disclosure. FIG. 9 is a partial cross-sectional view of a semiconductor device according to an embodiment of the present disclosure. FIG. 10 is a partial cross-sectional view of a semiconductor device according to an embodiment of the present disclosure. FIG. 11 is a partial cross-sectional view of a semiconductor device according to an embodiment of the present disclosure. FIG. 12 is a partial cross-sectional view of a semiconductor device according to an embodiment of the present disclosure. FIG. 13 is a partial cross-sectional view of a semiconductor device according to an embodiment of the present disclosure. FIG. 14 is a partial cross-sectional structural diagram of a semiconductor packaging structure according to an embodiment of the present disclosure. FIG. 15 is a schematic cross-sectional view of a semiconductor packaging structure according to an embodiment of the present disclosure.

100:Semiconductor components

1: Epitaxial layer

11: First semiconductor structure

111:Contact layer

12: Second semiconductor structure

13:Active area

14: The first localization layer

15: The second localization layer

2: First electrode

21: First electrode pad

22:Extended electrode

3: Second electrode

4: Conductive structure

41: First conductive oxide layer

42: Second conductive oxide layer

5: Reflective layer

6: Joint structure

7: Base

8: Insulation layer

81:Insulation Department

8a: First opening

S: upper surface

Claims (10)

A semiconductor device includes: an epitaxial layer; an insulating layer located on the epitaxial layer and having a plurality of openings and a surface away from the epitaxial layer; and a first conductive oxide layer located on the epitaxial layer. on the crystal stack and the insulating layer, and having a plurality of first conductive oxide parts separated from each other located in the plurality of openings; wherein the surface has a first part and a second part, and the first conductive oxide layer covers the first part part and does not cover this second part. The semiconductor device described in claim 1 of the patent application, wherein the first part is closer to the opening than the second part. The semiconductor device according to claim 1, wherein the epitaxial stack includes a contact layer located in the plurality of openings, and the first conductive oxide layer is in contact with the contact layer. In the semiconductor device described in claim 3 of the patent application, the contact layer includes a plurality of contact portions separated from each other. The semiconductor device described in claim 1 of the patent application further includes a second conductive oxide layer located on the first conductive oxide layer. The semiconductor device described in Item 1 of the patent application further includes a reflective layer located on the first conductive oxide layer and in direct contact with the first conductive oxide layer. As in the semiconductor device described in claim 5 of the patent application, the second conductive oxide layer has a plurality of mutually separated second conductive oxide portions located in the plurality of openings. A semiconductor component, including: An active area; a contact layer located on one side of the active area and having a plurality of contact portions separated from each other, each contact portion having a first surface away from the active area; an insulating layer located on any two adjacent contacts between the parts; a first conductive oxide layer is located on the side of the contact layer away from the active area, and has a plurality of mutually separated first conductive oxide parts respectively located on the first surface of the plurality of contact parts; wherein, the The first surface includes a first region and a second region, the first region contacts the first conductive oxide portion, and the second region contacts the insulating layer. The semiconductor device described in Item 8 of the patent application further includes a reflective layer located on a side of the first conductive oxide layer away from the contact layer and in contact with the first conductive oxide layer and the insulating layer. The semiconductor device described in item 8 of the patent application further includes a second conductive oxide layer located on a side of the first conductive oxide layer away from the contact layer; wherein each first conductive oxide portion has a A second surface parallel to the first surface and a side surface not parallel to the first surface, the second surface contacts the second conductive oxide layer, and the side surface contacts the insulating layer.

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