CN217086612U

CN217086612U - Semiconductor device with a plurality of semiconductor chips

Info

Publication number: CN217086612U
Application number: CN202122992675.7U
Authority: CN
Inventors: 吴宜翰; 黄国峰; 金明达; 江政兴; 黄文镝; 廖富祥; 沈庆兴; 高慧芳; 周允中; 温宛颐; 吕俊翰
Original assignee: Epistar Corp
Current assignee: Epistar Corp
Priority date: 2021-12-01
Filing date: 2021-12-01
Publication date: 2022-07-29
Anticipated expiration: 2031-12-01
Also published as: TW202324785A

Abstract

The utility model discloses a semiconductor device contains: an epitaxial structure comprising a first semiconductor structure having a first portion and a second portion, an active structure and a second semiconductor structure located on the second portion; a first electrode comprising a first surface on the first portion and a second surface on the second semiconductor structure, the first surface and the second surface having a height difference of 4 μm to 8 μm; a second electrode on the second semiconductor structure; and an insulating structure between the first electrode and the first portion.

Description

Semiconductor device with a plurality of semiconductor chips

Technical Field

The present invention relates to a semiconductor device, and more particularly to a photoelectric semiconductor device.

Background

The optoelectronic semiconductor device is a device that can convert an optical signal and an electrical signal, and can achieve mechanisms of absorbing energy and exciting radiation by using interaction of photons and electrons. Among them, Light Emitting Diodes (LEDs) which are optoelectronic semiconductor devices are often used in various lighting fixtures, traffic warning signs, etc. in daily life because they have advantages of small size, power saving, high brightness, high color saturation, and capability of modulating various colors.

However, in order to achieve the requirements of energy saving and power saving, how to make the light emitting diode in the optoelectronic semiconductor device have better light emitting efficiency is an urgent issue to be solved in the industry.

SUMMERY OF THE UTILITY MODEL

An object of the utility model is to provide a semiconductor device to solve the problem that prior art exists.

To achieve the above objects, the present invention provides a semiconductor device comprising an epitaxial structure including a first semiconductor structure having a first portion and a second portion, an active structure and a second semiconductor structure located on the second portion; a first electrode comprising a first surface on the first portion and a second surface on the second semiconductor structure, the first surface and the second surface having a height difference of 4 μm to 8 μm; a second electrode on the second semiconductor structure; and an insulating structure between the first electrode and the first portion.

The semiconductor device further includes a first contact structure between the first electrode and the first portion.

The insulating structure has a first opening filled with the first electrode, and the semiconductor device further includes a first connecting structure including a first cavity oppositely disposed in the first opening and a first conductive part covering the first cavity.

The first connecting structure further includes a first insulating portion located between the first cavity and the first conductive portion.

The insulating structure has a second opening filled with the second electrode, and the semiconductor device has a second connection structure including a second cavity and a second conductive portion covering the second cavity.

The semiconductor device further includes a second insulating portion between the first connection structure and the second connection structure.

The active structure is used for emitting light with a wavelength of 600nm to 1300 nm.

The epitaxial structure contains Al, Ga, As, P or In, and does not contain N.

The semiconductor device further includes an adhesion layer and a substrate, the adhesion layer being between the epitaxial structure and the substrate.

The substrate has an upper surface facing the epitaxial structure, the epitaxial structure has a lower surface facing the substrate, the upper surface has a first surface roughness, and the lower surface has a second surface roughness greater than the first surface roughness.

The first semiconductor structure has a first length, and the bonding layer has a second length greater than the first length.

The insulating structure is in direct contact with the adhesive layer.

The insulating structure is not in direct contact with the substrate.

The semiconductor device further includes a second contact structure located between the second electrode and the second semiconductor structure and in direct contact with the second semiconductor structure.

The second contact structure is a metal or metal alloy.

The insulating structure comprises a distributed bragg reflector structure.

The insulating structure comprises a first insulating layer and a second insulating layer, wherein the first insulating layer and the second insulating layer are positioned between the first insulating layer and the first electrode, the first insulating layer has a first thickness, and the second insulating layer has a second thickness larger than the first thickness.

The insulating structure further comprises a third insulating stack, the second insulating layer being positioned between the first insulating layer and the third insulating stack, the third insulating stack comprising a plurality of first and second sub-layers overlapping each other, the first sub-layer having a refractive index lower than the second sub-layer.

The third insulating stack further has a thickness inversion region, wherein the thickness of the first sub-layer in the thickness inversion region is less than the thickness of the adjacent second sub-layer.

Wherein a first sub-layer is connected with the second insulating layer and has the same material as the second insulating layer.

The first sub-layer and the second insulating layer have different characteristics and composition ratios.

The semiconductor device includes: an epitaxial structure comprising a first semiconductor structure having a first portion and a second portion, an active structure and a second semiconductor structure located on the second portion; a first electrode comprising a first surface on the first portion and a second surface on the second semiconductor structure; a second electrode on the second semiconductor structure; and an insulating structure between the first electrode and the first portion and comprising an insulating stack, the insulating stack comprising a plurality of first and second sublayers overlapping each other, the first sublayer having a refractive index lower than the second sublayer and each first sublayer having a thickness greater than the thickness of the adjacent second sublayer, the insulating stack having a thickness inversion region in which the thickness of the first sublayer is less than the thickness of the adjacent second sublayer.

The insulating structure further comprises a first insulating layer and a second insulating layer positioned between the first insulating layer and the insulating lamination layer, wherein the first insulating layer has a first thickness, and the second insulating layer has a second thickness larger than the first thickness.

The utility model has the advantages of, the utility model provides a semiconductor device can have the application extensively through the improvement of its structure, energy-conserving power saving, the technological effect of luminous efficiency preferred.

Drawings

Fig. 1 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention.

Fig. 2 is a schematic top view of a semiconductor device according to an embodiment of the present invention.

Fig. 3 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention.

Fig. 4 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention.

Fig. 5 is an enlarged partial cross-sectional view of a semiconductor device according to an embodiment of the present invention.

Fig. 6 is a top view of a light emitting module according to an embodiment of the present invention.

Fig. 7 is a schematic partial sectional view of a sensing module according to an embodiment of the present invention.

Description of the symbols

100,100' semiconductor component

1000,2000,3000 semiconductor device

1 semiconductor unit

10 epitaxial structure

10a lower surface

11 first semiconductor structure

111 first part

111a third surface

112 second part

12 active structure

12a fourth surface

13 second semiconductor structure

131 first part

132 second part

133 third part

20 first electrode

201 first surface

202 second surface

30 second electrode

40 insulating structure

401 first insulating layer

402 second insulating layer

403 third insulating stack

403' thickness inversion region

403a1 ~ 403an first sublayer

403b1 ~ 403b (n-1) second sub-layer

40a first opening

40b second opening

50 base

51 upper surface of

60 adhesive layer

70 first contact structure

71 first contact part

72 first extension part

721 first end portion

80 second contact structure

81 second contact part

82 second extension part

821 second end portion

91, 91' first connecting structure

911,911 ', 911' first cavity

912,912 ', 912' first conductive portion

913,913 ', 913' first insulation part

92, 92' second connecting structure

921,921' second hollow

922,922 ', 922' second conductive part

923,923 ', 923' second insulating part

93 third insulating part

931 third hollow

932 a third conductive portion

94, 94' fourth insulation

941 fourth hollow

942 fourth conductive part

95 fifth insulating part

951 fifth void

952 fifth conductive part

4000 luminous module

26 reflective wall

110,210,324 Carrier plate

1101,2101 first electrode pad

1102,2102 second electrode pad

5000 sensing module

320 carrier

311 first semiconductor element

331 second semiconductor element

321 first retaining wall

322 second retaining wall

323 third baffle wall

325 first space

326 second space

d minimum vertical distance

L1 first length

L2 second length

Width of first part D1

Width of second part D2

Width of third part D3

D area of notch

Difference in height of G

Thickness of T

E edge

a1, a2, a3 width

Detailed Description

The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, not all embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by a person of ordinary skill in the art without creative efforts belong to the protection scope of the present invention.

Unless otherwise specified, the general formula InGaP represents In _x0 Ga _1-x0 P, wherein 0<x0<1; the general formula AlInP represents Al _x1 In _1-x1 P, wherein 0<x1<1; al in the general formula AlGaInP _x2 Ga _x3 In _1-x2-x3 P is 0 in<x2<1 and 0<x3<1; the formula InGaAsP represents In _x4 Ga _1-x4 As _x5 P _1-x5 Wherein 0 is<x4<1， 0<x5<1; the general formula AlGaInAs represents Al _x6 Ga _x7 In _1-x6- _x7 As, wherein 0<x6<1，0<x7<1; the general formula InGaNAs represents In _x8 Ga _1-x8 N _x9 As _1-x9 Wherein 0 is<x8<1，0<x9<1; the general formula InGaAs represents In _x10 Ga _1-x10 As, wherein 0<x10<1; AlGaAs represents Al _x11 Ga _1-x11 As, wherein 0<x11<1. The content of each element can be adjusted for different purposes, such as but not limited to adjusting the size of the energy gap, or when the semiconductor device is a light emitting device, the dominant wavelength (domain wavelength) or peak wavelength (peak wavelength) of the light emitting element can be adjusted accordingly.

The semiconductor device of the present invention is, for example, a light emitting device (e.g., a light emitting diode (led) or a laser diode), a light absorbing device (e.g., a photodiode), or a non-light emitting device. The semiconductor device of the present invention can be obtained by analyzing the composition and dopant (dopant) of each layer in any suitable manner, such as Secondary Ion Mass Spectrometer (SIMS), and the thickness of each layer can be obtained by analyzing in any suitable manner, such as Transmission Electron Microscope (TEM) or Scanning Electron Microscope (SEM).

It will be appreciated by those of ordinary skill in the art that other components may be added to the embodiments described below. For example, unless specifically stated otherwise, a similar description of a first layer (or structure) being on a second layer (or structure) may include embodiments in which the first layer (or structure) is in direct contact with the second layer (or structure), and may also include embodiments in which there are other structures between the first layer (or structure) and the second layer (or structure) that are not in direct contact with each other. In addition, it is to be understood that the upper and lower positional relationship of the layers (or structures), etc. may be changed as viewed from different orientations.

In addition, in the present invention, the description of a layer or structure "consisting essentially of M" means that the layer or structure has a main composition of M, but does not exclude that the layer or structure contains dopants or unavoidable impurities (impurities).

Fig. 1 is a schematic cross-sectional view of a semiconductor device 1000 according to an embodiment of the present invention. The semiconductor device 1000 includes a semiconductor device 100, and a carrier 110 and a connecting member 9 are disposed between the semiconductor device 100 and the carrier 110.

The semiconductor device 100 includes an epitaxial structure 10, a first electrode 20, a second electrode 30, and an insulating structure 40. The first electrode 20 and the second electrode 30 are located on the epitaxial structure 10, and the insulating structure 40 is located between the first electrode 20 and the epitaxial structure 10 and between the second electrode 30 and the epitaxial structure 10. The semiconductor device 100 may optionally include a substrate 50 and an adhesive layer 60 between the substrate 50 and the epitaxial structure 10.

The epitaxial structure 10 includes a first semiconductor structure 11 having a first portion 111 and a second portion 112, an active structure 12 on the second portion 112, and a second semiconductor structure 13 on the active structure 12. In other words, the second portion 112 is sequentially covered by the active structure 12 and the second semiconductor structure 13 and the first portion 111 does not have any active structure 12 and second semiconductor structure 13 thereon. In the embodiment, a first contact structure 70 may be selectively disposed on the first portion 111, and a second contact structure 80 may be selectively disposed on the second semiconductor structure 13, wherein the first contact structure 70 is separated from the second contact structure 80. The arrangement of the first contact structure 70 and the second contact structure 80 helps to reduce the forward voltage (Vf) of the semiconductor device 100, thereby improving the electrical performance of the semiconductor device 100.

The insulating structure 40 covers the first portion 111 and the second portion 112, and the insulating structure 40 includes a first opening 40a on the first portion 111 and a second opening 40b on the second portion 112. The insulating structure 40 further covers the first contact layer 70 and the second contact layer 80, and the first opening 40a exposes a portion of the first contact layer 70 and the second opening 40b exposes a portion of the second contact layer 80. The second electrode 30 is located on the second semiconductor structure 13 and fills the second opening 40b to contact the second contact layer 80. A portion of the first electrode 20 is located on the first portion 111 and fills the first opening 40a to connect with the first contact layer 70, and another portion of the first electrode 20 spans the second semiconductor structure 13 and is located on the second portion 112. The insulating structure 40 is located between the first electrode 20 and the second portion 112.

In the present embodiment, the thickness of the second semiconductor structure 13 is 1 μm to 2.5 μm, and the vertical distance between the second semiconductor structure 13 and the first portion 111 is 2 μm to 3.5 μm. In detail, the first portion 111 has a third surface 111a, the second semiconductor structure 13 has a fourth surface 13a, and a minimum vertical distance d between the third surface 111a and the fourth surface 13a is 2 μm to 3.5 μm. In the present embodiment, the first electrode 20 has a first surface 201 on the first portion 111 and opposite to the first opening 40a, and a second surface 202 on the second portion 112. The first surface 201 and the second surface 202 have a height difference G between 4 μm and 8 μm, so that the semiconductor device 100 has good efficiency and reliability. In other words, the height difference G is the sum of the thicknesses of a portion of the second semiconductor structure 13 and the insulating structure 40, and when the height difference G is less than 4 μm, the thickness T of the insulating structure 40 may be less than 1.5 μm, which may not be enough to provide complete protection, insulation and/or reflection; when the height difference G is greater than 8 μm, the semiconductor device 100 may be electrically failed after being bonded to a carrier 110. In the present embodiment, the thickness T of the insulating structure 40 is 2 μm to 5 μm.

The semiconductor device 100 is bonded to the carrier 110 by the bonding member 9. The connection member 9 includes a first connection structure 91 and a second connection structure 92, and the first connection structure 91 is connected to and electrically connected to the first electrode 20. In the present embodiment, the first connection structure 91 includes a first cavity 911, a first conductive portion 912 and a first insulating portion 913, and the first conductive portion 912 covers the first cavity 911 or the first cavity 911 is embedded in the first conductive portion 912. The first insulating portion 913 is located between the first conductive portion 912 and the first cavity 911, that is, the first conductive portion 912 covers the first insulating portion 913 or the first insulating portion 913 is embedded in the first conductive portion 912, and the first insulating portion 913 covers the first cavity 911 or the first cavity 911 is embedded in the first insulating portion 913. In one embodiment, the first cavity 911 and the first insulating portion 913 are located opposite to the first opening 40 a. The first cavity 911 may be a vacuum or filled with a gas (e.g., nitrogen or air).

The second connection structure 92 is connected to and electrically connected to the second electrode 30. In the embodiment, the second connecting structure 92 includes a second cavity 921, a second conductive portion 922 and a second insulating portion 923, and the second conductive portion 922 is wrapped around the second cavity 921 or the second cavity 921 is embedded in the second conductive portion 922. The second insulating portion 923 is located between the second conductive portion 922 and the second cavity 921, in other words, the second conductive portion 922 covers the second insulating portion 923 or the second insulating portion 923 is embedded in the second conductive portion 922, and the second insulating portion 923 covers the second cavity 921 or the second cavity 921 is embedded in the second insulating portion 923. By the first connecting structure 91 and/or the second connecting structure 92 having the above features, the semiconductor device 100 can have higher reliability and yield after being connected to the carrier 110. In another embodiment, the first connecting structure 91 further comprises a first mixed layer (not shown) between the first cavity 911 and the first insulating layer 913, the first mixed layer having a different composition from the first insulating layer 913; the second connecting structure 92 further includes a second mixed layer (not shown) between the second cavity 921 and the second insulating layer 923, and the composition of the second mixed layer is different from that of the second insulating layer 923. For example: the first mixed layer and/or the second mixed layer may include a mixture or compound of a metal including gold, platinum, tin, titanium, nickel, gallium, aluminum, or the like, or a nonmetal including carbon, oxygen, phosphorus, silicon, or the like.

In order to enhance the bonding strength between the epitaxial structure 10 and the carrier 110, the connecting member 9 optionally has a third insulating portion 93 between the first connecting structure 91 and the second connecting structure 92. In detail, the carrier 110 has a first electrode pad 1101 and a second electrode pad 1102 facing the epitaxial structure 10, and the third insulating portion 93 is located between the first electrode pad 1101, the second electrode pad 1102, the first electrode 20, the second electrode 30, the first connecting structure 91, the second connecting structure 92 and the insulating structure 40. The semiconductor device 100 optionally includes a fourth insulating portion 94 and a fifth insulating portion 95. The fourth insulating portion 94 is located outside the first connecting structure 91, so that the first connecting structure 91 is located between the third insulating portion 93 and the fourth insulating portion 94; the fifth insulating portion 95 is located outside the second connecting structure 92, so that the second connecting structure 92 is located between the fourth insulating portion 94 and the fifth insulating portion 95. The fourth insulating portion 94 and the fifth insulating portion 95 help to protect the first connecting structure 91 and the second connecting structure 92 from being contaminated by external conductive substances to cause unexpected electrical failure. Further, the fourth insulating portion 94 and the fifth insulating portion 95 can increase the adhesion between the semiconductor device 100 and the carrier 110.

The substrate 50 has an upper surface 51, the upper surface 51 is a flat surface, and has no intentionally formed roughened structure or patterned structure existing on the upper surface 51, and particularly, the upper surface 51 has no intentionally formed regular patterned structure. In the present embodiment, the upper surface 51 has a first surface roughness. The epitaxial structure 10 has a lower surface 10a away from the first electrode 20 and the second electrode 30, the adhesive layer 60 is used to bond the epitaxial structure 10 and the substrate 50, and the adhesive layer 60 is located between the upper surface 51 of the substrate 50 and the lower surface 10a of the epitaxial structure 10. The lower surface 10a of the epitaxial structure 10 has a roughened structure or a patterned structure, and the lower surface 10a has a second surface roughness greater than the first surface roughness. In the present embodiment, since the epitaxial structure 10 is grown on another growth substrate, and then the epitaxial structure is fixed on the substrate 50 by the bonding layer 60 through the wafer bonding technique, the lower surface 10a of the epitaxial structure 10 has a larger roughness, which is helpful to increase the mechanical strength after being bonded with the substrate 50 and increase the light extraction efficiency. Since the substrate 50 is not a growth substrate of the epitaxial structure 10, no additional manufacturing process is required to form a patterned structure on the upper surface 51, and the specification requirement for the substrate 50 is relatively low, so as to achieve the effect of saving the manufacturing process cost.

If the semiconductor device 100 is a light emitting device, the adhesive layer 60 and the substrate 50 are transparent to the light emitted from the active structure 12 (e.g., the transmittance of the adhesive layer 60 and the substrate 50 to the light emitted from the active structure 112 is greater than 85%), so that the light can be emitted out of the semiconductor device 100 toward the substrate 50.

Fig. 2 is a schematic top view of a semiconductor device 100 according to an embodiment of the present invention. For clarity of illustration and description, only a portion of the layers are depicted in this figure. As shown in fig. 1 and 2, the first semiconductor structure 11 has a first length L1, the adhesive layer 60 has a second length L2 greater than the first length L1, and the adhesive layer 60 extends to protrude beyond the edge E of the first semiconductor structure 11. The insulating structure 40 and the adhesive layer 60 are in contact with each other, and since the adhesive layer 60 is located on the substrate 50 and a portion of the adhesive layer 60 is located between the insulating structure 40 and the substrate 50, the insulating structure 40 is not in direct contact with the substrate 50. From a top view, the second semiconductor structure 13 has a first portion 131 having a first portion width D1, a second portion 132 having a second portion width D2, and a third portion 133 having a third portion width D3, and the second portion 132 is located between the first portion 131 and the third portion 133. The width of the second semiconductor structure 13 decreases or increases from the first portion 131 to the third portion 133, and the decreasing or increasing of the width may be continuous or sectional. In the present embodiment, the first portion width D1 is smaller than the second portion width D2, and the third portion width D3 is larger than the second portion width D2. A first electrode 20 covering the first portion 131 and a second electrodeThe electrode 30 covers the third portion 133, and a portion of the second portion 132 is not covered by the first electrode 20 and the second electrode 30. In the present embodiment, the area of the second semiconductor structure 13 covered by the first electrode 20 occupies 48% to 60% of the area of the first electrode 20. In detail, when the area of the first electrode 20 is a1 and the area of the second semiconductor structure 13 covered by the first electrode 20 is a2 from the top view, the first electrode 20 has a smaller area than the second electrode 20

If it is

The bonding robustness with the first electrode pad 1101 through the first electrode 20 may not be high, thereby reducing the production yield of the semiconductor device 1000; if it is

The distance between the first electrode 20 and the second electrode 30 is affected, thereby increasing the probability of short circuit in the subsequent process.

From the top view, the first semiconductor structure 11 is substantially rectangular and has four corners C, the first contact structure 70 includes a first contact portion 71 and a first extension portion 72 connected to the first contact portion 71, a width a1 of the first contact portion 71 is greater than a width a2 of the first extension portion 72, the first extension portion 72 extends from the first contact portion 71 to the second electrode 30, and has a first end portion 721 away from the first contact portion 71, and the first end portion 721 and the second electrode 30 are not overlapped with each other.

The second contact structure 80 includes a second contact portion 81 and a second extension portion 82 connected to the second contact portion 82, and a width a3 of the second contact portion 81 is greater than a width a4 of the second extension portion 82, the second extension portion 82 extends from the second contact portion 81 toward the first electrode 20, and has a second end portion 821 away from the second contact portion 81 and extending to the first contact portion 71 (i.e., the second end portion 821 overlaps the first contact portion 71 in the Y direction shown in fig. 2). Referring to fig. 1 and 2, a portion of the second extension 82 is located below the first electrode 20, and in order to maintain the electrical normal connection, the insulating structure 40 is located between the second extension 82 below the first electrode 20 and the first electrode 20.

From the top view, the first contact portion 71 is adjacent to the first portion 131, and the second contact portion 81 is located at the third portion 133. The first electrode 20 is covered on the first portion 131, and the second electrode 30 is covered on the third portion 133. The first opening 40a of the insulating structure 40 is located opposite to the first contact portion 71, and the second opening 40b is located opposite to the second contact portion 82, and the current is injected into the first contact structure 70 and the second contact structure 81 through the first contact portion 71 and the second contact portion 81, respectively, so that the first contact portion 71 and the second contact portion 81 with larger widths can bear higher current density without being burned, and thus the durability of the semiconductor device 100 is improved.

In the present embodiment, the first extension portion 72 and the second extension portion 82 have uniform widths a2 and a4, and the width a2 of the first extension portion 72 is greater than the width a4 of the second extension portion 82. In other embodiments, the width a2 of the first extension portion 72 increases or decreases from the first contact portion 71 to the first end portion 721, and/or the width a4 of the second extension portion 82 increases or decreases from the second contact portion 81 to the second end portion 821. The widths a1, a2, a3, a4, the first portion width D1, the second portion width D2, and the third portion width D3 are oriented parallel to one side of the semiconductor element 100, for example, parallel to the X direction shown in fig. 2.

Fig. 3 is a schematic cross-sectional view of a semiconductor device 2000 according to an embodiment of the present invention. The semiconductor device 2000 comprises a semiconductor device 100, a carrier 111 and a first connecting structure 9'. The semiconductor device 2000 of the present embodiment has substantially the same components and the same connection relationship between the components as the semiconductor device 1000 of fig. 1, and the difference is the connection member 9' in the present embodiment. In detail, the connection member 9 'includes a first connection structure 91' located between the first electrode pad 1101 and the first electrode 20 and electrically connected to the first electrode pad 1101 and the first electrode 20, the first connection structure 91 'includes a first cavity 911' and a first conductive portion 912 ', the first conductive portion 912' covers the first cavity 911 'or the first cavity 911' is embedded in the first conductive portion 912 ', and in this embodiment, the first connection structure 91' does not have an insulating portion. The connecting member 9 'includes a second connecting structure 92' located between the second electrode pad 1102 and the second electrode 30 and electrically connected to the second electrode pad 1102 and the second electrode 30, the second connecting structure 92 'includes a second conductive portion 922' and a second insulating portion 923 ', the second conductive portion 922' covers the second insulating portion 923 'or the second insulating portion 923' is embedded in the second conductive portion 922 ', and in this embodiment, the second connecting structure 92' has no void. In short, the semiconductor device 2000 of the present embodiment shows different connection members 9 ', that is, the first connection structure 91 ' includes only the first conductive portion 912 ' and the first cavity 911 ', and the second connection structure 92 ' includes only the second conductive portion 922 ' and the second insulating portion 923 '. In other embodiments, the first connecting structure of the connecting member includes only the first conductive portion and the first insulating portion covered by the first conductive portion and has no cavity, and the second connecting structure includes only the second conductive portion and the second cavity covered by the second conductive portion and has no insulating portion.

Fig. 4 is a schematic cross-sectional view of a semiconductor device 3000 according to an embodiment of the present invention. The semiconductor device 3000 includes a semiconductor device 100, a carrier 111 and a connecting member 9 ″. The semiconductor device 3000 of the present embodiment has substantially the same members and the connection relationship of the members as the semiconductor device 2000 of fig. 3, with the difference being the connection member 9 ″. The connecting member 9 "includes a first connecting structure 91" and a second connecting structure 92 ".

The first connection structure 91 "includes a first cavity 911", a first conductive portion 912 ", and a first insulating portion 913", and the first conductive portion 912 "covers the first cavity 911" and the first insulating portion 913 ", or the first cavity 911" and the first insulating portion 913 "are embedded in the first conductive portion 912". In the present embodiment, the number of the first insulating portions 913 "is several, the first cavity 911" is not covered by the first insulating portions 913 ", and the plurality of first insulating portions 913" are distributed in the first conductive portions 912 "and are not connected to each other. The second connecting structure 92 "includes a second cavity 921", a second conductive part 922 "and a second insulating part 923", and the second conductive part 922 "covers the second cavity 921" and the second insulating part 923 ", or the second cavity 921" and the second insulating part 923 "are embedded in the second conductive part 922". In the present embodiment, the number of the second insulating portions 923 "is several, one of the second insulating portions 923" covers the second cavity 921 "and is located between the second cavity 921" and the second conductive portion 922 ", and the rest of the second insulating portions 923" are scattered in the second conductive portion 922 "and are not connected to each other.

The connecting member 9 "further includes a third insulating portion 93", a fourth insulating portion 94 ", and a fifth insulating portion 95". The third insulating portion 93 ″ has a third conductive portion 932 and/or a third cavity 931 therein, and the third cavity 931 and/or the third conductive portion 932 is covered by the third insulating portion 93 ″, so that the third conductive portion 932 is not connected to the first electrode pad 1101, the second electrode pad 1102, the first electrode 20, the second electrode 30, the first conductive portion 912 ″ or the second conductive portion 922 ″ to avoid a leakage path or an electrical failure of the semiconductor device 3000. Similarly, the fourth insulating portion 94 ″ has a fourth hollow 941 and/or a fourth conductive portion 942, and the fourth hollow 941 and/or the fourth conductive portion 942 are covered by the fourth insulating portion 94 ″ so that the fourth conductive portion 942 is not connected to the first electrode pad 1101, the first electrode 20, and the first conductive portion 912 to prevent the semiconductor device 3000 from generating a leakage path or electrical failure; the fifth insulating portion 95 ″ has a fifth cavity 951 and/or a fifth conductive portion 952 therein, and the fifth cavity 951 and/or the fifth conductive portion 952 are covered by the fifth insulating portion 95 ″ so that the fifth conductive portion 952 is not connected to the second electrode pad 1102, the second electrode 30, and the second conductive portion 921, thereby preventing the semiconductor device 3000 from generating a leakage path or electrical failure.

The first semiconductor structure 11 and the second semiconductor structure 13 may have different conductivity types. For example, the first semiconductor structure 11 is n-type, and the second semiconductor structure 13 is p-type; alternatively, the first semiconductor structure 11 is p-type and the second semiconductor structure 13 is n-type. Thus, the first semiconductor structure 11 and the second semiconductor structure 13 can provide electrons and holes or holes and electrons, respectively. The first semiconductor structure 11 has a first dopant and the second semiconductor structure 13 has a second dopant, such that the first semiconductor structure 11 and the second semiconductor structure 13 have different conductivities. The first dopant and the second dopant may be carbon respectively(C) Zinc (Zn), silicon (Si), germanium (Ge), tin (Sn), selenium (Se), magnesium (Mg) or tellurium (Te). In the present embodiment, the first semiconductor structure 11 is P-type, the first dopant is magnesium (Mg) or carbon (C), the second semiconductor structure 13 is N-type, the first dopant is tellurium (Te) or silicon (Si), and the doping concentration of the first semiconductor structure 11 and the second semiconductor structure 13 is about 5 × 10 ¹⁷ /cm ³ To 1X 10 ²⁰ /cm ³ 。

The first semiconductor structure 11, the second semiconductor structure 13, and the active structure 12 may each comprise a iii-v semiconductor material. The above group III-V semiconductor material may contain Al, Ga, As, P, or In. In one embodiment, the first semiconductor structure 11, the second semiconductor structure 13, and the active structure 12 do not include N. Specifically, the iii-v semiconductor material may be a binary compound semiconductor (e.g., GaAs or GaP), a ternary compound semiconductor (e.g., InGaAs, AlGaAs, InGaP, or AlInP), or a quaternary compound semiconductor (e.g., AlGaInAs, AlGaInP, InGaAsP, InGaAsN, or AlGaAsP). In one embodiment, the first active region 13 is substantially composed of a ternary compound semiconductor (e.g., InGaAs, AlGaAs, InGaP, or AlInP) or a quaternary compound semiconductor (e.g., AlGaInAs, AlGaInP, InGaAsP, or AlGaAsP).

The semiconductor device 100 may include a Double Heterostructure (DH), a double-side double heterostructure (DDH), or a Multiple Quantum Well (MQW) structure. According to an embodiment, when the semiconductor device 100 is a light emitting device, the active structure 12 emits a light from the second semiconductor structure 13 toward the first semiconductor structure 11. The light includes visible light or invisible light. The wavelength of light emitted by the semiconductor device 100 is determined by the material of the active structure 12. The material of the active structure 12 may include Ga, As, or/and P, such As InGaAs, AlGaAsP, GaAsP, InGaAsP, AlGaAs, AlGaInAs, InGaP, or AlGaInP. For example: the active structure 12 may emit infrared light having a peak wavelength of 700 to 1700nm, red light having a peak wavelength of 610nm to 700nm, or yellow light having a peak wavelength of 530nm to 600 nm. In this embodiment, the active structure 12 emits light having a peak wavelength of 600nm to 1300 nm.

In the present embodiment, the crystal system of each layer of the epitaxial structure is cubic (cubic) and belongs to zinc blende structure. In one embodiment, no polarization (polization) is present in the layers of the epitaxial structure, i.e., the polarization vectors of the layers are substantially zero.

The substrate 50 comprises a conductive or insulating material. Conductive materials such as gallium arsenide (GaAs), indium phosphide (InP), silicon carbide (SiC), gallium phosphide (GaP), zinc oxide (ZnO), gallium nitride (GaN), aluminum nitride (AlN), germanium (Ge), or silicon (Si). An insulating material such as Sapphire (Sapphire). In the present embodiment, the base 50 is a bonding substrate, not a growth substrate, which is bonded to the epitaxial structure 10 by the bonding layer 60, as shown in fig. 1, 3 and 4.

The first electrode 2 and the second electrode 3 are electrically connected to an external power source. The materials of the first electrode 2 and the second electrode 3 may be the same or different, and each may include, for example, a metal oxide, a metal, or an alloy. The metal oxide may be, for example, Indium Tin Oxide (ITO), indium oxide (InO), tin oxide (SnO), Cadmium Tin Oxide (CTO), Antimony Tin Oxide (ATO), Aluminum Zinc Oxide (AZO), Zinc Tin Oxide (ZTO), Gallium Zinc Oxide (GZO), zinc oxide (ZnO), gallium phosphide (GaP), Indium Cerium Oxide (ICO), indium tungsten oxide (IWO), indium titanium oxide (ITiO), Indium Zinc Oxide (IZO), Indium Gallium Oxide (IGO), Gallium Aluminum Zinc Oxide (GAZO), or a combination thereof. Examples of the metal include germanium (Ge), beryllium (Be), zinc (Zn), gold (Au), platinum (Pt), titanium (Ti), aluminum (Al), nickel (Ni), tin (Sn), and copper (Cu). The alloy may include at least two selected from the group consisting of the above metals, such as gold nickel germanium (GeAuNi), gold beryllium (BeAu), gold germanium (GeAu), or gold zinc (ZnAu), etc.

The bonding layer 60 connects the substrate 50 and the epitaxial structure 10. In one embodiment, the bonding layer 60 may be a single layer or multiple layers (not shown). The material of the bonding layer 60 may comprise a transparent insulating material including, but not limited to, titanium oxide (TiO) ₂ ) Niobium oxide (Nb) ₂ O ₅ ) Silicon oxide (SiO) ₂ ) Alumina (Al) ₂ O ₃ ) Silicon nitride (SiN), BCB, and the like.

In the present embodiment, the insulating structure 40 may be a single-layer, double-layer or multi-layer structure, such as: the insulating structure 40 comprises a distributed bragg reflector structure. Furthermore, the material of the insulating structure 40 may comprise a dielectric material, such as: silicon oxide, silicon nitride, niobium oxide, titanium oxide, or a combination thereof. In one embodiment, the insulating structure 40 includes a distributed bragg reflector structure formed by overlapping a silicon oxide layer and a titanium oxide layer.

Fig. 5 is a partially enlarged cross-sectional view of the semiconductor device 100 according to an embodiment of the present invention, in which the insulating structure 40 includes a first insulating layer 401, a second insulating layer 402 on the first insulating layer 401, and a third insulating stack 403 on the second insulating layer 401, the first insulating layer 401 has a first thickness T1, the second insulating layer 402 has a second thickness T2 greater than the first thickness T1, and the adhesion between the first insulating layer 401 and the second semiconductor structure 13 is greater than the adhesion between the second insulating layer 402 and the second semiconductor structure 13, so that the insulating structure 40 and the epitaxial structure 10 can have good mechanical strength after being combined. For example, the material of the first insulating layer 401 is silicon nitride, and the material of the second insulating layer 402 is silicon oxide. The third insulation stack 403 comprises a plurality of first and second sub-layers 403a, 403b overlapping each other, the first and second sub-layers 403a, 403b being of materials having different refractive indices, and the refractive index of the first sub-layer 403a being lower than the refractive index of the second sub-layer 403b, for example: the material of the first sub-layer 403a is silicon oxide (refractive index of 1.5), and the material of the second sub-layer 403b is titanium oxide (refractive index of 2.2). The thickness of each first sublayer 403a and each second sublayer 403b is less than the first thickness T1 and the second thickness T2. In this embodiment, the thickness of the first sub-layer 403a is greater than that of the adjacent second sub-layer 403b, however, in order to improve the reflectivity of the third insulation stack 403 to the light emitted from the epitaxial structure 10, the third insulation stack 403 has a thickness inversion region 403', that is: one of the first sub-layers 403a (n-3) in the third insulating stack 403 has a thickness smaller than that of the adjacent second sub-layer 403b (n-3), the thickness inversion region 403 ' is closer to the first electrode 20, in particular, the thickness inversion region 403 ' has a first distance D1 with the second semiconductor structure 13, and the thickness inversion region 403 ' has a second distance D2 with the first electrode 20 smaller than the first distance D1.

In the present embodiment, the material of the first sub-layer 403a1 connected to the second insulating layer 402 may be the same as the material of the second insulating layer 402, such as but not limited to silicon oxide. However, the second insulating layer 402 and the first sub-layer 403a1 are formed in different manners, and the second insulating layer 402 and the first sub-layer 403a1 are formed by, for example, Plasma Enhanced Chemical Vapor Deposition (PECVD), chemical plating, sputtering, or evaporation, so that the second insulating layer 402 and the first sub-layer 403a1 may have different characteristics and composition ratios, such as different compactness, different composition ratios (e.g., Si/O), different refractive indexes, and the like. In this embodiment, the first sub-layer 403a1 has a third thickness, for example, 800A to 3000A, and the second insulating layer 402 has a second thickness T2, for example, 5000A to 12000A. In an embodiment, the compactness of the second insulating layer 402 is greater than that of the first sub-layer 403a1 or/and the silicon oxygen composition ratio of the second insulating layer 402 is less than that of the first sub-layer 403a1, for example: the second insulating layer 402 has a silicon atom content of 55 at%, an oxygen atom content of 45 at%, and a silicon oxygen composition ratio of 1.2; the first sublayer 403a1 had a silicon atom content of 45 at%, an oxygen atom content of 55 at%, and a silicon oxygen composition ratio of 0.8. By the characteristics of the second insulating layer 402 and the first sub-layer 403a1, the effects of releasing the stress of the insulating structure 40, increasing the light extraction efficiency, and improving the reliability of the semiconductor device can be achieved.

The first contact structure 70 is located between the first electrode 20 and the first portion 111, the second contact structure 80 is located between the second electrode 30 and the second semiconductor structure 13, and the first electrode 20 is in direct contact with the first contact structure 70 through the first opening 40a, and the second electrode 30 is in direct contact with the second contact structure 80 through the second opening 40 b. The first contact structure 70 and the second contact structure 80 comprise metal or alloy, and since the semiconductor device 100 of the present embodiment emits light from the substrate 50, there is no need to consider whether the first contact structure 70 and the second contact structure 80 are light-shielding, so if the first contact structure 70 and the second contact structure 80 are metal or alloy with lower resistance, the optoelectronic performance of the semiconductor device 100 will be better.

Please refer to fig. 6, which is the present inventionIn a top view of the light emitting module 4000 according to an embodiment, the light emitting module 4000 includes a plurality of semiconductor devices 100 as shown in fig. 1. In detail, the light emitting module includes a plurality of semiconductor units 1, each semiconductor unit 1 includes three semiconductor devices 100,100',100 ″ respectively emitting a first light, a second light and a third light, and the first light, the second light and the third light are mixed to form a white light, wherein the first light is, for example, a red light, the second light is, for example, a green light, and the third light is, for example, a blue light. In one embodiment of the present invention, a plurality of semiconductor devices 1 have a common carrier 210 and are arranged in a two-dimensional matrix. The light emitting module 4000 may include a reflective wall 26 disposed between adjacent semiconductor units 1, the shape of the recess surrounded by the reflective wall 26 of each semiconductor unit 1 may be circular as in the present embodiment, or may be adjusted to be square or rectangular according to display requirements, and the single recess surrounded by the reflective wall 26 has a recess area D, and the recess area is preferably between 1 mm and 20mm ² . The light-emitting module 4000 can be further applied to a display device such as a television screen, a mobile phone screen, a computer screen, a pen-type screen, a billboard, a sports board, or the like. The light-emitting module 4000 includes a plurality of semiconductor units 1 as an array of pixels, and the number, color and arrangement of the semiconductor elements in the semiconductor units 1 and the distance between the semiconductor units 1 all affect the visual characteristics of a user when viewing, for example: the display device using the semiconductor units 1 of smaller size allows the light emitting module to have a larger resolution than the large semiconductor units 1 to accommodate a larger number of semiconductor units 1 in the same unit area.

Fig. 7 is a schematic partial cross-sectional view of a sensing module 5000 according to an embodiment of the present invention, in which the sensing module 5000 includes a carrier 320, a first semiconductor device 311, and a second semiconductor device 331. The first semiconductor device 311 and/or the second semiconductor device 331 may be the semiconductor device 100 shown in fig. 1. The carrier 320 includes a first wall 321, a second wall 322, a third wall 323, a carrier plate 324, a first space 325 and a second space 326, wherein the first semiconductor device 311 is located in the first space 325 between the first wall 321 and the second wall 322, and the second semiconductor device 331 is located in the second space 326 between the second wall 322 and the third wall 323. The first semiconductor device 311 and/or the second semiconductor device 331 may be a horizontal wafer as shown in fig. 1. The first semiconductor device 311 and the second semiconductor device 331 are disposed on the carrier 324 and electrically connected to a circuit connection structure (not shown) on the carrier 324. In this embodiment, the first semiconductor device 311 is a light emitting device, the second semiconductor device 331 is a light receiving device, and the sensing module 300 can be disposed in a wearable device (e.g., a watch, a headset), wherein light emitted from the first semiconductor device 311 passes through the skin and irradiates the body cells and blood, and then the second semiconductor device 331 absorbs light scattered/reflected from the body cells and blood, so as to detect physiological signals of the human body according to changes in the reflected and scattered light, such as: heart rate, blood glucose, blood pressure, blood oxygen concentration, etc.

Particularly, the utility model discloses an epitaxial structure, semiconductor component, light emitting module, sensing module can be applied to the product in fields such as illumination, medical treatment, demonstration, communication, sensing, electrical power generating system, for example lamps and lanterns, monitor, cell-phone, panel computer, automobile-used instrument board, TV, computer, dress device (like wrist-watch, bracelet, necklace etc.), traffic sign, outdoor display, medical equipment etc..

Although the present invention has been disclosed in connection with the above embodiments, it is not intended to limit the present invention, and those skilled in the art will appreciate that various modifications and changes may be made without departing from the spirit and scope of the present invention, and therefore, the scope of the present invention should be determined by reference to the appended claims. Furthermore, the foregoing embodiments may be combined with or substituted for those described, where appropriate, without limitation to the specific embodiments described. For example, parameters related to specific components or connection relationships between specific components and other components disclosed in one embodiment can be applied to other embodiments, and all of the embodiments fall within the scope of the present invention.

Claims

1. A semiconductor device, comprising:

an epitaxial structure comprising a first semiconductor structure having a first portion and a second portion, an active structure and a second semiconductor structure located on the second portion;

a first electrode comprising a first surface on the first portion and a second surface on the second semiconductor structure, the first surface and the second surface having a height difference of 4 μm to 8 μm;

a second electrode on the second semiconductor structure; and

an insulating structure between the first electrode and the first portion.

2. The semiconductor device of claim 1, further comprising a first contact structure between the first electrode and the first portion.

3. The semiconductor device of claim 1, wherein the insulating structure has a first opening filled with the first electrode, and further comprising a first connection structure comprising a first void pair in the first opening and a first conductive portion covering the first void.

4. The semiconductor device of claim 3, wherein the first connection structure further comprises a first insulating portion between the first void and the first conductive portion.

5. The semiconductor device according to claim 4, wherein the insulating structure has a second opening filled with the second electrode, and the semiconductor device has a second connection structure including a second cavity and a second conductive portion covering the second cavity.

6. The semiconductor device according to claim 5, further comprising a second insulating portion between the first connection structure and the second connection structure.

7. The semiconductor device according to claim 1, wherein the active structure is configured to emit light having a wavelength of 600nm to 1300 nm.

8. The semiconductor device of claim 1, wherein said epitaxial structure comprises Al, Ga, As, P, or In and does not comprise N.

9. The semiconductor device of claim 1, further comprising an adhesion layer and a substrate, the adhesion layer being between the epitaxial structure and the substrate.

10. The semiconductor device of claim 9, wherein the substrate has an upper surface facing the epitaxial structure, the epitaxial structure having a lower surface facing the substrate, the upper surface having a first surface roughness, the lower surface having a second surface roughness greater than the first surface roughness.

11. The semiconductor device of claim 9, wherein the first semiconductor structure has a first length and the adhesion layer has a second length greater than the first length.

12. The semiconductor device according to claim 9, wherein the insulating structure is in direct contact with the adhesive layer.

13. The semiconductor device of claim 9, wherein the insulating structure is not in direct contact with the substrate.

14. The semiconductor device of claim 1, further comprising a second contact structure between the second electrode and the second semiconductor structure and in direct contact with the second semiconductor structure.

15. The semiconductor device of claim 14, wherein the second contact structure is a metal or a metal alloy.

16. The semiconductor device of claim 1, wherein the insulating structure comprises a distributed bragg reflector structure.

17. The semiconductor device according to claim 1, wherein the insulating structure comprises a first insulating layer and a second insulating layer between the first insulating layer and the first electrode, and wherein the first insulating layer has a first thickness and the second insulating layer has a second thickness greater than the first thickness.

18. The semiconductor device according to claim 17, wherein the insulating structure further comprises a third insulating stack, the second insulating layer being between the first insulating layer and the third insulating stack, the third insulating stack comprising a plurality of first and second sub-layers overlapping each other, the first sub-layer having a refractive index lower than that of the second sub-layer.

19. The semiconductor device of claim 18, wherein each of the first sublayers has a thickness greater than a thickness of the adjacent second sublayers, and the third insulating stack further comprises a thickness inversion region, wherein the thickness of the first sublayers in the thickness inversion region is less than the thickness of the adjacent second sublayers.

20. The semiconductor device according to claim 18, wherein a first sub-layer is connected to the second insulating layer and has the same material as the second insulating layer.

21. The semiconductor device of claim 19, wherein said one of said first sub-layers and said second insulating layer have different characteristics and composition ratios.

22. A semiconductor device, comprising:

a first electrode comprising a first surface on the first portion and a second surface on the second semiconductor structure;

a second electrode on the second semiconductor structure; and

an insulating structure between the first electrode and the first portion and comprising an insulating stack comprising a plurality of first and second sub-layers overlapping each other, the first sub-layer having a refractive index lower than that of the second sub-layer, and each first sub-layer having a thickness greater than that of the adjacent second sub-layer, the insulating stack having a thickness inversion region in which the thickness of the first sub-layer is less than that of the adjacent second sub-layer.

23. The semiconductor device of claim 22, wherein the insulating structure further comprises a first insulating layer and a second insulating layer disposed between the first insulating layer and the insulating stack, and wherein the first insulating layer has a first thickness and the second insulating layer has a second thickness greater than the first thickness.

24. The semiconductor device according to claim 22, wherein a first sub-layer is connected to the second insulating layer and has the same material as the second insulating layer.

25. The semiconductor device of claim 24, wherein said one of said first sub-layers and said second insulating layer have different characteristics and composition ratios.