CN217740551U - Semiconductor device with a plurality of transistors - Google Patents
Semiconductor device with a plurality of transistors Download PDFInfo
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- CN217740551U CN217740551U CN202123062555.3U CN202123062555U CN217740551U CN 217740551 U CN217740551 U CN 217740551U CN 202123062555 U CN202123062555 U CN 202123062555U CN 217740551 U CN217740551 U CN 217740551U
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Abstract
The utility model discloses a semiconductor element, it includes that an epitaxial structure has a first epitaxial stromatolite. The first epitaxial stack has a first semiconductor structure, a second semiconductor structure on the first semiconductor structure, a first active region between the first and second semiconductor structures, a first confinement layer between the first active region and the first semiconductor structure, and a second confinement layer between the first active region and the second semiconductor structure. The first confining layer has a first thickness and the second confining layer has a second thickness greater than the first thickness.
Description
Technical Field
The present invention relates to semiconductor devices, and more particularly to semiconductor light emitting devices, such as light emitting diodes.
Background
The applications of semiconductor devices are very wide, and research and development of related materials are continuously carried out. For example, III-V semiconductor materials containing group III and group V elements can be applied to various optoelectronic semiconductor devices such as Light Emitting Diodes (LEDs), laser Diodes (LDs), photodetectors or Solar cells (Solar cells), or can be power devices such as switches or rectifiers, and can be used in the fields of illumination, medical treatment, display, communication, sensing, power supply systems, and the like. A light emitting diode, which is one of semiconductor light emitting elements, has advantages such as low power consumption and long life, and is therefore widely used.
SUMMERY OF THE UTILITY MODEL
An object of the utility model is to provide a semiconductor component to solve the problem that prior art exists.
To achieve the above objects, the present invention provides a semiconductor device including an epitaxial structure having a first epitaxial stack. The first epitaxial stack has a first semiconductor structure, a second semiconductor structure on the first semiconductor structure, a first active region between the first and second semiconductor structures, a first confinement layer between the first active region and the first semiconductor structure, and a second confinement layer between the first active region and the second semiconductor structure. The second semiconductor structure and the first semiconductor structure have different conductive types. The first confinement layer is directly contiguous with the first active region and has a first thickness, and the second confinement layer is directly contiguous with the first active region and has a second thickness greater than the first thickness.
The first active region includes a first well layer, a first barrier layer, a second well layer and a second barrier layer sequentially stacked on the first confinement layer, the first well layer is closer to the first confinement layer than the second well layer, and the thickness of the second well layer is greater than that of the first well layer.
The first active region further includes a third well layer on the second barrier layer, and the third well layer has a thickness greater than that of the second well layer.
The light emitted by the semiconductor device is infrared light.
The epitaxial structure further includes a second epitaxial stack on the first epitaxial stack, the second epitaxial stack having a third confinement layer, a fourth confinement layer, and a second active region between the third confinement layer and the fourth confinement layer, wherein the third confinement layer is closer to the first confinement layer than the fourth confinement layer, the third confinement layer has a third thickness, and the fourth confinement layer has a fourth thickness greater than the third thickness.
The first thickness is the same as the third thickness.
The second thickness is the same as the fourth thickness.
The first confinement layer is directly connected to the first semiconductor structure, and the second confinement layer is directly connected to the second semiconductor structure.
The first semiconductor structure is p-type and the second semiconductor structure is n-type.
The energy gap of the first semiconductor structure is larger than that of the first confinement layer.
The semiconductor device further includes a bonding structure and a substrate, the bonding structure being located between the first epitaxial stack and the substrate.
The first semiconductor structure is closer to the bonding structure than the second semiconductor structure.
The semiconductor element further comprises an intermediate layer located between the first epitaxial stack and the second epitaxial stack, the intermediate layer comprising a pn-junction.
The pn junction is formed by a first heavily doped layer having a first conductivity and a second heavily doped layer having a second conductivity.
The first confinement layer and the second confinement layer do not contain dopants.
The semiconductor element also comprises a conductive layer, a reflecting layer and a plurality of insulating parts, wherein the conductive layer is positioned between the first epitaxial lamination layer and the reflecting layer, the insulating parts are positioned between the first epitaxial lamination layer and the conductive layer, a plurality of pores are arranged among the insulating parts, and the conductive layer is filled into the pores and contacts the first epitaxial lamination layer.
The first epitaxial stack further includes a plurality of contacts between the first semiconductor structure and the conductive layer.
The semiconductor element also comprises a first electrode and a second electrode which are respectively positioned at the upper side and the lower side of the first epitaxial lamination, the first electrode is connected with the second semiconductor structure, and the second electrode is connected with one side of the substrate far away from the first semiconductor structure.
The first thickness is in the range of 150nm to 400nm, and the second thickness is in the range of 300nm to 650nm.
The first thickness is less than the thickness of the first semiconductor structure, and the second thickness is less than the thickness of the second semiconductor structure.
The first active region further includes a third well layer and a third barrier layer, the first thickness and the second thickness being greater than thicknesses of the first well layer, the first barrier layer, the second well layer, the second barrier layer, the third well layer, and the third barrier layer.
The second epitaxial stack further includes a third semiconductor structure located between the third confinement layer and the first epitaxial stack and a fourth semiconductor structure located on the fourth confinement layer and having a different conductivity type than the third semiconductor structure.
The third semiconductor structure and the first semiconductor structure have the same conductivity type.
The second active region and the first active region have a peak wavelength of 730nm to 1100nm.
The third thickness is in a range of 150nm to 400nm, and the fourth thickness is in a range of 300nm to 650nm.
The utility model has the advantages that it makes it have better photoelectric representation through the design to semiconductor element, for example: the light-emitting intensity is increased, the forward voltage (Vf) is reduced, and the like, and the light-emitting diode can be applied to products in the fields of illumination, medical treatment, display, communication, sensing, power systems and the like, such as lamps, monitors, mobile phones, tablet computers, automobile instrument panels, televisions, computers, wearable devices (such as watches, bracelets, necklaces and the like), traffic signs, outdoor displays, medical equipment and the like.
Drawings
Fig. 1 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention;
fig. 2 is a schematic view of an epitaxial structure of a semiconductor device according to another embodiment of the present invention;
fig. 3 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention;
fig. 4 is a schematic partial sectional view of a sensing module according to an embodiment of the present invention.
Description of the symbols
100. Semiconductor device with a plurality of semiconductor chips
1. First epitaxial stack
11. First semiconductor structure
111. Contact part
12. Second semiconductor structure
13. First active region
131. First well layer
132. The first barrier layer
133. Second well layer
134. The second barrier layer
135. Third well layer
136. The third barrier layer
14. First confinement layer
15. Second confinement layer
2. A first electrode
21. Electrode pad
22. Extension electrode
3. Second electrode
4. Conductive layer
5. Reflective layer
6. Joint structure
7. Substrate
8. Insulating part
8a pore space
81. Intermediate layer
811. First heavily doped layer
812. Second heavily doped layer
9. Second epitaxial stack
91. Third semiconductor structure
92. Fourth semiconductor structure
93. Second active region
931. Fourth well layer
932. The fourth barrier layer
933. Fifth well layer
934. The fifth barrier layer
935. Sixth well layer
936. The sixth barrier layer
94. Third confinement layer
95. A fourth confinement layer
T1 first thickness
T2 second thickness
T3 third thickness
T4 fourth thickness
300. Semiconductor assembly
31. Package substrate
32. Through-hole
33. Carrier
33a first part
33b second part
35. Bonding wire
36. Contact structure
36a first contact pad
36b second contact pad
38. Encapsulation layer
400. Sensing module
420. Riding carrier
411. First semiconductor element
431. Second semiconductor element
421. First retaining wall
422. Second retaining wall
423. Third retaining wall
424. Support plate
425. The first space
426. Second space
Detailed Description
The following embodiments will explain the concept of the present invention along with the accompanying drawings, in which similar or identical members will be explained using similar or identical reference numerals, and the shapes or sizes of the respective elements in the drawings are merely illustrative and not limited thereto if not specifically explained. It is noted that elements not shown or described in the figures may be of a type known to those skilled in the art.
Unless otherwise specified, the general formula InGaP represents In x0 Ga 1-x0 P is 0 in<x0<1; the general formula AlInP represents Al x1 In 1-x1 P, wherein 0<x1<1; al in the general formula AlGaInP x2 Ga x3 In 1-x2-x3 P, wherein 0<x2<1 and 0<x3<1; the formula InGaAsP represents In x4 Ga 1-x4 As x5 P 1-x5 Wherein 0 is<x4<1， 0<x5<1; the general formula AlGaInAs represents Al x6 Ga x7 In 1-x6- x7 As, wherein 0<x6<1，0<x7<1; the general formula InGaNAs represents In x8 Ga 1-x8 N x9 As 1-x9 Wherein 0 is<x8<1，0<x9<1; the general formula InGaAs represents In x10 Ga 1-x10 As, wherein 0<x10<1; of the formula AlGaAs for Al x11 Ga 1-x11 As, of which 0<x11<1. The content of each element can be adjusted for different purposes, such as but not limited to adjusting the size of the energy gap, or when the semiconductor device is a light emitting device, the dominant wavelength (domain wavelength) or peak wavelength (peak wavelength) of the light emitting device can be adjusted accordingly.
The semiconductor element of the present invention is, for example, a light emitting element (e.g., a light emitting diode (light-emitting diode), a laser diode (laser diode)), a light absorbing element (e.g., a photo-detector), or a non-light emitting element. The semiconductor device of the present invention can be obtained by analyzing the composition and dopant (dopant) of each layer in any suitable manner, such as Secondary Ion Mass Spectrometer (SIMS), and the thickness of each layer can be obtained by analyzing in any suitable manner, such as Transmission Electron Microscope (TEM) or Scanning Electron Microscope (SEM).
It should be understood by those of ordinary skill in the art that other components may be added on the basis of the embodiments described below. For example, unless specifically stated otherwise, a similar description of a first layer (or structure) being on a second layer (or structure) may include embodiments in which the first layer (or structure) is in direct contact with the second layer (or structure), and may also include embodiments in which there are other structures between the first layer (or structure) and the second layer (or structure) that are not in direct contact with each other. In addition, it is to be understood that the upper and lower positional relationship of the layers (or structures), etc. may be changed as viewed from different orientations.
In addition, in the present invention, the description of a layer or structure "consisting essentially of M" means that the layer or structure has a main composition of M, but does not exclude that the layer or structure contains dopants or unavoidable impurities (impurities).
Fig. 1 is a schematic cross-sectional view of a semiconductor device 100 according to an embodiment of the present invention. The semiconductor device 100 comprises an epitaxial structure comprising a first epitaxial stack 1. The semiconductor device 100 further includes a first electrode 2 and a second electrode 3 respectively disposed on the upper and lower sides of the first epitaxial stack 1, a conductive layer 4, a reflective layer 5, a bonding structure 6 and a substrate 7. The conductive layer 4 is located between the first epitaxial stack 1 and the reflective layer 5, and the bonding structure 6 is located between the substrate 7 and the reflective layer 5. The semiconductor device 100 optionally comprises a plurality of insulating portions 8 between the conductive layer 4 and the first epitaxial stack 1. The first electrode 2 may include an electrode pad 21 and an extension electrode 22 connected to the electrode pad 21. In one embodiment, the first electrode 2 comprises only the electrode pad and no extension electrode.
The first epitaxial stack 1 includes a first semiconductor structure 11, a second semiconductor structure 12, a first active region 13 between the first semiconductor structure 11 and the second semiconductor structure 12, a first confinement layer 14 between the first active region 13 and the first semiconductor structure 11, and a second confinement layer 15 between the first active region 13 and the second semiconductor structure 12. The first semiconductor structure 11 and the second semiconductor structure 12 may have different conductivity types. For example, the first semiconductor structure 11 is n-type, and the second semiconductor structure 12 is p-type; alternatively, the first semiconductor structure 11 is p-type and the second semiconductor structure 12 is n-type. Thus, the first semiconductor structure 11 and the second semiconductor structure 12 can provide electrons and holes or holes and electrons, respectively. The first semiconductor structure 11 has a first dopant, the second semiconductor structure 12 has a second dopant to make the first semiconductor structure 11 and the second semiconductor structure 12 have different conductivities. The first dopant and the second dopant may be carbon (C), zinc (Zn), silicon (Si), germanium (Ge), tin (Sn), selenium (Se), magnesium (Mg), or tellurium (Te), respectively. In the present embodiment, the second semiconductor structure 12 is of N-type, the first dopant is tellurium (Te) or silicon (Si), the first semiconductor structure 11 is of P-type, the first dopant is magnesium (Mg) or carbon (C), and the doping concentrations of the first semiconductor structure 11 and the second semiconductor structure 12 are about 5 × 10 17 /cm 3 To 1X 10 20 /cm 3 . The energy gaps of the first and second semiconductor structures 11 and 12 are larger than the first and second confinement layers 14 and 15, respectively, thereby further confining carriers in the first active region 13.
From the cross-sectional view of the semiconductor device, the first epitaxial stack 1 may optionally include a plurality of contacts 111 remote from the first active region 13 and proximate to the conductive layer 4. The plurality of contacts 111 have a first dopant, and the first dopant concentration in the plurality of contacts 111 is greater than the first dopant concentration of the first semiconductor structure 11. In the present embodiment, the contact portion 111 is not provided below the electrode pad 21, that is, the electrode pad 21 and the contact portion 111 are offset from each other. In other embodiments, the plurality of contact portions 111, the electrode pads 21 and the extension electrodes 22 may be offset from each other. Due to the above-mentioned offset relationship between the first electrode 2 and the contact portion 111, the current can be prevented from being directly conducted from the lower side of the first electrode 2, thereby increasing the current distribution and further improving the luminance of the semiconductor device 100. The material of the plurality of contacts 111 may comprise a group III-V semiconductor material, such as a binary group III-V semiconductor material, e.g., gaAs, gaP, gaN, etc.
The first semiconductor structure 11, the second semiconductor structure 12, the first active region 13, the first confinement layer 14, and the second confinement layer 15 may each comprise a group iii-v semiconductor material. The iii-v semiconductor material may include Al, ga, as, P, or In. In one embodiment, the first semiconductor structure 11, the second semiconductor structure 12, the first active region 13, the first confinement layer 14, and the second confinement layer 15 do not contain N. Specifically, the iii-v semiconductor material may be a binary compound semiconductor (e.g., gaAs or GaP), a ternary compound semiconductor (e.g., inGaAs, alGaAs, inGaP, or AlInP), or a quaternary compound semiconductor (e.g., alGaInAs, alGaInP, inGaAsP, inGaAsN, or AlGaAsP). In one embodiment, the first active region 13 is substantially composed of a ternary compound semiconductor (e.g., inGaAs, alGaAs, inGaP, or AlInP) or a quaternary compound semiconductor (e.g., alGaInAs, alGaInP, inGaAsP, or AlGaAsP).
The semiconductor device 100 may include a Double Heterostructure (DH), a double-side double heterostructure (DDH), or a Multiple Quantum Well (MQW) structure. According to an embodiment, when the semiconductor device 100 is a light emitting device, the first active region 13 can emit a light from the first semiconductor structure 11 toward the second semiconductor structure 12. The light includes visible light or invisible light. The wavelength of light emitted by the semiconductor device 100 is determined by the material of the first active region 13. The material of the first active region 13 may include InGaAs, alGaAsP, gaAsP, inGaAsP, alGaAs, alGaInAs, inGaP, or AlGaInP. For example: the first active region 13 may emit infrared light having a peak wavelength of 700 to 1700nm, red light having a peak wavelength of 610 to 700nm, or yellow light having a peak wavelength of 530 to 600 nm. In the present embodiment, the first active region 13 emits infrared light having a peak wavelength of 730nm to 1100nm.
In the present embodiment, the crystal system of each layer of the epitaxial structure is cubic (cubic) and belongs to zinc blende structure. In one embodiment, no polarization (polization) is present in the layers of the epitaxial structure, i.e., the polarization vectors of the layers are about zero.
Referring to fig. 1, the first active region 13 is located between the first confinement layer 14 and the second confinement layer 15, and in the embodiment, the first active region 13 is directly connected to the first confinement layer 14, and the first active region 13 is directly connected to the second confinement layer 15. The first active region 13 includes a first well layer 131, a first barrier layer 132, a second well layer 133 and a second barrier layer 134 sequentially stacked on the first confinement layer 14, and the first well layer 131 is closer to the first confinement layer 14 than the second well layer 133. The first active region 13 may further include a third well layer 135 and a third barrier layer 136 sequentially stacked on the second barrier layer 134, and the second well layer 133 is closer to the first local area layer 14 than the third well layer 135. The first well layer 131, the second well layer 133, and the third well layer 135 contain indium (In), and the indium composition ratio In the first well layer 131 is smaller than that In the second well layer 133, and the indium composition ratio In the second well layer 133 is smaller than that In the third well layer 135. When the first active region 13 has a plurality of well layers and barrier layers overlapping each other, the indium composition ratio of the well layers in the first active region 13 increases from the first confinement layer 14 toward the second confinement layer 15. In one embodiment, the difference in the indium composition ratio between the first well layer 131 and the second well layer 133 is 0.1% to 0.3%, the difference in the indium composition ratio between the second well layer 133 and the third well layer 135 is 0.1% to 0.3%, and the difference in the indium composition ratio between the first well layer 131 and the third well layer 133 is 0.2% to 0.6%.
In another embodiment, the first active structure 13 has a plurality of well layers (131, 133, 135) with the indium composition ratio gradually increasing from the first confining layer 14 to the second confining layer 15, and a plurality of well layers with a constant indium composition ratio are further provided on the third well layer 135. That is, the plurality of well layers have a constant indium composition ratio in the direction from the first confinement layer 14 to the second confinement layer 15, and the constant indium composition ratio is larger than the indium composition ratio of the third well layer 135. In another embodiment, the fixed indium composition ratio is smaller than the indium composition ratio of the third well layer 135.
In one embodiment, the first confining layer 14, the second confining layer 15 and the barrier layer (132, 134, 136) may have the same or different energy gaps. The first confinement layer 14, the second confinement layer 15, and the barrier layer (132, 134, 136) may be the same or different materials. The energy gap of the first confinement layer 14 and the second confinement layer 15 is larger than that of the well layer (131, 133, 135), and also helps carriers to be confined in the first active region 13.
In this embodiment, the material of the first well layer 131 and the second well layer 133 is InGaAs, and the material of the second barrier layer 132 and the second barrier layer 134 is AlGaAs. In other embodiments, the material of the first well layer 131 and the second well layer 133 is InGaAs, and the material of the second barrier layer 132 and the second barrier layer 134 is AlGaAsP; in another embodiment, the material of the first well layer 131 and the second well layer 133 is InGaAs, and the material of the second barrier layer 132 and the second barrier layer 134 is GaAsP. In the first active region 13 of the semiconductor device 100 of this embodiment, the well layers (131, 133, 135) have a thickness smaller than that of the barrier layers (132, 134, 136). The well layer and/or the barrier layer may or may not include dopants.
In another embodiment, the thickness of the first well layer 131 is less than that of the second well layer 133, and the thickness of the second well layer 133 is less than that of the third well layer 135. When the first active region 13 has a plurality of well layers and barrier layers overlapping each other, the thickness of the well layers in the first active region 13 increases from the first confinement layer 14 toward the second confinement layer 15. By designing the indium composition ratio and/or the thickness of the first well layer 131 and the second well layer 133, the semiconductor device 100 can have better photoelectric performance, for example: an increase in light emission intensity, a decrease in forward voltage (Vf), and the like.
When the semiconductor device is a light emitting device and is driven, the original peak (first signal) is shifted to a longer wavelength, or a longer second signal appears at the right side of the original peak. The design of the indium composition ratio and/or thickness of the first well layer 131 and the second well layer 133 is also helpful to prevent the optoelectronic semiconductor device from generating unexpected spectral variation, and achieve the effect of maintaining the stability of the light emitting wavelength of the semiconductor device under different current driving.
The first confinement layer 14 and the second confinement layer 15 are used to prevent overflow of carriers in the first active region 13. In an embodiment of the present invention, the first confinement layer 14 has a first thickness T1, and the second confinement layer 15 has a second thickness T2 greater than the first thickness T1, so as to prevent the second dopant in the second semiconductor structure 12 from entering the first active region 13 and affecting the light emitting characteristics of the semiconductor device 100. In the embodiment, the first thickness T1 is, for example, 150nm to 400nm, and the second thickness T2 is, for example, 300nm to 650nm. In one embodiment, T2/T1 is greater than 2. The thicker second confinement layer 15 effectively blocks the second dopants in the second semiconductor structure 12 from entering the first active region 13, thereby reducing the dopant concentration of the second dopants in the first active region 13. In other words, the first active region 13 may have the second dopant and the dopant concentrationDegree of less than 1X 10 16 /cm 3 . By the design manner in which the second thickness T2 is greater than the first thickness T1, the semiconductor device 100 can have better photoelectric performance, for example: an increase in light emission intensity, a decrease in forward voltage (Vf), and the like. In addition, the thinner first confinement layer 14 also facilitates carriers entering the first active region 13, thereby improving the photoelectric performance of the semiconductor device 100. In this embodiment, the first confinement layer 14 is directly connected to the first semiconductor structure 11, and the second confinement layer 15 is directly connected to the second semiconductor structure 12.
In one embodiment, the first confinement layer 14 and the second confinement layer 15 may or may not include dopants. The dopants may be intentionally doped or unintentionally doped. When the dopants in the first confinement layer 14 and the second confinement layer 15 are unintentionally doped, the dopants enter the first confinement layer 14 and the second confinement layer 15 during the epitaxy process, and the concentration of the unintentionally doped dopants is substantially (e.g., 1 to 2 orders of magnitude) less than the concentration of the dopants in the first semiconductor structure 11 and the second semiconductor structure 12, and in one embodiment, the concentration of the intentionally doped dopants or the unintentionally doped dopants existing in the first confinement layer 14 and the second confinement layer 15 is less than 1 × 10 17 /cm 3 . The first thickness T1 and the second thickness T2 are respectively smaller than the thickness of the first semiconductor structure 11 and the thickness of the second semiconductor structure 13, and the first thickness T1 and the second thickness T2 of the present embodiment are both larger than the thicknesses of the barrier layer (132, 134, 136) and the well layer (131, 133, 135) in the first active region 13.
The substrate 7 comprises a conductive or insulating material. Conductive materials such as gallium arsenide (GaAs), indium phosphide (InP), silicon carbide (SiC), gallium phosphide (GaP), zinc oxide (ZnO), gallium nitride (GaN), aluminum nitride (AlN), germanium (Ge), or silicon (Si). An insulating material such as Sapphire (Sapphire). In other embodiments, the base 7 is a growth substrate, i.e., the first epitaxial stack 1 may be epitaxially formed on the base 7 by, for example, metal Organic Chemical Vapor Deposition (MOCVD). In one embodiment, the base 7 is a bonding substrate, rather than a growth substrate, that may be bonded to the first epitaxial stack 1 by the bonding structure 6, as shown in fig. 1.
The first electrode 2 and the second electrode 3 are used for electrical connection with an external power supply. The materials of the first electrode 2 and the second electrode 3 may be the same or different, and for example, each includes a metal oxide material, a metal, or an alloy. The metal oxide material includes Indium Tin Oxide (ITO), indium oxide (InO), tin oxide (SnO), cadmium Tin Oxide (CTO), antimony Tin Oxide (ATO), aluminum Zinc Oxide (AZO), zinc Tin Oxide (ZTO), gallium Zinc Oxide (GZO), indium tungsten oxide (IWO), zinc oxide (ZnO), indium Zinc Oxide (IZO), or the like. Examples of the metal include germanium (Ge), beryllium (Be), zinc (Zn), gold (Au), platinum (Pt), titanium (Ti), aluminum (Al), nickel (Ni), and copper (Cu). The alloy may include at least two selected from the group consisting of the above metals, such as germanium gold nickel (GeAuNi), beryllium gold (BeAu), germanium gold (GeAu), or zinc gold (ZnAu), etc.
The insulating portion 8 comprises an insulating material having a refractive index (refractive index) of less than 2, such as silicon nitride (SiN) x ) Aluminum oxide (AlO) x ) Silicon oxide (SiO) x ) Magnesium fluoride (MgF) x ) Or a combination thereof. As shown in fig. 1, a plurality of apertures 8a are formed between the plurality of insulation portions 8, the conductive layer 4 may cover the plurality of insulation portions 8 and fill the apertures 8a, and the conductive layer 4 and the first epitaxial stack 1 may form a contact region at the apertures 8 a. Thereby, the conductive layer 4 may be electrically connected to the first epitaxial stack 1. The conductive layer 4 may comprise a metal oxide material, for example: indium Tin Oxide (ITO), indium oxide (InO), tin oxide (SnO), cadmium Tin Oxide (CTO), antimony Tin Oxide (ATO), aluminum Zinc Oxide (AZO), zinc Tin Oxide (ZTO), gallium Zinc Oxide (GZO), indium tungsten oxide (IWO), zinc oxide (ZnO), indium Zinc Oxide (IZO), or combinations thereof.
The reflective layer 5 can reflect the light emitted from the first active region 13 to exit the semiconductor device 100 toward the first electrode 2. The reflective layer 5 may comprise a semiconductor material, a metal or an alloy. The semiconductor material may comprise a group iii-v semiconductor material, such as a binary, ternary, or quaternary group iii-v semiconductor material. Metals include, but are not limited to, copper (Cu), aluminum (Al), tin (Sn), gold (Au), or silver (Ag), etc. The alloy may include at least two selected from the group consisting of the above metals. In one embodiment, the reflective layer 5 may comprise a Distributed Bragg Reflector (DBR) structure. The bragg reflector structure may be formed by alternately stacking two or more semiconductor materials having different refractive indices, for example, alAs/GaAs, alGaAs/GaAs, or InGaP/GaAs.
The bonding structure 6 connects the substrate 7 and the reflective layer 5. In one embodiment, the bonding structure 6 may be a single layer or multiple layers (not shown). The material of the bonding structure 6 may comprise a transparent conductive material, a metal or an alloy. The transparent conductive material includes, but is not limited to, indium Tin Oxide (ITO), indium oxide (InO), tin oxide (SnO), cadmium Tin Oxide (CTO), antimony Tin Oxide (ATO), aluminum Zinc Oxide (AZO), zinc Tin Oxide (ZTO), gallium Zinc Oxide (GZO), zinc oxide (ZnO), gallium phosphide (GaP), indium Cerium Oxide (ICO), indium tungsten oxide (IWO), indium titanium oxide (ITiO), indium Zinc Oxide (IZO), indium Gallium Oxide (IGO), gallium Aluminum Zinc Oxide (GAZO), graphene (graphene), or a combination thereof. Metals include, but are not limited to, copper (Cu), aluminum (Al), tin (Sn), gold (Au), silver (Ag), titanium (Ti), nickel (Ni), platinum (Pt), tungsten (W), or the like. The alloy may include at least two selected from the group consisting of the above metals.
Fig. 2 is a schematic view of an epitaxial structure of a semiconductor device according to another embodiment of the present invention. In the present embodiment, the epitaxial structure further includes a second epitaxial stack 9 on the first epitaxial stack 1 in addition to the first epitaxial stack 1, and an interlayer 81 is disposed between the first epitaxial stack 1 and the second epitaxial stack 9. The second epitaxial stack 9 includes a third semiconductor structure 91, a fourth semiconductor structure 92, a second active region 93 between the third semiconductor structure 91 and the fourth semiconductor structure 92, a third confinement layer 94 between the second active region 93 and the third semiconductor structure 91, and a fourth confinement layer 95 between the second active region 93 and the fourth semiconductor structure 92, wherein the third confinement layer 94 is closer to the first confinement layer 14 than the fourth confinement layer 95. The third semiconductor structure 91 and the fourth semiconductor structure 92 may have different conductive types. For example, the third semiconductor structure 91 is n-type, and the fourth semiconductor structure 92 is p-type; alternatively, the third semiconductor structure 91 is p-type and the fourth semiconductor structure 92 is n-type. Thus, the third semiconductor structure 91 and the fourth semiconductor structure 92 can provide electrons and holes, respectively, the third semiconductor structure 91 has a third dopant, and the fourth semiconductor structure 92 has a fourth dopant, so that they have different conductivities. The third dopant may be the same as or different from the first dopant, and the fourth dopant may be the same as or different from the second dopant. The material of the third dopant and the fourth dopant may be selected with reference to the material of the first dopant and the material of the second dopant.
In the present embodiment, the third semiconductor structure 91 has a conductivity type opposite to that of the second semiconductor structure 12, and has the same conductivity type as that of the first semiconductor structure 11. The interlayer 81 disposed between the third semiconductor structure 91 and the second semiconductor structure 12 is used to tunnel carriers between the first semiconductor stack 1 and the second semiconductor stack 9. In detail, the interlayer 81 includes a pn junction formed by a first heavily doped layer 811 (e.g., a semiconductor layer of n-type conductivity) having a first conductivity and a second heavily doped layer 812 (e.g., a semiconductor layer of p-type conductivity) having a second conductivity. The first and second heavily doped layers 811 and 812 have a doping concentration at least an order of magnitude (order) higher than that of the second and third semiconductor structures 12 and 91, e.g., greater than 1 × 10 18 /cm 3 To provide a low resistance electrical junction during operation.
The second active region 93 has similar structure, material composition and emission wavelength to the first active region 13, for example: the second active region 93 and the first active region 13 both emit infrared light having a peak wavelength of 730nm to 1100nm. In detail, the second active region 93 includes a fourth well layer 931, a fourth barrier layer 932, a fifth well layer 933, and a fifth barrier layer 934 sequentially stacked on the third confining layer 94, and the fourth well layer 931 is closer to the third confining layer 94 than the fifth well layer 933. The second active region 93 may further include a sixth well layer 935 and a sixth barrier layer 936 sequentially stacked on the fifth barrier layer 934, the fifth well layer 933 being closer to the third confining layer 94 than the sixth well layer 935. The fourth, fifth, and sixth well layers 931, 933, and 935 include indium (In), and the indium composition ratio In the fourth well layer 931 is smaller than that In the fifth well layer 933, and the indium composition ratio In the fifth well layer 933 is smaller than that In the sixth well layer 935. When the second active region 93 has a plurality of well layers and barrier layers overlapping each other, the indium composition ratio of the well layers in the second active region 93 increases from the third confining layer 94 toward the fourth confining layer 95. In another embodiment, the thickness of the fourth well layer 931 is less than the thickness of the fifth well layer 933, and the thickness of the fifth well layer 933 is less than the thickness of the sixth well layer 935. When the second active region 93 has a plurality of well layers and barrier layers overlapping each other, the thickness of the well layers in the second active region 93 increases from the third confining layer 94 toward the fourth confining layer 95. As described above, the semiconductor device can have a better photoelectric performance by designing the indium composition ratio and/or the thickness of the well layer.
The third confinement layer 94 and the fourth confinement layer 95 are used to prevent overflow of carriers in the second active region 93. The third confinement layer 94 has a third thickness T3, and the fourth confinement layer 95 has a fourth thickness T4 greater than the third thickness T3, so as to prevent the fourth dopants in the fourth semiconductor structure 92 from entering the second active region 93 and affecting the light emitting characteristics of the semiconductor device. In the present embodiment, the third thickness T3 is, for example, 150nm to 400nm, and the fourth thickness T4 is, for example, 300nm to 650nm. In one embodiment, T4/T3 is greater than 2, the third thickness T3 is substantially equal to the first thickness T1, and the fourth thickness T4 is substantially equal to the second thickness T2. In another embodiment, T3> T1, T4> T2, and T2> T1, T4> T3; in yet another embodiment, T3< T1, T4< T2, and T2> T1, T4> T3.
The thickness of the confinement layers 14, 15, 94, 95 (i.e. the second thickness T2 is greater than the first thickness T1 and/or the fourth thickness T4 is greater than the third thickness T3), the indium composition ratio of the well layers in the first active region 13 and/or the second active region 93 (i.e. the indium composition ratio of the well layers increases from the first confinement layer 14 to the second confinement layer 15 and/or from the third confinement layer 94 to the fourth confinement layer 95), and the thickness of the well layers in the first active region 13 and/or the second active region 93 (i.e. the thickness of the well layers increases from the first confinement layer 14 to the second confinement layer 15 and/or from the third confinement layer 94 to the fourth confinement layer 95), if the dopant concentration of the first semiconductor structure 11 and/or the second semiconductor structure 12 is increased to 8 × 10 17 ～5×10 18 /cm 3 And/or aluminum of the first semiconductor structure 11 and/or the second semiconductor structure 12The epitaxial structure with the content of 25% -50% is helpful for increasing the carrier concentration and/or enhancing the current dispersion effect, thereby achieving the effect of improving the luminous intensity of the semiconductor element 100. The above-described epitaxial structure features are particularly suitable for semiconductor devices operating at high current densities, e.g., current densities of 0.5A/mm 2 To 2A/mm 2 The semiconductor device of (1). The current density is the quotient of the current value applied to the semiconductor element 100 during operation and the surface area of the substrate 7. For example: the current value applied to the semiconductor element during operation was 100mA, and the substrate area of the semiconductor element was 0.125mm 2 Then the current density is 0.8A/mm 2 . The aluminum content refers to the atomic percentage of aluminum, for example, when the material of the first semiconductor structure 11 and/or the second semiconductor structure 12 is AlGaAs and the aluminum content is 25%, the material composition thereof is Al 0.25 Ga 0.75 As。
For example, in one embodiment, the semiconductor device is a light emitting device and has a first thickness T1 smaller than a second thickness T2, if the first semiconductor structure 11 is further doped with a dopant concentration of 8 × 10 17 ～5×10 18 /cm 3 Compared with a light-emitting device without the epitaxial structure, the epitaxial structure is operated at a current density of 1.7A/mm 2 In this case, the light-emitting element of the present embodiment can increase the light-emitting intensity by 2.8%. In another embodiment, the semiconductor device is a light emitting device and has a first thickness T1 less than a second thickness T2, and if the light emitting device is further combined with an epitaxial structure with an al content of 25% to 50% of the first semiconductor structure 11, the light emitting device can be operated at a current density of 1.7A/mm when compared with a light emitting device without the epitaxial structure 2 In this case, the light-emitting device of the present embodiment can increase the light-emitting intensity by 6.1%.
Fig. 3 is a schematic cross-sectional view of a semiconductor device 300 according to an embodiment of the present invention. Referring to fig. 3, a semiconductor device 300 includes a semiconductor device 100, a package substrate 31, a carrier 33, a bonding wire 35, a contact structure 36, and an encapsulation layer 38. The package substrate 31 may include a ceramic or glass material. The package substrate 31 has a plurality of through holes 32 therein. The vias 32 may be filled with a conductive material, such as a metal, to facilitate electrical conduction and/or heat dissipation. The carrier 33 is located on a surface of one side of the package substrate 31, and also includes a conductive material such as a metal. The contact structure 36 is located on the surface of the other side of the package substrate 31. In the present embodiment, the contact structure 36 includes a first contact pad 36a and a second contact pad 36b, and the first contact pad 36a and the second contact pad 36b can be electrically connected to the carrier 33 through the through hole 32. In one embodiment, the contact structure 36 may further include a thermal pad (not shown), for example, located between the first contact pad 36a and the second contact pad 36 b.
The semiconductor component 100 is located on a carrier 33. In the present embodiment, the carrier 33 includes a first portion 33a and a second portion 33b, and the semiconductor element 100 is electrically connected to the second portion 33b of the carrier 33 by a bonding wire 35. The material of the bonding wire 35 may include a metal, such as gold, silver, copper, aluminum, or an alloy containing at least one of the foregoing elements. The encapsulation layer 38 covers the semiconductor device 100, and has an effect of protecting the semiconductor device 100. Specifically, the encapsulation layer 38 may include a resin material such as epoxy resin (epoxy), silicone resin (silicone), or the like. Optionally, the encapsulating layer 38 may include a plurality of wavelength conversion particles (not shown) for converting the first light emitted from the semiconductor device 100 into a second light. The second light has a wavelength greater than the wavelength of the first light.
Fig. 4 is a schematic partial cross-sectional view of a sensing module 400 according to an embodiment of the present invention, in which the sensing module 400 includes a carrier 420, a first semiconductor element 411 and a second semiconductor element 431. The first semiconductor element 411 and/or the second semiconductor element 431 may be the semiconductor elements described above. The carrier 420 includes a first wall 421, a second wall 422, a third wall 423, a carrier 424, a first space 425 and a second space 426, wherein the first semiconductor element 411 is located in the space 425 between the first wall 421 and the second wall 422, and the second semiconductor element 431 is located in the space 426 between the second wall 422 and the third wall 423. The first semiconductor device 411 and/or the second semiconductor device 431 may be a vertical chip as shown in fig. 1, or a flip chip or a front chip having the epitaxial structure of fig. 1 or fig. 2. The first semiconductor device 411 and the second semiconductor device 431 are disposed on the carrier plate 424 and electrically connected to a circuit connection structure (not shown) on the carrier plate 424. In this embodiment, the first semiconductor element 411 is a light emitting element, the second semiconductor element 431 is a light receiving element, and the sensing module 400 can be disposed in a wearable device (e.g., a watch, a headset), wherein the light emitted from the first semiconductor element 411 passes through the skin and irradiates the body cells and blood, and the light scattered/reflected from the body cells and blood is absorbed by the second semiconductor element 431, so as to detect the physiological signals of the human body according to the change of the reflected and scattered light, such as: heart rate, blood glucose, blood pressure, blood oxygen concentration, etc.
Particularly, the utility model discloses an epitaxial structure, semiconductor component and semiconductor package can be applied to the product in fields such as illumination, medical treatment, demonstration, communication, sensing, electrical power generating system, for example lamps and lanterns, monitor, cell-phone, panel computer, automobile-used instrument board, TV, computer, wearing device (like wrist-watch, bracelet, necklace etc.), traffic sign, outdoor display, medical equipment etc..
Although the present invention has been disclosed in connection with the above embodiments, it is not intended to limit the present invention, and those skilled in the art will appreciate that various modifications and changes can be made without departing from the spirit and scope of the present invention, and therefore, the scope of the present invention should be determined by reference to the appended claims. Furthermore, the foregoing embodiments may be combined with or substituted for those described, where appropriate, without limitation to the specific embodiments described. For example, parameters related to specific components or connection relationships between specific components and other components disclosed in one embodiment can be applied to other embodiments, and all of the embodiments fall within the scope of the present invention.
Claims (25)
1. A semiconductor device, comprising:
an epitaxial structure comprising a first epitaxial stack, the first epitaxial stack comprising:
a first semiconductor structure;
a second semiconductor structure located on the first semiconductor structure and having a different conductivity type from the first semiconductor structure;
a first active region located between the first semiconductor structure and the second semiconductor structure;
a first confinement layer between the first active region and the first semiconductor structure, the first confinement layer directly contacting the first active region and having a first thickness; and
a second confinement layer between the first active region and the second semiconductor structure, the second confinement layer directly contacting the first active region and having a second thickness greater than the first thickness.
2. The semiconductor device of claim 1, wherein the first active region comprises a first well layer, a first barrier layer, a second well layer and a second barrier layer sequentially stacked on the first confining layer, the first well layer is closer to the first confining layer than the second well layer, and a thickness of the second well layer is greater than a thickness of the first well layer.
3. The semiconductor device of claim 2, wherein the first active region further comprises a third well layer on the second barrier layer, and wherein the third well layer has a thickness greater than a thickness of the second well layer.
4. The semiconductor device according to any one of claims 1 to 3, wherein the light emitted from the semiconductor device is infrared light.
5. The semiconductor device of any one of claims 1-3, wherein the epitaxial structure further comprises a second epitaxial stack on the first epitaxial stack, the second epitaxial stack having a third confinement layer, a fourth confinement layer, and a second active region between the third confinement layer and the fourth confinement layer, wherein the third confinement layer is closer to the first confinement layer than the fourth confinement layer, the third confinement layer has a third thickness, and the fourth confinement layer has a fourth thickness greater than the third thickness.
6. The semiconductor device of claim 5, wherein the first thickness is the same as the third thickness.
7. The semiconductor device as claimed in claim 5, wherein the second thickness is the same as the fourth thickness.
8. A semiconductor device according to any of claims 1 to 3, wherein the first confining layer is directly connected to the first semiconductor structure and the second confining layer is directly connected to the second semiconductor structure.
9. A semiconductor device according to any of claims 1 to 3, wherein the first semiconductor structure is p-type and the second semiconductor structure is n-type.
10. The semiconductor device as claimed in claim 1, wherein the first semiconductor structure has an energy gap larger than that of the first confinement layer.
11. The semiconductor device of claim 1, further comprising a bonding structure and a substrate, wherein the bonding structure is between the first epitaxial stack and the substrate.
12. The semiconductor device as claimed in claim 11, wherein the first semiconductor structure is closer to the bonding structure than the second semiconductor structure.
13. The semiconductor component of claim 5, further comprising an intermediate layer between the first epitaxial stack and the second epitaxial stack, the intermediate layer comprising a pn junction.
14. The semiconductor device of claim 13, wherein the pn junction is formed by a first heavily doped layer having a first conductivity and a second heavily doped layer having a second conductivity.
15. The semiconductor device of claim 1, wherein the first confinement layer and the second confinement layer do not contain dopants.
16. The semiconductor device as claimed in claim 1, further comprising a conductive layer between the first epitaxial stack and the reflective layer, a reflective layer, and a plurality of insulating portions between the first epitaxial stack and the conductive layer, wherein a plurality of voids are formed between the plurality of insulating portions, and the conductive layer fills the plurality of voids and contacts the first epitaxial stack.
17. The semiconductor device of claim 16, wherein said first epitaxial stack further comprises a plurality of contacts between said first semiconductor structure and said conductive layer.
18. The semiconductor device as claimed in claim 12, further comprising a first electrode and a second electrode respectively disposed on upper and lower sides of the first epitaxial stack, wherein the first electrode is connected to the second semiconductor structure, and the second electrode is connected to a side of the substrate away from the first semiconductor structure.
19. The semiconductor device as claimed in claim 1, wherein the first thickness is in a range of 150nm to 400nm, and the second thickness is in a range of 300nm to 650nm.
20. The semiconductor device of claim 1, wherein the first thickness is less than a thickness of the first semiconductor structure, and the second thickness is less than a thickness of the second semiconductor structure.
21. The semiconductor device of claim 2, wherein the first active region further comprises a third well layer and a third barrier layer, the first thickness and the second thickness being greater than the thicknesses of the first well layer, the first barrier layer, the second well layer, the second barrier layer, the third well layer, and the third barrier layer.
22. The semiconductor device of claim 5, wherein the second epitaxial stack further comprises a third semiconductor structure between the third confining layer and the first epitaxial stack and a fourth semiconductor structure on the fourth confining layer and having a different conductivity type than the third semiconductor structure.
23. The semiconductor device as claimed in claim 22, wherein the third semiconductor structure has the same conductivity type as the first semiconductor structure.
24. The semiconductor device according to claim 5, wherein a peak wavelength of light emission wavelengths of the second active region and the first active region is 730nm to 1100nm.
25. The semiconductor device as claimed in claim 5, wherein the third thickness is in a range of 150nm to 400nm, and the fourth thickness is in a range of 300nm to 650nm.
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