TW201916380A - Organic thin film transistor device and method for fabricating the same - Google Patents

Abstract

An organic thin film transistor device includes a substrate, a source, a drain, a barrier layer, an organic semiconductor layer, a gate dielectric layer and a gate. The source and drain are disposed on the substrate and respectively have a first sidewall and a second sidewall facing with and separated from each other. The barrier layer is disposed between the first sidewall and the second sidewall and has a top broadness substantially equal to the distance between the first sidewall and the second sidewall. The organic semiconductor layer covers on the source, the drain and the barrier. The gate dielectric layer is disposed on the organic semiconductor layer. The gate is disposed on the gate dielectric layer and separated from the organic semiconductor layer by the gate dielectric layer.

Description

Organic thin film transistor element and manufacturing method thereof

This disclosure relates to a thin film transistor device and a method for manufacturing the same. In particular, it relates to an organic thin film transistor element and a manufacturing method thereof.

Thin-film transistor elements have been widely used in the field of liquid crystal displays. As the display develops toward lighter, thinner, and flexible targets, organic thin-film transistors using organic materials as the channel layer of field-effect transistors ( Organic Thin Film Transistor (OTFT), due to its low process temperature (<200 ° C), low cost, and its suitability for flexible substrates (such as plastic substrates), has been gradually valued.

Generally speaking, organic thin film transistors can be mainly divided into two types: top-contact (TC) structure and bottom-contact (BC) structure. A typical method for forming an upper contact structure is to deposit an organic semiconductor (OSC) layer, and then perform a source / drain deposition and patterning process. In contrast, the formation method of the lower contact structure is to first perform a source / drain deposition and patterning process, and then deposit an organic semiconductor layer on the source / drain. Because the organic semiconductor material constituting the organic semiconductor layer is quite sensitive, it is easy to be damaged during the source / drain deposition and patterning process, resulting in component failure. Therefore, in order to maintain the stability of the manufacturing process and the yield rate, a lower contact structure manufacturing process is currently used to fabricate organic thin film transistors.

However, when an organic thin film transistor device is fabricated using a lower-contact structure process, the organic semiconductor layer deposited over the source / drain electrode will have a height difference of undulations as the thickness of the source / drain pattern changes. This makes the organic semiconductor layer uneven in thickness. Especially at the coner of the source / drain pattern, the thickness of the organic semiconductor layer will be thinner than the thickness above the source / drain, which will cause the channel length of the organic thin film transistor element ( Channel length) causes non-uniformity, which seriously affects the device performance of the organic thin film transistor device.

Therefore, there is a need to provide an advanced organic thin film transistor element and a manufacturing method thereof to solve the problems faced by the conventional technology.

An embodiment of the present specification discloses an organic thin film transistor device including a substrate, a source, a barrier layer, an organic semiconductor layer, a gate dielectric layer, and a gate electrode. The source is located on the substrate and has a first vertical wall. The drain electrode is located on the substrate and has a second vertical wall facing the first vertical wall and isolated from each other. The barrier layer is located between the first vertical wall and the second vertical wall, and the width of the top surface of the barrier layer is substantially equal to the distance between the first vertical wall and the second vertical wall. An organic semiconductor layer covering the source, drain and barrier layers. The gate dielectric layer is on the organic semiconductor layer. The gate is located on the gate dielectric layer, and is electrically isolated from the organic semiconductor layer by the gate dielectric layer.

Another embodiment of the present disclosure discloses a method for manufacturing an organic thin film transistor device, which includes the following steps: First, a source electrode and a drain electrode are formed on a substrate so that the source electrode has a first vertical wall, and the drain electrode has a first facing wall. A standing wall and a second standing wall isolated from each other. Then, a barrier layer is formed between the first vertical wall and the second vertical wall, so that the width of the barrier layer is substantially equal to the distance between the first vertical wall and the second vertical wall. An organic semiconductor layer is formed to cover the source, drain and barrier layers. Subsequently, a gate dielectric layer is formed on the organic semiconductor layer; a gate electrode is formed on the gate dielectric layer, and the gate dielectric layer is electrically isolated from the organic semiconductor layer.

According to the above embodiments, the present specification is to provide an organic thin film transistor element and a manufacturing method thereof. It adopts the lower contact structure process to make organic thin film transistor elements. A patterned source / drain is formed on the substrate first, and then a barrier layer is formed between the source / drain, so that the top width of the barrier layer is substantially equal to the distance between the source / drain. An organic semiconductor layer is formed to cover the source, drain and barrier layers. A gate dielectric layer and a gate are formed on the organic semiconductor layer.

By filling the barrier layer between the source / drain patterns, the height difference between the patterned source / drain electrodes is reduced (eliminated), so that the organics deposited on the patterned source / drain electrodes are subsequently deposited. The semiconductor layer has a substantially uniform thickness, so as to provide a uniform channel length of the organic thin film transistor element, thereby ensuring the device performance of the organic thin film transistor element.

In order to have a better understanding of the above and other aspects of this specification, the following specific examples are described in detail below in conjunction with the drawings:

This specification provides an organic thin film transistor device and a method for manufacturing the same, which can improve the device performance of an organic thin film transistor device with a lower contact structure. In order to make the above-mentioned embodiments and other objects, features, and advantages of this specification more comprehensible, an organic thin-film transistor and a manufacturing method thereof are given below as preferred embodiments, and described in detail with reference to the accompanying drawings.

It must be noted that these specific implementation cases and methods are not intended to limit the present invention. The invention can still be implemented with other features, elements, methods and parameters. The proposal of the preferred embodiment is only used to illustrate the technical features of the present invention, and is not intended to limit the scope of patent application of the present invention. Those with ordinary knowledge in the technical field can make equal modifications and changes according to the description of the following description without departing from the spirit of the present invention. In different embodiments and drawings, the same elements will be represented by the same element symbols.

Please refer to FIGS. 1A to 1E. FIGS. 1A to 1E are schematic cross-sectional views illustrating a process structure of fabricating an organic thin film transistor device 100 according to an embodiment of the present specification. The manufacturing method of the organic thin film transistor device 100 includes the following steps: First, a substrate 101 is provided (as shown in FIG. 1A). In some embodiments of the present specification, the substrate 101 may be a flexible flexible substrate, such as a plastic substrate. The material constituting the flexible substrate may be polyethylene- 6-naphthalate (PEN), polyethylene terephthalate (PET), or poly-ether sulfones, PES) or polyimide (PI). However, the substrate 101 is not limited to being implemented with a flexible substrate. In some embodiments of the present specification, a general glass substrate may also be used for implementation.

Thereafter, a source electrode 102 and a drain electrode 103 are formed on the surface 101a of the substrate 101, so that the source electrode 102 has a first vertical wall 102a, and the drain electrode 103 has a second vertical wall 103a facing the first vertical wall 102a and isolated from each other (such as the first 1B). As shown in the figure). In some embodiments of the present specification, the source electrode 102 and the drain electrode 103 may be formed by patterning a conductor layer formed on the surface 101 a of the substrate 101. The material constituting the conductor layer may include a metal, such as copper (Cu), gold (Au), platinum (Pt), or an alloy thereof.

In one embodiment, the formation of the source 102 and the drain 103 includes the following steps. First, a physical vapor deposition (PVD) process, such as an evaporation process or a sputtering process, is performed on the conductor layer on the surface 101a of the substrate 101 to form the conductor layer, wherein The conductor layer, for example, may include a metallic material. After that, a part of the conductor layer is removed by a lithography and etching process to form a source electrode 102 and a drain electrode 103 isolated from each other on the surface 101 a of the substrate 101. The distance D between the first vertical wall 102a of the source electrode 102 and the second vertical wall 103a of the drain electrode 103 is substantially between 3 μm and 10 μm.

Then, a barrier layer 104 is formed between the first vertical wall 102a and the second vertical wall 103a of the source 102 and the drain 103, so that the width B of the top surface of the barrier layer 104 is substantially equal to that between the first vertical wall 102a and the second vertical wall 103a. The distance D. The formation of the barrier layer 104 includes the following steps: First, a layer of a photosensitive material 105 is coated on the source 102 and the drain 103 and the surface 101 a of the substrate 101 to cover the source 101 and the drain 103. After that, a light source 106 is provided on the opposite side 101b of the surface 101a of the substrate 101, so that the light passes through the substrate 101 and the surface 101a of the substrate 101, and irradiates the photosensitive material 105 (as shown in FIG. 1C). Subsequently, a portion of the photosensitive material 105 located above the source 102 and the drain 103 is removed, at least a portion of the photosensitive material 105 located between the source 102 and the drain 103 is retained, and the remaining portion of the photosensitive material 105 is used as a barrier. Layer 104.

In some embodiments of the present specification, the photosensitive material 105 may be a negative photoresist (but not limited thereto), and the patterned source 102 and the drain 103 are used as a mask. The light source 106 performs exposure, and a portion of the photosensitive material 105 that is not exposed is removed by a development process. However, it is worth noting that the material and forming method of the barrier layer 104 are not limited thereto. Any method that can form the barrier layer 104 between the source 102 and the drain 103 is aligned with the source 102 (the first vertical wall 102a) and the drain 103 (the second vertical wall 103a) without departing from the present invention. The spiritual scope.

Subsequently, an organic semiconductor layer 107 is formed to cover the source 102, the drain 103, and the barrier layer 104. In some embodiments of the specification of this book, the material constituting the organic semiconductor layer 107 of the organic semiconductor layer 107 may include a pentacene or a derivative thereof. The step of forming the organic semiconductor layer 107 includes performing an evaporation method, a sputtering method, or a solution process. For example, in one embodiment, a single evaporation or sputtering process may be used to form a unipolar semiconductor layer composed of a pentaphenyl ring derivative over the source 102, the drain 103, and the barrier layer 104. In another embodiment, different evaporation or sputtering processes can also be used to vapor-deposit or sputtering N-type organic semiconductor materials, P-type organic semiconductor materials, N-type inorganic semiconductor materials, and P-type inorganic semiconductor materials, respectively; or Co-evaporation process is used to simultaneously vaporize N-type organic semiconductor materials, P-type organic semiconductor materials, or organic semiconductor materials with bipolar characteristics, and form the source 102, the drain 103, and the barrier layer 104. Bipolar semiconductor layer.

The thickness of the organic semiconductor layer 107 is substantially between 300 angstroms (angstrom Å) and 500 angstroms. In this embodiment, the source 102, the drain 103, and the top surfaces 102b, 103b, and 104a of the barrier layer 104 are substantially coplanar. Therefore, the thickness of the organic semiconductor layer 107 formed on the top surfaces 102b, 103b, and 104a of the source 102, the drain 103, and the barrier layer 104 is 107H. The faces 102b, 103b, and 104a are the lengths extending along the direction of the vertical distance D (the direction parallel to the Z axis).

Thereafter, a gate dielectric layer 108 is formed on the organic semiconductor layer 107. The material constituting the gate dielectric layer 108 includes an inorganic insulating material or an organic insulating material. Inorganic insulating materials, including silicon oxide, silicon nitride or hafnium oxide (HfO ₂ ). Organic insulating materials, including polyvinylphenol (PVP). The method for forming the gate dielectric layer 108 includes performing a physical vapor deposition process (such as an evaporation method) or a solution process. In one embodiment, a high-molecular-weight polymer comprising polyvinylphenol, propyleneglycol monomethylether acetate (PGMEA), and a polymer of polymelamine-co-formaldehyde (PMCF) may be formed first. Molecular solution, and then coating this polymer solution on the organic semiconductor layer 107 and baking to cross-link the polyvinyl phenol.

Subsequently, a gate electrode 109 is formed on the gate dielectric layer 108, and the gate electrode 109 is electrically isolated from the organic semiconductor layer 107 by the gate dielectric layer 108. A protective layer (not shown) is formed to cover the dielectric layer 108 and the gate electrode 109 to complete the organic thin film transistor element 100 as shown in FIG. 1E. The material constituting the gate electrode 109 may be a transparent conductive oxide or a metal. The transparent conductive oxide includes indium tin oxide (ITO) or indium zinc oxide (IZO). Metals include gold, silver (Ag), aluminum (Al), copper, titanium (Ti), chromium (Cr), or tantalum (Ta). In one embodiment, the method for forming the gate electrode 109 includes performing a physical vapor deposition process (such as a vapor deposition method), a conductive ink jet printing method, or other transfer technologies.

In this embodiment, the source 102 is far from the top surface 102a of the substrate 101 surface 101a, the drain 103 is far from the top surface 104a of the substrate 101 surface 101a, and the barrier layer 104 is far from the top surface 104a of the substrate 101 surface 101a. They are substantially coplanar (as shown in Figures 1D and 1E). Therefore, a flat surface (top surfaces 102b, 103b, and 104a) can be provided, so that the organic semiconductor layer 107 can be formed thereon without the phenomenon of height fluctuation and uneven thickness. It also helps to improve the process window of subsequent processes, so that the organic thin film transistor element 100 has a uniform channel length. In addition, in some embodiments of the present specification, the process temperature for forming the organic semiconductor layer 107, the gate dielectric layer 108, the gate electrode 109, and a protective layer (not shown) is substantially less than 150 ° C, which is much lower than the formation source. Process temperatures of the electrodes 102 and 103. Therefore, it can be ensured that the organic semiconductor layer 107 is not damaged by the high temperature of the subsequent process, and the device performance of the organic thin film transistor device 100 is ensured.

Please refer to FIG. 2. FIG. 2 is a schematic cross-sectional view of a structure of an organic thin film transistor 200 according to another embodiment of the present specification. The structure of the organic thin film transistor device 200 is substantially similar to the organic thin film transistor device 100 shown in FIG. 1E, and the difference is only that the height of the barrier layer 204 in the organic thin film transistor device 200 is different. In this embodiment, the top surface 204a of the barrier layer 204 far from the surface 101a of the substrate 101 is higher than the top surface 102b of the source 102 far from the surface 101a of the substrate 101 and the top surface of the drain 103 far from the top surface 101a of the substrate 101. 103b. A step height H2 is generated between the top surface 204a of the barrier layer 204 and the top surfaces 102b and 103b of the source 102 and the drain 103. Then, the organic semiconductor layer 207 and the gate dielectric layer 208 formed on the top surface 204a of the barrier layer 204, the top surfaces 102b and 103b of the source electrode 102 and the drain electrode 103 have a substantially flat top at the top, respectively. Type cross section, because the organic semiconductor layer 207 has leveling properties, even if the top surface 204a of the barrier layer 204 and the top surfaces 102b and 103b of the source 102 and the drain 103 generate a step height H2, the organic semiconductor The top 207a of the layer 207 may generate some undulations, but the height of these undulations will still be smaller than the gap H2. In other words, the top portion 207a of the organic semiconductor layer 207 is substantially flat.

In this embodiment, since the organic semiconductor layer 207 has a generally flat cross-section at the top, the thickness 207H of the organic semiconductor layer 207 refers to the direction of the vertical distance D from the top surface 204 a of the barrier layer 204. (The direction parallel to the Z axis) extends to the length of the top portion 207 a of the organic semiconductor layer 207.

In this embodiment, due to the difference H2 between the top surface 204a of the barrier layer 204 and the top surfaces 102b and 103b of the source and drain electrodes 102 and 103, the real value is smaller than the thickness of the organic semiconductor layer 207 (organic semiconductor layer 207). (The thickness is substantially between 300 angstroms and 500 angstroms). Therefore, even if the step difference H2 causes some fluctuations in the height of the organic semiconductor layer 207, it does not cause unevenness in thickness of the organic semiconductor layer 207. It can still provide a stable and flat process surface for subsequent processes, and can also make the channel length of the organic thin film transistor 200 uniform, so as to provide the engineering margin and ensure the performance of the organic thin film transistor 200.

Please refer to FIG. 3. FIG. 3 is a schematic cross-sectional view of a structure of an organic thin film transistor device 300 according to another embodiment of the present specification. The structure of the organic thin film transistor device 300 is substantially similar to the organic thin film transistor device 100 shown in FIG. 1E, and the difference is only that the height of the barrier layer 304 in the organic thin film transistor device 300 is different. In this embodiment, the top surface 304a of the barrier layer 304 far from the surface 101a of the substrate 101 is lower than the top surface 102b of the source 102 far from the surface 101a of the substrate 101 and the top surface of the drain 103 far from the top surface 101a of the substrate 101. 103b. The top surface 304a of the barrier layer 304 and the top surfaces 102b and 103b of the source 102 and the drain 103 are caused to have a gap H3. In addition, the organic semiconductor layer 307 and the gate dielectric layer 308 formed on the top surface 304a of the barrier layer 304, the top surfaces 102b and 103b of the source electrode 102 and the drain electrode 103 have flat T-shapes on the top, respectively section. Because the organic semiconductor layer 307 has leveling properties, even if the top surface 304a of the barrier layer 304 and the top surfaces 102b and 103b of the source 102 and the drain 103 generate a step height H3, the The top 307a may generate some undulations, but the height of these undulations will still be less than the gap H3. In other words, the top portion 307a of the organic semiconductor layer 307 is substantially flat.

In this embodiment, since the organic semiconductor layer 307 has a T-shaped flat cross section at the top, the thickness 307H of the organic semiconductor layer 307 refers to the direction of the vertical distance D from the top surface 304a of the barrier layer 304 ( The direction parallel to the Z axis) extends to the length of the top portion 307 a of the organic semiconductor layer 307.

In this embodiment, due to the gap H3 between the top surface 304a of the barrier layer 304 and the top surfaces 102b and 103b of the source 102 and the drain 103, the real value is smaller than the thickness 307H of the organic semiconductor layer 307 (organic semiconductor layer The thickness of 307 is substantially between 300 angstroms and 800 angstroms). Therefore, even if the step difference H3 causes some fluctuations in the height of the organic semiconductor layer 307, the thickness of the organic semiconductor layer 307 will not be uneven. It can still provide a stable and flat process surface for subsequent processes, and it can also make the channel length of the organic thin film transistor element 300 uniform, thereby achieving the purpose of providing engineering margin and ensuring the device performance of the organic thin film transistor element 300.

According to the above embodiments, the present specification is to provide an organic thin film transistor element and a manufacturing method thereof. It adopts the lower contact structure process to make organic thin film transistor elements. A patterned source / drain is formed on the substrate first, and then a barrier layer is formed between the source / drain, so that the top width of the barrier layer is substantially equal to the distance between the source / drain. An organic semiconductor layer is formed to cover the source, drain and barrier layers. A gate dielectric layer and a gate are formed on the organic semiconductor layer.

By filling the barrier layer between the source / drain patterns, the height difference between the patterned source / drain electrodes is reduced (eliminated), so that the organics deposited on the patterned source / drain electrodes are subsequently deposited. The semiconductor layer has a substantially uniform thickness, so as to provide a uniform channel length of the organic thin film transistor element, thereby ensuring the device performance of the organic thin film transistor element.

Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Any person with ordinary knowledge in this technical field can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the scope of the appended patent application.

100, 200, 300‧‧‧ organic thin film transistor elements

101‧‧‧ substrate

101a‧‧‧ Substrate surface

101b‧‧‧ Opposite side of substrate surface 1

102‧‧‧Source

102a‧‧‧First Wall

102b‧‧‧ Top surface of source

103‧‧‧ Drain

103a‧‧‧Second wall

103b‧‧‧ Top of drain

104, 204, 304‧‧‧ barrier layer

104a‧‧‧ Top surface of barrier layer

105‧‧‧photosensitive materials

106‧‧‧light source

107, 207, 307‧‧‧ organic semiconductor layers

107H, 207H, 307H‧‧‧thickness of organic semiconductor layer

108, 208, 308‧‧‧ Gate dielectric layer

109‧‧‧Gate

207a, 307a ‧‧‧ on top of organic semiconductor layer

D‧‧‧ the distance between the first and second walls

B‧‧‧ Top width of barrier layer

H2, H3 ‧‧‧ The difference between the top surface of the barrier layer and the top surface of the source and drain

FIG. 1A to FIG. 1E are schematic cross-sectional views of a process structure for fabricating an organic thin film transistor according to an embodiment of the present specification; and FIG. 2 is an organic thin film transistor according to another embodiment of the present specification. FIG. 3 is a schematic structural cross-sectional view of an organic thin film transistor according to another embodiment of the present disclosure.

no.

Claims (10)

An organic thin film transistor element includes: a substrate; a source electrode on the substrate having a first vertical wall; a drain electrode on the substrate having a second vertical wall facing the first vertical wall And is isolated from each other; a barrier layer is located between the first vertical wall and the second vertical wall, and the barrier layer has a top surface width substantially equal to a distance between the first vertical wall and the second vertical wall; An organic semiconductor layer covering the source, the drain, and the barrier layer; a gate dielectric layer on the organic semiconductor layer; and a gate electrode on the gate dielectric layer, and by The gate dielectric layer is electrically isolated from the organic semiconductor layer. According to the organic thin film transistor device described in the first item of the patent application scope, wherein the source electrode, the drain electrode, and the barrier layer each have a top surface, and the three are substantially coplanar. The organic thin film transistor device according to item 1 of the scope of patent application, wherein the organic semiconductor layer has a thickness, and a top surface step difference between the barrier layer and at least one of the source electrode and the drain electrode (step height) ) Is substantially smaller than the thickness. The organic thin film transistor device according to item 3 of the scope of patent application, wherein the barrier layer has a top surface higher than the source electrode and the drain electrode. The organic thin film transistor device according to item 3 of the application, wherein the barrier layer has a top surface lower than the source electrode and the drain electrode. The organic thin film transistor device described in item 3 of the scope of the patent application, wherein the thickness is substantially between 300 angstroms (angstrom Å) and 800 angstroms. The organic thin film transistor device according to item 3 of the patent application scope, wherein the barrier layer comprises a photosensitive material. A method for manufacturing an organic thin film transistor element includes: forming a source electrode and a drain electrode on a substrate, so that the source electrode has a first vertical wall, and the drain electrode has a second vertical wall facing the first vertical wall. And are isolated from each other; forming a barrier layer between the first standing wall and the second standing wall so that the barrier layer has a width substantially equal to a distance between the first standing wall and the second standing wall; forming a An organic semiconductor layer covering the source electrode, the drain electrode, and the barrier layer; forming a gate dielectric layer on the organic semiconductor layer; and forming a gate electrode on the gate dielectric layer, and by the The gate dielectric layer is electrically isolated from the organic semiconductor layer. The method for manufacturing an organic thin film transistor device according to item 8 of the scope of patent application, wherein the step of forming the barrier layer comprises: coating a photosensitive material on the substrate, and covering the source electrode and the drain electrode. Providing a light to irradiate the photosensitive material through the substrate; and removing a portion of the photosensitive material above the source and the drain. According to the manufacturing method of the organic thin film transistor element described in item 8 of the scope of the application patent, the step of forming the organic semiconductor layer, the gate dielectric layer, and the gate electrode has a temperature substantially less than 150 ° C.