TW201915505A - Test apparatus and testing circuit board thereof - Google Patents

Abstract

A test apparatus including at least one testing circuit board is disclosed. Each testing circuit board includes a cache memory module, a memory interface controller, a test vector generator, and a signal transmitting circuit. The cache memory module is adapted to read and store a plurality of testing vectors from a DRAM. The memory interface controller stores reading command for the cache memory module to read the testing vectors from the DRAM. The test vector generator read one of the plurality of testing vectors form the cache memory module according to a memory address of a micro command, and generates a test signal based on the read testing vector. The signal transmitting circuit is adapted to send out a test control signal generated by the test vector generator, or to receive another test control signal and transmit it to the test vector generator.

Description

Test device and test board

The present invention relates to a test device having a plurality of test boards, in particular, each of the test boards has a buffer memory module and a test vector generator for individually operating independently and jointly by the plurality of test boards Test equipment for all test items.

The system architecture of conventional test devices typically controls multiple functional boards by a central control board. The central channel control circuit board sequentially generates and transmits the test pattern data memory location of the functional circuit board to the plurality of functional circuit boards by reading test microinstructions in the memory of the circuit board. Subsequently, each functional circuit board tests the test object by reading test pattern data in the memory of the circuit board, and causing the plurality of channel waveform generators of the circuit board to generate test signals.

In the above architecture, the ability of the conventional functional circuit board test device to generate test signals is obviously limited by the performance of the central control circuit board. In detail, since the performance requirements of the central control circuit board must take into account the number of transmission lines, transmission line lengths, and transmission speeds of the shared backplane, when the test object needs to be tested, the function signal needs to be increased and more functional circuit boards need to be added. This not only causes the conventional test device to increase the number of slots that share the backplane, but is also more likely to replace the more powerful and faster central control board due to performance requirements. In addition, although it is simpler to control the architectural thinking of all functional boards with a single central control board, it will reduce the performance of the overall test system.

The invention provides a test device having at least one test circuit board, and each test circuit board has an independent operation capability, thereby solving the problem that the operational capability of the conventional test device is limited to the performance of the central controller.

The test device disclosed in the present invention comprises at least one test circuit board, each test circuit board is used for connecting a dynamic random access memory to read test vectors in the dynamic random access memory and generate test signals. Each of the test boards has an independent operation capability, and each of the test boards includes a buffer memory module, a memory interface controller, a test vector generator, and a transmission circuit. The buffer memory module is configured to be electrically connected to the dynamic random access memory and used to read and store a plurality of test vectors from the dynamic random access memory. The memory interface controller is coupled to the buffer memory module, and the memory interface controller stores at least a read command for the buffer memory module to read the test vectors from the dynamic random access memory. The test vector generator is coupled to the buffer memory module, and reads one of the plurality of test vectors from the buffer memory module according to a memory location in a test microinstruction, and generates the read test vector A test signal. The transmission circuit is coupled to the test vector generator, and the transmission circuit is configured to transmit a test control signal generated by the test vector generator or to receive another test control signal and transmit the test control signal to the test vector generator.

According to the test apparatus disclosed in the above invention, each test circuit board has independent operation capability, and both have a buffer memory module controller and a test vector generator, so that the actual position of the test object can be flexibly operated. By changing the number of test boards of the test device, a test signal corresponding to the actual pin position described above can be achieved. Moreover, when a plurality of test boards are grouped into a set of test circuits, since each test board of the set of test circuits has an independent working capability, the test circuit group accesses data, scheduling capability, The performance of generating test signals can also be increased correspondingly, effectively solving the problem that the operational capability of the conventional test device is limited to the performance of the central controller.

The above description of the disclosure and the following description of the embodiments of the present invention are intended to illustrate and explain the spirit and principles of the invention, and to provide further explanation of the scope of the invention.

The detailed features and advantages of the present invention are set forth in the Detailed Description of the Detailed Description of the <RTIgt; </ RTI> <RTIgt; </ RTI> </ RTI> </ RTI> <RTIgt; The objects and advantages associated with the present invention can be readily understood by those skilled in the art. The following examples are intended to describe the present invention in further detail, but are not intended to limit the scope of the invention.

Please refer to FIG. 1. FIG. 1 is a schematic diagram of a testing apparatus according to an embodiment of the invention. As shown in FIG. 1, the test apparatus has a plurality of test boards 1, each of which has pins, such as pins pin1 to pin3. Each of the pins 1 to 3 of the test circuit board 1 is electrically connected to a transmission line. That is to say, the pin pin1 of each test circuit board 1 is electrically connected to the transmission line tr1, and the pin pin 2 of each test circuit board 1 is electrically connected to the transmission line tr2, and the pin 3 of each test circuit board 1 is electrically connected. Connected to the transmission line tr3. The transmission line is, for example, a cable, a trace on the backplane, or other suitable transmission signal component. The plurality of test boards 1 transmit signals to each other through the pins pin1 to pin3 and the transmission lines tr1 to tr3 to synchronously generate a test signal to test the test object DUT. For example, the user can preset one of the plurality of test circuit boards 1 as a master through a software mode, and the other test circuit boards 1 are preset as a servo board, thereby generating synchronization by the main control board. The signal is transmitted to each servo board through pins pin1 to pin3 and transmission lines tr1 to tr3, so that all test boards 1 simultaneously generate test signals to test the test object DUT. Alternatively, the test object DUT may be tested by simultaneously generating a test signal by a part of the test circuit board 1 as needed. This embodiment is not limited.

In other words, each test circuit board 1 of the present embodiment has an independent operation capability, and can read data from an external memory and generate a test signal to the function of the test object DUT. However, when the test object DUT has a large number of test pins and a plurality of test signals need to be generated correspondingly, the plurality of test circuit boards 1 can be grouped into the above-mentioned pins pin1 to pin3 and the transmission lines tr1 to tr3. A set of test circuits that operate synchronously, that is, can test such a test object DUT with more testable feet without providing a more powerful central control circuit board. In addition, since each test circuit board 1 can operate independently, when a plurality of test circuit boards 1 are grouped to operate synchronously to generate a test signal, the test circuit formed by the test circuit is configured to access data, schedule capability, and generate The performance of test signals and the like can be simultaneously enhanced, and the problem that the operational capability of the conventional test device is limited by the performance of the central control circuit board is solved.

To implement the above test apparatus, the test circuit board 1 of one embodiment of the present invention has the architecture as shown in FIG. As shown in FIG. 2, each test circuit board 1 of the test apparatus has a buffer memory module 11, a memory interface controller 13, a test vector generator 15, and a transmission circuit 17, and each test circuit board 1 is connected to The DRAM 2 is operative to interact with the DRAM 2 in accordance with the instructions. The dynamic random access memory 2 is a memory component other than the test circuit board 1, for example, Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), next generation. Dynamic random access memory (DDR2 DRAM, DDR3 DRAM or DDR4 DRAM, etc.) or other suitable dynamic random access memory. The user-designed test vector is stored in the DRAM 2 for the test circuit board 1 to access the test vector of the memory address of the DRAM 2 according to the system instruction.

The buffer memory module 11 of the test circuit board 1 is configured to interact with the external random access memory 2 in accordance with an instruction, and the buffer memory module 11 includes at least the buffer memory 111 and the memory controller 113. The buffer memory 111 is, for example, a cache memory or other temporary storage memory having a high access speed; and the memory controller 113 is connected to the buffer memory 111, the memory interface controller 13, The test vector generator 15 and the read and write interfaces of the random access memory 2 are composed of a circuit. The memory controller 113 receives the read and write commands of the memory interface controller 13, and issues a write command from the memory interface controller 13 in accordance with the test vector command previously written by the user in the test vector generator 15. The dynamic random access memory 2 is stored, or the test vector designed by the user is stored in the dynamic random access memory 2.

The memory interface controller 13 of the test circuit board 1 stores read and write commands that the test circuit board 1 can perform on the dynamic random access memory 2, and the test vector must be written to the dynamic memory in the buffer memory module 11. When the random access memory 2 or the dynamic random access memory 2 reads the test vector, the memory interface controller 13 provides a read command or a write command for performing the above operation. The memory interface controller 13 is composed of a circuit.

The test vector generator 15 of the test circuit board 1 reads the test vector stored in the buffer memory 11 at the start of the test, and generates a test signal of the test object DUT, wherein the test vector generator 15 can be a circuit or a microcontroller. (Micro Control Unit), which comprises a test micro-instruction processing module 151 and a test pattern data processing module 153, and the test vector includes test micro-instructions (for example, a command group indicating that execution should be performed) and test pattern data (for example, representation logic) Value pattern). The test vector generator 15 can perform the test micro-instruction decoding according to the test vector stored in the buffer memory 111 of the buffer memory module 11, and perform the operations of the micro-instruction such as repeat, branch, etc. to generate pattern data. And further generate a test signal of the test object DUT. In detail, the test micro-instruction processing module 151 sequentially executes the above-mentioned test micro-instruction, for example, by referring to the memory address in the test micro-instruction, the buffer memory module 11 provides the test vector temporarily stored in the buffer memory 111. Alternatively, the memory controller 113 is required to further read the test vector to the dynamic random access memory 2 and store it in the buffer memory 111, or the test pattern data processing module 153 is required to operate, for example, in accordance with the test microinstruction. The test pattern data processing module 153 executes the pattern data processing mode in the test micro-instruction according to the instruction of the test micro-instruction processing module 151, and performs specific processing algorithms on the test pattern data to generate a test signal of the test object DUT. In other words, the test vector generator 15 executes the test microinstruction in the test vector, and reads the next test vector required to execute the test microinstruction according to the memory address address in the test microinstruction to the buffer memory module 11 and The test pattern data in each test vector is sequentially transmitted to the test pattern data processing module 153 to generate a test signal. Therefore, the above-mentioned operation does not include a compile program when the conventional CPU executes the program.

In detail, the pattern data processing mode of the test micro-instruction is, for example, a normal mode pattern data processing method, a scan mode (SCAN Function) pattern data processing method, and an algorithm pattern generation pattern (ALPG) pattern. Data processing method, logic pattern buffer mode (Data-Buffer) pattern data processing method or other pattern data processing method. For example, when the test pattern data processing mode is in the normal mode, each test vector can be effectively utilized by setting the test output end point, and each test vector includes all test output end points of the circuit board 1. If the test vector uses the scan mode, all pattern data of the test vector is divided into the set test output, in other words, the test vector is given a special test micro-instruction repeat command. When the test pattern data is based on the logic pattern calculation generation mode, the special ALPG micro-instruction can be used to generate the post-calculation test signal of the test object DUT through the logic pattern calculation. At this time, the test signal has better test efficiency for testing the memory component. In other words, the test micro-test of the test vector allows the test pattern data to generate a specific test signal type. In this way, a test device can generate test signals of various test functions to test different types or different functional test objects, but not limited thereto.

The transmission circuit 17 of the test circuit board 1 is used to connect the aforementioned pins pin1 to pin3 to transmit information to and from the other test circuit boards 1 through the transmission lines tr1 to tr3. In detail, when the test circuit board 1 is used as the main control board, it is required to actively provide the test related control signal to other test circuit boards, and the transmission circuit 17 of the test circuit board 1 (main control board) is based on The configuration signal outputs test control signals from the specific pins pin1 to pin3 to the transmission lines tr1 to tr3. On the contrary, when the test circuit board 1 is used as a servo board, the transmission circuit 17 of the test circuit board 1 (servo board) passively receives the test control signals on the transmission line, and each test circuit board 1 (servo board) The transmission circuit 17 also determines whether to receive or ignore the test control signals on the transmission lines tr1 to tr3 according to the configuration signal. Therefore, the plurality of test circuit boards 1 of the test apparatus of the present invention can use the test control signals as a starting reference for synchronous operation, so that all test circuit boards 1 synchronously generate test signals to test the test object DUT.

In the actual operation of the test device, when the test circuit board 1 as the main control board outputs the test control signal according to the configuration signal by the transmission circuit 17, or the test circuit board 1 as the servo board receives the test according to the configuration signal. When the signal is controlled, the test vector generator 15 of the test board 1 must obtain the test vector in the dynamic random access memory 2 to generate a test signal. At this time, the test vector generator 15 requests the buffer memory module 11 to quickly perform the dynamic random access memory 2 reading, and reads the used memory block to the buffer of the buffer memory module 11. In memory 111. Therefore, when the test vector required by the test vector generator 15 is temporarily stored in the buffer memory 111, the memory controller 113 does not need to read the test vector from the dynamic random access memory 2 repeatedly. The speed at which the test vector generator 15 reads the data can be effectively improved, and the mechanism for data reuse can also be provided when executing the loop instruction of the test microinstruction. Then, the test vector generator 15 of the test circuit board 1 receives the test vector stored therein from the buffer memory 111 of the buffer memory module 11, and generates a test signal according to the test pattern data provided by the test micro-instruction, wherein the test vector is generated. The operation mode of the test micro-instruction processing module 151 and the test pattern data processing module 153 in the device 15 is as described above, and therefore will not be described again.

Please refer to FIG. 2 and FIG. 3 together. FIG. 3 is a functional block diagram of a test vector generator according to another embodiment of the present invention. As shown, the test vector generator 35 of this embodiment has a first in first out memory 353 as compared to the test vector generator 15 of the previous embodiment. In other words, the test vector generator 35 has a test micro-instruction processing module 351, a first-in first-out memory 353, and a test pattern data processing module 355. When the test vector generator 35 is in operation, the test micro-instruction processing module 351 temporarily stores the generated test vector in the first-in first-out memory 353 to change the processing speed of the test micro-instruction by the characteristics of the first-in first-out memory 353. To test the pattern data processing speed, the test vectors are sequentially supplied to the test pattern data processing module 355 by the first in first out memory 353. In the example of the figure, the test pattern data processing module 353 may first pass the test vector through a plurality of calculation paths (for example, the four calculation paths shown in FIG. 3: the first calculation path to the fourth calculation path), so that the test vectors are generated. A variety of test signals. Then, the multiplexer 357 selects a signal according to the calculation of the test micro-instruction, and selects one of the plurality of test signals to test the test object DUT, but not limited thereto. In other embodiments, the test vector may be first executed by using multiple test vectors, and then the test vector generates a test signal according to the test micro-instruction and the test pattern data. Those having ordinary knowledge in the technical field can design according to actual needs and conditions, and the embodiment is not limited.

Next, please refer to Figure 1 and Figure 2 together. In practice, the speed at which the memory controller 113 reads each test vector from the DRAM 2 is slower than the test microinstruction processing of the test vector generator 15. Therefore, the test memory read from the DRAM 2 is stored in the buffer memory 111 by the buffer memory module 11 provided by the present invention, and is read from the random access memory 2 through the memory controller 113. The number of data of the test vector is read, and the memory controller 113 reads the test vector from the DRAM 2 in advance, in response to the test vector generator 15 reading the speed of the test vector.

In detail, in one embodiment, the test vector is read from the dynamic random access memory 2 by the memory controller 113 and stored in the buffer memory 111, and the test vector generator 15 is controlled by the memory. The processor 113 reads the difference between the speeds of the test vectors in the buffer memory 111, and the memory access data width of the memory controller 113 is asymmetric. Taking the memory storage data width of the buffer memory module 11 as 4 times the width of the read data, it is assumed that the data width read by the memory controller 113 is 512 bits, and the test vector generator 15 reads The width of the data to be fetched is 128 bits, and the buffer memory 111 needs to be stored in the data width of 512 bits, and the read buffer memory 111 needs to use the read data width of 128 bits. Therefore, by using the high data width of the dynamic random access memory 2, the high-speed data amount required by the test vector generator 15 can be satisfied, and the speed of the test vector stored in the buffer memory 111 and the reading can be effectively shortened. The difference between the speeds of the test vectors in the buffer memory 111.

In another embodiment, a block test vector interval is quickly read from the DRAM 2 through the memory controller 113, so that the test vector generator 15 reads the buffer through the memory controller 113. The speed of the test vector in memory 111. For example, when the test vector generator 15 test is initiated, a first test vector request is issued to the memory controller 113. At this time, the buffer memory module 11 quickly reads a block test vector interval from the dynamic random access memory 2 through the memory controller 13, and stores the block test vector interval in the buffer memory 111. . Then, continue to read the next block test vector interval in advance. That is, after the buffer memory module 11 quickly reads the test vector from the dynamic random access memory 2 through the memory controller 113, the buffer memory module 11 is based on the read dynamic random access memory. The memory address of 2 predicts the next test vector to be read from the dynamic random access memory 2. The predicted test vector is stored in the buffer memory 111 following the memory address of the read dynamic random access memory 2, so that the buffer memory module 11 can read the dynamic random access memory 2 at a speed that can cope with the test. The vector generator 15 reads the speed of the test vector.

When the test circuit board 1 is simultaneously applied to the above two embodiments, the buffer memory module 11 reads the four test vectors from the dynamic random access memory 2 at a time through the memory controller 113, and then according to the four The memory address of the dynamic random access memory 2 read by the test vector predicts the next four test vectors, and the predicted four test vectors and four memory addresses of the dynamic random access memory 2 are stored. In the buffer memory 111, the speed at which the test vector generator 15 reads the test vector is dealt with.

In still another embodiment, when the test vector generator 15 reads the test vector stored in the buffer memory 111 and the test microinstruction processing module 151 then executes the loop instruction of the microinstruction, such as a repeat command, The test microinstruction processing module 151 must repeatedly transmit the test vector to the test pattern data processing module 153. At this time, by using the mechanism of the test vector stored in the buffer memory 111 again, the test vector can be quickly transferred from the buffer memory 111 to the test pattern data processing module 153 without having to be again by the dynamic random access memory. 2 Read this test vector. In other words, when the test micro-instruction obtained by the test vector generator 15 from the test vector stored in the buffer memory is a loop instruction, the buffer memory module 11 predicts the next test vector to be read from the random access memory 2. Whether it is already in the buffer memory 111. If so, the test vector is continuously read by the buffer memory 111 to the test vector generator 15, so that the existing test vector can be quickly and directly read from the buffer memory 111 to cope with the test vector generator 15 The buffer memory 111 reads the speed of the test vector.

The data reuse mechanism is combined with the buffer memory module 11 to quickly read a block test vector interval from the dynamic random access memory 2, and then the test vector generator 15 performs a loop according to the test microinstruction. At the time of the instruction, the memory controller 113 determines whether or not the buffer memory 111 has the position of the next data of the test vector generator 15. In other words, the buffer memory module 11 does not need to read the next block test vector interval from the DRAM 2 in accordance with the position of the next data.

In addition, in another embodiment, the test vector generator 15 reads the conditional jump address from the DRAM 2 according to the test micro-instruction execution condition instruction, and the test vector generator 15 according to the test micro-instruction One of the two conditional branch instructions of the executed conditional instruction reads a block test vector interval of the dynamic random access memory 2 at the conditional jump address. In other words, when the test vector generator 15 reads the test vector from the buffer memory 111, the test vector generator 15 predicts that the next test vector to be accessed from the dynamic random access memory 2 is indicated by one of the conditional branch instructions. Conditional hopping address. For example, when the prediction condition of the test vector generator 15 is satisfied, the memory controller 113 is required to read the test vector when the condition is satisfied from the DRAM 2 in advance and store it in the buffer memory 111. When the conditional instruction does not hold, the test vector generator 15 can quickly obtain the test vector to be read when the condition is satisfied by the buffer memory 111.

If the execution mechanism of the above conditional instruction is combined with the manner in which the buffer memory module 11 quickly reads a block test vector interval from the dynamic random access memory 2, the test vector generator 15 executes the condition according to the test microinstruction. The test vector memory address of the instruction, when the first block test vector interval located in the first test vector address is read from the DRAM 2, the test vector generator 15 can execute the condition according to the test microinstruction. The conditional branch instruction when the instruction is established reads the second block test vector interval from the DRAM 2 and stores it in the buffer memory 111 together with the first block test vector interval.

In summary, the embodiment of the present invention provides that each test circuit board 1 has independent operation capability, that is, each test circuit board 1 can read the test vector stored in the dynamic random access memory 2, and according to the test. The vector generates a test signal for delivery to the test object DUT. When a plurality of test circuit boards 1 transmit related control signals to each other and group into a set of test circuits, the pins of each of the test circuit boards 1 for connecting to the test object DUT are the test circuit groups. The test pin is used to increase the number of signals that the test circuit group performs a synchronous test on the test object DUT. Moreover, since each test circuit board has an independent working capability, when a plurality of test circuit boards are grouped to work together to generate a test signal, the test circuit group accesses data, schedules, generates test signals, and the like. Work performance can be enhanced at the same time. Therefore, when the test object DUT is changed and more test pins are required, with the test device of the present invention, only an additional test circuit board 1 needs to be added and the additional test circuit board and the original test are in software. The circuit is grouped to generate test signals in synchronization with the original test circuit. Therefore, the test apparatus and the test circuit board 1 of the present invention can effectively solve the problem that the operation capability of the test signal generated by the conventional test device is limited by the performance of the central control circuit board, and does not require any hard work for different test object DUTs. Physical change.

Although the present invention has been disclosed above in the foregoing embodiments, it is not intended to limit the invention. All modifications and refinements are within the scope of the invention as defined by the scope of the invention. Please refer to the attached patent application for the scope of protection defined by the present invention.

1‧‧‧Test circuit board

11‧‧‧Buffered Memory Module

111‧‧‧Buffered memory

113‧‧‧ memory controller

13‧‧‧Memory interface controller

15‧‧‧Test Vector Generator

151‧‧‧Test micro-instruction processing module

153‧‧‧Test pattern data processing module

17‧‧‧Transmission circuit

2‧‧‧Dynamic random access memory

35‧‧‧Test Vector Generator

351‧‧‧Test micro-instruction processing module

353‧‧‧First In First Out Memory

355‧‧‧Test pattern data processing module

357‧‧‧Solution multiplexer

DUT‧‧‧ test object

Pin1~pin3‧‧‧ pins

Tr1～tr3‧‧‧ transmission line

1 is a schematic diagram of a test apparatus according to an embodiment of the invention. 2 is a functional block diagram of a test circuit board according to an embodiment of the invention. 3 is a functional block diagram of a test vector generator according to another embodiment of the present invention.

Claims (7)

A test device includes at least one test circuit board, each test circuit board is configured to connect a dynamic random access memory to read test vectors in the dynamic random access memory and generate test signals, each of which The test circuit boards each have independent operation capability, and each of the test circuit boards includes: a buffer memory module for electrically connecting to the dynamic random access memory and used for the dynamic random access memory Reading and storing a plurality of test vectors; a memory interface controller connecting the buffer memory module, and the memory interface controller storing at least a read command for the buffer memory module to be dynamically stored from the buffer Taking the memory to read the test vectors; a test vector generator, connecting the buffer memory module, and reading the plurality of test vectors from the buffer memory module according to the memory location in a test microinstruction And generating a test signal by using the read test vector; and a transmission circuit connecting the test vector generator, and the transmission circuit is configured to send the test vector to generate A control signal generated by the test, or for receiving a control signal and transmits another test to the test vector generator. The test apparatus of claim 1, wherein the test microinstruction is pre-written in the test vector generator or included in the read test vector. The test device of claim 2, wherein the test vector generator comprises a test micro-instruction processing module and a test pattern data processing module, the test vector further comprising a test pattern data, the test micro-instruction processing module Performing the test microinstruction to read a test vector in the buffer memory module and controlling the test pattern data processing module, the test pattern data processing module performing an algorithm on the test pattern data according to the test microinstruction To generate the test signal. The test device of claim 1, wherein the number of the at least one test circuit board is plural, one of the plurality of test circuit boards is a main control board, and the rest of the plurality of test circuit boards are at least one servo The transmission circuit of the main control board sends a test control signal, and the transmission circuit of the at least one servo board receives the test control signal, wherein the test control signal serves as a synchronous operation start reference of the plurality of test boards. The test device of claim 1, wherein the read data width of the buffer memory module is greater than the read data width of the test vector generator. The test device of claim 1, wherein the test vector generator comprises a test micro-instruction processing module, a first-in first-out memory and a test pattern data processing module, which are sequentially connected, and the test vector further comprises a test vector Testing the pattern data, the test micro-instruction processing module executes the test micro-instruction to read the test vector in the buffer memory module and store the first-in first-out memory, the FIFO memory sequentially The stored test vector is provided to the test pattern data processing module. The test pattern data processing module executes a plurality of algorithms on the test pattern data according to the test micro-instruction to generate a plurality of test signals including the test signal. The test device of claim 6, wherein the test vector generator further comprises a demultiplexer, the demultiplexer is connected to the test pattern data processing module, and the demultiplexer is configured according to the test microinstruction A calculation selection signal is selected from the plurality of test signals.