TWI661208B - Test apparatus and testing circuit board thereof - Google Patents

Abstract

A test device includes at least one test circuit board, each of which has an independent operation capability, and each of the test circuit boards includes: a buffer memory module for reading from a dynamic random access memory And store a plurality of test vectors; a memory interface controller stores a read command for the buffer memory module to read the test vectors; a test vector generator selects the test vector from the memory position in a test microinstruction The buffer memory module reads one of the plurality of test vectors and generates a test signal based on the read test vectors; and a transmission circuit is used for transmitting a test control signal generated by the test vector generator, or receiving Another test control signal is transmitted to the test vector generator.

Description

Test device and test circuit board

The invention relates to a test device with multiple test circuit boards, in particular, each test circuit board has a buffer memory module and a test vector generator for individual independent operation and completion by the multiple test circuit boards. Test fixture for all test items.

The system architecture of the conventional test device usually controls a plurality of functional circuit boards through a central control circuit board. The central channel control circuit board sequentially generates and transmits the test pattern data memory locations of the functional circuit boards to a plurality of functional circuit boards by reading the test micro-instructions in the memory of the circuit board. Subsequently, each functional circuit board tests the test object by reading test pattern data in the memory of the circuit board, so that a plurality of channel waveform generators of the circuit board generate test signals.

In the above architecture, the operation capability of the conventional functional circuit board test device to generate test signals is obviously limited by the effectiveness of the central control circuit board. In detail, due to the performance requirements of the central control circuit board, factors such as the number of transmission lines, transmission line length, and transmission speed of the shared backplane must be considered. Therefore, when the test object requires more functional signals, more functional circuit boards must be added accordingly. As a result, not only does the conventional test device need to increase the number of slots for the common backplane, but it is also more likely that the central control circuit board with a more powerful and faster operation must be replaced due to performance requirements. In addition, although a single central control circuit board is used to control all functional circuit boards, the architectural thinking is relatively simple, but it will reduce the performance of the overall test system.

The invention is to provide a test device, which has at least one test circuit board, and each test circuit board has an independent operation capability, thereby solving the problem that the operation capability of the conventional test device is limited to the performance of the central controller.

The test device disclosed in the present invention includes at least one test circuit board, and each test circuit board is used to connect a dynamic random access memory to read a test vector in the dynamic random access memory and generate a test signal. Each of the test circuit boards has an independent operation capability, and each of the test circuit boards includes a buffer memory module, a memory interface controller, a test vector generator, and a transmission circuit. The buffer memory module is used for being electrically connected to the dynamic random access memory, and used for reading and storing a plurality of test vectors from the dynamic random access memory. The memory interface controller is connected to the buffer memory module, and the memory interface controller stores at least a read command for the buffer memory module to read the test vectors from the dynamic random access memory. The test vector generator is connected to the buffer memory module, and reads one of the plurality of test vectors from the buffer memory module according to the memory position in a test microinstruction, and generates the test vector from the read test vector. A test signal. The transmission circuit is connected to the test vector generator, and the transmission circuit is used to send a test control signal generated by the test vector generator, or to receive another test control signal and send it to the test vector generator.

According to the test device disclosed in the present invention, each test circuit board has an independent operation capability, and each has a buffer memory module controller and a test vector generator, which can realize the mobility according to the actual foot position of the test object. Changing the number of test circuit boards of the test device can achieve the generation of test signals corresponding to the above-mentioned actual pins. Moreover, when multiple test circuit boards are grouped into a set of test circuits, each test circuit board in the set of test circuits has an independent working capability, which makes the test circuit group access data, schedule, The work efficiency such as generating test signals can also be correspondingly increased, which effectively solves the problem that the operating capacity of the conventional test device is limited to the performance of the central controller.

The above description of the contents of this disclosure and the description of the following embodiments are used to demonstrate and explain the spirit and principle of the present invention, and provide a further explanation of the scope of the patent application of the present invention.

The detailed features and advantages of the present invention are described in detail in the following embodiments. The content is sufficient for any person skilled in the art to understand and implement the technical contents of the present invention. Anyone skilled in the relevant art can easily understand the related objects and advantages of the present invention. The following examples further illustrate the viewpoints of the present invention in detail, but do not limit the scope of the present invention in any way.

Please refer to FIG. 1, which is a schematic diagram of a test device according to an embodiment of the present invention. As shown in FIG. 1, the test apparatus has a plurality of test circuit boards 1, and each test circuit board 1 has pins, such as pins pin1 to pin3. Pins 1 to 3 of each test circuit board 1 are electrically connected to a transmission line, respectively. That is, the pin 1 of each test circuit board 1 is electrically connected to the transmission line tr1, the pin 2 of each test circuit board 1 is electrically connected to the transmission line tr2, and the pin 3 of each test circuit board 1 is electrically Connected to transmission line tr3. The transmission line is, for example, a cable, a trace on the backplane, or other components suitable for transmitting signals. The plurality of test circuit boards 1 transmit signals to each other through pins pin1 to pin3 and transmission lines tr1 to tr3, so as to simultaneously generate test signals to test the test object DUT. For example, the user can preset one of the plurality of test circuit boards 1 as a master through software, and the other test circuit boards 1 are preset as server boards, so that the master control board generates synchronization. The signals are transmitted to each servo board through the pins pin1 to pin3 and the transmission lines tr1 to tr3, so that all the test circuit boards 1 generate test signals synchronously to test the test object DUT. Alternatively, only a part of the test circuit board 1 may be used to synchronously generate test signals to test the test object DUT according to requirements, which is not limited in this embodiment.

In other words, each test circuit board 1 in this embodiment has an independent operation capability, and functions of reading data from an external memory and generating a test signal to a test object DUT. However, when there are many pins to be tested in the test object DUT and multiple test signals need to be generated correspondingly, multiple test circuit boards 1 can be grouped into the pin 1 through pin 3 and the transmission lines tr 1 through tr 3 as described above. A set of test circuits that operate synchronously can test such DUTs with more pins to be tested without the need to provide a more powerful central control circuit board. In addition, since each test circuit board 1 can operate independently, when multiple test circuit boards 1 are grouped to operate synchronously to generate a test signal, the test circuit formed by the test circuit board 1 accesses data, schedules, and generates data. The test signal and other work efficiency can be enhanced at the same time, which solves the problem that the operating capability of the conventional test device is limited by the performance of the central control circuit board.

To implement the above-mentioned test device, a test circuit board 1 according to an embodiment of the present invention has a structure as shown in FIG. 2. As shown in FIG. 2, each test circuit board 1 of the test device has a buffer memory module 11, a memory interface controller 13, a test vector generator 15, and a transmission circuit 17, and each test circuit board 1 is connected to The dynamic random access memory 2 is used to interact with the dynamic random access memory 2 according to instructions. Among them, the dynamic random access memory 2 is a memory component other than the test circuit board 1, such as a double data rate synchronous dynamic random access memory (DDR SDRAM), Dynamic random access memory (DDR2 DRAM, DDR3 DRAM or DDR4 DRAM, etc.) or other suitable dynamic random access memory. The dynamic random access memory 2 stores a test vector designed by a user, so that the test circuit board 1 accesses the test vector to the memory address of the dynamic random access memory 2 according to a system instruction.

The buffer memory module 11 of the test circuit board 1 is configured to interact with the external random access memory 2 according to instructions. The buffer memory module 11 includes at least a buffer memory 111 and a memory controller 113. The buffer memory 111 is, for example, a cache memory or other temporary memory with high access speed; and the memory controller 113 is connected to the buffer memory 111, the memory interface controller 13, The reading and writing interface of the test vector generator 15 and the random access memory 2, the memory controller 113 is composed of a circuit. The memory controller 113 receives the read and write instructions from the memory interface controller 13 and issues a write command from the memory interface controller 13 according to the test vector instructions written in the test vector generator 15 by the user in advance. Go to the dynamic random access memory 2 or store the test vector designed by the user in the dynamic random access memory 2.

The memory interface controller 13 of the test circuit board 1 stores the read and write instructions that the test circuit board 1 can execute on the dynamic random access memory 2 and the test vector must be written into the dynamic state in the buffer memory module 11 When the random access memory 2 or the test vector is read from the dynamic random access memory 2, the memory interface controller 13 provides a read instruction or a write instruction for performing the above-mentioned actions. The memory interface controller 13 is composed of a circuit.

The test vector generator 15 of the test circuit board 1 reads the test vectors stored in the buffer memory 11 when the test is started, and generates a test signal of the test object DUT accordingly. The test vector generator 15 may be a circuit or a microcontroller. (Micro Control Unit), which includes a test microinstruction processing module 151 and a test pattern data processing module 153, and the test vector includes a test microinstruction (such as a group of commands to be executed) and test pattern data (such as a logic Value pattern). The test vector generator 15 can decode test microinstructions according to the test vectors stored in the buffer memory 111 of the buffer memory module 11, and execute microinstruction actions such as Repeat, Branch, etc. to generate pattern data And further generate a test signal for the test object DUT. In detail, the test microinstruction processing module 151 sequentially executes the above test microinstructions, for example, referring to the memory address in the test microinstructions, the buffer memory module 11 is required to provide the test vectors temporarily stored in the buffer memory 111. Or, the memory controller 113 is further requested to read the test vector from the dynamic random access memory 2 and stored in the buffer memory 111, or for example, the test pattern data processing module 153 is required to operate according to the test microinstruction. The test pattern data processing module 153 executes the pattern data processing mode in the test microinstruction according to the instructions of the test microinstruction processing module 151, performs a specific processing algorithm on the test pattern data, and generates a test signal of the test object DUT. In other words, the test vector generator 15 executes the test microinstructions in the test vector, reads the next test vector required to execute the test microinstruction according to the memory address contained in the test microinstruction to the buffer memory module 11, and The test pattern data in each test vector is sequentially transmitted to the test pattern data processing module 153 to generate a test signal. Therefore, the above-mentioned operation does not include a compile program of the conventional CPU when executing the program.

In detail, the pattern data processing mode of the test microinstruction is, for example, a normal function pattern data processing method, a scan mode (SCAN Function) pattern data processing method, or an algorithm pattern generation algorithm (Algorithm Logic Pattern Generate, ALPG) pattern. Data processing method, logical pattern buffer mode (Data-Buffer) pattern data processing method or other pattern data processing method. For example, when the test pattern data processing method is the normal mode, the set test output endpoints can effectively use each test vector, and it is specifically stated that each test vector includes all test output endpoints of the circuit board 1. If the test vector uses the scan mode, all the pattern data of the test vector is divided and used for the set test output. In other words, changing the test vector will give a special test microinstruction repeat command. When the test pattern data is generated based on the logic pattern calculation mode, special ALPG micro instructions can be used to generate the test test signal of the test object DUT through the logic pattern calculation. At this time, the test signal has better test efficiency for testing the memory element. In other words, the test micro-instruction of the test vector allows the test pattern data to generate a dedicated test signal type. In this way, one test device can generate test signals with multiple test functions to test different types or different test objects, but not limited to this.

The transmission circuit 17 of the test circuit board 1 is used to connect the aforementioned pins pin1 to pin3 to transmit messages to and from other test circuit boards 1 through the transmission lines tr1 to tr3. In detail, when the test circuit board 1 is used as the main control board, it needs to actively provide test-related control signals to other test circuit boards. The transmission circuit 17 of this test circuit board 1 (the main control board) will be based on The configuration signal outputs the test control signal from the specific pins pin1 to pin3 to the transmission lines tr1 to tr3. Conversely, when the test circuit board 1 is used as a servo board, the transmission circuit 17 of the test circuit board 1 (servo board) passively receives the test control signal on the transmission line, and each test circuit board 1 (servo board) The transmission circuit 17 may also decide to receive or ignore the test control signals on the transmission lines tr1 to tr3 according to the configuration signal. Therefore, the plurality of test circuit boards 1 of the test device of the present invention can use the test control signals as a starting reference for synchronous operation, so that all the test circuit boards 1 generate test signals synchronously to test the test object DUT.

In the actual operation of the test device, when the test circuit board 1 serving as the main control board is configured to output the test control signal according to the configuration signal, or when the test circuit board 1 serving as the servo board receives the test according to the configuration signal When controlling the signals, the test vector generator 15 of the test circuit board 1 must obtain the test vectors in the dynamic random access memory 2 in order to generate the test signals. At this time, the test vector generator 15 requires the buffer memory module 11 to quickly read the dynamic random access memory 2 and read the used memory block to the buffer of the buffer memory module 11 In memory 111. Therefore, when the test vectors required by the test vector generator 15 are temporarily stored in the buffer memory 111, the memory controller 113 does not need to read the test vectors from the dynamic random access memory 2 repeatedly. The data reading speed of the test vector generator 15 can be effectively improved, and a mechanism for data reuse can also be provided when the loop instruction of the test microinstruction is executed. Subsequently, the test vector generator 15 of the test circuit board 1 receives the test vectors stored therein by the buffer memory 111 of the buffer memory module 11 and generates a test signal according to the test pattern data provided by the test microinstruction, wherein the test vector generates The operation modes of the test micro-instruction processing module 151 and the test pattern data processing module 153 in the processor 15 are as described above, so they are not repeated here.

Please refer to FIG. 2 and FIG. 3 together. FIG. 3 is a functional block diagram of a test vector generator according to another embodiment of the present invention. As shown in the figure, compared with the test vector generator 15 of the previous embodiment, the test vector generator 35 of this embodiment has a first-in-first-out memory 353. In other words, the test vector generator 35 includes a test micro-instruction processing module 351, a first-in-first-out memory 353, and a test pattern data processing module 355. When the test vector generator 35 operates, the test microinstruction processing module 351 temporarily stores the generated test vector in the first-in-first-out memory 353 to change the processing speed of the test micro-instructions by using the characteristics of the first-in-first-out memory 353. In order to test the processing speed of the pattern data, the FIFO memory 353 sequentially provides the test vectors to the test pattern data processing module 355. In the example of the figure, the test pattern data processing module 353 may first pass the test vector through multiple calculation paths (for example, the four calculation paths shown in FIG. 3: the first calculation path to the fourth calculation path) to generate the test vector. Various test signals. Subsequently, the demultiplexer 357 selects a signal according to the calculation of the test microinstruction, and selects one of the above-mentioned multiple test signals for testing the DUT, but not limited to this. In other embodiments, one of a plurality of test vectors may be executed first, and then the test vector may be used to generate a test signal according to the test microinstruction and test pattern data. Those with ordinary knowledge in the technical field may design according to actual needs and conditions, and this embodiment is not limited.

Next, please refer to FIG. 1 and FIG. 2 together. In practice, the speed at which the memory controller 113 reads each test vector from the dynamic random access memory 2 is slower than the processing speed of the test microinstructions of the test vector generator 15. Therefore, the test vector read from the dynamic random access memory 2 is stored in the buffer memory 111 by the buffer memory module 11 provided by the present invention, and is transferred from the random access memory 2 through the memory controller 113. The amount of data in the test vector is read, and the speed at which the test vector generator 15 reads the test vector is determined by the memory controller 113 reading the test vector from the dynamic random access memory 2 in advance.

Specifically, in one embodiment, the speed at which the test controller reads the test vector from the dynamic random access memory 2 and stores it in the buffer memory 111 in accordance with the memory controller 113, and the test vector generator 15 controls the speed through the memory. There is a gap between the speed at which the processor 113 reads the test vectors in the buffer memory 111, and the memory access data width of the memory controller 113 is designed asymmetrically. Taking the width of the data stored in the buffer memory module 11 as 4 times the width of the read data as an example, it is assumed that the width of the data read by the memory controller 113 is 512 bits, and the width of the data read by the test vector generator 15 is The fetched data width is 128 bits, so the buffer memory 111 needs to use a data width of 512 bits, and the read buffer memory 111 needs to use a read data width of 128 bits. Thereby, by using the high data width when the dynamic random access memory 2 is read, the high-speed data amount required by the test vector generator 15 can be satisfied, and the speed and reading of the test vector into the buffer memory 111 can be effectively reduced. The difference between the speeds of the test vectors in the buffer memory 111 is buffered.

In another embodiment, the memory controller 113 quickly reads a block of test vector intervals from the dynamic random access memory 2 in advance to respond to the test vector generator 15 reading the buffer through the memory controller 113. The speed of the test vector in the memory 111. For example, when the test of the test vector generator 15 is started, the first test vector request is issued to the memory controller 113. At this time, the buffer memory module 11 quickly reads a block test vector interval from the dynamic random access memory 2 through the memory controller 13 and stores the block test vector interval in the buffer memory 111. . Then, the test vector interval of the next block is read in advance. That is, after the buffer memory module 11 quickly reads the test vector from the dynamic random access memory 2 through the memory controller 113, the buffer memory module 11 will read the dynamic random access memory according to the read The memory address of 2 predicts the next test vector to be read from dynamic random access memory 2. The predicted test vector will be stored in the buffer memory 111 along with the memory address of the read dynamic random access memory 2 so that the speed of the buffer memory module 11 to read the dynamic random access memory 2 can meet the test. The speed at which the vector generator 15 reads the test vectors.

When the test circuit board 1 is applied to the above two embodiments at the same time, the buffer memory module 11 reads four test vectors from the dynamic random access memory 2 at a time through the memory controller 113, and then according to the four tests The memory address of the dynamic random access memory 2 read by the test vector predicts the next four test vectors, and the predicted four test vectors and the memory address of the four read dynamic random access memory 2 are stored. The buffer memory 111 responds to the speed at which the test vector generator 15 reads the test vectors.

In yet another embodiment, when the test vector generator 15 reads the test vectors stored in the buffer memory 111 and the test microinstruction processing module 151 then executes the microinstruction loop instructions such as the repeat instruction, then The test microinstruction processing module 151 must repeatedly transmit the test vector to the test pattern data processing module 153. At this time, by using the mechanism of the test vector stored in the buffer memory 111 again, the test vector can be quickly transferred from the buffer memory 111 to the test pattern data processing module 153 without the need for the dynamic random access memory again. 2 Read this test vector. In other words, when the test microinstruction obtained by the test vector generator 15 from the test vector stored in the buffer memory is a loop instruction, the buffer memory module 11 predicts the next test vector to be read from the random access memory 2 Whether it is already in the buffer memory 111. If yes, the test vector continues to be read from the buffer memory 111 to the test vector generator 15, so the existing test vectors can be quickly and directly read from the buffer memory 111 to deal with the test vector generator 15 from The speed at which the buffer memory 111 reads the test vectors.

If the above-mentioned data reuse mechanism is combined with the foregoing buffer memory module 11 to read a block of test vector intervals from the dynamic random access memory 2 in advance, the test vector generator 15 executes a loop according to the test microinstruction. When instructed, the memory controller 113 determines whether the buffer memory 111 has a position of the next piece of data in the test vector generator 15. In other words, the buffer memory module 11 does not need to read the next block test vector interval from the dynamic random access memory 2 according to the position of the next piece of data.

Also, in another embodiment, the test vector generator 15 executes the conditional instruction according to the test microinstruction, reads the conditional jump address from the dynamic random access memory 2, and the test vector generator 15 executes the conditional instruction according to the test microinstruction. One of the two conditional branch instructions of the executed conditional instruction reads a block test vector interval of the dynamic random access memory 2 at the conditional jump address. In other words, when the test vector generator 15 reads the test vector from the buffer memory 111, the test vector generator 15 predicts the next test vector to be accessed from the dynamic random access memory 2 as indicated by one of the conditional branch instructions. Conditional jump address. For example, when the test vector generator 15 predicts that the condition is satisfied, the memory controller 113 is required to read the test vector when the condition is satisfied from the dynamic random access memory 2 in advance and store the test vector in the buffer memory 111. When the condition instruction is true, the test vector generator 15 can quickly obtain the test vector to be read when the condition is satisfied from the buffer memory 111.

If the execution mechanism of the above-mentioned conditional instruction is combined with the manner in which the foregoing buffer memory module 11 reads a block of test vector intervals from the dynamic random access memory 2 in advance, when the test vector generator 15 executes the conditions according to the test microinstruction When the test vector memory address of the instruction is used to read the first block test vector interval located at the first test vector address from the dynamic random access memory 2, the test vector generator 15 may perform the test microinstruction execution condition. The conditional branch instruction when the instruction is established reads the second block test vector interval from the dynamic random access memory 2 and stores it in the buffer memory 111 together with the first block test vector interval.

To sum up, the embodiment of the present invention provides an independent operation capability of each test circuit board 1, that is, each test circuit board 1 can read the test vectors stored in the dynamic random access memory 2 and perform test according to the test. The vector generates a test signal to send to the test object DUT. When multiple test circuit boards 1 pass related control signals to each other and are grouped into a group of test circuits, the pins of each test circuit board 1 in the group for connecting to the test object DUT belong to this test circuit group. The number of signals for the test circuit group to perform a synchronous test on the DUT under test increases. Furthermore, since each test circuit board has independent working capabilities, when multiple test circuit boards are grouped to work together to generate test signals, the test circuit group accesses data, schedules capabilities, generates test signals, etc. Work efficiency can be enhanced at the same time. Therefore, when the test object DUT is changed and more test pins are required, with the test device of the present invention, it is only necessary to add an additional test circuit board 1 and software to compare the additional test circuit board with the original test. By grouping the circuits, a test signal can be generated synchronously with the original test circuit. Therefore, the test device and the test circuit board 1 of the present invention can effectively solve the problem that the operating ability of the conventional test device to generate test signals is limited by the performance of the central control circuit board, and it is not necessary to perform any hardening for different test objects DUT Physical change.

Although the present invention is disclosed in the foregoing embodiments, it is not intended to limit the present invention. Changes and modifications made without departing from the spirit and scope of the present invention belong to the patent protection scope of the present invention. For the protection scope defined by the present invention, please refer to the attached patent application scope.

1 Test circuit board 11 Buffer memory module 111 Buffer memory 113 Memory controller 13 Memory interface controller 15 Test vector generator 151 Test micro-instruction processing module 153 Test pattern data processing module 17 Transmission circuit 2 Dynamic random Access memory 35 Test vector generator 351 Test micro-instruction processing module 353 FIFO memory 355 Test pattern data processing module 357 Demultiplexer DUT Test object pin1 ～ pin3 pins tr1 ～ tr3 transmission line

FIG. 1 is a schematic diagram of a testing device according to an embodiment of the present invention. FIG. 2 is a functional block diagram of a test circuit board according to an embodiment of the present invention. FIG. 3 is a functional block diagram of a test vector generator according to another embodiment of the present invention.

Claims (6)

A test device includes a plurality of test circuit boards, and each test circuit board is used to connect a dynamic random access memory to read a test vector in the dynamic random access memory and generate a test signal, each of which Each of the test circuit boards has an independent operation capability, and each of the test circuit boards includes: a buffer memory module for electrically connecting to the dynamic random access memory and for using the dynamic random access memory Read and store multiple test vectors; a memory interface controller connected to the buffer memory module, and the memory interface controller stores at least a read command for the buffer memory module to randomly store from the dynamic memory; Fetch memory to read the test vectors; a test vector generator connected to the buffer memory module, and reading the plurality of test vectors from the buffer memory module according to the memory position in a test microinstruction A test signal is generated from the read test vector; and a transmission circuit is connected to the test vector generator, and the transmission circuit is used to send the test vector to generate A test control signal generated or used to receive another test control signal and send it to the test vector generator; wherein one of the plurality of test circuit boards is a main control board, and the rest of the plurality of test circuit boards For at least one servo board, the transmission circuit of the main control board sends a test control signal, and the transmission circuit of the at least one servo board receives the test control signal, wherein the test control signal is started as a synchronous operation of the plurality of test circuit boards Benchmark. The test device according to claim 1, wherein the test microinstruction is written in the test vector generator in advance, or is contained in the read test vector. The test device according to claim 2, wherein the test vector generator includes a test microinstruction processing module and a test pattern data processing module, the test vector further includes a test pattern data, and the test microinstruction processing module It executes the test microinstruction to read the test vector in the buffer memory module and controls the test pattern data processing module. The test pattern data processing module executes an algorithm on the test pattern data according to the test microinstruction. To generate the test signal. The test device according to claim 1, wherein the read data width of the buffer memory module is greater than the read data width of the test vector generator. The test device according to claim 1, wherein the test vector generator includes a test microinstruction processing module, a first-in-first-out memory, and a test pattern data processing module connected in sequence. The test vector further includes a Test pattern data. The test microinstruction processing module executes the test microinstruction to read the test vector in the buffer memory module and stores the test vector in the FIFO memory. The FIFO memory sequentially stores The stored test vector is provided to the test pattern data processing module, and the test pattern data processing module executes various algorithms on the test pattern data according to the test microinstruction to generate a plurality of test signals including the test signal. The test device according to claim 5, wherein the test vector generator further includes a demultiplexer, the demultiplexer is connected to the test pattern data processing module, and the demultiplexer is based on the test microinstruction. A calculation selects a signal and outputs one of the plurality of test signals.