TW201913124A - Method for testing wafer level electronic component including a preliminary step and a detecting step - Google Patents

Abstract

A method for testing a wafer level electronic component is suitable for testing a wafer having a plurality of electrical contacts. The method also includes a preliminary step of preparing a test device, and a detecting step of performing tests using the test device. The test device includes a probe card having a plurality of perforations spaced apart and parallel to each other and penetrating through, and a plurality of probes respectively positioned in the perforations to define a plurality of axes respectively passing through the perforations along the axis. The probes are respectively disposed along the axes. Each perforation is an aperture of single size which is not smaller than a distance between the axes of two adjacent perforations, which equals to the spacing of the smallest distance of the two adjacent electrical contacts. When the test is being performed, the electrical contacts are in contact with the probes to form electrical connections.

Description

Wafer-level electronic component testing method

The invention relates to a test method, in particular to a test method for wafer level electronic components.

Before the electronic chip is assembled or shipped, it is necessary to use the test device to perform various electrical performance tests to ensure that the electronic components function normally and can operate normally. At present, in order to meet the demand of electronic products on the market, it is an inevitable trend to reduce the volume and improve the precision. Therefore, the density of electronic components and circuits on the electronic chip to be matched is higher and higher, and even the electronic component spacing must be achieved in the process. The "Wafer Level Chip Scale Package" below 0.5 mm (mm) is indeed in line with market demand. When testing electronic wafers in wafer level package, it must be tested in the test device and test method to be able to reliably detect the function of the fabricated electronic chip.

Referring to FIG. 1 , a prior art test apparatus 1 includes a base 11 made of metal and a plurality of spring probes 12 disposed in the base 11 . The test element 100 is functionally tested by electrically connecting the spring probe 12 to a test component 100, that is, electrically conductive. Since the base body 11 is made of metal, by shielding the electromagnetic wave from the metal material, each spring probe 12 can be shielded by the seat body 11 to prevent the spring probes 12 from interfering with each other. This improves test performance.

However, in order to position the spring probes 12 in the seat body 11, the seat body 11 includes a plurality of through holes 111 for receiving the spring probes 12, respectively, but each of the through holes 111 is by radial direction. The wide and narrow variation limits the respective spring probes 12, and the width and narrowness of the perforations 111 are designed such that the spacing of the spring probes 12 must match the width of the widest portion of the perforations 111, and cannot be further The reduction, thus affecting the test limits of the test device 1, makes it difficult to meet the testing requirements of wafer-scale packaged electronic wafers.

Referring additionally to FIG. 2, when each spring probe 12 is assembled, since the design of the width and width of each of the through holes 111 is difficult to process therein, a plurality of insulating rings are usually placed on the spring probe 12 first. 19. The spring probe 12 is placed in the corresponding through hole 111. However, the test requirements of the electronic wafers in the wafer level package are also considered. The dimensions of the spring probes 12 and the through holes 111 are relatively small, so that the fine operation of the insulating rings 19 is relatively difficult. Implementation, the technical level of the relevant process is thus improved, and also affects the yield at the time of manufacture.

Accordingly, it is an object of the present invention to provide a test method for wafer level electronic components that meets the needs of precision testing.

Therefore, the method for testing a wafer level electronic component of the present invention is suitable for testing an electronic component formed on a wafer having a substrate portion and a plurality of electrical contact portions disposed on the substrate portion. The spacing between the smallest adjacent ones of the electrical contacts is less than or equal to a wafer level package scale equal to 0.5 mm, the test method of the electronic component includes a preliminary step of preparing a test device, and a test device is used A test step to test the wafer.

In the preliminary step, the test device includes a probe card having a plurality of perforations that are parallel to each other and are penetrating, and a plurality of probes respectively positioned in the perforations. The probe card is made of metal. Defining a plurality of axes respectively passing through the perforations along an axis, the probes being respectively disposed along the axis, each perforation being a single-sized aperture having a distance between at least two adjacent perforations Is equal to the spacing of the smallest of the two electrical contacts.

In the detecting step, the wafer is tested using the test device, and the electrical contacts are in contact with the probes to form an electrical connection.

The effect of the present invention is that since the probe card is made of a metal material and each of the perforations has a single-size aperture, when the test device is used to test the wafer, the At the wafer level package scale, the test device having the smaller aperture is used, and the perforation design can be used to shorten the distance between the probes, so that the probes can be matched with the wafer. The scale of the electrical contacts is required for precision testing with a small scale.

Before the present invention is described in detail, it should be noted that in the following description, similar elements are denoted by the same reference numerals.

Referring to FIG. 3 and FIG. 4, an embodiment of a method for testing a wafer level electronic component according to the present invention is applicable to testing an electronic component formed on a wafer 9 having a substrate portion 91, and The plurality of electrical contacts 92 are provided on the substrate portion 91. The spacing between the smallest of the two electrical contacts 92 is less than or equal to a wafer level package scale of 0.5 mm. This embodiment includes a preliminary step 31 of preparing a test device 4, and a detection step 32 for testing the wafer 9 using the test device 4.

In the preliminary step 31, the testing device 4 includes a probe card 41 having a plurality of through-holes 411 that are parallel to each other and penetrating in a plurality, and a plurality of probes 42 respectively positioned in the holes 411, and a plurality of separate sets The insulating layers 43 of the probes 42 are positioned in the through holes 411. The probe card 41 has an upper body 401 and a lower base 402. The through hole 411 extends through the upper base 401 and the lower base 402. A plurality of axes L passing through the perforations 411 are defined along the axis, respectively, and the probes 42 are respectively disposed along the axis L.

Wherein, since each of the through holes 411 has a single-size aperture, when the adjacent through holes 411 are closely arranged, the pitch of the probes 42 positioned in the holes 411 can be as thin as possible. Underneath, only the hole radius is almost equal to twice, thereby effectively reducing the detection scale that the test device 4 can match. The distance d between the axes L of at least two adjacent perforations 411 of the perforations 411 is equal to the spacing of the smallest of the two adjacent electrical contacts 92 such that the probes positioned in the perforations 411 42. The electrical contacts 92 that are fabricated on a wafer level package scale are indeed contacted. Therefore, in order to match the wafer level package dimensions, the minimum distance between the axes L of any two adjacent vias 411 of the through holes 411 is less than or equal to 0.5 mm, so that the minimum distance between adjacent probes 42 is also 0.5 mm. scale.

In the detecting step 32, the electrical contact portions 92 on the wafer 9 are respectively in contact with the probes 42 to form an electrical connection, and cooperate with a crystal that is electrically connected to the probes 42. The circular test substrate 5 detects the function of the electrical contact portions 92 on the wafer 9, and ensures that the electronic components formed by the electrical contact portions 92 on the wafer 9 are good. It should be particularly noted that since the probe card 41 of the testing device 4 is made of a metal material, the shielding property of the metal material for electromagnetic waves can be surely reduced when the probes 42 transmit electrical signals. The detection performance of the test device 4 is effectively improved.

Referring to FIG. 5 and FIG. 4, each probe 42 has a side surface 421 and two needle ends 422 respectively at opposite ends, and each insulating layer 43 completely covers the side peripheral surface of the corresponding probe 42. 421, but does not cover the needle ends 422. With the insulating layer 43, the electrical signals transmitted in each of the probes 42 can be isolated to prevent the electrical signals from affecting the electrical signals of the other probes 42 via the probe card 41 made of metal. The insulating layers 43 do not cover the needle ends 422, so that the probes 42 can still reliably contact the electrical contacts 92 to avoid affecting the performance of the detection. It should be particularly noted that since the through holes 411 all have a single aperture design, it is advantageous to fill the insulating layers 43 in the holes 411 before assembling the probes 42 as compared with the drawings. In the processing of the plurality of insulating rings 19 shown in FIG. 2, the process can be simplified, and the manufacturing yield is also improved.

In addition, in the general test device 4, the probes 42 can be divided into three functions of providing power, transmitting signals, and grounding, that is, at least one of the probes 42 is used for providing power, at least one of which is performed. Ground, the rest is used as a signal transmission. Since the probe 42 is used for grounding, it is required to directly contact the probe card 41 to generate a grounding effect. When the probe 42 is used to supply power, a relatively good insulation effect is required to avoid a short circuit. The insulating layer 43 can also completely cover the side peripheral surface 421 of the probe 42 for supplying power to avoid short circuit. The situation happened.

Referring to FIG. 6, another type of the testing device 4 is different from the embodiment shown in FIG. 5 in that each insulating layer 43 is in partial contact with the side peripheral surface 421 of the corresponding probe 42 to locate the probe. The needle 42 forms an air gap 8 between the probe 42 and the probe card 41. As shown in FIG. 6 , although the air gap 8 is formed, the same effect as the design as illustrated in FIG. 5 can be achieved. Besides, the size of the air gap 8 can be used for adjustment. The impedance matching of each of the probes 42 is substantially a single hole diameter through the perforation 411 of the probe card 41, and the impedance matching of each probe 42 can be easily adjusted, thereby adjusting the action. The impedance matching can be made more precise and stable, and the test performance of the testing device 4 is effectively improved.

Referring to FIG. 7, the probe card 41 of the testing device 4 further includes a guiding member 409 disposed on the upper housing 401, which can be matched with the wafer dicing block 9'. The type of the wafer dicing block 9 ′ is surrounded by the accommodating space 400 for supporting the substrate portion 91 . When the sizes of the wafer dicing pieces 9' are different, the guiding members 409 of different sizes can be replaced, so that the accommodating space 400 is sized to match the wafer dicing 9' to be tested. Since the probes 42 are facing the accommodating space 400 and the positions are respectively corresponding to the electrical contact portions 92, when the wafer dicing block 9' is placed in the accommodating space 400, a pressing die can be matched. Group 6 applies a pressing force to the wafer dicing 9' to ensure that the electrical contacts 92 are in positive contact with the probes 42.

In summary, in the test method of the wafer level electronic component of the present invention, in the test device 4 prepared in the preliminary step 31, each of the through holes 411 of the probe card 41 is a single hole of a single size aperture. It is relatively easy to reduce the distance between the axes L of the perforations 411 to reduce the scale that the probes 42 can fit. Therefore, the test device 4 is used to test the wafer 9 in the detecting step 32. When the test device 4 is prepared according to the wafer level package scale, the distance between the probes 42 disposed in the through holes 411 can be matched with the required dimensions, and the electrical contact portions 92 are surely contacted to perform the scale comparison. The small high-precision detection makes it possible to achieve the object of the present invention.

However, the above is only the embodiment of the present invention, and the scope of the invention is not limited thereto, and all the equivalent equivalent changes and modifications according to the scope of the patent application and the patent specification of the present invention are still The scope of the invention is covered.

19‧‧‧Insulation ring

31‧‧‧Preparatory steps

32‧‧‧Test steps

4‧‧‧Testing device

400‧‧‧ accommodating space

401‧‧‧The upper body

402‧‧‧ lower body

409‧‧‧Guide

41‧‧‧ Probe Card

411‧‧‧Perforation

42‧‧‧Probe

421‧‧‧ side circumference

422‧‧‧needle end

43‧‧‧Insulation

5‧‧‧ Wafer test substrate

6‧‧‧Compression module

8‧‧‧ Air gap

9‧‧‧ wafer

91‧‧‧Parts Department

92‧‧‧Electrical contact

9'‧‧‧ wafer dicing

D‧‧‧distance

L‧‧‧ axis

Other features and effects of the present invention will be apparent from the following description of the drawings, wherein: Figure 1 is a cross-sectional view showing a prior art test device and the test limits of the test device; Figure 2 is a schematic view FIG. 3 is a flow chart illustrating an embodiment of a test method for wafer level electronic components of the present invention; FIG. 4 is a cross-sectional view, and FIG. 1 is a preliminary step and a test device used in a detecting step; FIG. 5 is a partially enlarged view showing the effect of the embodiment; FIG. 6 is a partially enlarged view showing another embodiment of the test device; Figure 7 is a cross-sectional view showing a test apparatus capable of testing electronic components that are segmented on a wafer.

Claims (7)

A method for testing a wafer level electronic component, which is suitable for testing an electronic component formed on a wafer, the wafer having a substrate portion and a plurality of electrical contacts disposed on the substrate portion, the same The spacing between the smallest adjacent ones of the sexual contacts is less than or equal to a wafer level package scale equal to 0.5 mm. The test method of the electronic component comprises: a preliminary step of preparing a test device, the test device comprising a plurality of a probe card having mutually parallel perforations and perforations, and a plurality of probes respectively positioned in the perforations, the probe card being made of a metal material defining a plurality of axes respectively passing through the perforations along the axis The probes are respectively disposed along the axes, each of the perforations being a single-sized aperture, and the distance between the axes of at least two adjacent perforations in the perforations is equal to the smallest phase of the electrical contacts. a spacing between the two; and a detecting step of testing the wafer using the test device, the electrical contacts being in contact with the probes to form an electrical connection. The method of testing a wafer level electronic component according to claim 1, wherein a minimum distance between axes of any two adjacent perforations is less than or equal to 0.5 mm. The method of testing a wafer level electronic component according to claim 1, wherein the testing device further comprises a plurality of insulating layers respectively disposed in the through holes for positioning the probes. The method for testing a wafer level electronic component according to claim 3, wherein each probe has one side peripheral surface and two needle end portions respectively located at opposite ends, and each insulating layer is completely coated with the corresponding probe. The side of the perimeter, but does not cover the endpoints. The method for testing a wafer level electronic component according to claim 3, wherein each probe has one side peripheral surface and two needle end portions respectively located at opposite ends, each insulating layer being a side circumference of the corresponding probe The face is in partial contact to position the probe and form an air gap between the probe and the probe card. The method for testing a wafer level electronic component according to claim 1, wherein the probe card has an upper body and a lower body, and the through hole is penetrated through the upper body and the lower body. The test method of the wafer level electronic component of claim 6, wherein the probe card further has a guiding member connected to the upper seat body, and the guiding member and the upper seat body together surround one for receiving The accommodation space of the wafer.