CN109557444A - The test method of wafer scale electronic building brick - Google Patents

The test method of wafer scale electronic building brick Download PDF

Info

Publication number
CN109557444A
CN109557444A CN201710879888.4A CN201710879888A CN109557444A CN 109557444 A CN109557444 A CN 109557444A CN 201710879888 A CN201710879888 A CN 201710879888A CN 109557444 A CN109557444 A CN 109557444A
Authority
CN
China
Prior art keywords
probe
perforation
wafer
building brick
electronic building
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201710879888.4A
Other languages
Chinese (zh)
Inventor
陈冠忠
林政辉
孙家彬
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
WinWay Technology Co Ltd
Original Assignee
WinWay Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by WinWay Technology Co Ltd filed Critical WinWay Technology Co Ltd
Priority to CN201710879888.4A priority Critical patent/CN109557444A/en
Publication of CN109557444A publication Critical patent/CN109557444A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851Testing of integrated circuits [IC]
    • G01R31/2886Features relating to contacting the IC under test, e.g. probe heads; chucks

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

A kind of test method of wafer scale electronic building brick has multiple wafers for being electrically connected with contact portion suitable for testing one, and includes the preliminary step of one test device of a preparation and the detecting step that one is tested using the test device.The test device includes one with multiple probe cards for being spaced each other perforation parallel and in penetration state and multiple probes being respectively positioned in the perforation, and each perforation defines the axis extended along its axle center, and the probe is arranged along the axis respectively.Each perforation is the aperture in single size, and at least there are two the distances between the axis of adjacent perforated, equal to the spacing for being electrically connected with minimum adjacent the two in contact portion.When being tested, the portion in electrical contact contacts with the probe respectively and forms electrical connection.

Description

The test method of wafer scale electronic building brick
Technical field
The present invention relates to a kind of test methods, more particularly to a kind of test method of wafer scale electronic building brick.
Background technique
Electronic chip needs to carry out the test of every electrical property efficiency using test device, before assembling or shipment to ensure The function of the electronic building brick is normal and can operate really.Currently in order to reducing body in response to the demand of electronic product in the market Accumulating and improving precision is inevitable trend, therefore the density of electronic building brick and circuit on electronic chip joined together is all It is higher and higher, or even electronic building brick spacing must be reached in 0.5 millimeter (mm) " wafer scale Scale Package below on processing procedure (Wafer Level Chip Scale Package) ", is just accorded with the demands of the market really.And it is directed to wafer scale Scale Package Electronic chip when being tested, also must be in response to being just able to detect institute really in test device and test method The function of electronic chip is made.
Refering to fig. 1, it is a kind of existing test device 1, with pedestal 11 made of metal and multiple is set to this comprising one Spring probe 12 in pedestal 11.It is electrically connected through the spring probe 12 with a test suite 100 formation, it can be electrically to lead Whether logical, functional test is carried out to the test suite 100.Since the pedestal 11 is to utilize metal material pair made by metal Shielding electromagnetic waves property can make shielding action of each spring probe 12 by the pedestal 11, prevent the spring probe 12 mutual interference, improve test performance whereby.
However, the pedestal 11 includes multiple for dividing in order to positively locate the spring probe 12 in the pedestal 11 The perforation 111 of the spring probe 12 is not accommodated, but each perforation 111 is to limit corresponding spring by radial width variation Probe 12, and the width of the perforation 111 changes design, but also the spacing of the spring probe 12, must cooperate the perforation The diameter of 111 widest portions is wide, can not further reduce, thus affects the test limits of the test device 1, it is difficult to match synthetic The testing requirement of the electronic chip of circle grade Scale Package.
With additional reference to Fig. 2, when assembling each spring probe 12, because the width variation of each perforation 111 is set Meter, it is more difficult to be processed wherein, therefore be usually that multiple dead rings 19 are first arranged on the spring probe 12, just by the bullet Spring probe 12 is set in corresponding perforation 111.However, it is also contemplated that the survey of the electronic chip of cooperation wafer scale Scale Package The scale of examination demand, the spring probe 12 and the perforation 111 certainly will be all fairly small, therefore is arranged the essence of the dead ring 19 Spy's industry is also relatively difficult to implement, and the technical level of related process thus improves, and also influences yield when manufacture.
Summary of the invention
The purpose of the present invention is to provide a kind of test sides of wafer scale electronic building brick for being able to cooperation precision measurement demand Method.
The test method of wafer scale electronic building brick of the present invention, is surveyed suitable for being formed by electronic building brick to a wafer There is a baseplate part and multiple be set on the baseplate part to be electrically connected with contact portion for examination, the wafer.It is described to be electrically connected with minimum in contact portion Both adjacent spacing is less than or equal to 0.5 millimeter of wafer-level packaging scale, and the test method of the electronic building brick includes one pre- The detecting step that the wafer is tested using the test device for the preliminary step of a test device and one.
In the preliminary step, which includes one with multiple perforation for being spaced each other in parallel and be in penetration state Probe card and multiple probes being respectively positioned in the perforation.The probe card is made by metal material.Each perforation is fixed One axis extended along its axle center of justice, the probe are arranged along the axis respectively, and each perforation is the hole in single size Diameter, at least there are two the distances between the axis of adjacent perforated in the perforation, are electrically connected with minimum adjacent two in contact portion equal to described The spacing of person.
In the detecting step, the wafer is tested using the test device, the portion in electrical contact respectively with institute It states probe contact and forms electrical connection.
The object of the invention to solve the technical problems also can be used following technical measures and further realize.
Preferably, the test method of aforementioned wafer scale electronic building brick, wherein the axis of wantonly two adjacent perforated in the perforation Between minimum range be less than or equal to 0.5 millimeter.
Preferably, the test method of aforementioned wafer scale electronic building brick, wherein the test device further includes multiple is respectively set In the insulating layer for being used to position the probe in the perforation.
Preferably, the test method of aforementioned wafer scale electronic building brick, wherein each probe has a lateral circle surface, and Two are located at the needle end part of opposite end, and each insulating layer is the complete lateral circle surface for coating corresponding probe, but is not coated The needle end part.
Preferably, the test method of aforementioned wafer scale electronic building brick, wherein each probe has a lateral circle surface, and Two are located at the needle end part of opposite end, each insulating layer is with the lateral circle surface localized contact of corresponding probe to position the spy Needle, and make to form air gap between the probe and the probe card.
Preferably, the test method of aforementioned wafer scale electronic building brick, wherein the probe card has a upper pedestal and one Lower base, the perforation are through the upper pedestal and the lower base.
Preferably, the test method of aforementioned wafer scale electronic building brick, wherein also there is the probe card one to be connected on this The guide member of pedestal, the guide member and the upper pedestal surround out one for accommodating the accommodating space of the wafer jointly.
Beneficial effect of the invention is: because the probe card is with made by metal material, and each perforation is all In the aperture of single size, therefore using the test device come when testing the wafer, as long as the wafer scale envelope that cooperation is described Scale is filled, using the lesser test device in the aperture, by the design of the perforation, that is, is able to cooperate between shortening the probe Distance carry out that scale is lesser accurate to be surveyed so that the probe is able to cooperate the scale for being electrically connected with contact portion of the wafer Examination demand.
Detailed description of the invention
Fig. 1 is a cross-sectional view, illustrates an existing test device and the test limits of the test device;
The case where Fig. 2 is a schematic diagram, illustrates the wherein probe for assembling the test device;
Fig. 3 is a flow chart, illustrates an embodiment of the test method of wafer scale electronic building brick of the present invention;
Fig. 4 is a cross-sectional view, and auxiliary Fig. 3 illustrates the survey used in a preliminary step of the embodiment and a detecting step Trial assembly is set;
The effect of Fig. 5 is a partial enlarged view, illustrates the embodiment;
Fig. 6 is a partial enlarged view, illustrates another state sample implementation of the test device;And
Fig. 7 is a cross-sectional view, illustrates the test device for being able to test the electronic building brick being partitioned on a wafer.
Specific embodiment
The following describes the present invention in detail with reference to the accompanying drawings and embodiments.
Refering to Fig. 3,4, an embodiment of the test method of wafer scale electronic building brick of the present invention is suitable for on a wafer 9 It is formed by electronic building brick to be tested, which has a baseplate part 91 and multiple electrical property being set on the baseplate part 91 Contact portion 92.It is described to be electrically connected in contact portion 92 minimum both adjacent spacing and be less than or equal to wafer-level packaging scale, and the crystalline substance Circle grade package dimensions are 0.5 millimeter.The embodiment includes the preliminary step 31 and a use of a prepared test device 4 The detecting step 32 that the test device 4 tests the wafer 9.
In the preliminary step 31, which is spaced each other parallel and wearing in penetration state with multiple including one The probe card 41 in hole 411, multiple probes 42 being respectively positioned in the perforation 411 and multiple it is respectively arranged at the perforation It is used to position the insulating layer 43 of the probe 42 in 411.The probe card 41 has a upper pedestal 401 and a lower base 402, the perforation 411 is through the upper pedestal 401 and the lower base 402.Each perforation defines one and extends along its axle center Axis L, the probe 42 respectively along the axis L be arranged.
Wherein, due to the aperture that each perforation 411 is in single size, therefore when adjacent perforated 411 is closely arranged, positioning The spacing of the probe 42 in the perforation 411 is only no better than twice under the premise of hole wall can be thinned as far as possible Pore radius, can effectively reduce the detection scale that the test device 4 is able to cooperate whereby.At least two in the perforation 411 Distance d between a 411 axis L of adjacent perforated, equal to the spacing for being electrically connected with minimum adjacent the two in contact portion 92, so that positioning Probe 42 in the perforation 411 is able to be contacted really to be electrically connected with contact portion 92 described in the manufacture of wafer-level packaging scale.Cause This, in order to cooperate wafer-level packaging scale, the minimum range in the perforation 411 between the axis L of wantonly two adjacent perforated 411 is less than Equal to 0.5 millimeter, so that the smallest distance is also able to reach 0.5 millimeter of scale between adjacent probe 42.
In the detecting step 32, described on the wafer 9 is electrically connected with contact portion 92, is able to contact with the probe 42 respectively And the wafer test substrate 5 for forming electrical connection, and being just electrically connected originally with the probe 42 with unification, it detects on the wafer 9 The function of being electrically connected with contact portion 92, it is ensured that it is good that described on the wafer 9, which is electrically connected with contact portion 92 to be formed by electronic building brick, Product.It should be particularly noted that, since the probe card 41 of the test device 4 is made of to utilize pair of metal material with metal material In shielding electromagnetic waves property, the case where interfering with each other when the probe 42 transmits electric signal can be reduced really, effectively improves this The detection performance of test device 4.
Refering to Fig. 5 and cooperate Fig. 4, each probe 42 is located at the needle end of opposite end with a lateral circle surface 421 and two Portion 422, and each insulating layer 43 is the complete lateral circle surface 421 for coating corresponding probe 42, but does not coat the needle end part 422.It is logical The insulating layer 43 is crossed, the electric signal transmitted in each probe 42 can be completely cut off, electric signal is avoided to be made via with metal material Probe card 41 and influence the electric signals of other probes 42.And the insulating layer 43 does not coat the needle end part 422, so that institute It states probe 42 to remain to be electrically connected with contact portion 92 described in contact really, avoids the performance for influencing detection.It is worth illustrating, by The design in single aperture is all presented in the perforation 411, therefore is conducive to before assembling the probe 42, in advance in the perforation The insulating layer 43 is filled in 411, compared to it is as shown in Figure 2 be arranged the processing of multiple dead rings 19 for, can effectively letter Change processing procedure, manufacturing yield is also with promotion.
In addition, general test device 4, the probe 42, which can be divided into, provides three kinds of power supply, transmitting signals, ground connection function It can, that is to say, that in the probe 42, having at least one, at least one is grounded as the purposes of power supply is provided, remaining Then as the transmitting of signal.Due to the probe 42 as ground connection purposes, need to directly be contacted with the probe card 41 to generate ground connection and make With.And the probe 42 is for when providing power supply, then needing quite good insulation effect to occur to avoid the situation of short circuit, it is described Insulating layer 43 can also coat completely provides the lateral circle surface 421 of the probe 42 of power supply, occurs to avoid the situation of short circuit.
Refering to Fig. 6, for another kenel of the test device 4, with the form shown as shown graphically in fig 5 the difference is that: it is each Insulating layer 43 is and to make the probe 42 and the probe with 421 localized contact of lateral circle surface of corresponding probe 42 to position the probe 42 Air gap 8 is formed between card 41.The design as depicted in Fig. 6 remains to reach and shows design as shown graphically in fig 5 although being formed with air gap 8 Equivalent efficacy, in addition to this, the size of the air gap 8 can be used to adjust the impedance matching of each probe 42, through the probe card 41 each perforation 411 is essentially the design of the straight hole in single aperture, can more be easily adjusted the impedance of each probe 42 Match, adjustment acts and enables impedance matching more precisely and stable whereby, effectively improves the test performance of the test device 4.
Refering to Fig. 7, when needing to test the wafer stripping and slicing 9 ' for being divided into particular size, the spy of the test device 4 Needle card 41 further includes a guide member 409 being set on the upper pedestal 401, the kenel of the wafer stripping and slicing 9 ' is able to cooperate, with this Upper pedestal 401 is around out one for carrying the accommodating space 400 of the baseplate part 91.When the size of the wafer stripping and slicing 9 ' is different When, then the different guide member 409 of size can be replaced, the size of the accommodating space 400 is enable to cooperate wafer stripping and slicing 9 ' to be measured. Since the probe 42 is directed towards the accommodating space 400, and position be respectively correspond it is described be electrically connected with contact portion 92, when the wafer is cut Block 9 ' is placed in the accommodating space 400, then can impose press power to the wafer stripping and slicing 9 ' with unification compression module 6, it is ensured that institute It states and is electrically connected with contact portion 92 and can contact the probe 42 really.

Claims (7)

1. a kind of test method of wafer scale electronic building brick, suitable for testing to being formed by electronic building brick on a wafer, The wafer has a baseplate part and multiple contact portions that are electrically connected with being set on the baseplate part, described to be electrically connected with minimum in contact portion Both adjacent spacing is less than or equal to 0.5 millimeter of wafer-level packaging scale;It is characterized by: the test method of the electronic building brick Include:
One preliminary step, one test device of preparation, which, which includes one, has and multiple are spaced each other parallel and are in The probe card of the perforation of penetration state and multiple probes being respectively positioned in the perforation, the probe card are with metal material institute It is made, each perforation defines the axis extended along its axle center, and the probe is arranged along the axis respectively, each is worn Hole is the aperture in single size, and at least there are two the distances between the axis of adjacent perforated in the perforation, is equal to the electrical property The spacing of minimum adjacent the two in contact portion;And
One detecting step tests the wafer using the test device, the portion in electrical contact respectively with the probe It contacts and forms electrical connection.
2. the test method of wafer scale electronic building brick according to claim 1, it is characterised in that: wantonly two is adjacent in the perforation Minimum range between the axis of perforation is less than or equal to 0.5 millimeter.
3. the test method of wafer scale electronic building brick according to claim 1, it is characterised in that: the test device further includes more A be respectively arranged in the perforation and the insulating layer for being used to position the probe.
4. the test method of wafer scale electronic building brick according to claim 3, it is characterised in that: each probe has one Lateral circle surface and two are located at the needle end part of opposite end, and each insulating layer is the complete lateral circle surface for coating corresponding probe, But the needle end part is not coated.
5. the test method of wafer scale electronic building brick according to claim 3, it is characterised in that: each probe has one Lateral circle surface and two are located at the needle end part of opposite end, each insulating layer is the lateral circle surface localized contact with corresponding probe To position the probe, and make to form air gap between the probe and the probe card.
6. the test method of wafer scale electronic building brick according to claim 1, it is characterised in that: the probe card has on one Pedestal and a lower base, the perforation are through the upper pedestal and the lower base.
7. the test method of wafer scale electronic building brick according to claim 6, it is characterised in that: the probe card also has one It is connected to the guide member of the upper pedestal, the guide member and the upper pedestal surround out an accommodating sky for accommodating the wafer jointly Between.
CN201710879888.4A 2017-09-26 2017-09-26 The test method of wafer scale electronic building brick Pending CN109557444A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201710879888.4A CN109557444A (en) 2017-09-26 2017-09-26 The test method of wafer scale electronic building brick

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201710879888.4A CN109557444A (en) 2017-09-26 2017-09-26 The test method of wafer scale electronic building brick

Publications (1)

Publication Number Publication Date
CN109557444A true CN109557444A (en) 2019-04-02

Family

ID=65863086

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201710879888.4A Pending CN109557444A (en) 2017-09-26 2017-09-26 The test method of wafer scale electronic building brick

Country Status (1)

Country Link
CN (1) CN109557444A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112305278A (en) * 2020-10-09 2021-02-02 渭南高新区木王科技有限公司 Preparation method of small-spacing test probe module
CN112305279A (en) * 2020-10-09 2021-02-02 渭南高新区木王科技有限公司 Booth is apart from test probe module
CN112698057A (en) * 2019-10-23 2021-04-23 高天星 Conduction device for electrical property test

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101256201A (en) * 2007-02-27 2008-09-03 南茂科技股份有限公司 Probe head module group capable of detecting multiple positions
CN101431039A (en) * 2007-11-08 2009-05-13 久元电子股份有限公司 Wafer detection system
CN101996912A (en) * 2009-08-11 2011-03-30 台湾积体电路制造股份有限公司 Method for wafer-level testing of integrated circuits, system and method for testing of semiconductor device
CN102539852A (en) * 2012-03-14 2012-07-04 中南大学 Test head for automatically detecting wafer-level packaged chips and implementing method for test head
CN204925272U (en) * 2015-08-13 2015-12-30 颖崴科技股份有限公司 Electronic component's testing arrangement
CN207263851U (en) * 2017-09-26 2018-04-20 颖崴科技股份有限公司 Electronic assembly test device and its system

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101256201A (en) * 2007-02-27 2008-09-03 南茂科技股份有限公司 Probe head module group capable of detecting multiple positions
CN101431039A (en) * 2007-11-08 2009-05-13 久元电子股份有限公司 Wafer detection system
CN101996912A (en) * 2009-08-11 2011-03-30 台湾积体电路制造股份有限公司 Method for wafer-level testing of integrated circuits, system and method for testing of semiconductor device
CN102539852A (en) * 2012-03-14 2012-07-04 中南大学 Test head for automatically detecting wafer-level packaged chips and implementing method for test head
CN204925272U (en) * 2015-08-13 2015-12-30 颖崴科技股份有限公司 Electronic component's testing arrangement
CN207263851U (en) * 2017-09-26 2018-04-20 颖崴科技股份有限公司 Electronic assembly test device and its system

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112698057A (en) * 2019-10-23 2021-04-23 高天星 Conduction device for electrical property test
CN112305278A (en) * 2020-10-09 2021-02-02 渭南高新区木王科技有限公司 Preparation method of small-spacing test probe module
CN112305279A (en) * 2020-10-09 2021-02-02 渭南高新区木王科技有限公司 Booth is apart from test probe module

Similar Documents

Publication Publication Date Title
TWI717585B (en) Improved probe card for high-frequency applications
US9863976B2 (en) Module test socket for over the air testing of radio frequency integrated circuits
KR101552922B1 (en) Magnetic sensor test apparatus and method
CN109557444A (en) The test method of wafer scale electronic building brick
TWI447414B (en) Test apparatus and test method
US10566256B2 (en) Testing method for testing wafer level chip scale packages
KR102193694B1 (en) Electrostatic chuck with embedded flat device for plasma diagnostics
KR101421051B1 (en) Device for Semiconductor Test
JP5588347B2 (en) Probe apparatus and test apparatus
TW201435348A (en) Probe card, probe structure and method for manufacturing the same
CN105445509B (en) A kind of cantalever type probe system applied to more radio frequency chip concurrent testings
US20150115986A1 (en) Alignment testing for tiered semiconductor structure
CN104198772A (en) Embedded chip testing socket and manufacturing method thereof
TW202125994A (en) Electronic component handling device, electronic component testing device and socket capable of performing an Over the Air test in a near-field
KR20200112126A (en) Wafer type apparatus with embedded flat device for plasma diagnostics
CN101090113B (en) Semiconductor device
TWI735729B (en) Shielding for vertical probe heads
KR101789274B1 (en) Apparatus and Method for Near Field Scan Calibration
TW202138825A (en) Electronic component testing apparatus and replacement parts for electronic component testing apparatus, and sockets
CN214795006U (en) A device that is used for all-in-one test CM product insulation resistance
CN103134961B (en) Probe card
KR101421048B1 (en) Device For Testing Semiconductor On Mounted Active Element Chip
TWM547673U (en) Improved structure of wafer testing probe
US11867643B2 (en) Planar-type plasma diagnosis apparatus, wafer-type plasma diagnosis apparatus in which planar-type plasma diagnosis apparatus is buried, and electrostatic chuck in which planar-type plasma diagnosis apparatus is buried
CN103809099B (en) The detection method of wafer probe testing time

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
WD01 Invention patent application deemed withdrawn after publication

Application publication date: 20190402

WD01 Invention patent application deemed withdrawn after publication