TW201913122A - Semiconductor testing apparatus, semiconductor testing system and semiconductor testing method - Google Patents

Abstract

The present disclosure provides a semiconductor testing apparatus, including: a substrate; a golden finger structure, disposed at a side of the substrate.

Description

Semiconductor test device, semiconductor test system, and semiconductor test method

The disclosure relates to the field of semiconductors, and more particularly to a semiconductor test device, a semiconductor test system, and a semiconductor test method.

The global market currently forces manufacturers of a large number of products to provide high quality products at low prices. Therefore, it is important to increase yield and process efficiency to minimize production costs. This is especially the case in the field of semiconductor manufacturing because it combines cutting edge technology with mass production technology. Therefore, the goal of semiconductor manufacturers is to improve the efficiency of the development phase while improving the yield of the mass production process. In view of this, it is an object of the present invention to provide a semiconductor test apparatus and related systems and methods to improve the efficiency of Board Level Reliability Tests (BLRT) during development.

Some embodiments of the present disclosure provide a semiconductor testing device including: a substrate; a gold finger contact structure disposed on one side of the substrate. Some embodiments of the present disclosure provide a semiconductor test system including: a test carrier having a plurality of channels; a slot disposed on the test carrier; a plurality of wires disposed in the slot; and, as claimed in the patent application The semiconductor test device of item 1 is inserted into the socket; wherein the plurality of wires of the gold finger contact structure of the semiconductor test device respectively contact the plurality of wires of the socket. Some embodiments of the present disclosure provide a semiconductor testing method for testing the board reliability of a package component to be tested on a substrate, wherein the substrate is connected to a test carrier by a gold finger contact structure. The method includes: testing the gold finger contact structure by using a short feedback path; soldering the package component to be tested to the substrate by surface adhesion technology; and testing the package component to be tested by using a long feedback path test Board reliability on the substrate. The semiconductor test device, semiconductor test system, and semiconductor test method proposed by the present disclosure can improve the efficiency of Board Level Reliability Tests (BLRT).

The disclosure provides several different implementations or embodiments that can be used to implement different features of the invention. For simplicity of explanation, the present disclosure also describes examples of specific components and arrangements. Please note that these specific examples are provided for demonstration purposes only and are not intended to be limiting. For example, in the following description of how the first feature is on or above the second feature, certain embodiments may be included, where the first feature is in direct contact with the second feature, and the description may include other differences Embodiments wherein there are other features in between the first feature and the second feature such that the first feature is not in direct contact with the second feature. In addition, various examples in the disclosure may use repeated reference numerals and/or text annotations to make the document more simplistic and clear, and such repeated reference numerals and annotations do not represent an association between different embodiments and configurations. In addition, the disclosure uses spatially related narrative vocabulary such as "under", "low", "lower", "above", "above", "down", "top", "bottom" For the sake of brevity, the use of one element or feature in the illustration is to be described in the <RTIgt; In addition to the angular orientations shown in the figures, these spatial relative terms are also used to describe the possible angles and directions of the device in use and during operation. The angular orientation of the device may vary (rotating 90 degrees or other orientations), and the spatially related descriptions used in this disclosure may be interpreted in the same manner. Although the present disclosure proposes a wide range of numerical values and approximate number of meals, the numerical values set forth in the specific examples are as accurate as possible. However, any numerical nature contains some of the necessary errors caused by the standard deviations obtained in individual test measurements. Similarly, as used herein, the term "about" generally refers to within 10%, 5%, 1%, or 0.5% of a given value or range. Alternatively, the term "about" refers to an acceptable standard error of the average when considered by one of ordinary skill in the art. Except in the operating/working examples, or unless otherwise stated, such as the amount of material, time period, temperature, operating conditions, proportions of quantities, and all numerical ranges, quantities, values, and The percentage should be understood as being modified by the word "about" in all cases. Accordingly, the numerical parameters set forth in the disclosure and the appended claims are intended to be a At a minimum, each numerical parameter should be interpreted at least in terms of the number of significant digits reported and the well-known carry technique. In this context, a range can be expressed as from one end to another or between two ends. Unless otherwise stated, all ranges disclosed herein are inclusive of the endpoints. In the advanced process, the number of output pins of the integrated circuit (IC) increases, the requirements for the ball pitch (Ball Pitch) tend to be strict, and the printed circuit board (PCB) package is mounted. For the adjustment of the size of the integrated circuit package and the position of the signal output pin, a package method using integrated fan-out (InFO) packaging technology has emerged. The integrated fan-out package technology takes the form of a pull-out and uses Wafer Level Packaging (WLP) technology to embed a variety of different bare crystals, essentially equivalent to reducing a package. In other words, the integrated fan-out package technology can save more than one layer of package structure when more than one die is placed, thereby reducing the package size and overall manufacturing cost. The integrated fan-out package technology can be placed on the printed circuit board with Surface Mount Technology (SMT). Surface adhesion technology is a convenient and fast emerging technology. The surface adhesion technology can quickly solder electronic parts. The circuit between the part and the substrate is maintained on the substrate. However, integrated fan-out package components using surface mount technology may cause short-circuit or open-circuit problems for some reasons, such as "hot" or "water vapor". Board Level Reliability Tests (BLRT) are procedures used to ensure that components are soldered without short-circuit and/or open-circuit problems during the development phase. The semiconductor test device, the semiconductor test system and the semiconductor test method proposed in the following embodiments can improve the performance of the board reliability test and achieve the purpose of automated test. FIG. 1 is a schematic diagram of an embodiment of a semiconductor testing device according to the present disclosure. A semiconductor testing device 100 includes a substrate 102 and a gold finger contact structure 106. The gold finger contact structure 106 is disposed on one side of the substrate 102. The gold finger contact structure 106 includes a plurality of wires 108 composed of a conductive material. For example, it can be made by gold plating or tin plating. The format of the gold finger structure 106 can be a dual inline memory module (DIMM) interface and a peripheral component connection interface (Peripheral). Component Interface (PCI), a Peripheral Component Interface-Express (PCI-E), a Universal Serial Bus (USB) interface, or an Accelerated Graphics Port (AGP) The interface, etc., that is, the semiconductor test device 100 can be an interface card of various signal transmission formats. The semiconductor test device 100 is inserted into one of the slots of the test carrier of the semiconductor test machine to describe the automated test method of the semiconductor test device 100 using the semiconductor test system. A plurality of integrated fan-out package components 104_1 to 104_4 are disposed on the substrate 102 by surface adhesion techniques. In this embodiment, the configurations of the integrated fan-out type package components 104_1 104104_4 are merely exemplary. In fact, the number and configuration of the integrated fan-out package components are not limited thereto. In addition, it should be noted that although the embodiment of the present disclosure improves the board reliability test of the integrated fan-out package technology with the surface mount technology on the printed circuit board, the disclosure is not limited thereto. The disclosed embodiments can also be applied to any other feasible packaging technique as well as any other feasible bonding technique. 2 is a side view of the semiconductor testing device of FIG. 1 . As can be seen from FIG. 2, in this embodiment, the plurality of wires 108 of the gold finger contact structure 106 are further divided into a plurality of wires 108_1 disposed on the front surface of the gold finger contact structure 106, and configured in the gold finger contact structure. The plurality of wires 108_2 on the back of the 106 are used to increase the number of signals that can be tested, and finally achieve the purpose of increasing the test coverage. However, the disclosure is not limited thereto. 3 is a schematic diagram of an embodiment of a semiconductor test system of the semiconductor test device of FIG. 1 inserted into a test carrier of a semiconductor test machine. A test carrier 110 is provided with at least one slot 112_1 for receiving the gold finger contact structure 106 of the semiconductor testing device 100, and the slot 112_1 is provided with a plurality of wires 114 for corresponding to the gold finger contact structure. A plurality of wires 108 of 106 are used to electrically connect the semiconductor test device 100 to the test carrier 110 of the semiconductor test machine. For the sake of convenience, only the slot 112_1 is shown in the front view of FIG. 3. However, in this embodiment, a plurality of slots 112_1~112_n may be actually included, and n is an arbitrary integer greater than 1. 4 is a side view of the test carrier board of the semiconductor test device of FIG. 1 inserted into the semiconductor test machine. Referring to FIG. 4, the arrangement of the slots 112_1 to 112_n of the embodiment can be understood, wherein n semiconductor test devices 100_1~ 100_n corresponds to the slots 112_1 to 112_n, respectively. 4 also illustrates that the plurality of wires 114 are further divided into a plurality of wires 114_1 corresponding to the plurality of wires 108_1 on the front surface of the gold finger contact structure 106, and a plurality of wires corresponding to the plurality of wires 108_2 on the back surface of the gold finger contact structure 106. 114_2. When the semiconductor test devices 100_1 100 100_n are respectively inserted into the slots 112_1 - 112_n, the gold finger contact structure 106 is embedded in the recess of the slot, so that the plurality of wires 108_1 on the front surface of the gold finger contact structure 106 contact a plurality of recesses located in the recess of the slot. The wire 114_1, and the plurality of wires 108_2 on the back side of the gold finger contact structure 106, contact a plurality of wires 114_2 located in the recess of the slot. 5 is a schematic diagram of another embodiment of a semiconductor test system in which a semiconductor test device of the present disclosure is inserted into a test carrier of a semiconductor test machine. A semiconductor test device 500 has a structure similar to that of the semiconductor test device 100, and includes a substrate 502 and a gold finger contact structure 506. The plurality of integrated fan-out package components 504_1-504_4 are disposed on the substrate 502 by surface adhesion techniques. A test carrier 510 has a structure similar to that of the test carrier 110, and is provided with at least one slot 512_1 for accommodating the gold finger contact structure 506 of the semiconductor testing device 500, and the socket 512_1 is provided with a plurality of Wire 514 is coupled to a plurality of wires 508 of gold finger contact structure 506 to electrically connect semiconductor test device 500 to test carrier 510 of the semiconductor test machine. The semiconductor test device 500 differs from the semiconductor test device 100 in that the gold finger contact structure 506 has an lead-in structure A, and the slot 512_1 is different from the slot 112_1 of FIG. 3 in that the slot 512_1 has an lead-in structure A. ', its appearance features correspond to the introduction structure A and can be combined with each other. In the present embodiment, the introduction structure A is a concave structure; the introduction structure A' is a convex structure, and the gold finger contact structure is in the process of the gold finger contact structure 506 of the semiconductor testing device 500 entering the slot 512_1. The concave structure A of the 506 can help the gold finger contact structure 506 be introduced into the correct position, and finally tightly coupled with the convex structure A' of the socket 512_1, ensuring that the plurality of wires 508 are properly in contact with the corresponding plurality of wires. 514. However, the present disclosure is not limited thereto. The introduction structure A of the gold finger contact structure 506 may have other external features, and the introduction structure A' of the slot 512_1 may have an appearance characteristic corresponding to the introduction structure A. For example, the introduction structure A may be a convex structure, and the introduction structure A' may be a concave structure. 6 and FIG. 7 are schematic diagrams showing an embodiment of a test circuit configuration of a semiconductor test system according to the present disclosure. The test line configuration of Figures 6 and 7 includes a plurality of short loopback paths and a plurality of long loopback paths. In FIG. 6, the short feedback path is indicated by an arrow, and is primarily used to test whether the plurality of wires 108 of the gold finger contact structure 106 are normally in contact with the plurality of wires 114 of the slot 112_1. In the present embodiment, the plurality of wires 114 of the slot 112_1 are electrically connected to a plurality of channels on the test carrier 110, respectively, and the plurality of wires 108 of the gold finger contact structure 106 are configured after entering the substrate 102. For the two-phase connection, when the gold finger contact structure 106 is inserted into the slot 112_1, the test signal can reach the substrate 102 from the first channel Ch1 of the test carrier 110 through the slot 112_1 and the gold finger contact structure 106. And a second channel Ch2 of the test carrier 110 is directly sent back through the gold finger contact structure 106 and the slot 112_1 without passing through the plurality of integrated fan-out package components 104_1 104104_4. By using the plurality of short feedback paths, it is possible to ensure that the plurality of wires 108 of the gold finger contact structure 106 can normally and the slot 112_1 before the test substrate 102 and the integrated fan-out package components 104_1 104104_4 are formally started. A plurality of wires 114 are electrically connected. For example, if the number of wires of the gold finger contact structure 106 is 204, then 102 short feedback paths will be generated, and 102 channels on the test carrier 110 need to be used. In FIG. 7, the long feedback path is indicated by an arrow and is primarily used to test whether a plurality of integrated fan-out package components 104_1-104_4 are electrically connected to substrate 102 as intended. In the present embodiment, the plurality of wires 108 of the gold finger contact structure 106 are planned to have a redundancy configuration, which reduces the probability of test failure between the gold finger contact structure 106 and the slot 112_1 due to poor contact. Specifically, more than one of the plurality of wires 108 is connected to the input of each test chain. For example, two of the plurality of wires 108 are connected to an input of a first test chain. Chain1_H, and there will be more than one wire being connected to the output of each test chain, for example the other two wires of the plurality of wires 108 are connected to an output terminal Chain1_T of the first test chain. The first test chain passes through at least one of a plurality of integrated fan-out package components 104_1 104104_4. When the gold finger contact structure 106 is inserted into the slot 112_1, the test signal can reach the substrate 102 from the first channel Ch1 and the second channel Ch2 of the test carrier 110 through the slot 112_1 and the gold finger contact structure 106, and enter the first The input of the test chain, Chain1_H. The first test chain passes through at least one of the plurality of integrated fan-out package components 104_1 104104_4, and is fed back from the output terminal Chain1_T through the gold finger contact structure 106 and the slot 112_1 to the third of the test carrier 110. Channel Ch3 and fourth channel Ch4. Since the first channel Ch1 and the second channel Ch2 are the same signal when testing the long feedback path, the third channel Ch3 and the fourth channel Ch4 are the same signal, and the subsequent channels are also the same, so FIG. 7 will be FIG. The first channel Ch1 and the second channel Ch2 are merged in the middle, and the third channel Ch3 and the fourth channel Ch4 are merged, and the subsequent channels are also merged in pairs, and the same effect can be achieved. 9 is a schematic diagram of an embodiment of a test line extension of the semiconductor test system of FIGS. 6-7. The n semiconductor test devices 100_1 to 100_n in FIG. 9 are respectively inserted into the slots 112_1 to 112_n of the test carrier 110. In the case where each of the semiconductor test apparatuses 100_1 to 100_n has the same short feedback path and long feedback path configuration, the corresponding short feedback path/long feedback path of each of the semiconductor test apparatuses 100_1 to 100_n can be adopted. Test together in series to save test time. For example, the test of the first test chain is performed on the semiconductor test devices 100_1 100 100_n respectively, that is, the signal output ends of the first test chain of the semiconductor test devices 100_1 100 100_n should be respectively connected to the third test. Channel Ch3 and fourth channel Ch4, but in FIG. 9, the signal output end of the first test chain of the semiconductor testing device 100_1 is serially connected to the signal input end of the first test chain of the semiconductor testing device 100_2, the semiconductor testing device The signal output end of the first test chain of 100_2 is serially connected to the signal input end of the first test chain of the semiconductor testing device 100_3, and is connected in series to the semiconductor testing device 100_n, and finally the semiconductor testing device 100_n The signal output end of the first test chain is connected to the third channel Ch3 and the fourth channel Ch4. 10 is a schematic diagram of an embodiment of a test line extension of the semiconductor test system of FIG. The n semiconductor test devices 100_1 to 100_n in FIG. 10 are respectively inserted into the slots 112_1 to 112_n of the test carrier 110. In the case that each of the semiconductor test devices 100_1 100 100_n has the same long feedback path configuration, the corresponding long feedback paths of each of the semiconductor test devices 100_1 100 100_n can be connected together for testing to save the test. time. For example, the test of the first test chain is performed on the semiconductor test devices 100_1 100 100_n respectively, that is, the signal output end of the first test chain of the semiconductor test devices 100_1 100 100_n should be connected to the second channel. Ch2, but in FIG. 10, the signal output end of the first test chain of the semiconductor testing device 100_1 is serially connected to the signal input end of the first test chain of the semiconductor testing device 100_2, and the first test of the semiconductor testing device 100_2 The signal output end of the chain is serially connected to the signal input end of the first test chain of the semiconductor testing device 100_3, and is connected in series to the semiconductor testing device 100_n in this manner, and finally the first test chain of the semiconductor testing device 100_n The signal output is connected to the second channel Ch2. FIG. 11 is a schematic diagram of an embodiment of a semiconductor test system according to the present disclosure during high and low temperature testing. When performing the high and low temperature test, a temperature isolation device (not shown) may be used to cover the dotted line of the test carrier 110 to generate the required temperature in the temperature isolation device for testing. In this embodiment, depending on the specifications of the temperature isolation device, a portion of the semiconductor test device needs to be removed from the slot in conjunction with the test. For example, if the temperature barrier device is to be overlaid on the semiconductor test device 100_2, the semiconductor test devices 100_1 and 100_3 are removed from the slots 112_1 and 112_3. However, this disclosure is not limited to this. FIG. 12 is a schematic diagram of an embodiment of a semiconductor testing method according to the present disclosure. The semiconductor test method 1200 includes steps 1202 through 1216, wherein the order of the various steps does not imply that the steps must be performed in the order. Rather, these steps can be performed in any suitable order. Steps 1202 to 1204 are achieved by using the short feedback path in the foregoing embodiment, and steps 1208 to 1216 are achieved by using the long feedback path in the foregoing embodiment. In step 1202, a continuation test is performed on the gold finger contact structure 106 of the disclosed embodiment to verify whether the plurality of wires 108 of the gold finger contact structure 106 are normal and a plurality of slots 112_1. The wire 114 is in contact. In step 1204, a short-circuit test is performed on the gold finger contact structure 106 of the disclosed embodiment to verify whether the plurality of wires 108 of the gold finger contact structure 106 and the plurality of wires 114 of the slot 112_1 are short-circuited with each other. In this embodiment, the short circuit test may include a N-leak test. In step 1206, the integrated fan-out package components 104_1-104_4 are soldered to the substrate 102 by surface bonding techniques to prepare for subsequent board-level reliability testing of the integrated fan-out package components 104_1-104_4 and the substrate 102. In step 1208, a test chain open circuit test is performed. For example, in the present embodiment, the test chain open circuit test includes a chain resistance test. In step 1210, a test chain short circuit test is performed. For example, in the present embodiment, the test chain short circuit test includes a chain N-leak test. When the first round of test chain open circuit test and test chain short circuit test are performed, in step 1212, a test chain high voltage short circuit test (chain N-leak stress) is used to perform the path through which the test chain passes under high voltage conditions. Short circuit test. Finally, in steps 1214-1216, the tests of steps 1208-1212 are repeated to check if the path the test chain passes is still normal after passing the high voltage. Some embodiments of the present disclosure provide a semiconductor testing device for arranging a package component to be tested, the semiconductor testing device comprising: a substrate; and a gold finger contact structure disposed on one side of the substrate. Some embodiments of the present disclosure provide a semiconductor test system including: a test carrier having a plurality of channels; a slot disposed on the test carrier; a plurality of wires disposed in the slot; and, as claimed in the patent application The semiconductor test device of item 1 is inserted into the socket; wherein the plurality of wires of the gold finger contact structure of the semiconductor test device respectively contact the plurality of wires of the socket. Some embodiments of the present disclosure provide a semiconductor test method for testing the board reliability of an integrated fan-out package component on a substrate, wherein the substrate is connected to a test carrier by a gold finger contact structure. The method includes: testing the gold finger contact structure with a short feedback path; soldering the integrated fan-out package component to the substrate by surface adhesion technology; and testing the integration using a long feedback path test The board reliability of the fan-out package component on the substrate. The foregoing is a summary of the features of the embodiments, and those skilled in the art can understand the various aspects of the disclosure. Those skilled in the art will appreciate that the present disclosure can be readily utilized as a basis for designing or modifying other processes and structures to achieve the same objectives and/or the same advantages as the embodiments described herein. A person skilled in the art should understand that the present invention is not limited to the spirit and scope of the disclosure, and those skilled in the art can make various changes, substitutions and substitutions without departing from the spirit and scope of the disclosure.

100, 500‧‧‧ semiconductor test equipment

102, 502‧‧‧ substrate

104_1～104_4‧‧‧Integrated fan-out package components

504_1～504_4‧‧‧Integrated fan-out package components

106, 506‧‧‧ Gold finger contact structure

108, 508‧‧‧ a plurality of wires

108_1, 108_2‧‧‧Multiple wires

110, 510‧‧‧ test carrier

112_1~112_n‧‧‧Slots

512_1‧‧‧ slots

114, 514‧‧‧ a plurality of wires

114_1~114_2‧‧‧Multiple wires

100_1～100_n‧‧‧Semiconductor test device

A, A'‧‧‧ import structure

Chain1_H‧‧‧Input of the first test chain

Chain1_T‧‧‧output of the first test chain

Ch1‧‧‧ first channel

Ch2‧‧‧Second channel

Ch3‧‧‧ third channel

Ch4‧‧‧fourth channel

1200‧‧‧ method

1202~1216‧‧‧Steps

In order to assist the reader to achieve the best understanding, it is recommended to refer to the attached figure and its detailed text description when reading this disclosure. Please note that in order to comply with industry standards, the drawings in this patent specification are not necessarily drawn to the correct scale. In some drawings, the dimensions may be deliberately enlarged or reduced to assist the reader in understanding the discussion. 1 is a schematic view of an embodiment of a semiconductor testing device according to the present disclosure; FIG. 2 is a side view of the semiconductor testing device of FIG. 1; FIG. 3 is a test load of the semiconductor testing device of FIG. FIG. 4 is a side view of the test carrier board of the semiconductor test device of FIG. 1 inserted in the semiconductor test machine; FIG. 5 is a semiconductor test device of the present disclosure inserted in the semiconductor test FIG. 6 and FIG. 7 are schematic diagrams showing an embodiment of a test circuit configuration of a semiconductor test system according to the present disclosure; FIG. 8 is a schematic view of a semiconductor test system according to the present disclosure; FIG. 9 is a schematic diagram of an embodiment of a test circuit extension of the semiconductor test system of FIGS. 6-7; FIG. 10 is a schematic diagram of an embodiment of a test circuit extension of the semiconductor test system of FIG. 8; 11 is a schematic diagram of an embodiment of a semiconductor test system according to the present disclosure during high and low temperature testing; and FIG. 12 is a semiconductor tester of the present disclosure. A schematic diagram of an embodiment of the method.

no

Claims (10)

A semiconductor testing device for arranging a package component to be tested, the semiconductor testing device comprising: a substrate; and a gold finger contact structure disposed on one side of the substrate. The device of claim 1, further comprising: a plurality of wires disposed on a front side and a back side of the gold finger contact structure. The device of claim 1, wherein the gold finger contact structure has an introduction structure. The device of claim 3, wherein the introduction structure is a concave structure. A semiconductor test system comprising: a test carrier having a plurality of channels; a slot disposed on the test carrier; a plurality of wires disposed in the slot; and a semiconductor test as described in claim 1 The device is inserted into the slot; wherein the plurality of wires of the gold finger contact structure of the semiconductor testing device respectively contact the plurality of wires of the slot. The system of claim 5, wherein the semiconductor test system has at least one test chain, the test chain path being one of the plurality of channels of the test carrier, passing the slot and the golden finger The contact structure reaches the package component to be tested disposed in the semiconductor test device, and passes through the gold finger contact structure and the slot back to the other of the plurality of channels of the test carrier. The system of claim 6, wherein the path of the test chain passes through the slot and the gold finger contact structure to reach the semiconductor test device, and the first of the plurality of wires passing through the gold finger contact structure a wire and a second wire; and a path of the test chain passing through the gold finger contact structure and the slot returning to the test carrier, a third of a plurality of wires passing through the gold finger contact structure A wire and a fourth wire. The system of claim 7, wherein the path of the test chain passes through the slot and the gold finger contact structure to reach the semiconductor test device, and passes through a first wire of the plurality of wires of the slot and a second wire; and a path of the test chain passing through the gold finger contact structure and the slot returning to the test carrier, a third wire and a fourth wire of the plurality of wires passing through the slot . The system of claim 5, further comprising: another slot; and another semiconductor test device as described in claim 1 is inserted into the other slot. A semiconductor test method for testing the board reliability of a package component to be tested on a substrate, wherein the substrate is connected to a test carrier by a gold finger contact structure, the method comprising: utilizing a short feedback The path is used to test the gold finger contact structure; the package component to be tested is soldered to the substrate; and a long feedback path test is used to test the board reliability of the package component to be tested on the substrate.