TW201903976A - Semiconductor package and semiconductor device - Google Patents
Semiconductor package and semiconductor device Download PDFInfo
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- TW201903976A TW201903976A TW107102818A TW107102818A TW201903976A TW 201903976 A TW201903976 A TW 201903976A TW 107102818 A TW107102818 A TW 107102818A TW 107102818 A TW107102818 A TW 107102818A TW 201903976 A TW201903976 A TW 201903976A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16195—Flat cap [not enclosing an internal cavity]
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Abstract
Description
本發明係關於一種用以搭載半導體元件並將其密封之半導體封裝及使用該半導體封裝之半導體裝置。The present invention relates to a semiconductor package for mounting and sealing a semiconductor element and a semiconductor device using the same.
先前，使用封裝來搭載元件並將其密封。此種封裝例如由可搭載元件之容器、及用以將容器內密封之蓋構件構成。作為收容於封裝之元件，例如，已知有CCD(Charge Coupled Device，電荷耦合元件)或CMOS(Complementary Metal Oxide Semiconductor，互補金氧半導體)等固體攝像元件、發光元件、或MEMS(Microelectromechanical System，微機電系統)等。 於下述專利文獻1中，揭示有用以收容電子元件之封裝。專利文獻1之封裝具備封裝基板及蓋體，該封裝基板具有凹部與配置於其周圍之階部。上述封裝基板之階部與上述蓋體係經由設置於其間之接合層而接合。於專利文獻1中，記載有上述接合層較佳為由包括鉍系玻璃等低熔點玻璃之封接材料而構成之內容。於專利文獻1中，藉由對此種封接材料通過蓋體照射雷射，使封接材料熔融及固化，而使上述封裝基板之階部與上述蓋體接合。 [先前技術文獻] [專利文獻] [專利文獻1]日本專利特開2016-27610號公報Previously, packages were used to mount components and seal them. Such a package is composed, for example, of a container in which an element can be mounted and a cover member for sealing the inside of the container. As an element housed in a package, for example, a solid-state imaging device such as a CCD (Charge Coupled Device) or a CMOS (Complementary Metal Oxide Semiconductor), a light-emitting element, or a MEMS (Micro Electromechanical System) is known. Electromechanical systems) and so on. Patent Document 1 listed below discloses a package useful for accommodating electronic components. The package of Patent Document 1 includes a package substrate and a lid having a concave portion and a step portion disposed around the package. The step portion of the package substrate and the cap system are joined via a bonding layer provided therebetween. Patent Document 1 describes that the bonding layer is preferably composed of a sealing material including a low-melting glass such as bismuth glass. In Patent Document 1, a sealing material is irradiated with a laser through the lid member to melt and solidify the sealing material, and the step portion of the package substrate is joined to the lid body. [Prior Art Document] [Patent Document] [Patent Document 1] Japanese Patent Laid-Open No. 2016-27610
[發明所欲解決之問題] 然而，於在專利文獻1之封裝中收容有固體攝像元件等半導體元件之情形時，有因來自封裝之構成構件之α射線之游離作用而產生半導體元件之軟性誤差的情況。 本發明之目的在於提供一種不易產生因α射線之游離作用所致之半導體元件之軟性誤差的半導體封裝及使用該半導體封裝之半導體裝置。 [解決問題之技術手段] 本發明之半導體封裝之特徵在於：其係用以搭載半導體元件並將其密封者，且具備：容器，其具有供上述半導體元件搭載之底部與配置於該底部上之框狀之側壁部；玻璃蓋，其配置於上述容器之側壁部之上方，且用以將上述容器內密封；及封接材料層，其配置於上述容器之側壁部與上述玻璃蓋之間；且以使上述側壁部之一部分存在於上述封接材料層之上述半導體元件側之上端部與上述半導體元件之上表面之外周緣之間之方式，設置上述側壁部。 本發明之半導體封裝較佳為，比A/B與比C/D滿足A/B＜C/D，比A/B係將上述封接材料層之厚度設為A，將上述封接材料層之上述半導體元件側之上端部與上述側壁部之上述半導體元件側之上端部的俯視時之距離設為B時的比，比C/D係將上述側壁部之上表面與上述半導體元件之上表面之高度差設為C，將上述側壁部之上述半導體元件側之上端部與上述半導體元件之與上述封接材料層為相反側之上端部的俯視時之距離設為D時的比。 本發明之半導體封裝較佳為，上述封接材料層由玻璃料而構成。 本發明之半導體封裝較佳為，上述玻璃料包含鉍系玻璃。 本發明之半導體裝置之特徵在於：具備根據本發明而構成之半導體封裝、及收容於上述半導體封裝之內部之半導體元件。 本發明之半導體裝置較佳為，上述半導體元件為固體攝像元件。 [發明之效果] 根據本發明，可提供一種不易產生因α射線之游離作用所致之半導體元件之軟性誤差的半導體封裝。[Problems to be Solved by the Invention] However, when a semiconductor element such as a solid-state image sensor is housed in the package of Patent Document 1, there is a soft error in the semiconductor element due to the free action of the α-ray from the constituent member of the package. Case. SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor package which is less susceptible to soft errors of semiconductor elements due to the free action of α rays, and a semiconductor device using the semiconductor package. [Means for Solving the Problems] The semiconductor package of the present invention is characterized in that it is used to mount and seal a semiconductor element, and includes a container having a bottom portion on which the semiconductor element is mounted and disposed on the bottom portion a frame-shaped side wall portion; a glass cover disposed above the side wall portion of the container for sealing the inside of the container; and a sealing material layer disposed between the side wall portion of the container and the glass cover; The side wall portion is provided such that one of the side wall portions is present between the upper end portion of the sealing member layer on the semiconductor element side and the outer peripheral surface of the upper surface of the semiconductor element. Preferably, the semiconductor package of the present invention has a ratio of A/B and ratio C/D of A/B<C/D, and the thickness of the sealing material layer is set to A by A/B, and the sealing material layer is used. The distance between the upper end portion on the semiconductor element side and the upper end portion on the semiconductor element side of the side wall portion in the plan view is set to B, and the upper surface of the side wall portion and the semiconductor element are higher than the C/D system. The height difference of the surface is C, and the ratio of the upper end portion of the side wall portion on the semiconductor element side to the upper end portion of the semiconductor element opposite to the sealing material layer is set to D. In the semiconductor package of the present invention, it is preferable that the sealing material layer is made of a glass frit. In the semiconductor package of the present invention, it is preferable that the glass frit contains bismuth-based glass. A semiconductor device according to the present invention includes a semiconductor package configured in accordance with the present invention and a semiconductor element housed inside the semiconductor package. In the semiconductor device of the present invention, it is preferable that the semiconductor element is a solid-state image sensor. [Effect of the Invention] According to the present invention, it is possible to provide a semiconductor package which is less likely to cause a soft error of a semiconductor element due to a free action of α rays.
以下，對較佳之實施形態進行說明。但是，以下之實施形態只不過為例示，本發明並不限定於以下之實施形態。又，於各圖式中，存在具有實質上相同之功能之構件由相同之符號參照之情形。 圖1係表示本發明之一實施形態之半導體封裝及半導體裝置之模式性剖視圖。又，圖2係將本發明之一實施形態之半導體封裝及半導體裝置中設置有封接材料層之部分放大表示之模式性剖視圖。 [半導體封裝] 如圖1所示，半導體封裝1係用以搭載半導體元件7並將其密封之半導體封裝。作為搭載於半導體封裝1之半導體元件7，例如，可列舉CCD或CMOS等固體攝像元件。 半導體封裝1具備容器2、玻璃蓋5及封接材料層6。 於本實施形態中，容器2由LTCC(Low Temperature Co-fired Ceramics，低溫共燒陶瓷)而構成。但是，容器2亦可由其他材料而構成，容器2之材料並不特別限定。 容器2具有底部3及側壁部4。底部3係容器2中供半導體元件7搭載之部分。於底部3上，配置有框狀之側壁部4。又，於側壁部4之上表面4a上，配置有玻璃蓋5。玻璃蓋5係用以將容器2密封之構件。 再者，於側壁部4與玻璃蓋5之間設置有封接材料層6。藉由封接材料層6而將側壁部4與玻璃蓋5接合。於本實施形態中，封接材料層6由包含鉍系玻璃之玻璃料而構成。但是，封接材料層6亦可由其他材料而構成，並不特別限定。再者，於本實施形態中，封接材料層6之剖面形狀為矩形，但封接材料層6之側面6b亦可具有帶弧度之形狀，封接材料層6之形狀並不特別限定。 於本實施形態之半導體封裝1中，於封接材料層6之上端部6a與半導體元件7之外周緣7b之間，以存在側壁部4之一部分之方式設置有側壁部4。再者，封接材料層6之上端部6a係封接材料層6之半導體元件7側之上端部。又，外周緣7b係半導體元件7之上表面7a之外周緣。 又，於半導體封裝1中，於封接材料層6之上端部6a與半導體元件7之上端部7c之間，以存在側壁部4之一部分之方式設置有側壁部4。半導體元件7之上端部7c係與封接材料層6之上端部6a為相反側之半導體元件7之上端部。 於半導體封裝1中，於封接材料層6之上端部6a與半導體元件7之外周緣7b之間，以存在側壁部4之一部分之方式設置有側壁部4，故而不易產生因α射線之游離作用所致之半導體元件7之軟性誤差。再者，關於該情況可如下所述般進行說明。 於本實施形態之半導體封裝1中，如上所述，使用包含鉍系玻璃之玻璃料，將側壁部4與玻璃蓋5接合。此時，包含鉍系玻璃之玻璃料存在包含如鉛般釋放α射線之雜質之情形。因此，於使用此種玻璃料之先前之半導體封裝中，有因自玻璃料釋放之α射線之游離作用而產生半導體元件之軟性誤差的情況。 相對於此，於本實施形態之半導體封裝1中，如上所述，於封接材料層6之上端部6a與半導體元件7之外周緣7b之間，以存在側壁部4之一部分之方式設置有側壁部4。因此，可藉由側壁部4而遮蔽自封接材料層6釋放並朝向半導體元件7之α射線。因此，自封接材料層6釋放之α射線不易照射至半導體元件7，從而可不易產生因α射線之游離作用所致之半導體元件7之軟性誤差。 如此，於半導體封裝1中，由於在將封接材料層6之上端部6a與半導體元件7之外周緣7b連接之所有直線上存在側壁部4之一部分，故而可藉由側壁部4而遮蔽自封接材料層6釋放且朝向半導體元件7之α射線，藉此可不易產生因α射線之游離作用所致之半導體元件7之軟性誤差。 再者，如上所述，於封接材料層6之剖面之形狀並非矩形，而是例如封接材料層6之側面6b具有帶弧度之形狀之情形時，較佳為於封接材料層6之側面6b中最靠半導體元件7側之部分與半導體元件7之外周緣7b之間，以存在側壁部4之一部分之方式設置有側壁部4。於該情形時，可藉由側壁部4進一步確實地遮蔽α射線，從而可更不易產生因α射線之游離作用所致之半導體元件7之軟性誤差。 於本發明中，較佳為圖1及圖2所示之A、B、C及D滿足A/B＜C/D。 再者，上述A為封接材料層6之厚度。上述B為封接材料層6之上端部6a與側壁部4之上端部4b之俯視時之距離。再者，側壁部4之上端部4b係側壁部4之半導體元件7側之上端部。又，上述B係封接材料層6之上端部6a與側壁部4之上端部4b之俯視時之最短距離。 上述C為側壁部4之上表面4a與半導體元件7之上表面7a之高度差(側壁部4之上表面4a－半導體元件7之上表面7a)。又，上述D為側壁部4之上端部4b與半導體元件7之上端部7c之俯視時之距離。半導體元件7之上端部7c係半導體元件7之與封接材料層6為相反側之上端部。更具體而言，半導體元件7之上端部7c係設置於與求出上述B時所使用之封接材料層6之上端部6a為相反側之半導體元件7之上端部。半導體元件7之上端部7c係半導體元件7之外周緣7b中離求出上述B時所使用之封接材料層6之上端部6a最遠之部分。 於圖1及圖2所示之A、B、C及D滿足A/B＜C/D之情形時，可藉由側壁部4而進一步確實地遮蔽α射線。因此，可更不易產生因α射線之游離作用所致之半導體元件7之軟性誤差。 A/B(A相對於B之比)較佳為未達0.1，更佳為0.05以下。於A/B為上述上限以下之情形時，可藉由側壁部4而進一步確實地遮蔽α射線，從而可更不易產生因α射線之游離作用所致之半導體元件7之軟性誤差。再者，A/B較佳為0.001以上。於該情形時，可進一步提高側壁部4與玻璃蓋5之接合強度。 C/D(C相對於D之比)較佳為0.05以上，更佳為0.1以上。於C/D為上述下限以上之情形時，可藉由側壁部4而進一步確實地遮蔽α射線，可更不易產生因α射線之游離作用所致之半導體元件7之軟性誤差。C/D之上限值例如可設為50。 以下，對構成半導體封裝1之各構件之詳細情況進行說明。 (容器) 容器2具有底部3及側壁部4。容器2既可為底部3及側壁部4一體成形者，亦可為藉由接著劑等將底部3及側壁部4分別單獨成形者接合而成。 容器2例如由陶瓷或玻璃陶瓷等構成。作為陶瓷，可列舉氧化鋁、氮化鋁、氧化鋯、莫來石等。作為玻璃陶瓷，可列舉LTCC(Low Temperature Co-fired Ceramics)等。作為LTCC之具體例，可列舉氧化鈦或氧化鈮等無機粉末與玻璃粉末之燒結體等。 (玻璃蓋) 作為構成玻璃蓋5之玻璃，例如，可使用SiO2 -B2 O3 -RO(R為Mg、Ca、Sr或Ba)系玻璃、SiO2 -B2 O3 -R'2 O(R'為Li、Na或Ka)系玻璃、SiO2 -B2 O3 -RO-R'2 O系玻璃(R'為Li、Na或Ka)、SnO-P2 O5 系玻璃、TeO2 系玻璃或Bi2 O3 系玻璃等。 (封接材料層) 作為用以形成封接材料層6之封接材料，例如，可使用玻璃料。其中，較佳為包含Bi2 O3 系玻璃粉末(鉍系玻璃粉末)、SnO-P2 O5 系玻璃粉末、V2 O5 -TeO2 系玻璃粉末等低熔點之玻璃料。尤其，於照射雷射而進行封接之情形時，自使封接材料以更短時間之加熱軟化之必要性與進一步提高接合強度之觀點而言，玻璃料更佳為使用軟化點非常低之鉍系玻璃粉末。又，玻璃料亦可包含低膨脹耐火性填料或雷射吸收材等。作為低膨脹耐火性填料，例如，可列舉堇青石、矽鋅礦、氧化鋁、磷酸鋯系化合物、鋯英石、氧化鋯、氧化錫、石英玻璃、β-石英固溶體、β-鋰霞石、鋰輝石。又，作為雷射吸收材，例如，可列舉選自Fe、Mn、Cu等之至少1種金屬或包含該金屬之氧化物等化合物。 [半導體裝置] 半導體裝置10具備上述半導體封裝1與半導體元件7。半導體元件7收容於半導體封裝1之內部。半導體裝置10由於具備上述半導體封裝1，故而不易產生因α射線之游離作用所致之半導體元件7之軟性誤差。 如此，於半導體裝置10中不易產生因α射線之游離作用所致之半導體元件7之軟性誤差，故而作為半導體元件7，例如可較佳地使用CCD或CMOS等固體攝像元件。 以下，一面參照圖3(a)～(d)，一面對半導體封裝1及半導體裝置10之製造方法之一例進行說明。 (半導體封裝及半導體裝置之製造方法) 首先，如圖3(a)所示，準備具有底部3及側壁部4之容器2。繼而，如圖3(b)所示，於容器2之側壁部4之上表面4a上，印刷封接材料。作為封接材料，例如，可使用包含鉍系玻璃之玻璃料。封接材料之印刷後，使之乾燥，進而進行熱處理，藉此使封接材料燒結，形成封接材料層6。再者，封接材料層6亦可形成於玻璃蓋5側。 其次，如圖3(c)所示，於容器2之底部3上搭載半導體元件7。再者，於本製造方法中，於搭載該半導體元件7時，於封接材料層6之上端部6a與半導體元件7之外周緣7b之間，以存在側壁部4之一部分之方式形成有側壁部4或封接材料層6。 其次，如圖3(d)所示，於側壁部4之上表面4a上設置有封接材料層6之部分，配置玻璃蓋5。再者，玻璃蓋5只要以俯視時至少一部分與設置有封接材料層6之部分重疊之方式配置即可。但是，較佳為，玻璃蓋5以俯視時與設置有封接材料層6之部分完全重疊之方式配置。 其次，於在側壁部4之上表面4a上介隔封接材料層6而配置有玻璃蓋5之狀態下，照射來自雷射光源之雷射，藉此，使封接材料層6軟化，使容器2之側壁部4及玻璃蓋5接合。藉此，將容器2之內部氣密密封，獲得圖1所示之半導體封裝1及半導體裝置10。根據該方法，由於能夠僅對封接材料層6局部地進行加熱，故而可不使耐熱性較低之半導體元件7劣化地將半導體封裝1氣密密封。作為上述雷射，例如，可使用波長為600 nm～1600 nm之雷射。 又，於照射雷射時，首先，將來自雷射光源之雷射通過玻璃蓋5照射至封接材料層6。此時，雷射於框狀之側壁部4之上表面4a上進行掃描並環繞。環繞之雷射照射至超過雷射照射之起點之位置為止。藉此，將容器2密封。雷射之終點既可為超過使雷射環繞後之起點之位置，亦可為與起點相同之位置。 再者，於本發明中，亦可不照射雷射，僅藉由對封接材料層6進行加熱，而使封接材料層6軟化，使容器2之側壁部4及玻璃蓋5接合。 於所獲得之半導體裝置10中，由於在封接材料層6之上端部6a與半導體元件7之外周緣7b之間，以存在側壁部4之一部分之方式設置有側壁部4，故而不易產生因α射線之游離作用所致之半導體元件7之軟性誤差。 以下，關於本發明，基於具體性的實施例，進而詳細地進行說明，但本發明並不受以下之實施例任何限定，能夠於不變更其主旨之範圍內適當變更而實施。 (實施例1) 首先，準備具有底部及側壁部且由LTCC而構成之容器。 其次，於容器之側壁部之上表面印刷玻璃料。於印刷後，進行乾燥、熱處理而使玻璃料燒結，形成封接材料層。再者，作為玻璃料，使用以莫耳%計具有39%之Bi2 O3 、23.7%之B2 O3 、14.1%之ZnO、2.7%之Al2 O3 、20%之CuO、0.5%之Fe2 O3 之組成的玻璃粉末。 其次，於所準備之容器之內側底部之特定區域，具體而言於搭載半導體元件時供半導體元件之上表面配置之區域設置閃爍計數器。 其次，於容器之側壁部上方之設置有封接材料層之部分配置玻璃蓋。繼而，對容器之側壁部之設置有封接材料層之部分，自玻璃蓋上方之雷射光源照射雷射，使封接材料層軟化，使容器之側壁部與玻璃蓋接合。藉此，將容器之內部密封，獲得半導體封裝。 再者，於實施例1中，以如下方式設計半導體封裝，即，封接材料層之厚度A為5 μm，於搭載有半導體元件時，封接材料層之半導體元件側之上端部與側壁部之半導體元件側之上端部的俯視時之距離B成為300 μm。又，以如下方式設計半導體封裝，即，側壁部之上表面與半導體元件上表面之高度差C為400 μm，側壁部之半導體元件側之上端部與半導體元件之與封接材料層為相反側之上端部的俯視時之距離D成為7200 μm。 再者，於所獲得之半導體封裝中，於搭載有半導體元件之情形時，於封接材料層之半導體元件側之上端部與半導體元件之上表面之外周緣之間，以存在側壁部之一部分之方式設置有側壁部。 (比較例1) 於比較例1中，以如下方式設計半導體封裝，即，封接材料層之厚度A為5 μm，於搭載有半導體元件時，封接材料層之半導體元件側之上端部與側壁部之半導體元件側之上端部的俯視時之距離B成為10 μm。又，以如下方式設計半導體封裝，即，側壁部之上表面與半導體元件上表面之高度差C為400 μm，側壁部之半導體元件側之上端部與半導體元件之與封接材料層為相反側之上端部的俯視時之距離D成為7200 μm；除此以外與實施例1同樣地獲得半導體封裝。 再者，於所獲得之半導體封裝中，於搭載有半導體元件之情形時，於封接材料層之半導體元件側之上端部與半導體元件之上表面之外周緣之間，不存在側壁部之一部分。 (評估) 藉由以上述方式配置之閃爍計數器，而測定α射線量。 再者，以下所示之α射線量之值係用由上述方法(閃爍計數器)24小時測定出之計數值除以時間及半導體元件搭載面之面積而算出。 於實施例1中，入射至閃爍計數器之α射線量為0.00 cph/cm2 。另一方面，於比較例1中，入射至閃爍計數器之α射線量為2.80 cph/cm2 。Hereinafter, preferred embodiments will be described. However, the following embodiments are merely illustrative, and the present invention is not limited to the following embodiments. Further, in each of the drawings, members having substantially the same functions are referred to by the same symbols. Fig. 1 is a schematic cross-sectional view showing a semiconductor package and a semiconductor device according to an embodiment of the present invention. 2 is a schematic cross-sectional view showing a portion in which a sealing material layer is provided in a semiconductor package and a semiconductor device according to an embodiment of the present invention. [Semiconductor Package] As shown in FIG. 1, the semiconductor package 1 is a semiconductor package for mounting and sealing the semiconductor element 7. As the semiconductor element 7 mounted on the semiconductor package 1, for example, a solid-state imaging element such as a CCD or a CMOS can be cited. The semiconductor package 1 includes a container 2, a glass cover 5, and a sealing material layer 6. In the present embodiment, the container 2 is composed of LTCC (Low Temperature Co-fired Ceramics). However, the container 2 may be composed of other materials, and the material of the container 2 is not particularly limited. The container 2 has a bottom portion 3 and a side wall portion 4. The portion of the bottom 3 series container 2 on which the semiconductor element 7 is mounted. On the bottom portion 3, a frame-shaped side wall portion 4 is disposed. Further, a glass cover 5 is disposed on the upper surface 4a of the side wall portion 4. The glass cover 5 is a member for sealing the container 2. Further, a sealing material layer 6 is provided between the side wall portion 4 and the cover glass 5. The side wall portion 4 is joined to the glass cover 5 by the sealing material layer 6. In the present embodiment, the sealing material layer 6 is composed of a glass frit containing bismuth-based glass. However, the sealing material layer 6 may be composed of other materials, and is not particularly limited. Further, in the present embodiment, the cross-sectional shape of the sealing material layer 6 is rectangular, but the side surface 6b of the sealing material layer 6 may have a curved shape, and the shape of the sealing material layer 6 is not particularly limited. In the semiconductor package 1 of the present embodiment, the side wall portion 4 is provided between the end portion 6a of the sealing material layer 6 and the outer peripheral edge 7b of the semiconductor element 7 so as to have a portion of the side wall portion 4. Further, the upper end portion 6a of the sealing material layer 6 seals the upper end portion of the material layer 6 on the semiconductor element 7 side. Further, the outer peripheral edge 7b is a peripheral edge of the upper surface 7a of the semiconductor element 7. Further, in the semiconductor package 1, the side wall portion 4 is provided between the end portion 6a of the sealing material layer 6 and the upper end portion 7c of the semiconductor element 7 so as to have a part of the side wall portion 4. The upper end portion 7c of the semiconductor element 7 is an upper end portion of the semiconductor element 7 opposite to the upper end portion 6a of the sealing material layer 6. In the semiconductor package 1, between the end portion 6a of the sealing material layer 6 and the outer peripheral edge 7b of the semiconductor element 7, the side wall portion 4 is provided so as to exist as a part of the side wall portion 4, so that it is not easily generated by the α-ray. The soft error of the semiconductor component 7 due to the action. Furthermore, this case can be described as follows. In the semiconductor package 1 of the present embodiment, as described above, the side wall portion 4 and the cover glass 5 are joined by using a glass frit containing a bismuth-based glass. At this time, the glass frit containing the lanthanide glass has a case where impurities containing α rays are released as lead. Therefore, in the prior semiconductor package using such a glass frit, there is a case where a soft error of the semiconductor element occurs due to the free action of the α-ray released from the frit. On the other hand, in the semiconductor package 1 of the present embodiment, as described above, between the upper end portion 6a of the sealing material layer 6 and the outer peripheral edge 7b of the semiconductor element 7, a portion of the side wall portion 4 is provided. Side wall portion 4. Therefore, the alpha rays released from the sealing material layer 6 and facing the semiconductor element 7 can be shielded by the side wall portion 4. Therefore, the α-rays released from the sealing material layer 6 are less likely to be irradiated to the semiconductor element 7, so that the softness error of the semiconductor element 7 due to the free action of the α-rays is less likely to occur. As described above, in the semiconductor package 1, since one portion of the side wall portion 4 exists on all the straight lines connecting the end portion 6a of the sealing material layer 6 and the peripheral edge 7b of the semiconductor element 7, the side wall portion 4 can be shielded from the self-sealing. The bonding material layer 6 releases and faces the alpha rays of the semiconductor element 7, whereby the softness error of the semiconductor element 7 due to the free action of the alpha rays can be less likely to occur. Furthermore, as described above, the shape of the cross section of the sealing material layer 6 is not rectangular, but, for example, when the side surface 6b of the sealing material layer 6 has a curved shape, it is preferably the sealing material layer 6. A side wall portion 4 is provided between a portion of the side surface 6b closest to the semiconductor element 7 side and the outer peripheral edge 7b of the semiconductor element 7 so as to have a portion of the side wall portion 4. In this case, the α-rays can be further reliably shielded by the side wall portion 4, so that the softness error of the semiconductor element 7 due to the free action of the α-rays can be less likely to occur. In the present invention, it is preferable that A, B, C, and D shown in FIGS. 1 and 2 satisfy A/B<C/D. Furthermore, the above A is the thickness of the sealing material layer 6. The above B is the distance in the plan view of the upper end portion 6a of the sealing material layer 6 and the upper end portion 4b of the side wall portion 4. Further, the upper end portion 4b of the side wall portion 4 is an upper end portion of the side wall portion 4 on the side of the semiconductor element 7. Further, the shortest distance between the upper end portion 6a of the B-type sealing material layer 6 and the upper end portion 4b of the side wall portion 4 in plan view. The above C is the difference in height between the upper surface 4a of the side wall portion 4 and the upper surface 7a of the semiconductor element 7 (the upper surface 4a of the side wall portion 4 - the upper surface 7a of the semiconductor element 7). Further, the above D is a distance in a plan view of the upper end portion 4b of the side wall portion 4 and the upper end portion 7c of the semiconductor element 7. The upper end portion 7c of the semiconductor element 7 is an upper end portion of the semiconductor element 7 opposite to the sealing material layer 6. More specifically, the upper end portion 7c of the semiconductor element 7 is provided on the upper end portion of the semiconductor element 7 on the side opposite to the upper end portion 6a of the sealing material layer 6 used for obtaining the above B. The upper end portion 7c of the semiconductor element 7 is the portion of the outer peripheral edge 7b of the semiconductor element 7 which is the farthest from the upper end portion 6a of the sealing material layer 6 used for obtaining the above B. When A, B, C, and D shown in FIGS. 1 and 2 satisfy A/B<C/D, the α-rays can be surely shielded by the side wall portion 4. Therefore, the softness error of the semiconductor element 7 due to the free action of the alpha ray can be less likely to occur. A/B (ratio of A to B) is preferably less than 0.1, more preferably 0.05 or less. When A/B is equal to or less than the above upper limit, the α-ray can be surely shielded by the side wall portion 4, and the softness error of the semiconductor element 7 due to the free action of the α-ray can be less likely to occur. Further, A/B is preferably 0.001 or more. In this case, the bonding strength between the side wall portion 4 and the cover glass 5 can be further improved. C/D (ratio of C to D) is preferably 0.05 or more, more preferably 0.1 or more. When C/D is equal to or higher than the above lower limit, the α-ray can be surely shielded by the side wall portion 4, and the softness error of the semiconductor element 7 due to the free action of the α-ray can be less likely to occur. The C/D upper limit value can be set, for example, to 50. Hereinafter, details of each member constituting the semiconductor package 1 will be described. (Container) The container 2 has a bottom portion 3 and a side wall portion 4. The container 2 may be formed by integrally molding the bottom portion 3 and the side wall portion 4, or may be formed by separately forming the bottom portion 3 and the side wall portion 4 by an adhesive or the like. The container 2 is made of, for example, ceramic or glass ceramic. Examples of the ceramics include alumina, aluminum nitride, zirconia, and mullite. Examples of the glass ceramics include LTCC (Low Temperature Co-fired Ceramics) and the like. Specific examples of the LTCC include inorganic powders such as titanium oxide and cerium oxide, and sintered bodies of glass powder. (Glass cover) As the glass constituting the cover glass 5, for example, SiO 2 -B 2 O 3 -RO (R is Mg, Ca, Sr or Ba)-based glass, SiO 2 -B 2 O 3 -R' 2 can be used. O (R' is Li, Na or Ka) glass, SiO 2 -B 2 O 3 -RO-R' 2 O glass (R' is Li, Na or Ka), SnO-P 2 O 5 glass, TeO 2 based glass or Bi 2 O 3 based glass or the like. (Sealing Material Layer) As the sealing material for forming the sealing material layer 6, for example, a glass frit can be used. Among them, a glass frit having a low melting point such as a Bi 2 O 3 -based glass powder (fluorene-based glass powder), a SnO—P 2 O 5 -based glass powder, or a V 2 O 5 —TeO 2 -based glass powder is preferable. In particular, in the case of sealing by laser irradiation, the glass frit is preferably used at a very low softening point from the viewpoint of the necessity of softening the sealing material in a shorter period of time and further improving the bonding strength. Lanthanum glass powder. Further, the glass frit may also contain a low expansion fire resistant filler or a laser absorbing material. Examples of the low-expansion refractory filler include cordierite, strontium zinc ore, alumina, zirconium phosphate-based compound, zircon, zirconia, tin oxide, quartz glass, β-quartz solid solution, and β-lithium Stone, spodumene. In addition, examples of the laser absorbing material include at least one metal selected from the group consisting of Fe, Mn, and Cu, and a compound containing an oxide of the metal. [Semiconductor Device] The semiconductor device 10 includes the above-described semiconductor package 1 and semiconductor element 7. The semiconductor element 7 is housed inside the semiconductor package 1. Since the semiconductor device 10 includes the semiconductor package 1, the softness error of the semiconductor element 7 due to the free action of the α-ray is less likely to occur. As described above, in the semiconductor device 10, a soft error of the semiconductor element 7 due to the free action of the α-ray is less likely to occur. Therefore, as the semiconductor element 7, for example, a solid-state imaging element such as a CCD or a CMOS can be preferably used. Hereinafter, an example of a method of manufacturing the semiconductor package 1 and the semiconductor device 10 will be described with reference to FIGS. 3(a) to 3(d). (Method of Manufacturing Semiconductor Package and Semiconductor Device) First, as shown in FIG. 3(a), a container 2 having a bottom portion 3 and a side wall portion 4 is prepared. Then, as shown in Fig. 3 (b), a sealing material is printed on the upper surface 4a of the side wall portion 4 of the container 2. As the sealing material, for example, a glass frit containing lanthanum glass can be used. After the sealing material is printed, it is dried and further heat-treated, whereby the sealing material is sintered to form the sealing material layer 6. Further, the sealing material layer 6 may be formed on the side of the cover glass 5. Next, as shown in FIG. 3(c), the semiconductor element 7 is mounted on the bottom 3 of the container 2. Further, in the present manufacturing method, when the semiconductor element 7 is mounted, a sidewall is formed between the end portion 6a of the sealing material layer 6 and the outer peripheral edge 7b of the semiconductor element 7 so as to have a portion of the side wall portion 4. Portion 4 or sealing material layer 6. Next, as shown in FIG. 3(d), a portion of the sealing material layer 6 is provided on the upper surface 4a of the side wall portion 4, and the glass cover 5 is disposed. Further, the glass cover 5 may be disposed so that at least a part thereof overlaps with a portion where the sealing material layer 6 is provided in a plan view. However, it is preferable that the cover glass 5 is disposed so as to completely overlap the portion where the sealing material layer 6 is provided in a plan view. Next, the sealing material layer 6 is softened by irradiating a laser beam from the laser light source while the glass cover 5 is placed on the upper surface 4a of the side wall portion 4 with the sealing material layer 6 interposed therebetween. The side wall portion 4 of the container 2 and the glass cover 5 are joined. Thereby, the inside of the container 2 is hermetically sealed, and the semiconductor package 1 and the semiconductor device 10 shown in FIG. 1 are obtained. According to this method, since only the sealing material layer 6 can be locally heated, the semiconductor package 1 can be hermetically sealed without deteriorating the semiconductor element 7 having low heat resistance. As the above-described laser, for example, a laser having a wavelength of 600 nm to 1600 nm can be used. Further, when irradiating the laser, first, the laser light from the laser light source is irradiated to the sealing material layer 6 through the glass cover 5. At this time, the laser is scanned and surrounded on the upper surface 4a of the frame-shaped side wall portion 4. The surrounding laser is illuminated until it reaches the starting point of the laser illumination. Thereby, the container 2 is sealed. The end of the laser can be either beyond the starting point after the laser is surrounded or at the same position as the starting point. Further, in the present invention, the sealing material layer 6 may be softened only by heating the sealing material layer 6 without irradiating the laser, and the side wall portion 4 of the container 2 and the glass cover 5 may be joined. In the obtained semiconductor device 10, since the side wall portion 4 is provided between the end portion 6a of the sealing material layer 6 and the peripheral edge 7b of the semiconductor element 7 so as to exist as a part of the side wall portion 4, it is not easy to cause a cause. The soft error of the semiconductor element 7 due to the free action of the alpha ray. In the following, the present invention will be described in detail based on the specific examples, but the present invention is not limited to the following examples, and can be appropriately modified without departing from the scope of the invention. (Example 1) First, a container having a bottom portion and a side wall portion and composed of LTCC was prepared. Next, the glass frit is printed on the upper surface of the side wall portion of the container. After printing, drying and heat treatment are performed to sinter the glass frit to form a sealing material layer. Further, as the glass frit, 39% of Bi 2 O 3 , 23.7% of B 2 O 3 , 14.1% of ZnO, 2.7% of Al 2 O 3 , 20% of CuO, and 0.5% were used. A glass powder composed of Fe 2 O 3 . Next, a scintillation counter is provided in a specific region on the inner bottom of the prepared container, specifically, in a region where the upper surface of the semiconductor element is disposed when the semiconductor element is mounted. Next, a glass cover is disposed on a portion of the side wall portion of the container where the sealing material layer is provided. Then, a portion of the side wall portion of the container provided with the sealing material layer is irradiated with a laser from a laser light source above the glass cover to soften the sealing material layer to engage the side wall portion of the container with the glass cover. Thereby, the inside of the container is sealed to obtain a semiconductor package. Further, in the first embodiment, the semiconductor package is designed such that the thickness A of the sealing material layer is 5 μm, and when the semiconductor element is mounted, the upper end portion and the side wall portion of the semiconductor element side of the sealing material layer are provided. The distance B in the plan view of the upper end portion on the semiconductor element side is 300 μm. Further, the semiconductor package is designed such that the height difference C between the upper surface of the side wall portion and the upper surface of the semiconductor element is 400 μm, and the upper end portion of the semiconductor element side of the side wall portion is opposite to the sealing material layer of the semiconductor element The distance D of the upper end portion in plan view is 7200 μm. Further, in the obtained semiconductor package, in the case where the semiconductor element is mounted, between the upper end portion of the semiconductor element side of the sealing material layer and the outer peripheral surface of the upper surface of the semiconductor element, there is a part of the side wall portion The side is provided with a side wall portion. (Comparative Example 1) In Comparative Example 1, a semiconductor package was designed in such a manner that the thickness A of the sealing material layer was 5 μm, and when the semiconductor element was mounted, the upper end portion of the sealing material layer on the semiconductor element side was The distance B in the plan view of the upper end portion of the side wall portion on the semiconductor element side was 10 μm. Further, the semiconductor package is designed such that the height difference C between the upper surface of the side wall portion and the upper surface of the semiconductor element is 400 μm, and the upper end portion of the semiconductor element side of the side wall portion is opposite to the sealing material layer of the semiconductor element A semiconductor package was obtained in the same manner as in Example 1 except that the distance D in the plan view of the upper end portion was 7200 μm. Further, in the obtained semiconductor package, when the semiconductor element is mounted, there is no part of the side wall portion between the upper end portion of the semiconductor element side of the sealing material layer and the outer peripheral surface of the upper surface of the semiconductor element . (Evaluation) The amount of α rays was measured by the scintillation counter configured in the above manner. In addition, the value of the amount of α-rays shown below is calculated by dividing the count value measured by the above method (flicker counter) for 24 hours by the time and the area of the semiconductor element mounting surface. In Example 1, the amount of α rays incident on the scintillation counter was 0.00 cph/cm 2 . On the other hand, in Comparative Example 1, the amount of α rays incident on the scintillation counter was 2.80 cph/cm 2 .
1‧‧‧半導體封裝1‧‧‧Semiconductor package
2‧‧‧容器2‧‧‧ Container
3‧‧‧底部3‧‧‧ bottom
4‧‧‧側壁部4‧‧‧ Sidewall
4a‧‧‧上表面4a‧‧‧ upper surface
4b‧‧‧上端部4b‧‧‧Upper
5‧‧‧玻璃蓋5‧‧‧glass cover
6‧‧‧封接材料層6‧‧‧Sealing material layer
6a‧‧‧上端部6a‧‧‧Upper end
6b‧‧‧側面6b‧‧‧ side
7‧‧‧半導體元件7‧‧‧Semiconductor components
7a‧‧‧上表面7a‧‧‧Upper surface
7b‧‧‧外周緣7b‧‧‧ outer periphery
7c‧‧‧上端部7c‧‧‧Upper
10‧‧‧半導體裝置10‧‧‧Semiconductor device
圖1係表示本發明之一實施形態之半導體封裝及半導體裝置之模式性剖視圖。 圖2係將本發明之一實施形態之半導體封裝及半導體裝置中設置有封接材料層之部分放大表示之模式性剖視圖。 圖3(a)～(d)係用以說明本發明之一實施形態之半導體封裝之製造方法的模式性剖視圖。Fig. 1 is a schematic cross-sectional view showing a semiconductor package and a semiconductor device according to an embodiment of the present invention. Fig. 2 is a schematic cross-sectional view showing a portion in which a sealing material layer is provided in a semiconductor package and a semiconductor device according to an embodiment of the present invention. 3(a) to 3(d) are schematic cross-sectional views for explaining a method of manufacturing a semiconductor package according to an embodiment of the present invention.
Claims (6)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2017073737A JP2018181880A (en) | 2017-04-03 | 2017-04-03 | Semiconductor package and semiconductor device |
| JP2017-073737 | 2017-04-03 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| TW201903976A true TW201903976A (en) | 2019-01-16 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW107102818A TW201903976A (en) | 2017-04-03 | 2018-01-26 | Semiconductor package and semiconductor device |
Country Status (3)
| Country | Link |
|---|---|
| JP (1) | JP2018181880A (en) |
| TW (1) | TW201903976A (en) |
| WO (1) | WO2018185997A1 (en) |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5599153U (en) * | 1978-12-28 | 1980-07-10 | ||
| JPS5739439U (en) * | 1980-08-18 | 1982-03-03 | ||
| JP2013185214A (en) * | 2012-03-08 | 2013-09-19 | Jx Nippon Mining & Metals Corp | BISMUTH OR BISMUTH ALLOY HAVING SMALL AMOUNT OF α-RAY, AND METHOD FOR PRODUCING THE SAME |
| JP2016027610A (en) * | 2014-06-27 | 2016-02-18 | 旭硝子株式会社 | Package substrate, package, and electronic device |
-
2017
- 2017-04-03 JP JP2017073737A patent/JP2018181880A/en active Pending
-
2018
- 2018-01-22 WO PCT/JP2018/001707 patent/WO2018185997A1/en active Application Filing
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Also Published As
| Publication number | Publication date |
|---|---|
| WO2018185997A1 (en) | 2018-10-11 |
| JP2018181880A (en) | 2018-11-15 |
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