TW201839940A - 具有暴露重分佈層特徵之一半導體封裝及相關封裝及測試方法 - Google Patents

具有暴露重分佈層特徵之一半導體封裝及相關封裝及測試方法 Download PDF

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TW201839940A
TW201839940A TW107111507A TW107111507A TW201839940A TW 201839940 A TW201839940 A TW 201839940A TW 107111507 A TW107111507 A TW 107111507A TW 107111507 A TW107111507 A TW 107111507A TW 201839940 A TW201839940 A TW 201839940A
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redistribution
layer
package
semiconductor
redistribution layer
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TW107111507A
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文傑 林
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美商微晶片科技公司
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    • H01L21/76837—Filling up the space between adjacent conductive structures; Gap-filling properties of dielectrics
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Abstract

一種封裝一半導體裝置之方法，該半導體裝置具有在該半導體裝置之一表面上之一接合墊，該方法包括：形成電耦合至該接合墊之一重分佈材料；形成一介電材料於該重分佈材料上方；及移除該介電材料之一第一部分以暴露該重分佈材料之一第一部分。半導體封裝可包括一重分佈層，該重分佈層具有：一第一部分，其相鄰於且耦合至該封裝之一第一接觸件；一第二部分，其藉由一介電材料中之一第一開口而被暴露；及一重分佈線，其電耦合至一第一接合墊、該第一部分、及該第二部分。可使至少一探測針與該封裝之至少一終端接觸、透過該終端提供來自該探測針之一測試信號至該封裝、及使用該探測針來偵測信號，來測試此一封裝。

Description

具有暴露重分佈層特徵之一半導體封裝及相關封裝及測試方法 【優先權主張】
本申請案主張2017年4月7日申請之美國臨時專利申請案第62/483,253號「SEMICONDUCTOR PACKAGE HAVING EXPOSED REDISTRIBUTION LAYER FEATURES AND RELATED METHODS OF PACKAGING AND TESTING(具有暴露重分佈層特徵之一半導體封裝及相關封裝及測試方法)」之權利。
本揭露大致上關於半導體封裝以及封裝及測試半導體封裝之方法。一些具體揭示之實施例係關於在最終封裝組態中具有重分佈層之一或多個暴露部分之晶圓級晶片尺寸封裝(WLCSP)以及封裝及測試此類晶圓級晶片尺寸封裝之方法。
在封裝程序(包括高溫程序步驟)期間，在半導體裝置中之電氣組件及電路系統會損壞或其等之特性改變。可利用諸如晶圓探測之技術以測試半導體裝置及偵測該等電氣組件及電路系統之損壞及/或特性變更。若偵測到損壞或變更，減輕步驟有時候係可行的。
圖1A及圖1B表示已知之當前最新技術。圖1A係含一經囊封重分佈層30之一半導體封裝10的截面圖。半導體封裝10包括一半導體裝置11，該半導體裝置上具有一鈍化層12及至少一接合墊13。半導體封裝10亦包括一介電層14、一重分佈層15、一介電層16、一黏著劑層160(例如，一可焊接黏著性金屬層)、及封裝接觸件17。重分佈層30僅可藉由封裝接觸件17從外部接達。舉非限制性實例而言，封裝接觸件可係焊球、焊料凸塊、銅柱凸塊、或其等之組合。
圖1B係圖1A所繪示之半導體封裝10的平面圖。半導體封裝10之重分佈層30僅可藉由封裝接觸件17從外部接達。
需要依具成本效益方式促進測試及減輕缺陷之半導體封裝及封裝技術。其他劣勢及缺點可存在於先前技術中。
依據本發明之一實施例，係特地提出一種封裝一半導體裝置之方法，該半導體裝置具有在該半導體裝置之一表面上之至少一接合墊，該方法包含：形成電耦合至該至少一接合墊之一重分佈材料；形成一介電材料在與該至少一接合墊相對的該重分佈材料之一側上；及移除該介電材料之一第一部分以暴露該重分佈材料之一第一部分。
10‧‧‧半導體封裝
11‧‧‧半導體裝置
12‧‧‧鈍化層
13‧‧‧接合墊
14‧‧‧介電層
15‧‧‧重分佈層
16‧‧‧介電層
17‧‧‧封裝接觸件
30‧‧‧重分佈層
40‧‧‧測試程序
100‧‧‧半導體封裝
110‧‧‧半導體裝置；半導體晶粒
111‧‧‧底部表面
112‧‧‧頂部表面
114‧‧‧鈍化層
120‧‧‧接合墊；重佈線接合墊
121‧‧‧測試接合墊
122‧‧‧測試接合墊
123‧‧‧功能接合墊
124‧‧‧功能接合墊
125‧‧‧功能接合墊
126‧‧‧功能接合墊
130‧‧‧(第一)介電層
131‧‧‧開口
140‧‧‧重分佈層
141‧‧‧終端
142‧‧‧重分佈線
143‧‧‧重分佈區域
144‧‧‧重分佈線
145‧‧‧終端
146‧‧‧重分佈區域
150‧‧‧(第二)介電層
151‧‧‧開口
152‧‧‧開口
160‧‧‧黏著劑層
161‧‧‧底層凸塊金屬化(UBM)
170‧‧‧封裝接觸件
200‧‧‧半導體封裝
210‧‧‧半導體裝置；半導體晶粒
211‧‧‧底部表面
212‧‧‧頂部表面
214‧‧‧鈍化層
220‧‧‧接合墊
221‧‧‧測試接合墊
222‧‧‧測試接合墊
223‧‧‧功能接合墊
224‧‧‧功能接合墊
225‧‧‧功能接合墊
226‧‧‧功能接合墊
240‧‧‧重分佈層
241‧‧‧終端
242‧‧‧重分佈線
243‧‧‧重分佈區域
244‧‧‧重分佈線
245‧‧‧終端
246‧‧‧重分佈區域
250‧‧‧介電層
251‧‧‧開口
252‧‧‧開口
260‧‧‧黏著劑層
261‧‧‧底層凸塊金屬化(UBM)
270‧‧‧封裝接觸件
S21‧‧‧操作；程序動作
S22‧‧‧操作；程序動作
S23‧‧‧操作；程序動作
S24‧‧‧操作；程序動作
S25‧‧‧操作；程序動作
S26‧‧‧操作；程序動作
S27‧‧‧操作；程序動作
S28‧‧‧操作；程序動作
S31‧‧‧操作；程序動作
S32‧‧‧操作；程序動作
S33‧‧‧操作；程序動作
S34‧‧‧操作；程序動作
S35‧‧‧操作；程序動作
S41‧‧‧操作；程序動作
S42‧‧‧操作；程序動作
S43‧‧‧操作；程序動作
S44‧‧‧操作；程序動作
S45‧‧‧操作；程序動作
圖1A係表示已知當前最新技術的含一經囊封重分佈層之一半導體封裝之一部分的示意截面圖。
圖1B係表示已知所屬技術領域之開始的含一經囊封重分佈層之一半導體封裝的示意等角視圖。
圖2A係根據本揭露一實施例之具有一重分佈層之至少一暴露部分之一半導體封裝之一部分的示意截面圖。
圖2B係根據本揭露一實施例之具有至少一暴露重分佈層之一半導體封裝的示意等角視圖。
圖3係根據本揭露實施例之根據本揭露實施例之用於封裝具有一重分佈層之至少一暴露部分之一半導體裝置之一程序中之動作的流程圖。
圖4A至圖4E係根據本揭露一實施例之經受暴露一重分佈層之至少一部分之一封裝程序的一半導體裝置之部分的示意截面圖。
圖5A至圖5E係根據本揭露一實施例之經受暴露一重分佈層之至少一部分之一封裝程序的一半導體裝置的示意平面圖。
圖6係根據本揭露一實施例之具有一重分佈層之至少一暴露部分之一半導體封裝之一部分的示意截面圖。
圖7係根據本揭露實施例之用於封裝具有一重分佈層之至少一暴露部分之一半導體裝置之一程序中之動作的流程圖。
圖8A至圖8D係根據本揭露一實施例之經受暴露一重分佈層之至少一部分之一封裝程序的一半導體裝置之一部分的示意截面圖。
圖9A至圖9D係根據本揭露一實施例之經受暴露一重分佈層之至少一部分之一封裝程序的一半導體裝置的示意平面圖。
圖10係根據本揭露一實施例之用於測試具有一重分佈層之暴露部分之一半導體封裝之一程序中之動作的流程圖。
本文所提出之圖解闡釋非意欲係一種製造一半導體裝置之方法中之任何特定動作、此一方法之中間產物、半導體裝置、或其組件的實際視圖，而僅僅係經採用以描述本揭露之闡釋性實施例的理想化表示。因此，圖式非必然按比例繪製。
所揭示之實施例大致上關於半導體封裝以及封裝及測試半導體封裝之方法。一些具體揭示之實施例係關於可包括重分佈層之一或多個暴露部分的半導體封裝。該等重分佈層之該等暴露部分可包括一或多個終端，該一或多個終端係導電性且可接達用於與一測試裝置之探針電氣接觸等等。如下文進一步所描述，參考圖5A至圖5E及圖9A至圖9D，重分佈層可包括超過一個終端；事實上，該一或多個重分佈層之重分佈區域可各包括一或多個終端。
本揭露之各種實施例係關於半導體裝置，該等半導體裝置包含「內嵌」或「整合」在裝置之矽或半導體材料中的電氣電路系統。有時候這些半導體裝置亦係稱為半導體晶片。電氣電路系統之實例包括但不限於一積體電路(IC)、一特殊應用積體電路(ASIC)、一微處理器、一記憶體裝置、及其等之組合。
一半導體裝置可係保護該半導體裝置之電路系統、散熱、及固持用於電氣且實體地耦合該半導體裝置與外部電路系統之外部電氣接觸件(例如，凸塊、接針及/或引線)的一「總成」或「封裝」之部分。
用於封裝之技術包括但不限於線接合、捲帶式自動接合、及覆晶。該等封裝技術之中係「晶片尺寸封裝」，其中半導體封裝具有與半導體裝置相同或近似相同之外觀尺寸。習知，晶片尺寸封裝包括導致封裝對晶粒之一比率小於或等於1.2：1的任何封裝程序。當封裝此類半導體裝置時，當維持一較大晶圓之部分包含複數個此類裝置時，該等封裝通常稱為晶圓級晶片尺寸封裝(WLCSP)。
圖2A係根據本揭露一實施例之具有至少一暴露重分佈層140之一半導體封裝100的截面圖。半導體封裝100包括一半導體裝置110、一介電層130、一重分佈層140、一介電層150，及一黏著劑層160，及封裝接觸件170。在半導體裝置110之頂部表面上形成至少一接合墊120及一鈍化層114。
圖2B係根據本揭露一實施例之具有一重分佈層140之至少一暴露部分之一半導體封裝100的等角視圖。經暴露重分佈層140包含終端141及145，該等終端係導電性且可接達至一測試裝置之探針，並且圖2B所展示之其他終端亦係導電性且實體地可接達，但為了簡化論述而未特別參照。
圖3係根據本揭露一實施例之根據本揭露實施例之用於封裝具有至少一暴露重分佈層之一半導體裝置之一程序中之動作的流程圖。
圖4A至圖4E繪示根據本揭露一實施例之一半導體封裝100之一封裝程序的截面圖，該封裝程序暴露半導體封裝100之一重分佈層140之一或多個部分。
參考圖4A，展示一半導體晶粒110具有一近似平坦底部表面111及與底部表面111相對之一近似平坦頂部表面112。半導體晶粒110具有形成於頂部表面112上之至少一接合墊120。半導體晶粒110具有形成於頂部表面112上之一合適厚度的一鈍化層114(例如，氮化物，諸如氮化矽)，使得接合墊120被開放，即，使得鈍化層114覆蓋頂部表面112，但未覆蓋接合墊120之一些或全部。
參考圖4B，展示一合適厚度的一第一介電層130形成於鈍化層114上。第一介電層130可覆蓋整個鈍化層114且形成有開口131，使得接合墊120被暴露。舉非限制性實例而言，第一介電層130之一合適厚度可於3μm與20μm之間(包含3μm與20μm)變化。
在一實施例中，藉由一微影程序形成開口131，該微影程序包含：施加一光阻材料至介電層130；根據一預定圖案遮罩該光阻層；暴露該經遮罩光阻層；顯影該光阻層且蝕刻第一介電層130之一部分，以形成開口131且暴露接合墊120；剝除任何剩餘光阻材 料；及固化該介電材料。所屬技術領域中具有通常知識者將瞭解，該微影程序之變化存在或係可行的且可使用。
舉非限制性實例而言，該介電材料可係聚醯亞胺、苯並環丁烯(Benzocyclobutane)、聚苯并惡唑(Polybenzoxazole)、雙馬來醯亞胺-三氮雜環(bismaleimidetriazine)、酚醛(Phenolic)樹脂、環氧化物、聚矽氧、氧化物層、氮化物層、及相似材料。在一實施例中，在攝氏100度至攝氏400度(包含攝氏100度與攝氏400度)執行聚醯亞胺介電材料之固化歷經一或多個固化相，達至多90分鐘直到達成所欲硬度。可取決於所選擇用作為該介電材料的材料來選擇固化條件。
在另一實施例中，第一介電層130之介電材料係由一光可界定性聚合物所構成，舉例而言，一正片作用性聚醯亞胺、一負影調性(negative tone)聚醯亞胺、或一負片作用性聚醯亞胺。開口131係藉由下列而形成：藉由旋轉塗佈、一輥塗或相似程序塗佈一光可界定性聚合物於鈍化層114上；半固化該材料；遮罩半固化介電層130；暴露經遮罩第一介電層130；顯影第一介電層130以形成開口131且暴露接合墊120；及最終固化該光可界定性聚合物以形成第一介電層130。
參考圖4C，展示一合適厚度的一重分佈層140形成於第一介電層130上。舉非限制性實例而言，重分佈層140之一合適厚度可於1μm與20μm之間(包含1μm與20μm)變化。
在一實施例中，重分佈層140可藉由一濺射沉積程序而形成於第一介電層130及經暴露接合墊120上。在其他實施例中，可 利用其他沉積程序，舉例而言，濺射後續接著電鍍。重分佈層140之一區域經形成以具有一預界定長度(截面圖)及面積(平面圖)。該重分佈層之一部分經定位而相鄰於封裝接觸件170(例如，在該封裝接觸件下方)以電氣且實體地耦合接合墊120至封裝接觸件170。重分佈層140進一步經形成以包括一終端141。在此實施例中，終端141經重新定位遠離接合墊120及封裝接觸件170，且電耦合至該接合墊及該封裝接觸件；然而，如將參考圖5A至圖5D而更詳細地解釋，終端141之部位係一設計考慮。舉非限制性實例而言，終端可依一對角、圓等而組織成圍繞一半導體封裝之一表面之周長、在一半導體封裝之一表面之中心中經分群組一起、在一半導體封裝之側壁上。
在一實施例中，重分佈層140包含一經濺射鈦黏著性層、一經濺射銅導電層、及增層鍍(plated-up)銅。重分佈層140可由其他材料所製成，該等其他材料合適地導電且合適地黏附至第一介電層130及介電層150之聚合物(參見圖2A)。舉非限制性實例而言，重分佈層140可包含鈦、鉻、鋁、銅、鎳、鎢、鈷、及其等之組合之任一者之一或多個層或合金。
參考圖4D，展示一合適厚度的一第二介電層150形成於重分佈層140及第一介電層130上。舉非限制性實例而言，第二介電層150之一合適厚度可於3μm與20μm之間(包含3μm與20μm)變化。
第二介電層150經形成而具有開口151(其使得在將定位該封裝接觸件所在之區域中暴露重分佈層140之至少一部分)及開 口152(其在終端141上方之區域中)。在一實施例中，開口151及152係藉由本文所描述用以在介電層130中形成開口131(參見圖4B)之實質上相同程序之一者而形成。
舉非限制性實例而言，第二介電層150之介電材料可係聚醯亞胺、苯並環丁烯、聚苯并惡唑、雙馬來醯亞胺-三氮雜環、酚醛樹脂、環氧化物、聚矽氧、氧化物層、氮化物層、及相似材料。舉進一步非限制性實例而言，第二介電層150之介電材料亦可係一光可界定性聚合物。
參考圖4E，展示一黏著劑層160及封裝接觸件170(在此實施例中，一焊球)經形成而橫跨開口151並且在重分佈層140上且與該重分佈層導電耦合。舉非限制性實例而言，黏著劑層160之一合適厚度可於1μm與20μm之間(包含1μm與20μm)變化。
黏著劑層160可部分覆蓋第二介電層150。在一實施例中，黏著劑層160可可藉由一濺射沉積程序透過開口151而形成於重分佈層140上。在其他實施例中，可利用其他沉積程序，舉例而言，蒸鍍、濺射後續接著電鍍、或蒸鍍後續接著電鍍。在一實施例中，黏著劑層160係一可焊接黏著性金屬層且包含一經濺射鈦黏著性層、一經濺射銅導電層、及增層鍍銅。
黏著劑層160可由其他材料所製成，該等其他材料合適地導電且合適地黏附至重分佈層140及封裝接觸件170，並且允許封裝接觸件170合適地回焊。舉非限制性實例而言，黏著劑層160可包含鈦、鉻、鋁、銅、鎳、鎢、鈷、及其等之組合之任一者之一或多個 層或合金。在一實施例中，黏著劑層160係一底層凸塊金屬化(UBM)層或層堆疊。
封裝接觸件170形成於黏著劑層160上且黏附至該黏著劑層。在一實施例中，封裝接觸件170可係包含(舉非限制性實例而言)錫、錫合金、銀、銅、鈷、鉍鋅、及其等之任何組合的一無鉛合金焊球。
雖然結合圖4E所繪示之實施例來繪示及描述一黏著劑層160，然而具體設想，在另一實施例中，自結構部分或完全省略黏著劑層160。在此一實施例中，封裝接觸件170(例如，一焊球)形成於重分佈層140之一或多個部分上並且電氣且實體地耦合至重分佈層140。
仍參考圖4E，半導體封裝100包括在開口152上方之終端141。開口152及終端141提供導電接達至接合墊120，並且實現測試及重新程式化在半導體裝置110中之半導體電子器件，包括一WLSCP之晶圓級之一積體電路。
用以固化介電層130及介電層150之聚合物之高溫可引起半導體封裝100超出規格操作。在之一WLSCP特定案例中，高溫可引起積體電路中之電荷損失，而導致程式化邊限偏移超出規格。可在封裝程序中之各種步驟執行測試及補救。較佳地，在封裝程序中之所有高溫處理步驟後(舉例而言，在固化介電層後)執行測試及補救。測試圖1A及圖1B所繪示之半導體封裝之類型之一WLCSP具挑戰性且費用高。在半導體裝置上之某些接合墊係特定用於測試，並且 必須在封裝層之前執行測試而使該等接合墊無法接達。然而，應在會影響電荷特性的所有高溫程序步驟後執行重調節基礎電路系統之程式化邊限偏移。
如將參考圖5A至圖5E所描述，藉由開口151促進測試及重新程式化圖2A及圖2B所繪示之半導體封裝100，該等開口容許導電接達至測試接合墊(用於測試電路系統)且導電接達至功能接合墊(用於介接及重新程式化電路系統)。
圖5A至圖5E繪示根據本揭露一實施例之圖4A至圖4E所展示之半導體封裝100之封裝程序的平面圖，該封裝程序暴露半導體封裝100之重分佈層140之至少一部分。
參考圖5A，展示半導體晶粒110及頂部表面112的平面圖。亦展示接合墊120，在此實施例中，該等接合墊包含測試接合墊121及122，以及功能接合墊123、124、125及126。接合墊120之部位與數目係可基於下列而變化的一設計考慮：半導體晶粒之尺寸；該晶粒中之電子器件；最終半導體封裝將遵循之標準；該最終半導體封裝之形式、契合度、功能需求；及其等之組合。
參考圖5B，展示根據本揭露一實施例之部分組裝之半導體封裝100(且更具體而言，介電層130及接合墊120)的平面圖。測試接合墊121及122以及功能接合墊123、124、125、及126之各者歸因於形成於介電層130中之開口而被暴露。在此實施例中，在形成介電層120後，半導體晶粒110上的所有接合墊130被暴露，然而在此實施例中，具體設想一些接合墊120可被介電層130所覆 蓋。舉非限制性實例而言，用以測試半導體封裝100之功能操作的外來之接合墊120可被介電層130覆蓋。
參考圖5C，展示根據本揭露一實施例之部分組裝之半導體封裝100(且更具體而言，重分佈層140)的平面圖。在此實施例中，重分佈層140包含六個導電重分佈區域，然而為了簡化此論述，圖5C僅參照重分佈區域143及146。重分佈區域143包含一重分佈線142及一終端141。重分佈線142電氣且實體地耦合功能接合墊124至將定位一外部封裝接觸件所在之區域(參見圖2A)以及耦合至終端141。重分佈區域146包含一重分佈線144及一終端145。重分佈線144電氣且實體地耦合測試接合墊121至終端145。
參考圖5D，展示根據本揭露一實施例之部分組裝之半導體封裝100(且更具體而言，介電層150、以及重佈線測試接合墊及重佈線功能接合墊)的平面圖。對於重分佈區域143及146之重佈線接合墊(且相似地，對於其他重分佈區域)，歸因於形成於介電層150中之開口151而分別暴露終端141及145。將定位封裝接觸件170(參見圖2A)的重分佈線142之部分亦歸因於形成於介電層150中之開口152而被暴露。
參考圖5E，展示根據本揭露一實施例之部分組裝之半導體封裝100(且更具體而言，黏著劑層160)的平面圖。圖中展示含封裝接觸件的四個UBM，然而僅參照含有定位於其上之封裝接觸件170之UBM 161。重佈線接合墊120之終端被暴露，且可獨立於該封裝接觸件來電氣且實體地接達該等終端及接合墊120。
在圖5E所展示之實施例中，終端141及145之表面被實體且電氣暴露，然而在替代實施例中，終端141及145可塗佈有合適地導電的另一材料。此一材料可在封裝及其他程序期間保護終端141及145免於污染物。在一實施例中，用於施加黏著劑層160之程序可包括至該等重分佈區域之該等終端。
在另一實施例中，一金屬填充物可沉積於該等暴露終端上直至由介電層150之開口151所形成之間隙。可沉積預定量之該金屬填充物，或可沉積金屬填充物直至在介電層150之頂部表面下方或上方之一定準位。在一實施例中，該金屬填充物之該頂部表面與介電層150之頂部表面近似齊平。
圖6繪示根據本揭露一實施例之一半導體封裝200的截面圖，其中重分佈層240形成於鈍化層214上，且無一介電層介於該重分佈層與該鈍化層之間。
圖7繪示根據本揭露實施例之用於封裝具有至少一暴露重分佈層之一半導體封裝200之一程序中之動作的流程圖。
圖8A至圖8D繪示根據本揭露另一實施例之用於封裝一半導體封裝200之一程序的截面圖，該程序暴露半導體封裝200之至少一重分佈層240。
參考圖8A，展示一半導體晶粒210具有一近似平坦底部表面211及與底部表面211相對之一近似平坦頂部表面212。半導體晶粒210具有形成於頂部表面212上之至少一接合墊220。半導體晶粒210具有形成於頂部表面212上之一合適厚度的一鈍化層214 (例如，氮化物或氮化矽)，使得接合墊220被開放，即，使得鈍化層214覆蓋頂部表面212，但未覆蓋接合墊220之一些或全部。
參考圖8B，展示一合適厚度的一重分佈層240形成於鈍化層214上。舉非限制性實例而言，重分佈層130之一合適厚度可於1μm與20μm之間(包含1μm與20μm)變化。
在一實施例中，重分佈層240可藉由一濺射沉積程序而形成於鈍化層214及經暴露接合墊220上。在其他實施例中，可利用其他沉積程序，舉例而言，濺射後續接著電鍍。重分佈層240之一區域經形成以具有一預界定長度(截面圖)及面積(平面圖)。重分佈層240之一部分經定位而相鄰於封裝接觸件270以直接電氣且實體地耦合接合墊220至封裝接觸件270。重分佈層240進一步經形成以包括一終端241。在此實施例中，終端241經重新定位遠離接合墊220及封裝接觸件270，且電耦合至該接合墊及該封裝接觸件；然而，如將參考圖9A至圖9D而更詳細地解釋，終端241之部位係一設計考慮。舉非限制性實例而言，終端可依一對角、一圓等而組織成圍繞一半導體封裝之一表面之周長、在一半導體封裝之一表面之中心中經分群組一起、在一半導體封裝之側壁上。
在一實施例中，重分佈層240包含一經濺射鈦黏著性層、一經濺射銅導電層、及增層鍍銅。重分佈層240可由其他材料所製成，該等其他材料合適地導電且合適地黏附至介電層250(參見圖6)及鈍化層214之聚合物。舉非限制性實例而言，重分佈層240可包 含鈦、鉻、鋁、銅、鎳、鎢、鈷、及其等之組合之任一者之一或多個層或合金。
參考圖8C，展示一合適厚度的一介電層250形成於重分佈層240及鈍化層214上。舉非限制性實例而言，介電層250之一合適厚度可於1μm與20μm之間(包含1μm與20μm)變化。
介電層250經形成而具有開口251(其使得在將定位該封裝接觸件所在之區域中暴露重分佈層240之至少一部分)及開口252(其用以暴露終端241)。
在各種實施例中，藉由一微影程序形成開口251及252，該微影程序包含：施加一光阻材料至介電層250；根據一預定圖案遮罩該光阻層；暴露該經遮罩光阻層；顯影該光阻層且蝕刻介電層250之部分，以形成開口251及252且暴露終端241及將定位該封裝接觸件所在的重分佈層240之部分；剝除任何剩餘光阻材料；及固化該介電材料。所屬技術領域中具有通常知識者將瞭解，該微影程序之變化存在或係可行的且可使用。
舉非限制性實例而言，該介電材料可係聚醯亞胺、苯並環丁烯、聚苯并惡唑、雙馬來醯亞胺-三氮雜環、酚醛樹脂、環氧化物、聚矽氧、氧化物層、氮化物層、及相似材料。在一實施例中，在攝氏100度至攝氏400度(包含攝氏100度與攝氏400度)執行固化歷經一或多個固化相，達至多90分鐘直到達成所欲硬度。
在另一實施例中，介電層250之介電材料係由一光可界定性聚合物所構成，舉例而言，一正片作用性聚醯亞胺、一負影調性 聚醯亞胺、或一負片作用性聚醯亞胺。開口231及232係藉由下列而形成：藉由旋轉塗佈、一輥塗或相似程序塗佈一光可界定性聚醯亞胺於重分佈層240上；半固化該材料；遮罩介電層250；暴露經遮罩介電層250；顯影介電層250以形成開口251及252且暴露終端241及將定位該封裝接觸件所相鄰的重分佈層240之部分；及最終固化該光可界定性聚醯亞胺以形成介電層250。
參考圖8D，展示一黏著劑層260及封裝接觸件270經形成而橫跨開口251並且電氣且實體地耦合至重分佈層240。舉非限制性實例而言，黏著劑層260之一合適厚度可於1μm與20μm之間(包含1μm與20μm)變化。
黏著劑層260可部分覆蓋介電層250。在一實施例中，黏著劑層260可可藉由一濺射沉積程序透過開口251而形成於重分佈層240上。在其他實施例中，可利用其他沉積程序，舉例而言，蒸鍍、濺射後續接著電鍍、或蒸鍍後續接著電鍍。在一實施例中，黏著劑層260係一可焊接黏著性金屬層且包含一經濺射鈦黏著性層、一經濺射銅導電層、及增層鍍銅。
黏著劑層260可由其他材料所製成，該等其他材料合適地導電且合適地黏附至重分佈層240及封裝接觸件270，並且允許封裝接觸件270合適地回焊。舉非限制性實例而言，黏著劑層260可包含鈦、鉻、鋁、銅、鎳、鎢、鈷、及其等之組合之任一者之一或多個層或合金。在一實施例中，可焊接黏著性金屬層260係一底層凸塊金屬化(UBM)層或層堆疊。
封裝接觸件270形成於黏著劑層260上且黏附至該黏著劑層。在一實施例中，封裝接觸件270可係包含(舉非限制性實例而言)錫、錫合金、銀、銅、鈷、鉍鋅、及其等之任何組合的一無鉛合金焊球。
雖然結合圖8E所繪示之實施例來繪示及描述一黏著劑層260，然而具體設想，在另一實施例中，自結構部分或完全省略黏著劑層260。在此一實施例中，封裝接觸件270形成於重分佈層240之一或多個部分上並且電氣且實體地耦合至重分佈層140。
仍參考圖8D，半導體封裝200包括在終端241上方之開口252。開口252及終端241提供導電接達至接合墊220，並且實現測試及重新程式化在半導體晶粒210中之半導體電子器件，包括一WLSCP之晶圓級之一積體電路。
如將參考圖9A至圖9D而明白，藉由開口251促進測試及重新程式化圖6所繪示之半導體封裝200，該等開口實現導電接達至測試接合墊(例如，用以測試電路系統)且導電接達至功能接合墊(例如，用以與電路系統互動及重新程式化電路系統)。
圖9A至圖9E繪示根據本揭露一實施例之圖8A至圖9E所展示之半導體封裝200之封裝程序的平面圖，該封裝程序暴露半導體封裝200之重分佈層240之至少一部分。
參考圖9A，展示半導體晶粒210及頂部表面212的平面圖。亦展示接合墊220，在此實施例中，該等接合墊包含測試接合墊221及222，以及功能接合墊223，224，225及226。接合墊220 之部位與數目係可基於下列而變化的一設計考慮：半導體晶粒之尺寸；該晶粒中之電子器件；最終半導體封裝將遵循之標準；該最終半導體封裝之形式、契合度、功能需求；及其等之組合。
參考圖9B，展示根據本揭露一實施例之部分組裝之半導體封裝200(且更具體而言，重分佈層240)的平面圖。在此實施例中，重分佈層240包含六個重分佈區域，然而為了簡化此論述，圖7C僅參照重分佈區域243及246。重分佈區域243包含一重分佈線242及一終端241。重分佈線242電氣且實體地耦合功能接合墊224至將定位一封裝接觸件所相鄰的該重分佈區域之部分(參見圖6)以及終端241。重分佈區域246包含一重分佈線244及一終端245。重分佈線244電氣且實體地耦合測試接合墊221至終端245。
參考圖9C，展示根據本揭露一實施例之部分組裝之半導體封裝200(且更具體而言，介電層250、以及重佈線測試接合墊及重佈線功能接合墊)的平面圖。對於重分佈區域243及246之重佈線接合墊(且相似地，對於其他重分佈區域)，歸因於形成於介電層250中之開口251而分別暴露終端241及245。形成於介電層250中之開口252亦暴露封裝接觸件270將黏附於其上的重分佈線242之部分(參見圖6)。
參考圖9D，展示根據本揭露一實施例之部分組裝之半導體封裝200(且更具體而言，黏著劑層260)的平面圖。圖中展示含封裝接觸件的四個UBM，然而僅參照含有定位於其上之封裝接觸件 270之UBM 261。重佈線接合墊220之終端被暴露，且可獨立於該封裝接觸件來電氣且實體地接達該等終端及接合墊220。
在此實施例中，直接暴露終端241及245之表面，然而，在替代實施例中，終端241及245可塗佈有合適地導電的另一材料。此一材料可在封裝及其他程序期間保護終端241及245免於污染物。在一實施例中，用於施加黏著劑層260之程序可包括施加黏著劑層260至該等重分佈區域之該等終端。
在另一實施例中，一金屬填充物可沉積於該等暴露終端上直至由介電層250之開口251所形成之間隙。可沉積預定量之該金屬填充物，或可沉積金屬填充物直至在介電層250之頂部表面下方或上方之一定準位。在一實施例中，該金屬填充物之該頂部表面與介電層250之頂部表面近似齊平。
圖10繪示根據本揭露一例示性實施例之一半導體封裝(諸如半導體封裝100及半導體封裝200)或一部分組裝之變體之一測試程序40。
在操作S41中，提供具有一暴露重分佈層之一半導體封裝。在此實施例中，該半導體封裝係一部分封裝，諸如圖4D、圖5D、圖8C及圖9C所展示之部分封裝，但是亦可係一完全組裝之半導體封裝。較佳地，測試封裝的階段可與完成所有高溫程序步驟一致。為了簡化說明，將使用圖4D及圖5D所展示之部分封裝之元件符號。
在S42操作中，介接一晶圓探測器(圖中未展示)與該半導體封裝。一晶圓探測器探測針可經定位成與該半導體封裝之暴露終端141及145之一或多者導電接觸。
在S43操作中，藉由該晶圓探測器執行該半導體封裝之電氣測試。電氣測試可包括藉由在暴露終端141及144之一或多者處產生測試電壓及讀取終端141及144之一或多者處的電壓來測試該半導體裝置之基礎電氣電路系統。
在S44操作中，偵測到電荷損失及/或程式化邊限偏移規格(或無電荷損失及/或程式化邊限偏移)。若偵測到程式化邊限偏移，則在S45操作中，可重新程式化基礎電路。
雖然已就某些層而論來描述本揭露之各種實施例，然而本揭露之範疇不應如此受限制。具體設想，在封裝封裝中可包括額外層。舉非限制性實例而言，黏著性層可包括於一重分佈層與介電層之間以耦合該重分佈層之金屬至該等介電層之聚合物。
進一步具體設想，在封裝程序中可形成超過一個重分佈層。舉例而言，可新增重分佈層以促進透過封裝之導電以用於接地平面及電力平面。此類重分佈層可包括或可不包括經暴露終端，諸如重分佈層140。
最終，雖然已就具有一「厚度」之層而論來描述本揭露之各種實施例，並且附圖可似乎展示一致厚度，然而具體設想，一層之厚度可變化，舉非限制性實例而言，以適應最終封裝之所欲特性， 舉例而言，信號特性、熱、結構強度、及類似物。進一步，厚度可簡單地鑑於應用程序之不完美而變化。
雖然藉由或結合圖1至圖9及隨附文字所說明的各操作敘述以特定次序實施的動作，本揭露的實施例不必然需要以所敘述的次序操作。所屬技術領域中具有通常知識者將認知許多變化，包括平行地或以不同的次序實施動作。
下文提出本揭露之額外非限制性實例實施例。
實施例1：一種封裝一半導體裝置之方法，該半導體裝置具有在該半導體裝置之一表面上之至少一接合墊，該方法包含：形成電耦合至該至少一接合墊之一重分佈材料；形成一介電材料在與該至少一接合墊相對的該重分佈材料之一側上；及移除該介電材料之一第一部分以暴露該重分佈材料之一第一部分。
實施例2：如實施例1之方法，其進一步包含移除該介電材料之一第二部分以暴露該重分佈材料之一第二部分。
實施例3：如實施例2之方法，其進一步包含形成一黏著劑材料於該重分佈材料之該第二部分上。
實施例4：如實施例3之方法，其中該黏著劑材料係一可焊接黏著劑。
實施例5：如實施例4之方法，其進一步包含提供一封裝接觸件於該黏著劑材料上。
實施例6：如實施例2至5中任一項之方法，其進一步包含提供一封裝接觸件於該重分佈材料之該第二部分上。
實施例7：如實施例5或實施例6之方法，其中在提供該封裝接觸件後該重分佈層之該第一部分維持被暴露。
實施例8：一種重分佈層，其包含：一第一部分，其經形成而相鄰於且電耦合至一半導體封裝之一第一接觸件；一第二部分，其藉由一介電材料中之一第一開口而被暴露；及一重分佈線，其電耦合至一第一接合墊、該第一部分、及該第二部分。
實施例9：如實施例8之重分佈層，其中該第二部分可經由該介電材料中之該第一開口而電氣且實體地接達。
實施例10：如實施例8之重分佈層，其進一步包含一第三部分，該第三部分藉由該介電材料中之一第二開口而被暴露。
實施例11：如實施例10之重分佈層，其中該第三部分電耦合至一第二接合墊。
實施例12：如實施例11之重分佈層，其中該第一接合墊係用於與一半導體裝置進行輸入/輸出，且該第二接合墊係用於測試該半導體裝置。
實施例13：一種半導體封裝，其包含實施例8至13中任一項之重分佈層。
實施例14：一種半導體封裝，其包含：一或多個電氣且實體地可接達終端；及在該半導體封裝之一表面處之一或多個接觸件。
實施例15：一種測試一半導體封裝之方法，其包含：使至少一探測針與一半導體封裝之至少一終端電氣且實體接觸；透過 該至少一終端提供來自該至少一探測針之一或多個測試電信號至該半導體封裝；及偵測指示一電荷損失或程式化邊限偏移之信號。
實施例16：如實施例15之方法，其進一步包含回應於該等所偵測信號而重新程式化該半導體封裝之電路系統。
實施例17：如實施例16之方法，其中重新程式化該半導體封裝之電路系統包含使用至少一封裝接觸件。
實施例18：如實施例17之方法，其中該至少一封裝接觸件遠離該至少一終端。
雖然特定繪示的實施例已結合該等圖式而描述，所屬技術領域中具有通常知識者將理解並了解本揭露的範圍不限於本揭露明確表示及描述的實施例。此外，可對本揭露所描述之實施例的添加、刪除、及修飾以產生在本揭露範圍內的實施例，諸如所特別請求的，包括法律均等物。另外，自一所揭露的實施例之特徵可與另一所揭露的實施例的特徵結合，同時仍在本揭露的範圍內，如本案發明人設想者。

Claims (17)

  1. 一種封裝一半導體裝置之方法，該半導體裝置具有在該半導體裝置之一表面上之至少一接合墊，該方法包含：形成電耦合至該至少一接合墊之一重分佈材料；形成一介電材料在與該至少一接合墊相對的該重分佈材料之一側上；及移除該介電材料之一第一部分以暴露該重分佈材料之一第一部分。
  2. 如請求項1之方法，其進一步包含移除該介電材料之一第二部分以暴露該重分佈材料之一第二部分。
  3. 如請求項2之方法，其進一步包含形成一黏著劑材料於該重分佈材料之該第二部分上。
  4. 如請求項3之方法，其中該黏著劑材料係一可焊接黏著劑。
  5. 如請求項4之方法，其進一步包含提供一封裝接觸件於該黏著劑材料上。
  6. 如請求項2至5中任一項之方法，其進一步包含提供一封裝接觸件於該重分佈材料之該第二部分上。
  7. 如請求項6之方法，其中在提供該封裝接觸件後該重分佈材料之該第一部分維持被暴露。
  8. 如請求項2至5中任一項之方法，其進一步包含在移除該介電材料之該第一部分後及在移除該介電材料之該第二部分後測試該半導體裝置，該測試包含：使至少一探測針與該重分佈材料之該第一部分電氣且實體接觸； 透過該重分佈材料之該第一部分提供來自該至少一探測針之一或多個測試電信號至該半導體封裝；及偵測指示一電荷損失或程式化邊限偏移之信號。
  9. 如請求項8之方法，其進一步包含回應於該等所偵測信號而重新程式化該半導體封裝之電路系統。
  10. 如請求項9之方法，其中重新程式化該半導體封裝之電路系統包含使用至少一封裝接觸件。
  11. 如請求項10之方法，其中該至少一封裝接觸件遠離該重分佈材料之該第一部分。
  12. 一種重分佈層，其包含：一第一部分，其經形成而相鄰於且電耦合至一半導體封裝之一第一接觸件；一第二部分，其藉由一介電材料中之一第一開口而被暴露；及一重分佈線，其電耦合至一第一接合墊、該第一部分、及該第二部分。
  13. 如請求項12之重分佈層，其中該第二部分可經由該介電材料中之該第一開口而電氣且實體地接達。
  14. 如請求項12之重分佈層，其進一步包含一第三部分，該第三部分藉由該介電材料中之一第二開口而被暴露。
  15. 如請求項14之重分佈層，其中該第三部分電耦合至一第二接合墊。
  16. 如請求項15之重分佈層，其中該第一接合墊係用於與一半導體裝置進行輸入/輸出，且該第二接合墊係用於測試該半導體裝置。
  17. 一種半導體封裝，其包含如請求項12至16中任一項之重分佈層。
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