TW201832334A - 電子封裝結構 - Google Patents

電子封裝結構 Download PDF

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Publication number
TW201832334A
TW201832334A TW106104871A TW106104871A TW201832334A TW 201832334 A TW201832334 A TW 201832334A TW 106104871 A TW106104871 A TW 106104871A TW 106104871 A TW106104871 A TW 106104871A TW 201832334 A TW201832334 A TW 201832334A
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Taiwan
Prior art keywords
package structure
electronic package
stress
conductive layer
substrate
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TW106104871A
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English (en)
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TWI632653B (zh
Inventor
張景堯
張道智
呂芳俊
韓偉國
高國書
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財團法人工業技術研究院
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Application filed by 財團法人工業技術研究院 filed Critical 財團法人工業技術研究院
Priority to TW106104871A priority Critical patent/TWI632653B/zh
Priority to CN201710217037.3A priority patent/CN108428671A/zh
Priority to US15/487,754 priority patent/US20180233477A1/en
Application granted granted Critical
Publication of TWI632653B publication Critical patent/TWI632653B/zh
Priority to US16/108,272 priority patent/US11114387B2/en
Publication of TW201832334A publication Critical patent/TW201832334A/zh

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  • Engineering & Computer Science (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Die Bonding (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

一種電子封裝結構係將晶片結合於承載件之金屬凸塊上，且藉由應力緩衝材包覆該金屬凸塊周圍以作為應力緩衝部，而提升應力緩衝之效果，藉此防止該晶片因應力而破裂之問題。

Description

電子封裝結構
本揭露係有關一種電子封裝結構，尤指一種能提升可靠度之電子封裝結構。
隨著電子產業的蓬勃發展，電子產品也逐漸邁向多功能、高性能的趨勢。目前應用於晶片封裝領域之技術，例如晶片尺寸構裝(Chip Scale Package，簡稱CSP)、晶片直接貼附封裝(Direct Chip Attached，簡稱DCA)或多晶片模組封裝(Multi-Chip Module，簡稱MCM)等覆晶型態的封裝模組、或將晶片立體堆疊化整合為三維積體電路(3D IC)晶片堆疊技術等。
一般的半導體封裝技術中，例如，第1圖所示之打線封裝技術，半導體封裝結構1係於一封裝基板10(或導線架)之置晶墊100上藉由結合層11(例如膠材)結合一半導體晶片14(其主要材質例如為矽)之非主動面14b，再利用打線製程形成複數銲線15以電性連接該封裝基板10之線路層101與該半導體晶片14之主動面14a之電極140。之後，該封裝基板10可藉由形成於其下側之銲球(圖未示)電性連接至電路板(圖未示)或外部裝置(圖未示)。
使用該半導體封裝結構1之方式係例如將該半導體封裝結構1與控制系統外掛於馬達週邊，透過信號線與馬達連接，藉以控制馬達運轉與接收馬達迴授訊號，以偵測到所需之馬達數據。
然而，隨著科技之演進及空間配置之需求，係將該半導體封裝結構1直接設置於馬達本體(外殼或內部空間)，故於馬達與該半導體封裝結構1運作時，不僅馬達本身會發熱，該半導體封裝結構1也會發熱，使得該半導體封裝結構1在高溫下運作，將會發生劇烈的潛變(Creep)效應，不利於銲點機械強度的維持而無法滿足模組對可靠度的要求。機械應力也是另一個造成模組損壞的原因，機械應力的來源不外乎使用機械方式固定該半導體封裝，或馬達運轉產生的震動，都是造成銲點或晶片因機械應力產生破壞的可能性。
因此，為了改良上述缺失，遂將該半導體晶片14之主要材質改為碳化矽(Silicon carbide，簡稱SiC)以作為功率元件，且該結合層11之材質改為金屬材，以抵制應力(熱應力與機械應力)之傳遞，例如，該結合層11之材質係為燒結銀，其燒結壓力可降低燒結銀的孔洞而提昇接點緻密性，且配合銀的高導熱效果，能顯著提升該半導體晶片14運作發熱之散熱。另一方面，於接合該半導體晶片14與該結合層11之金屬材後，會於兩者之間形成一介金屬化合物，其為脆性材料，承受熱應力與機械應力之能力較弱，特別是該半導體晶片14之外側邊緣的銲接位置。
惟，使用銀材結合層11燒結接合大尺寸的半導體晶片14，該結合層11之外圍常因壓力不均，導致燒結不完全而形成較多孔隙，且製程也常受印刷塗佈方式之影響，導致該結合層11之外圍底部會局部鏤空，故上述因素會造成該半導體晶片14橫向破裂，且破裂之啟始位置為該半導體晶片14之側壁，如第1圖所示之破裂處k。
另一方面，銀接點材質較硬，對於應力釋放能力較弱，當承受熱應力與機械應力時，容易從該半導體晶片14之外側處開始破裂，如第1圖所示之破裂處k。
因此，如何克服一般技術之種種缺點，實為目前各界亟欲解決之技術問題。
本發明揭露一種電子封裝結構，係包括：基板；導電層，係形成於該基板上；介金屬化合物，係形成於該導電層上；應力緩衝材，係形成於該基板上並鄰接該導電層；以及電子元件，係設於該介金屬化合物與該應力緩衝材上且接觸該介金屬化合物。
本發明之電子封裝結構主要藉由該應力緩衝材鄰接該導電層，使該導電層與該應力緩衝材一併作為應力緩衝部，故相較於一般技術，本發明之電子封裝結構能提升應力緩衝之效果，以有效防止該電子元件因應力而破裂之問題。
1‧‧‧半導體封裝結構
10‧‧‧封裝基板
100‧‧‧置晶墊
101‧‧‧線路層
11‧‧‧結合層
14‧‧‧半導體晶片
14a‧‧‧主動面
14b‧‧‧非主動面
140‧‧‧電極
15‧‧‧銲線
2,3‧‧‧電子封裝結構
20,30‧‧‧基板
21‧‧‧導電層
22‧‧‧介金屬化合物
23,33‧‧‧應力緩衝材
24‧‧‧電子元件
24a‧‧‧金屬層
300‧‧‧結合墊
330‧‧‧銲料
331‧‧‧有機材料
A‧‧‧正投影面積
B,C,D‧‧‧佈設區域面積
k‧‧‧破裂處
第1圖係為一般半導體封裝結構之剖面示意圖； 第2圖係為本揭露之電子封裝結構之一實施例的局部剖面示意圖；以及第2’圖係為第2圖之局部下視示意圖；第3圖係為本揭露之電子封裝結構之另一實施例的局部剖面示意圖；以及第3’圖係為第3圖之局部下視示意圖。
以下藉由特定的具體實施例說明本揭露之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本揭露之其他優點及功效。
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本揭露可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本揭露所能產生之功效及所能達成之目的下，均應仍落在本揭露所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如「上」及「一」等之用語，亦僅為便於敘述之明瞭，而非用以限定本揭露可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本揭露可實施之範疇。
第2圖係為本揭露之電子封裝結構之一實施例的局部剖面示意圖。如第2圖所示，本揭露之電子封裝結構2係包括：一承載用之基板20、一導電層21、一介金屬化合物(Intermetallic compound，簡稱IMC)22、一應力緩衝材 23以及一電子元件24。
所述之基板20係為金屬板，如金板、銀板、銅板或鎳板。
所述之導電層21係形成於該基板20上且包含金屬材。於本實施例中，該金屬材係以銀為例，即該導電層21為各種態樣之銀層，但於其它實施例中，該金屬材亦可為金、銅、鎳或其它金屬材質。因此，該導電層21之材質並無特別限制，只需符合低熱組/高導熱、低組抗、低溫組裝/高溫應用、耐高溫(大於400℃)等特性即可，且該導電層21與基板20的材質可選擇相同或不同。
所述之介金屬化合物22係形成於該導電層21上。具體地，該介金屬化合物22係為該電子元件24與該導電層21熱結合(銲料接合)後於兩者之間所產生之結構物，故如後所述，該介金屬化合物22之材質取決該應力緩衝材23之銲料材質。
所述之應力緩衝材23係形成於該基板20上並鄰接該導電層21，且該應力緩衝材23可依需求鄰接該介金屬化合物22。於製作時，係先將該應力緩衝材23包覆該導電層21之側面與頂面，待該電子元件24放置至該應力緩衝材23上後，再熱壓接合方式使該電子元件24與該應力緩衝材23接合，且於該導電層21之頂面上之應力緩衝材23會與該導電層21及該電子元件24背面的金屬層24a(其材質如鎳、銅、銀或其它可銲接之金屬材，以接合該應力緩衝材23之銲料材質)反應形成該介金屬化合物22以接合該 電子元件24。
於本實施例中，該應力緩衝材23係包含銲料(solder)，例如，無鉛銲料或高溫銲料等。
再者，該應力緩衝材23包圍該導電層21之側面，且該應力緩衝材23可依需求包圍該介金屬化合物22之側面。
所述之電子元件24係設於該介金屬化合物22與該應力緩衝材23上並接觸該介金屬化合物22，且該電子元件24可依需求接觸該應力緩衝材23。
於本實施例中，該電子元件24係為半導體元件，係以SiC功率半導體晶片為例，其可例如為金屬氧化物半導體場效電晶體(Metal-Oxide-Semiconductor Field-Effect Transistor，簡稱MOSFET)、絕緣柵雙極電晶體(Insulated Gate Bipolar Transistor，簡稱IGBT)、接面場效電晶體(junction field-effect transistor，簡稱JFET)或二極體(Diode)。
再者，該電子元件24係以該介金屬化合物22與該導電層21作為接地路徑或散熱路徑。
另外，該電子元件24之正投影面積A內之應力緩衝材23之銲料佈設區域面積D係佔該電子元件24之正投影面積A之1%至50%，如第2及2’圖所示。
本發明之電子封裝結構2藉由該應力緩衝材23鄰接(或包圍)該導電層21之側面，以除了該導電層21可作為散熱用之外，該應力緩衝材23亦能作為應力緩衝用，以避免應力傳遞至該電子元件24之側面，故相較於一般技 術，本發明之電子封裝結構2能提升應力緩衝之效果，以有效防止該電子元件24因應力(如習知來自馬達之熱應力)而自其側壁開始破裂之問題。
第3圖係為本揭露之電子封裝結構3之另一實施例的局部剖面示意圖。本實施例與上述實施例之差異在於基板與應力緩衝材之設計，其餘構造大致相同，故以下僅詳細說明相異處，而不再贅述相同處，特此述明。
如第3圖所示，該基板30係具有用以結合該導電層21之結合墊300，且該應力緩衝材33係包含銲料330與有機材料331。
所述之結合墊300係為金屬墊(如銅墊)，且該基板30復具有線路層(圖略)，其可依需求電性連接或未電性連接該結合墊300
於本實施例中，該基板30之板材係為陶瓷板材或有機材料，如玻纖樹脂、介電材或印刷電路板等，但不限於上述。
所述之有機材料331係為絕緣材料，如矽膠或環氧樹脂類型(Epoxy-based)之膠材。
於本實施例中，該電子元件24之正投影面積A內之有機材料331之佈設區域面積B與銲料330之佈設區域面積C之總和(B+C)係佔該電子元件24之正投影面積A之1%至50%，如第3及3’圖所示。
本發明之電子封裝結構3藉由該應力緩衝材33鄰接(或包圍)該導電層21之側面，以除了該導電層21可作 為散熱用之外，該應力緩衝材33亦能作為應力緩衝用，以避免應力傳遞至該電子元件24之側面，故相較於一般技術，本發明之電子封裝結構3能提升應力緩衝之效果，以有效防止該電子元件24因應力(如習知來自馬達之熱應力)而自其側壁開始破裂之問題。
綜上所述，本發明之電子封裝結構係藉由該應力緩衝材鄰接該導電層，使該導電層與該應力緩衝材一併作為應力緩衝部，以提升應力緩衝之效果，而能有效防止該電子元件因應力而破裂之問題，故能提升該電子封裝結構之可靠度。
上述實施例係用以例示性說明本揭露之原理及其功效，而非用於限制本揭露。任何熟習此項技藝之人士均可在不違背本揭露之精神及範疇下，對上述實施例進行修改。因此本揭露之權利保護範圍，應如後述之申請專利範圍所列。

Claims (11)

  1. 一種電子封裝結構，係包括：基板；導電層，係形成於該基板上；介金屬化合物，係形成於該導電層上；應力緩衝材，係形成於該基板上並鄰接該導電層；以及電子元件，係設於該介金屬化合物與該應力緩衝材上且接觸該介金屬化合物。
  2. 如申請專利範圍第1項所述之電子封裝結構，其中，該基板係為金屬板。
  3. 如申請專利範圍第1項所述之電子封裝結構，其中，該基板係具有用以結合該導電層之至少一結合墊。
  4. 如申請專利範圍第1項所述之電子封裝結構，其中，該導電層係包含金屬材。
  5. 如申請專利範圍第4項所述之電子封裝結構，其中，該金屬材係為金、銀、銅或鎳。
  6. 如申請專利範圍第1項所述之電子封裝結構，其中，該應力緩衝材係包含銲料。
  7. 如申請專利範圍第6項所述之電子封裝結構，其中，該應力緩衝材更包含有機材料。
  8. 如申請專利範圍第7項所述之電子封裝結構，其中，該電子元件之正投影面積內之有機材料之佈設區域面積與銲料之佈設區域面積之總和係佔該正投影面積之1% 至50%。
  9. 如申請專利範圍第1項所述之電子封裝結構，其中，該應力緩衝材係包圍該導電層。
  10. 如申請專利範圍第1項所述之電子封裝結構，其中，該電子元件係為半導體元件。
  11. 如申請專利範圍第1項所述之電子封裝結構，其中，該電子元件之正投影面積內之應力緩衝材之佈設區域面積係佔該正投影面積之1%至50%。
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