TW201830587A - 半導體封裝結構及製作半導體封裝結構的方法 - Google Patents

半導體封裝結構及製作半導體封裝結構的方法 Download PDF

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TW201830587A
TW201830587A TW106114593A TW106114593A TW201830587A TW 201830587 A TW201830587 A TW 201830587A TW 106114593 A TW106114593 A TW 106114593A TW 106114593 A TW106114593 A TW 106114593A TW 201830587 A TW201830587 A TW 201830587A
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layer
wafer
coefficient
stress
thermal expansion
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范文正
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力成科技股份有限公司
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Abstract

半導體封裝結構包含封裝層、晶片、應力緩解層及重配置線路層。封裝層具有開口，且晶片設置於封裝層的開口內。應力緩解層設置於晶片及封裝層之間。重配置線路層設置於晶片、應力緩解層及封裝層上方。

Description

半導體封裝結構及製作半導體封裝結構的方法
本發明係有關於一種半導體封裝結構，特別係有關於一種具有應力緩解層的半導體封裝結構。
隨著電子裝置對於晶片面積的要求日漸嚴格，半導體裝置的封裝也面臨了縮減體積的挑戰。由於扇入型與扇出型封裝具有體積小的優勢，因此也成為一種受歡迎的半導體封裝類型。
為了減少晶圓級封裝之腳位所需的面積，重配置線路層常用來對輸入輸出埠重新繞線以增加晶片接腳的間距。較大的晶片接腳間距能夠便於設置焊接錫球或焊接凸塊，以利連接至晶片外部的基板或印刷電路板。
隨著輸入輸出埠的數量增加，有部分的錫球可能會設置在超出晶片本身的面積範圍，也就是所謂的扇出結構。在這類型的扇出型封裝中，重配置線路層會形成於兩種不同的材料上，亦即晶片及包圍晶片的封裝層(例如模封樹脂)。由於晶片和封裝層的熱膨脹係數不同(矽晶片的熱膨脹係數約為2-4ppm/°C，封裝層的熱膨脹係數約為10-50ppm/°C)，重配置線路層的結構可能因為劇烈溫度變化所引起的強熱應力而被破壞。
本發明之一實施例提供一種半導體封裝結構，半導體封裝結構包含封裝層、晶片、應力緩解層及重配置線路層。
封裝層具有開口，而晶片設置於封裝層之開口內。應力緩解層設置於晶片及封裝層之間。重配置線路層設置於晶片、應力緩解層及封裝層上方。應力緩解層用以緩衝晶片及封裝層之間的應力以避免重配置線路層受到損害。
本發明之另一實施例提供一種製作半導體封裝結構的方法，其方法包含將晶片設置於載體，形成應力緩解層於晶片上，封模載體上之晶片以形成包覆晶片之封裝層，及於晶片、應力緩解層及封裝層上形成重配置線路層。
應力緩解層用以緩衝晶片及封裝層之間的應力以避免重配置線路層受到損害。
第1圖為本發明一實施例之半導體封裝結構100的剖面圖。半導體封裝結構100包含封裝層110、晶片120、應力緩解層130及重配置線路層140。
封裝層110可利用如環氧模封材料或樹脂形成。在第1圖中，封裝層110具有開口，而晶片120則可設置於封裝層110的開口內。晶片120可為自晶圓切割所得之晶片，並且可設計成能夠透過其輸入/輸出埠124來執行操作。輸入/輸出埠124可設置於晶片120的主動面。在部分實施例中，晶片120還可包含設置在主動面上的介電層122，且介電層122可在輸入/輸出埠124處留下開口。介電層122可用來避免晶片120暴露於外部空氣以至於受損或不預期地被短路。
重配置線路層140可形成於晶片120及封裝層110的上方以電性連接至晶片120的輸入/輸出埠124。重配置線路層140可為電鍍於晶片120及封裝層110上的導電材料層。導電材料可例如為銅、鋁、合金或其他可導電的材料。
在第1圖中，半導體封裝結構100還可包含焊接凸塊150。焊接凸塊150可設置於重配置線路層140上以電性連接至對應的輸入/輸出埠124。如此一來，晶片120之輸入/輸出埠124就能被重新繞線以進一步使用晶片120周邊外圍的區域。
此外，應力緩解層130可設置於封裝層110與晶片120之間。應力緩解層130可為低楊式係數材料薄膜，其材料可例如包含聚合物、環氧樹脂、高分子材料、樹脂、光阻劑或前述任兩項以上的組合。應力緩解層130的厚度可介於15至100微米。然而應力緩解層的厚度並不限定於前述的範圍。根據設計或製造時所能使用的技術或製程，應力緩解層130的厚度可能會有所差異。在部分實施例中，應力緩解層130的楊式係數可低於200MPa。低楊式係數材料具有彈性、可伸縮的特性使得應力緩解層130成為善於吸收應力的緩解層。因此，雖然晶片120和封裝層110的熱膨脹係數有所差異，但應力緩解層130能夠緩解晶片120及封裝層110之間因為劇烈溫度變化而產生的熱應力，進而避免重配置線路層140受損害。
也就是說，在第1圖中，由於重配置線路層140可形成於晶片120、應力緩解層130及封裝層140的上方，因此透過應力緩解層130吸收晶片120和封裝層110之間的應力，就能夠避免重配置線路層140變形。因此，半導體封裝結構100可以承受劇烈的溫度變化，同時不至於讓重配置線路層140產生破壞。
此外，在部分實施例中，應力緩解層130的熱膨脹係數可介於晶片120的熱膨脹係數與封裝層110的熱膨脹係數之間，其中晶片120的熱膨脹係數為三者之中最小者。
再者，在設置焊接凸塊150之前，半導體封裝結構100可還可包含介電層160，介電層160可設置於重配置線路層140上不需設置焊接凸塊150的部分，因此能夠進一步保護重配置線路層140。
第2圖為本發明另一實施例之半導體封裝結構200的俯視圖。半導體封裝結構200包含封裝層210、晶片120及220、應力緩解層230、重配置線路層240及焊接凸塊250。半導體封裝結構200與半導體封裝結構100具有相似的結構。也就是說，晶片120或晶片220的橫切剖面圖可能會與第1圖所示的橫切剖面圖相同。此外，在部分實施例中，半導體封裝結構還可根據需求包含更多數量的晶片。
由於具有低楊式係數的應力緩解層230是設置於晶片120與封裝層210之間以及晶片220與封裝層210之間，因此應力緩解層230可在溫度變化時，緩解具有不同熱膨脹係數之晶片120、220及封裝層210之間所產生的應力，進而能夠避免重配置線路層240產生形變損壞。
第3圖為製作半導體封裝結構100之方法300的流程圖。方法300包含步驟S310至S380。第4至11圖為對應步驟S310至S380的結構示意圖。
S310： 將晶片120設置於載體CR；
S320： 形成應力緩解層130於晶片120上；
S330： 模封載體CR上之晶片120以形成包覆晶片120之封裝層110；
S340： 移除上部的封裝層110以顯露出晶片120；
S350： 於晶片120、應力緩解層130及封裝層110上形成重配置線路層140；
S360： 於重配置線路層140上形成介電層160；
S370： 移除載體CR；
S380： 於重配置線路層140上設置複數個焊接凸塊150。
在步驟S310中，可利用細對準機台將晶片120放置於載體CR。在步驟S320中，可透過在晶片120上噴塗低楊式係數材料薄膜來形成低應力緩解層130。低模料材料可例如為聚合物、環氧樹脂、高分子材料、樹脂、光阻劑或前述任兩者以上的結合。
在步驟S330中，透過對晶片120進行模封即可形成封裝層110並可保護晶片120。在此實施例中，晶片120是以主動面朝上的方式設置於載體CR上，因此在步驟S340中，會將封裝層110的上部去除以顯露出晶片120的主動面。此外，在步驟S340中，位於晶片120上方的低楊式係數材料薄膜也會被一併被去除，然而位於晶片120側邊的低楊式係數材料薄膜則仍會保留下來。在部分實施例中，步驟S340可以透過研磨及/或蝕刻的方式來去除封裝層110。
在步驟S350中，重配置線路層140可形成於晶片120、應力緩解層130及封裝層110上方以將晶片120的輸入/輸出埠124重新繞線安排。重配置線路層140可以透過在晶片120、應力緩解層130及封裝層110上電鍍一層導電材料來形成，而導電材料可例如為銅、鋁、合金或其他具有導電性的材料。
在步驟S360中，介電層160可形成於重配置線路層140上，且介電層160可透過光罩蝕刻的程序在部分區域留下開口以便後續設置焊接凸塊150。在步驟S370中，載體CR會被移除，而在步驟S380中，即可將焊接凸塊設置於重配置線路層140。
雖然方法300在將晶片120放置於載體CR上時，是以其主動面朝上，然而在部分實施例中，晶片120也可以主動面朝下的方式放置於載體CR上。
第12圖為製作半導體封裝結構100之方法400的流程圖。方法400包含步驟S410至S470。第13至19圖為對應步驟S410至S470的結構示意圖。
S410： 將晶片120設置於載體CR；
S420： 形成應力緩解層130於晶片120上；
S430： 模封載體CR上之晶片120以形成包覆晶片120之封裝層110；
S440： 移除載體CR；
S450： 於晶片120、應力緩解層130及封裝層110上形成重配置線路層140；
S460： 於重配置線路層140上形成介電層160；
S470： 於重配置線路層140上設置複數個焊接凸塊150。
在步驟S410中，晶片120在放置於載體CR時可將主動面朝下，因此在步驟S430中對晶片120進行模封之後，即可在步驟S440中移除載體CR以顯露出晶片120的輸入/輸出埠124。如此一來，即可在步驟S450中，於晶片120、應力緩解層130及封裝層110上形成重配置線路層140。此外，在部分實施例中，在步驟S420形成應力緩解層130之後，且在步驟S430形成封裝層110之前，可將位於晶片120上的部份應力緩解層130去除，並保留附著於晶片120側邊的應力緩解層130。然而，在部分實施例中，也可如第14及15圖所示，將去除部分應力緩解層130的步驟省略。
此外，為了進一步減少半導體封裝結構100的厚度，方法400還可包含研磨封裝層110以顯露出晶片120背面的步驟。
透過方法300及400，由於具有低楊式係數的應力緩解層130可形成於封裝層110和晶片120之間，因此由劇烈溫度變化所導致的應力可被應力緩解層130吸收。因此能夠保護重配置線路層140的結構。
綜上所述，本發明之實施例所提供的半導體封裝結構和製作半導體封裝結構的方法可以利用設置於晶片和封裝層之間的應力緩解層來避免封裝層及晶片交界處上方的重配置線路層受到熱應力而導致形變。因此半導體封裝結構能夠抵抗在極端環境下溫度變化所導致的應力。 以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。
100、200‧‧‧半導體封裝結構
110、210‧‧‧封裝層
120、220‧‧‧晶片
122、160‧‧‧介電層
124‧‧‧輸入/輸出埠
130、230‧‧‧應力緩解層
140、240‧‧‧重配置線路層
150、250‧‧‧焊接凸塊
300、400‧‧‧方法
S310至S380、S410至S470‧‧‧步驟
CR‧‧‧載體
第1圖為本發明一實施例之半導體封裝結構的剖面圖。 第2圖為本發明另一實施例之半導體封裝結構的俯視圖。 第3圖為本發明一實施例之製作第1圖之半導體封裝結構的方法流程圖。 第4至11圖為對應第3圖之方法步驟的結構示意圖。 第12圖為本發明另一實施例之製作第1圖之半導體封裝結構的方法流程圖。 第13至19圖為對應第12圖之方法步驟的結構示意圖。

Claims (10)

  1. 一種半導體封裝結構，包含： 一封裝層，具有一開口； 一晶片，設置於該封裝層之該開口內； 一應力緩解層，設置於該晶片及該封裝層之間；及 一重配置線路層，設置於該晶片、該應力緩解層及該封裝層上方； 其中該應力緩解層係用以緩衝該晶片及該封裝層之間的應力以避免該重配置線路層受到損害。
  2. 如請求項1所述之半導體封裝結構封裝，其中該應力緩解層之一熱膨脹係數係介於該晶片之一熱膨脹係數及該封裝層之一熱膨脹係數之間，並且該晶片之該熱膨脹係數小於該封裝層之該熱膨脹係數。
  3. 如請求項1所述之半導體封裝結構封裝，另包含: 複數個焊接凸塊，設置於該重配置線路層上；及 一介電層，形成於該重配置線路層上。
  4. 如請求項1所述之半導體封裝結構封裝，其中該應力緩解層係為一低楊式係數材料薄膜，該低楊式係數材料薄膜包含聚合物、環氧樹脂、高分子材料、樹脂及/或光阻劑。
  5. 一種製作半導體封裝結構的方法，包含： 將一晶片設置於一載體； 形成一應力緩解層於該晶片上； 封模該載體上之該晶片以形成包覆該晶片之一封裝層；及 於該晶片、該應力緩解層及該封裝層上形成一重配置線路層； 其中該應力緩解層係用以緩衝該晶片及該封裝層之間的應力以避免該重配置線路層受到損害。
  6. 如請求項5所述之方法，其中形成該應力緩解層於該晶片上係於該晶片上噴塗一低楊式係數材料薄膜，該低楊式係數材料薄膜包含聚合物、環氧樹脂、高分子材料、樹脂及/或光阻劑。
  7. 如請求項6所述之方法，另包含移除該晶片上的部分該低楊式係數材料薄膜，同時保留附著於該晶片側邊之部分該低楊式係數材料薄膜。
  8. 如請求項5所述之方法，其中於該晶片、該應力緩解層及該封裝層上形成該重配置線路層係於該晶片、該應力緩解層及該封裝層上電鍍一層導電材料。
  9. 如請求項5所述之方法，其中該應力緩解層之一熱膨脹係數係介於該晶片之一熱膨脹係數及該封裝層之一熱膨脹係數之間，並且該晶片之該熱膨脹係數小於該封裝層之該熱膨脹係數。
  10. 如請求項5所述之方法，另包含: 於該重配置線路層上設置複數個焊接凸塊；及 於該重配置線路層上形成一介電層。
TW106114593A 2016-12-25 2017-05-03 半導體封裝結構及製作半導體封裝結構的方法 TW201830587A (zh)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI713177B (zh) * 2019-04-12 2020-12-11 力成科技股份有限公司 半導體封裝及其製造方法
CN113471160A (zh) * 2021-06-29 2021-10-01 矽磐微电子(重庆)有限公司 芯片封装结构及其制作方法

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10163693B1 (en) 2017-12-21 2018-12-25 Micron Technology, Inc. Methods for processing semiconductor dice and fabricating assemblies incorporating same
TWI756000B (zh) * 2020-12-28 2022-02-21 欣興電子股份有限公司 晶片封裝結構及其製作方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5353498A (en) * 1993-02-08 1994-10-11 General Electric Company Method for fabricating an integrated circuit module
WO2002027786A1 (fr) * 2000-09-25 2002-04-04 Ibiden Co., Ltd. Element semi-conducteur, procede de fabrication d'un element semi-conducteur, carte a circuit imprime multicouche, et procede de fabrication d'une carte a circuit imprime multicouche
US20050110168A1 (en) * 2003-11-20 2005-05-26 Texas Instruments Incorporated Low coefficient of thermal expansion (CTE) semiconductor packaging materials
US8034661B2 (en) * 2009-11-25 2011-10-11 Stats Chippac, Ltd. Semiconductor device and method of forming compliant stress relief buffer around large array WLCSP
US9000584B2 (en) * 2011-12-28 2015-04-07 Taiwan Semiconductor Manufacturing Company, Ltd. Packaged semiconductor device with a molding compound and a method of forming the same
US9704769B2 (en) * 2014-02-27 2017-07-11 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming encapsulated wafer level chip scale package (EWLCSP)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI713177B (zh) * 2019-04-12 2020-12-11 力成科技股份有限公司 半導體封裝及其製造方法
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