TW201827131A - 上膠設備及其使用方法 - Google Patents

上膠設備及其使用方法 Download PDF

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TW201827131A
TW201827131A TW106102379A TW106102379A TW201827131A TW 201827131 A TW201827131 A TW 201827131A TW 106102379 A TW106102379 A TW 106102379A TW 106102379 A TW106102379 A TW 106102379A TW 201827131 A TW201827131 A TW 201827131A
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詹慕萱
王愉博
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矽品精密工業股份有限公司
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Priority to CN201710072810.1A priority patent/CN108346596A/zh
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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    • H01L22/00Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10Measuring as part of the manufacturing process
    • H01L22/12Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
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    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/20Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
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    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
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    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
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    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
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    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/741Apparatus for manufacturing means for bonding, e.g. connectors
    • H01L2224/743Apparatus for manufacturing layer connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

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Abstract

一種上膠設備,係包括:機台本體、設於該機台本體上之供膠裝置以及感應式量測裝置,以藉由該感應式量測裝置量測該供膠裝置所形成至一物件上之膠材之份量。本發明復提供該上膠設備之使用方法。

Description

上膠設備及其使用方法
本發明係有關一種形成膠材之製程,尤指一種上膠設備及其使用方法。
隨著半導體封裝技術的演進,半導體裝置(Semiconductor device)已開發出不同的封裝型態,其中,球柵陣列式(Ball grid array,簡稱BGA),例如PBGA、EBGA、FCBGA等,,其主要於相同單位面積之承載件上可容納更多輸入/輸出連接端(I/O connection)以符合高度集積化(Integration)之半導體晶片之需求。
如第1圖所示,習知覆晶製程係先將一如半導體晶片之電子元件91藉由複數如銲錫凸塊之導電元件92設於一如封裝基板之承載件90上,再回銲(reflow)該些導電元件92,之後進行點膠步驟,即利用一填膠設備1之點膠器11將如底膠之膠材8填入該電子元件91與該承載件90之間以包覆該些導電元件92,藉以避免該些導電元件92遭受汙損及損毀。之後,移動該填膠設備1之機械式量測器12,使其向下抵觸該膠材8(如第1圖所示之虛線),以判 斷該膠材8之填入量是否足夠。
然而,隨著半導體製程微小化的發展,使得電子元件91的線路愈來愈細,而伴隨電子元件91與承載件90之間接合的導電元件92尺寸也相對微小化,如此,當該導電元件92之間的間距(pitch)t或該電子元件91與該承載件90之間的空間距離h過小時,該膠材8之所需填入量亦會減小(亦即只需少量的膠材8即可包覆該些導電元件92),導致該機械式量測器12於量測時,受限於接觸區域之限制(例如,無法接觸某些區域的膠材8,因而產生接觸死角),而使誤差量或精確度無法配合微量之膠材8之需求,造成膠量不易控制問題,導致產品可靠度下降。
再者,習知機械式量測器12需實際觸碰該膠材8,但隨著該電子元件91與該承載件90之間的空間距離h縮小,觸碰式的量測會受限於該機械式量測器12之量測能力的極限,導致同樣無法達到準確控制膠量之目的。
因此,如何克服習知技術中之種種問題,實已成目前亟欲解決的課題。
鑑於上述習知技術之缺失,本發明係揭露一種上膠設備,係包括:機台本體;供膠裝置,係設於該機台本體上,用以形成膠材於物件上;以及感應式量測裝置,係設於該機台本體上,用以量測形成於該物件上之該膠材之份量。
本發明亦揭露一種上膠設備之使用方法,係包括:提供一前述之上膠設備;藉由該供膠裝置將該膠材形成於該 物件上;以及藉由該感應式量測裝置量測形成於該物件上之該膠材之份量。
前述之上膠設備及其使用方法中,該感應式量測裝置係包含感測器,例如,該感測器係為光學式或聲波式,以發出偵測訊號至該膠材;再者,該感應式量測裝置復包含接收器,以接收相關該感測器先前所發出之訊號,例如,該接收器係為影像擷取器。
前述之上膠設備及其使用方法中,復藉由電性連接該感應式量測裝置之控制裝置進行分析與處理該感應式量測裝置之訊號。另外,復包括透過電性連接該控制裝置之警示裝置以警示使用者該上膠設備發生異常狀況。
由上可知,本發明之上膠設備及其使用方法,主要藉由該感應式量測裝置發出偵測訊號來量測物件上之膠材之份量,因而於進行量測時無需接觸該膠材,故相較於習知技術在量測包覆設於電子元件與承載件間之導電元件的膠材份量時,即使導電元件之間的間距或電子元件與承載件之間的空間距離極小,本發明之該感應式量測裝置不會受限於區域空間之限制(如不會產生感應死角),使其誤差量或精確度能滿足少量之膠材之需求,以利於應用於膠量較小的微量填膠製程,而有效控制膠量。
再者,即便隨著該電子元件與該承載件之間的距離縮小,本發明之該感應式量測裝置的量測不會如傳統觸碰式的量測受限於量測能力的極限,因而能達到準確控制微量填膠之目的。
1‧‧‧填膠設備
11‧‧‧點膠器
12‧‧‧機械式量測器
2,3,4‧‧‧上膠設備
20‧‧‧機台本體
21‧‧‧供膠裝置
22‧‧‧感應式量測裝置
220‧‧‧感測器
221‧‧‧接收器
23‧‧‧控制裝置
24‧‧‧警示裝置
8‧‧‧膠材
9‧‧‧物件
90‧‧‧承載件
91‧‧‧電子元件
910‧‧‧電極墊
92‧‧‧導電元件
t‧‧‧間距
h‧‧‧空間距離
X,Y‧‧‧箭頭方向
第1圖係為習知覆晶與點膠製程的剖視示意圖;第2圖係為本發明之上膠設備於使用時之側面示意圖;以及第3及4圖係為本發明之上膠設備之不同實施例的立體示意圖。
以下藉由特定的具體實施例說明本發明之實施方式,熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知,本說明書所附圖式所繪示之結構、比例、大小等,均僅用以配合說明書所揭示之內容,以供熟悉此技藝之人士之瞭解與閱讀,並非用以限定本發明可實施之限定條件,故不具技術上之實質意義,任何結構之修飾、比例關係之改變或大小之調整,在不影響本發明所能產生之功效及所能達成之目的下,均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時,本說明書中所引用之如「上」、及「一」等之用語,亦僅為便於敘述之明瞭,而非用以限定本發明可實施之範圍,其相對關係之改變或調整,在無實質變更技術內容下,當亦視為本發明可實施之範疇。
如第2圖所示,本發明之上膠設備2係包括:一機台本體20、一設於該機台本體20上之供膠裝置21(圖中僅以標號表示其佈設位置,並未顯示其詳細機構)、以及一設 於該機台本體20上之感應式量測裝置22(圖中僅以標號表示其佈設位置,並未顯示其詳細機構)。
所述之機台本體20係配置上膠製程相關之機電配備。
所述之供膠裝置21係用以形成膠材8於一物件9上。有關該供膠裝置21之機構種類繁多,並無特別限制。
所述之感應式量測裝置22係緊鄰該供膠裝置21且用以量測該物件9上之膠材8之份量。
於本實施例中,該感應式量測裝置22係包含一感測器220,以偵測該物件9上之膠材8。例如,該感測器220係為光學式或聲波式,以發出偵測訊號至該膠材。具體地,若該感測器220為光學式,可如雷射測距,或例如一般常見的紅外線、藍光或綠光等;或者,若該感測器220為聲波式,例如,以超音波方式進行測距。
再者,該感應式量測裝置22復包含一接收器221,以接收相關該感測器220先前所發出之訊號。例如,當該感測器220發射光線或聲波至該膠材8上(如箭頭方向X)時,會產生反射的物理作用(即產生反射的光波或聲波),該接收器221可接收反射的光波或聲波(如箭頭方向Y),並儲存如時間差或反射角度之資料。
或者,該接收器221可為影像擷取器,如感光耦合元件(Charge-coupled Device,簡稱CCD),以即時拍攝目前的膠材8之份量。
於一實施例中,如第3圖所示,該上膠設備3復包括一控制裝置23,係電性連接該感應式量測裝置22,以分析 與處理該感應式量測裝置22之訊號。
所述之控制裝置23係為中央控制單元、訊號處理器、訊號產生單元、或電腦等,其外接至該機台本體20,用以操控該供膠裝置21與該感應式量測裝置22之作動;應可理解地,該控制裝置23亦可內建於該機台本體20中。
具體地,該控制裝置23具有一記憶單元及一計算單元,其中,該記憶單元可儲存該接收器221的訊號,並傳輸至該計算單元,經該計算單元計算訊號(如時間差或反射角度)或處理影像訊號後,計算出目前的膠材8的厚度及位置,且該計算單元還可依據目前的膠材8之份量進行計算,以計算出該供膠裝置21需於何處再填入多少膠量。
因此,於該計算單元運算後,若發現有任何與設定膠材之份量或位置不同的情況時,如填膠位置偏移、填膠量即將界入臨界值等,便會主動通知使用者或即刻停止該供膠裝置21之作動,以進行修正填膠動作之作業。
另外,如第4圖所示,該上膠設備4復包括一電性連接該控制裝置23之警示裝置24,以警示使用者該上膠設備2之異常狀況。例如,該警示裝置24可為燈光、影像(如LCD、LED)、聲音或其組合。
因此,所述之上膠設備2,3,4之使用方法係藉由該控制裝置23控制該供膠裝置21將該膠材8形成於該物件9上,再藉由該感應式量測裝置22量測該物件9上之膠材8之份量。之後,經由該控制裝置23之分析與處理,以根據計算後之資料,令該供膠裝置21進行修正填膠動作之作 業。
於本實施例中,主要係將一如第2圖所示之待進行上膠處理之物件9置放於該機台本體20上,該物件9係包括一具有複數銲墊與線路(圖略)之承載件90、及一設於該承載件90上且具有複數電極墊910與線路(圖略)之電子元件91,其中,該電子元件91藉由複數如銲錫凸塊之導電元件92結合至該承載件90上,且該膠材8係為底膠,其形成於該電子元件91與該承載件90之間,使該膠材8包覆該些導電元件92。
再者,該承載件90係為封裝基板,其例如為半導體板材(玻璃、矽晶圓或矽中介板)、陶瓷板材或絕緣板材等,並無特別限制。
又,該電子元件91係為主動元件、被動元件或其二者組合,且該主動元件係例如半導體晶片,而該被動元件係例如電阻、電容及電感。
另外,所述之線路、銲墊與電極墊910係為金屬材質,如銅材或鋁材,但不限於上述。
綜上所述,本發明之上膠設備2,3,4及其使用方法,係藉由該感應式量測裝置22量測該物件9上之膠材之份量,因而於進行量測時無需接觸該膠材8,故於該感應式量測裝置22進行量測時,即使該導電元件92之間的間距t或該電子元件91與該承載件90之間的空間距離h極小,該感應式量測裝置22不會受限於區域空間之限制,使其誤差量或精確度能滿足少量之膠材8之需求,以利於應用於 膠量較小的微量填膠製程,而有效控制膠量。
再者,即便隨著該電子元件91與該承載件90之間的距離縮小,該感應式量測裝置22的量測不會如傳統觸碰式的量測受限於量測能力的極限,因而能達到準確控制微量填膠之目的。
上述實施例係用以例示性說明本發明之原理及其功效,而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下,對上述實施例進行修改。因此本發明之權利保護範圍,應如後述之申請專利範圍所列。

Claims (14)

  1. 一種上膠設備,係包括:機台本體;供膠裝置,係設於該機台本體上,用以形成膠材於物件上;以及感應式量測裝置,係設於該機台本體上,用以量測形成於該物件上之該膠材之份量。
  2. 如申請專利範圍第1項所述之上膠設備,其中,該感應式量測裝置係包含感測器。
  3. 如申請專利範圍第2項所述之上膠設備,其中,該感測器係為光學式或聲波式。
  4. 如申請專利範圍第2項所述之上膠設備,其中,該感應式量測裝置復包含接收器。
  5. 如申請專利範圍第4項所述之上膠設備,其中,該接收器係為影像擷取器。
  6. 如申請專利範圍第1項所述之上膠設備,復包括控制裝置,係用於分析與處理該感應式量測裝置之訊號。
  7. 如申請專利範圍第6項所述之上膠設備,復包括電性連接該控制裝置之警示裝置。
  8. 一種上膠設備之使用方法,係包括:提供一如申請專利範圍第1項所述之上膠設備;藉由該供膠裝置將該膠材形成於該物件上;以及藉由該感應式量測裝置量測形成於該物件上之該膠材之份量。
  9. 如申請專利範圍第8項所述之上膠設備之使用方法,其中,該感應式量測裝置係包含感測器。
  10. 如申請專利範圍第9項所述之上膠設備之使用方法,其中,該感測器係為光學式或聲波式。
  11. 如申請專利範圍第9項所述之上膠設備之使用方法,其中,該感應式量測裝置復包含接收器。
  12. 如申請專利範圍第11項所述之上膠設備之使用方法,其中,該接收器係為影像擷取器。
  13. 如申請專利範圍第8項所述之上膠設備之使用方法,復包括藉由一控制裝置分析與處理該感應式量測裝置之訊號。
  14. 如申請專利範圍第13項所述之上膠設備之使用方法,復包括藉由電性連接該控制裝置之警示裝置以警示該上膠設備之異常狀況發生。
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