TW201810460A - Method of manufacturing semiconductor device - Google Patents

Method of manufacturing semiconductor device Download PDF

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Publication number
TW201810460A
TW201810460A TW106104198A TW106104198A TW201810460A TW 201810460 A TW201810460 A TW 201810460A TW 106104198 A TW106104198 A TW 106104198A TW 106104198 A TW106104198 A TW 106104198A TW 201810460 A TW201810460 A TW 201810460A
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Taiwan
Prior art keywords
bonding
bonding wires
wire
gap
bonding wire
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TW106104198A
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Chinese (zh)
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TWI647768B (en
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佐野雄一
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東芝記憶體股份有限公司
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/4847Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48471Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area being a ball bond, i.e. wedge-to-ball, reverse stitch
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/48475Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball
    • H01L2224/48476Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball between the wire connector and the bonding area
    • H01L2224/48477Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball between the wire connector and the bonding area being a pre-ball (i.e. a ball formed by capillary bonding)
    • H01L2224/48478Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball between the wire connector and the bonding area being a pre-ball (i.e. a ball formed by capillary bonding) the connecting portion being a wedge bond, i.e. wedge on pre-ball
    • H01L2224/48479Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball between the wire connector and the bonding area being a pre-ball (i.e. a ball formed by capillary bonding) the connecting portion being a wedge bond, i.e. wedge on pre-ball on the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8512Aligning
    • H01L2224/85121Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8512Aligning
    • H01L2224/85121Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors
    • H01L2224/85122Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors by detecting inherent features of, or outside, the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85909Post-treatment of the connector or wire bonding area
    • H01L2224/8593Reshaping, e.g. for severing the wire, modifying the wedge or ball or the loop shape
    • H01L2224/85947Reshaping, e.g. for severing the wire, modifying the wedge or ball or the loop shape by mechanical means, e.g. "pull-and-cut", pressing, stamping

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

The embodiment of the present invention provides a method of manufacturing a semiconductor device capable of effectively enlarging a gap between bonding lines that are brought into contact with a wire bond. The method includes the steps of: electrically connecting a plurality of first junctions and a plurality of second junctions with bonding wires using a capillary tube into which a bonding wire is inserted; measuring the gaps between the adjacent bonding wires; setting a capillary tube between a group of binding wires with a gap below the set value, and enabling the capillary side to move in the wiring direction of the at least one bonding wire contact edge connecting line to widen the gap between the adjacent bonding wires.

Description

半導體裝置之製造方法Manufacturing method of semiconductor device

本發明之實施形態係關於一種半導體裝置之製造方法。An embodiment of the present invention relates to a method for manufacturing a semiconductor device.

NAND型快閃記憶體等內置記憶體晶片之半導體存儲裝置中,小型化及高容量化快速發展。如半導體存儲裝置之半導體裝置中,為了兼顧小型化與高容量化,例如,應用如下構成:於電路基材上依序積層複數個記憶體晶片等半導體晶片,且用樹脂層將該等半導體晶片密封。進而,關於電路基材之端子或半導體晶片之電極墊,形成間距之窄間距化不斷發展。用接合線將此種電路基材之端子與半導體晶片之電極墊電性連接時,相鄰之接合線間會產生接觸,或者即使於打線接合時未產生接觸,亦會因線間隔變窄而容易由後續步驟之樹脂密封步驟中之線偏移引起接合線間之接觸。 打線接合步驟或樹脂密封步驟等中,相鄰之接合線間產生接觸之半導體裝置會作為不良品處理,導致半導體裝置之良率降低。雖提出了各種防止相鄰之接合線間之接觸之技術,但若使用附加之構造物,會導致半導體裝置之製造成本或製造工時增加。進而,越使電路基材之端子或半導體晶片之電極墊之形成間距窄間距化,越容易產生接合線間之接觸,所以線間接觸之防止變得越來越困難。又,亦研究出利用可進行微細控制之檢查裝置等,由作業者手動擴大接合線間之間隔,但此種作業生產效率極低,不可避免地帶來半導體裝置之製造成本或製造工時之增加。In semiconductor memory devices with built-in memory chips such as NAND-type flash memory, miniaturization and high-capacity development are rapidly progressing. In a semiconductor device such as a semiconductor memory device, in order to achieve both miniaturization and high capacity, for example, a configuration is adopted in which semiconductor wafers such as a plurality of memory wafers are sequentially laminated on a circuit substrate, and the semiconductor wafers are laminated with a resin layer. seal. Furthermore, as for the terminals of the circuit substrate or the electrode pads of the semiconductor wafer, the formation of narrower pitches has continued to progress. When a terminal of such a circuit substrate is electrically connected to an electrode pad of a semiconductor wafer with a bonding wire, contact may occur between adjacent bonding wires, or even if no contact occurs during wire bonding, the wire interval may be narrowed. The contact between the bonding wires is easily caused by a line shift in the resin sealing step of the subsequent step. In the wire bonding step or the resin sealing step, a semiconductor device that is brought into contact between adjacent bonding wires is treated as a defective product, resulting in a decrease in the yield of the semiconductor device. Although various techniques for preventing contact between adjacent bonding wires have been proposed, if additional structures are used, the manufacturing cost or manufacturing man-hours of a semiconductor device will increase. Furthermore, the narrower the pitch of the formation of the terminals of the circuit substrate or the electrode pads of the semiconductor wafer, the more likely it is that contact between the bonding wires will occur, so it becomes more and more difficult to prevent contact between the wires. In addition, it has also been developed that the interval between the bonding wires can be manually enlarged by the operator using an inspection device that can perform fine control. However, this operation has extremely low production efficiency, which inevitably leads to an increase in the manufacturing cost or man-hours of the semiconductor device .

本發明之實施形態提供一種半導體裝置之製造方法,能有效擴大有可能於打線接合時產生接觸、或者於後續步驟中產生接觸之接合線間之間隔。 實施形態之半導體裝置之製造方法包括以下步驟:使用插通有接合線之銲針,以接合線分別將複數個第1接合部與複數個第2接合部之間電性連接,上述複數個第1接合部設置於第1裝置構成零件,上述複數個第2接合部設置於第2裝置構成零件;於連接上述複數個第1接合部與上述複數個第2接合部之複數個上述接合線中,測定相鄰之上述接合線間之間隙;選擇測定出之上述相鄰之接合線間之間隙為設定值以下之一組接合線;及於所選擇之上述一組接合線間,配置上述銲針,使上述銲針一面與上述接合線之至少一者接觸、一面沿上述接合線之接線方向移動,而擴大上述一組接合線間之間隙。An embodiment of the present invention provides a method for manufacturing a semiconductor device, which can effectively expand the interval between bonding wires that may cause contact during wire bonding or contact in subsequent steps. The method of manufacturing a semiconductor device according to an embodiment includes the following steps: using a solder pin inserted with a bonding wire to electrically connect a plurality of first bonding portions and a plurality of second bonding portions with the bonding wires, the plurality of 1 joint part is provided in the first device constituent part, and the plurality of second joint parts are provided in the second device constituent part; in the plurality of joint lines connecting the plurality of first joint parts and the plurality of second joint parts To measure the gap between the adjacent bonding wires; select the group of bonding wires whose measured gap between the adjacent bonding wires is below a set value; and arrange the welding between the selected group of the bonding wires The needle causes one side of the soldering pin to contact at least one of the bonding wires, and moves the welding pin along the wiring direction of the bonding wires to expand the gap between the group of bonding wires.

以下,參照圖式對實施形態之半導體裝置之製造方法進行說明。圖1係表示實施形態之製造方法中使用之半導體製造裝置之構成之圖。圖1所示之半導體製造裝置(打線接合裝置)1不僅實施打線接合動作(步驟),即,分別藉由接合線將第1裝置構成零件之複數個第1接合部與第2裝置構成零件之複數個第2接合部電性連接,亦實施線修復動作(步驟),即,當連接複數個第1接合部與複數個第2接合部之複數條接合線中,相鄰之接合線間之間隙為設定值以下時擴大間隙。 圖1所示之半導體製造裝置1包括設置於X-Y平台2上之接合頭3。於接合頭3,安裝有接合臂4。於接合頭3之接合臂4之前端側,配置有接合平台5。於接合平台5上,例如載置裝有複數個半導體晶片6之基板7,作為接合零件。接合平台5能藉由未圖示之移動機構沿X-Y方向移動。 接合臂4構成為,由未圖示之Z方向馬達繞旋轉中心驅動,其前端相對於作為接合面之半導體晶片6之墊面及基板7之端子面呈弧狀進行相接及分離動作。於接合臂4之前端,安裝有銲針8。接合頭3構成為能利用X-Y平台2於沿接合面之面內(X-Y面內)自由移動。進而,接合臂4之前端及安裝於接合臂4之前端之銲針8構成為,能藉由用Z方向馬達驅動接合臂4而沿X-Y-Z方向自由移動。 銲針8例如使用瓶頸形狀之銲針。如圖2所示,銲針8包括具有圓錐狀前端部9之圓柱體,於其中心沿軸方向設置有貫通孔10。銲針8之貫通孔10中插通有接合線11。接合線11係由配置於接合頭3上之線軸12供給。接合線11可使用金細線、銀細線、銅細線等。接合臂4包括超聲振子13,自超聲振子13向銲針8供給超聲能量。 接合頭3包括線夾14,上述線夾14固持插通於銲針8中之接合線11。線夾14位於銲針8之上方,能與銲針8一併沿X-Y-Z方向自由移動。又,線夾14能單獨沿Z方向移動。線夾14包括開合機構15,利用開合機構15對線夾14進行開合驅動。 於接合頭3安裝有作為拍攝部之相機(例如CMOS(Complementary Metal Oxide Semiconductor,互補金屬氧化物半導體)圖像感測器或CCD(Charge Coupled Device,電荷耦合器件)圖像感測器)16,以獲取半導體晶片6或基板7等之圖像、以及下述連接半導體晶片6與基板7之接合線11之圖像。構成為根據相機16所拍攝之圖像,進行打線接合步驟時及線修復步驟時銲針8於X-Y方向之定位,並且控制線修復步驟時銲針8向X-Y方向之移動。半導體製造裝置1之各部分之位置檢測及動作係由控制部17控制。 作為使用實施形態之半導體製造裝置1實施打線接合動作及線修復動作之接合零件,如圖3所示,列舉以下半導體零件:於作為第1裝置構成零件之配線基板或插入式基板等電路基板7上,裝有作為第2裝置構成零件之半導體晶片6。半導體晶片6包括沿外形邊以特定間距形成之複數個電極墊21。電路基板7包括以與複數個電極墊21對應之方式,以特定間距形成之複數個接合墊22。接合零件中,亦可使用引線框代替電路基板7。 接合零件亦可為以下半導體零件:包括作為第1裝置構成零件之第1半導體晶片、及作為第2裝置構成零件積層於第1半導體晶片上之第2半導體晶片。作為被積層之第1及第2半導體晶片之例,列舉NAND型快閃記憶體等之記憶體晶片。於積層有複數個記憶體晶片之半導體零件中,記憶體晶片之電極墊間、及電路基材之第1接合部(端子)與記憶體晶片之電極墊由接合線電性連接。接合零件亦可為以下半導體零件:於作為第1半導體晶片之單層或積層而成之複數個記憶體晶片上,作為第2半導體晶片積層有控制器晶片、介面晶片、邏輯晶片、RF(Radio Frequency,射頻)晶片等系統LSI(Large Scale Integrated circuit,大規模積體電路)晶片等。 於如上所述之半導體零件中,電路基板7之接合墊22與半導體晶片6之電極墊21由接合線23電性連接。或者,第1半導體晶片之第1電極墊與積層於第1半導體晶片上之第2半導體晶片之第2電極墊由接合線電性連接。進而,如圖3所示,連接接合墊21與電極墊22之接合線231產生彎曲或傾斜等,與相鄰之接合線232接觸,或者,即使未接觸,相鄰之接合線231、232之間隙亦為設定值以下時,例如進行接合線231之修復。藉由該等步驟,製造所需之半導體裝置。 其次,對實施形態之半導體製造裝置(打線接合裝置)1之動作及步驟進行說明。首先,參照圖4所示之流程圖對半導體製造裝置1之第1動作控制例進行敍述。再者,以下主要針對以接合線23將電路基板7之接合墊22與半導體晶片6之電極墊21電性連接之情形進行說明,但使用引線框代替電路基板7、或將第1半導體晶片之第1電極墊與第2半導體晶片之第2電極墊電性連接之情形時之動作及步驟亦相同。 首先,實施打線接合步驟(S101)。於打線接合步驟之前,先利用相機16拍攝電路基板7之接合墊22及半導體晶片6之電極墊21。根據該拍攝結果,識別接合墊22及電極墊21於X-Y方向之各位置。打線接合步驟及線修復步驟中之銲針8之移動等係根據接合墊22及電極墊21之位置識別結果予以控制。 於打線接合步驟中,例如使銲針8於第1接合墊22a上移動,將形成於接合線11之前端之球連接於第1接合墊22a(球形接合)。自銲針8送出接合線11並使銲針8以特定軌跡於第1電極墊21a上移動。將接合線11連接(針腳式接合)於第1電極墊21a後,以線夾14固持並切斷接合線11。藉此,以第1接合線23a將第1接合墊22a與第1電極墊21a連接。對所有之接合墊22及電極墊21實施如上所述之打線接合步驟。 利用接合線23實現之接合墊22與電極墊21之接線構造並不限於上述接合構造(逆向(逆)接合)。接合構造亦可為以下構造(正向(正)接合):將形成於接合線11之前端之球連接(球形接合)於電極墊21後,將接合線11連接(針腳式接合)於接合墊22。惟藉由逆向接合,能夠降低接合線23之迴路高度,且亦可相對簡化迴路形狀。 其次,以相機16對連接於接合墊22與電極墊21之所有接合線23進行拍攝,而測定相鄰之接合線23間之間隔(餘隙(clearance))(S102)。根據相鄰之接合線23間之餘隙之測定結果,選擇設定值以下之接合線23。相鄰之接合線23間之餘隙之測定例如係根據接合線23之拍攝結果而測量一接合線23偏離設定軌跡(虛擬線)之量,若該測量值為設定值以上,則為需要修復之接合線23。另外,判斷與當測量值為設定值以上時需要修復之接合線23相鄰之接合線23中,是否有於偏離設定軌跡之方向相鄰之接合線23存在。若有於偏離設定軌跡之方向相鄰之接合線23存在時,選擇測量值為設定值以上而需要修復之接合線23、與於偏離設定軌跡之方向相鄰之接合線23,作為需要修復之一組接合線23。或者,亦可直接測定相鄰之接合線23間之間隔,當間隙之最小值為設定值以下(包括接觸(餘隙=零))時,選擇其等作為需要修復之一組接合線23。 用來選擇需要修復之接合線23之設定值(閾值)並不僅限於能判斷出相鄰之接合線23間接觸之值,亦可設定為包括例如於後續步驟中相鄰之接合線23間之接觸可能性高之值(間隔)。例如,一般而言,於打線接合步驟後,實施對半導體晶片6進行樹脂密封之步驟。若於半導體晶片6之樹脂密封中使用轉移成形,有可能會引起接合線之偏移(線偏移),而導致相鄰之接合線間接觸。亦可將此種後續步驟中接合線23間之接觸可能性高之線間隔設為設定值(閾值)。若於後續步驟中接合線23間無接觸之可能性,亦可僅選擇能判斷出相鄰之接合線23間接觸之接合線23。 其次,使銲針8於上述線間隔測定步驟中判定(選擇)為需要修復之一組接合線23之附近移動(S103),使銲針8之前端部9一面與該一組接合線23中之至少一者接觸、一面沿接線方向移動,修復接合線23(S104)。線修復步驟中係使用圖2所示之銲針8之瓶頸構造之前端部9。接觸接合線23之部分較佳為例如較前端部9之前端直徑T大、且較瓶頸高度H低之部分。藉由使用如上所述之部分,容易使銲針8之前端部9一面與連接於窄間距化不斷發展之接合墊22與電極墊21間之接合線23接觸一面移動。 於線修復步驟中,如圖5及圖6所示,以銲針8之前端部9位於所選擇之一組接合線23中需要修復之接合線231與和其相鄰之接合線232之間之方式,使銲針8移動。如圖5及圖6所示,前端部9之配置位置例如係接近相鄰電極墊21間之位置。銲針8之移動係根據電極墊21之X-Y面內之位置識別結果及電極墊21之設定高度(半導體晶片6之接合等級(bond level))來實施。使銲針8之前端部9自上述位置一面與接合線231接觸一面沿接線方向朝接合墊22移動。 如圖5所示,銲針8之前端部9既可按擴大相鄰之接合線231與接合線232之間之間隔之方式移動,換言之一面與兩接合線231、232分別接觸一面移動,亦可根據一接合線23之彎曲或傾斜等之變形方向,一面與一接合線23接觸一面移動。銲針8之前端部9之移動亦可根據接合線23之變形模式進行調整。而且,前端部9既可僅沿與電路基板7之接合面大致平行之部分移動(沿X-Y方向移動),亦可沿接合線23之立起部分移動至接合墊22附近(沿X-Y-Z方向移動)。 如圖7所示,線修復步驟中之銲針8之前端部9亦可首先配置於電極墊21之附近位置,自該位置開始後自接合線23之立起部分沿與接合面大致平行之部分移動至電極墊21附近(沿X-Y-Z方向移動)。於該情形時,前端部9之包括Z方向在內之移動例如係根據接合線23之設定軌跡(設定迴路形狀)進行控制。又,亦可另行設置拍攝接合線23於Z方向之位置之相機,根據拍攝結果,控制前端部9之包括Z方向在內之移動。對判定為需要修復之所有接合線23實施此種線修復步驟。 藉由實施上述線修復步驟,如圖8所示,可擴大判定為需要修復之接合線231、232間之間隔。因此,可抑制打線接合步驟中產生之相鄰之接合線23間之接觸、或者因後續步驟中產生之接合線23間之接觸所導致之半導體裝置良率降低。接合線23間之接觸容易產生於接合墊22或電極墊21之形成間距窄間距化之情形、及接合線23細線化之情形。因此,包含實施形態之線修復步驟之半導體裝置之製造方法係於接合墊22之形成間距為100 μm以下、進而為60 μm以下,且電極墊21之形成間距為60 μm以下之情形時有效。於接合線23之直徑為30 μm以下、進而為20 μm以下之情形時有效。 其次,參照圖9所示之流程圖,對半導體製造裝置1之第2動作控制例進行敍述。第2動作控制例包括於接合線23之修復步驟後再次測定相鄰之接合線23間之間隔之動作(步驟)。即,與第1動作控制例同樣地,實施打線接合步驟(S201)、及相鄰之接合線23間之間隔(餘隙)之測定步驟(S202)。其次,比較間隔之測定結果與設定值(閾值),若測定結果為設定值以下,則選擇為需要修復之接合線23(S203)。實施使銲針8向判定(選擇)為需要修復之接合線23附近移動之步驟(S204)、及利用銲針8之前端部9修復該接合線23之步驟(S205)。 實施接合線23之修復步驟(S205)後,再次測定接合線23間之間隔(S202)。其次,比較間隔之測定結果與設定值(閾值),反覆進行接合線23之修復步驟,直至所有測定結果均超過設定值為止。藉由實施以上步驟,即使相鄰之接合線23間之間隔未能以一次修復步驟而充分擴大,最終仍能使所有相鄰之接合線23間之間隔成為超過設定值之狀態。因此,可使半導體裝置之良率進一步提高。 其次,參照圖10所示之流程圖,對半導體製造裝置1之第3動作控制例進行敍述。第3動作控制例於接合線23之修復步驟之前,具備以下動作(步驟):用線夾14固持接合線11且使其上升,將接合線11之前端收納於銲針8內。實施打線接合步驟後,接合線11之前端自銲針8之前端突出。若於該狀態下實施接合線23之修復步驟,有可能於突出部分產生彎曲等,而於下一打線接合步驟產生異常。對於上述情形,藉由於接合線23之修復步驟之前將接合線11之前端收納於銲針8內,能防止突出部分之彎曲等。 即,與第2動作控制例同樣地,實施打線接合步驟(S301)、相鄰之接合線23間之間隔(餘隙)之測定步驟(S302)、間隔之測定結果與設定值(閾值)之比較步驟(需要修復之接合線23之選擇步驟)(S303)後,實施將接合線11之前端收納於銲針8內之步驟(S304)。其次,與第2動作控制例同樣地,實施銲針8之移動步驟(S305)、接合線23之修復步驟(S306)、及相鄰之接合線23間之間隔之再次測定步驟(S302)。反覆進行接合線23之修復步驟,直至所有測定結果超過設定值為止。藉由實施上述步驟,不會對打線接合步驟帶來不良影響地,而可實施接合線23之修復步驟。 其次,參照圖11所示之流程圖對半導體製造裝置1之第4動作控制例進行敍述。第4動作控制例包括於接合線23之修復步驟之後僅測定經修復之接合線23之間隔之動作(步驟)。如此,藉由將修復步驟後之間隔測定對象限定為經修復之接合線23,能縮短間隔之再次測定所需之時間。 即,與第3動作控制例同樣地實施打線接合步驟(S401)、相鄰之接合線23間之間隔之測定步驟(S402)、間隔之測定結果與設定值(閾值)之比較步驟(需要修復之接合線23之選擇步驟)(S403)、銲針8之移動步驟(S404)、及接合線23之修復步驟(S405)。之後,實施對經修復之接合線23之線間隔進行測定之步驟(S407)。反覆進行接合線23之修復步驟,直至該測定結果超過設定值。藉由實施上述步驟,能於縮短半導體裝置之製造步驟之基礎上進一步提高良率。 上述第2至第4動作控制能分別組合使用。例如圖12係將半導體製造裝置1之第3動作控制例與第4動作控制例組合之第5動作控制例之流程圖。即,第5動作控制例包括將接合線11之前端收納於銲針8內之步驟(S504)、及測定經修復之接合線23之線間隔之步驟(S508)。此時,如圖13所示,亦可於銲針8之移動步驟(S604)之後實施將接合線11之前端收納於銲針8內之步驟(S605)。 另外,雖對本發明之若干實施形態進行了說明,但該等實施形態係作為示例而提出,並不意圖限定發明之範圍。該等新穎之實施形態能以其他各種方式實施,且於不脫離發明主旨之範圍內,可進行各種省略、置換、變更。該等實施形態及其變化包含於發明之範圍或主旨中,且包含於申請專利範圍所記載之發明及其均等範圍內。 [相關申請案] 本案享有以日本專利申請案2016-53320號(申請日:2016年3月17日)為基礎申請案之優先權。本案藉由參照該基礎申請案而包含基礎申請案之所有內容。Hereinafter, a method for manufacturing a semiconductor device according to an embodiment will be described with reference to the drawings. FIG. 1 is a diagram showing a configuration of a semiconductor manufacturing apparatus used in the manufacturing method of the embodiment. The semiconductor manufacturing apparatus (wire bonding apparatus) 1 shown in FIG. 1 not only performs a wire bonding operation (step), that is, a plurality of first bonding portions of a first device constituent part and a second device constituent part are respectively bonded by a bonding wire. The plurality of second joints are electrically connected, and a line repair operation (step) is also performed. That is, when a plurality of joint lines connecting the plurality of first joints and the plurality of second joints are adjacent to each other, Increase the gap when the gap is less than the set value. The semiconductor manufacturing apparatus 1 shown in FIG. 1 includes a bonding head 3 provided on an X-Y stage 2. A joint arm 4 is attached to the joint head 3. A joint platform 5 is disposed on the front end side of the joint arm 4 of the joint head 3. On the bonding stage 5, for example, a substrate 7 on which a plurality of semiconductor wafers 6 are mounted is mounted as a bonding component. The engaging platform 5 can be moved in the X-Y direction by a moving mechanism (not shown). The bonding arm 4 is configured to be driven around a rotation center by a Z-direction motor (not shown), and the front end of the bonding arm 4 is connected to and separated from the pad surface of the semiconductor wafer 6 and the terminal surface of the substrate 7 as bonding surfaces. A welding pin 8 is mounted on the front end of the engaging arm 4. The joint head 3 is configured to be able to move freely in the plane (in the X-Y plane) along the joint surface using the X-Y stage 2. Furthermore, the front end of the joint arm 4 and the welding pin 8 attached to the front end of the joint arm 4 are configured to be able to move freely in the X-Y-Z direction by driving the joint arm 4 with a Z-direction motor. As the welding pin 8, for example, a bottle-shaped welding pin is used. As shown in FIG. 2, the welding pin 8 includes a cylindrical body having a conical front end portion 9, and a through hole 10 is provided at the center of the cylindrical body. A bonding wire 11 is inserted into the through hole 10 of the solder pin 8. The bonding wire 11 is supplied from a spool 12 arranged on the bonding head 3. As the bonding wire 11, a gold thin wire, a silver thin wire, a copper thin wire, or the like can be used. The engaging arm 4 includes an ultrasonic vibrator 13, and ultrasonic energy is supplied from the ultrasonic vibrator 13 to the welding pin 8. The bonding head 3 includes a wire clip 14 that holds the bonding wire 11 inserted in the solder pin 8. The wire clip 14 is located above the welding pin 8 and can move freely along with the welding pin 8 in the X-Y-Z direction. The clamp 14 can be moved in the Z direction alone. The wire clip 14 includes an opening and closing mechanism 15, and the opening and closing mechanism 15 is used to open and close the wire clip 14. A camera (for example, a CMOS (Complementary Metal Oxide Semiconductor) image sensor or a CCD (Charge Coupled Device) image sensor) 16 is mounted on the bonding head 3 as an imaging unit, An image of the semiconductor wafer 6 or the substrate 7 and an image of a bonding wire 11 connecting the semiconductor wafer 6 and the substrate 7 described below are acquired. According to the image captured by the camera 16, the welding pin 8 is positioned in the X-Y direction during the wire bonding step and the wire repair step, and the movement of the solder pin 8 in the X-Y direction is controlled during the wire repair step. The position detection and operation of each part of the semiconductor manufacturing apparatus 1 are controlled by the control unit 17. As a bonding part that performs the wire bonding operation and the wire repair operation using the semiconductor manufacturing apparatus 1 of the embodiment, as shown in FIG. 3, the following semiconductor parts are listed: a circuit board 7 such as a wiring board or a plug-in board as a component of the first device A semiconductor wafer 6 as a component of the second device is mounted thereon. The semiconductor wafer 6 includes a plurality of electrode pads 21 formed at specific intervals along the outer edges. The circuit board 7 includes a plurality of bonding pads 22 formed at a specific pitch in a manner corresponding to the plurality of electrode pads 21. In the bonding component, a lead frame may be used instead of the circuit board 7. The bonding component may be a semiconductor component including a first semiconductor wafer as a first device component, and a second semiconductor wafer laminated on the first semiconductor wafer as a second device component. Examples of the stacked first and second semiconductor wafers include a memory wafer such as a NAND flash memory. In a semiconductor component in which a plurality of memory chips are stacked, the electrode pads of the memory chip and the first joint (terminal) of the circuit substrate and the electrode pads of the memory chip are electrically connected by a bonding wire. The bonding part may also be a semiconductor part which is laminated on a plurality of memory wafers which are single layers or laminated layers of the first semiconductor wafer, and a controller wafer, an interface wafer, a logic wafer, and RF (Radio) are laminated as the second semiconductor wafer. Frequency (radio frequency) chip and other system LSI (Large Scale Integrated circuit, large scale integrated circuit) chip. In the semiconductor component described above, the bonding pad 22 of the circuit board 7 and the electrode pad 21 of the semiconductor wafer 6 are electrically connected by a bonding wire 23. Alternatively, the first electrode pad of the first semiconductor wafer and the second electrode pad of the second semiconductor wafer laminated on the first semiconductor wafer are electrically connected by a bonding wire. Further, as shown in FIG. 3, the bonding wires 231 connecting the bonding pads 21 and the electrode pads 22 are bent or inclined, and come into contact with the adjacent bonding wires 232, or even if they are not in contact, When the gap is also below the set value, for example, repair of the bonding wire 231 is performed. With these steps, a required semiconductor device is manufactured. Next, operations and procedures of the semiconductor manufacturing apparatus (bonding apparatus) 1 according to the embodiment will be described. First, a first operation control example of the semiconductor manufacturing apparatus 1 will be described with reference to a flowchart shown in FIG. 4. In addition, the following mainly describes the case where the bonding pad 22 of the circuit substrate 7 and the electrode pad 21 of the semiconductor wafer 6 are electrically connected by the bonding wire 23, but a lead frame is used instead of the circuit substrate 7, or the first semiconductor wafer is The operations and steps are the same when the first electrode pad is electrically connected to the second electrode pad of the second semiconductor wafer. First, a wire bonding step is performed (S101). Before the wire bonding step, the camera 16 is used to photograph the bonding pads 22 of the circuit board 7 and the electrode pads 21 of the semiconductor wafer 6. Based on this photographing result, each position of the bonding pad 22 and the electrode pad 21 in the X-Y direction is identified. The movement of the welding pin 8 in the wire bonding step and the wire repair step is controlled based on the position recognition results of the bonding pad 22 and the electrode pad 21. In the wire bonding step, for example, the solder pin 8 is moved on the first bonding pad 22a, and a ball formed at the front end of the bonding wire 11 is connected to the first bonding pad 22a (ball bonding). The bonding wire 11 is sent out from the welding pin 8 and the welding pin 8 is moved on the first electrode pad 21 a with a specific trajectory. After the bonding wire 11 is connected (pin-type bonding) to the first electrode pad 21 a, the bonding wire 11 is held and cut by the clip 14. Thereby, the first bonding pad 22a and the first electrode pad 21a are connected by the first bonding wire 23a. The wire bonding step described above is performed on all the bonding pads 22 and the electrode pads 21. The wiring structure of the bonding pad 22 and the electrode pad 21 realized by the bonding wire 23 is not limited to the above-mentioned bonding structure (reverse (reverse) bonding). The bonding structure may also be a structure (positive (positive) bonding): a ball connection (spherical bonding) formed at the front end of the bonding wire 11 is connected to the electrode pad 21, and the bonding wire 11 is connected (pin bonding) to the bonding pad twenty two. However, by the reverse bonding, the loop height of the bonding wire 23 can be reduced, and the loop shape can be relatively simplified. Next, all the bonding wires 23 connected to the bonding pad 22 and the electrode pad 21 are photographed by the camera 16, and the interval (clearance) between adjacent bonding wires 23 is measured (S102). According to the measurement result of the clearance between the adjacent bonding wires 23, the bonding wires 23 below the set value are selected. The measurement of the gap between adjacent bonding wires 23 is, for example, measuring the amount of deviation of a bonding wire 23 from a set trajectory (virtual line) according to the shooting results of the bonding wire 23. If the measured value is above the set value, it needs to be repaired Of the bonding wire 23. In addition, it is determined whether or not the bonding wire 23 adjacent to the bonding wire 23 that needs to be repaired when the measured value is equal to or greater than the set value exists in the direction deviating from the set trajectory. If there is a bonding wire 23 adjacent to the direction deviating from the set trajectory, select the bonding wire 23 whose measurement value is greater than the set value and needs to be repaired, and the bonding line 23 adjacent to the direction deviating from the set trajectory as the need for repair A group of bonding wires 23. Alternatively, the interval between adjacent bonding wires 23 can also be directly measured. When the minimum value of the gap is less than a set value (including contact (clearance = zero)), it is selected as a group of bonding wires 23 to be repaired. The set value (threshold value) used to select the bonding wire 23 to be repaired is not limited to a value capable of judging the contact between adjacent bonding wires 23, but may also be set to include, for example, the value between the adjacent bonding wires 23 in a subsequent step. High value (interval) of contact possibility. For example, generally, the step of resin-sealing the semiconductor wafer 6 is performed after the wire bonding step. If transfer molding is used for the resin sealing of the semiconductor wafer 6, there is a possibility that the bonding wire may be shifted (line shifted), which may cause contact between adjacent bonding wires. The line interval with a high possibility of contact between the bonding wires 23 in such a subsequent step may be set as a set value (threshold value). If there is no possibility of contact between the bonding wires 23 in the subsequent steps, only the bonding wires 23 that can determine the contact between the adjacent bonding wires 23 may be selected. Next, the welding pin 8 is judged (selected) to be repaired near the group of bonding wires 23 in the above-mentioned line interval measurement step (S103), so that the front end portion 9 of the welding pin 8 is in contact with the group of bonding wires 23 At least one of them contacts and moves along the wiring direction to repair the bonding wire 23 (S104). In the thread repairing step, the front end portion 9 is constructed using the bottleneck of the solder pin 8 shown in FIG. 2. The portion contacting the bonding wire 23 is preferably, for example, a portion that is larger than the diameter T of the front end of the front end portion 9 and lower than the height H of the bottleneck. By using the above-mentioned portion, it is easy to move the front end portion 9 of the solder pin 8 and the bonding wire 23 connected to the bonding pad 22 and the electrode pad 21 that are continuously narrowed. In the wire repairing step, as shown in FIG. 5 and FIG. 6, the front end 9 of the welding pin 8 is located between the bonding wire 231 to be repaired in the selected group of bonding wires 23 and the adjacent bonding wire 232. In this way, the welding pin 8 is moved. As shown in FIGS. 5 and 6, the arrangement position of the front end portion 9 is, for example, a position close to between adjacent electrode pads 21. The movement of the solder pin 8 is performed based on the position recognition result in the X-Y plane of the electrode pad 21 and the set height of the electrode pad 21 (bond level of the semiconductor wafer 6). The front end portion 9 of the solder pin 8 is moved toward the bonding pad 22 in the wiring direction from the above-mentioned position while contacting the bonding wire 231. As shown in FIG. 5, the front end 9 of the welding pin 8 can be moved in such a manner as to increase the interval between the adjacent bonding wires 231 and 232. In other words, one side and the two bonding wires 231 and 232 are in contact with each other. According to the deformation direction such as the bending or tilting of a bonding wire 23, it can move while contacting a bonding wire 23. The movement of the front end 9 of the welding pin 8 can also be adjusted according to the deformation mode of the bonding wire 23. Furthermore, the front end portion 9 can be moved only along a portion substantially parallel to the bonding surface of the circuit board 7 (moving in the XY direction), or along the rising portion of the bonding wire 23 to the vicinity of the bonding pad 22 (moving in the XYZ direction). . As shown in FIG. 7, the front end portion 9 of the solder pin 8 in the wire repair step may also be first disposed near the electrode pad 21, and since this position, the rising portion of the bonding wire 23 is substantially parallel to the bonding surface. Partly moves to the vicinity of the electrode pad 21 (moves in the XYZ direction). In this case, the movement of the front end portion 9 including the Z direction is controlled based on the set trajectory (set circuit shape) of the bonding wire 23, for example. In addition, a camera for photographing the position of the bonding wire 23 in the Z direction may be separately provided, and the movement of the front end portion 9 including the Z direction may be controlled according to the photographing result. This line repair step is performed on all the bonding wires 23 determined to be in need of repair. By performing the above-mentioned line repair step, as shown in FIG. 8, the interval between the bonding wires 231 and 232 determined to be repaired can be enlarged. Therefore, it is possible to suppress a decrease in the yield of the semiconductor device due to the contact between the adjacent bonding wires 23 generated in the wire bonding step or the contact between the bonding wires 23 generated in the subsequent steps. The contact between the bonding wires 23 easily occurs when the bonding pad 22 or the electrode pad 21 is formed with a narrow pitch, and when the bonding wire 23 is thinned. Therefore, the manufacturing method of the semiconductor device including the wire repair step of the embodiment is effective when the formation pitch of the bonding pad 22 is 100 μm or less, and further 60 μm or less, and the formation pitch of the electrode pad 21 is 60 μm or less. This is effective when the diameter of the bonding wire 23 is 30 μm or less and further 20 μm or less. Next, a second operation control example of the semiconductor manufacturing apparatus 1 will be described with reference to a flowchart shown in FIG. 9. The second operation control example includes an operation (step) of measuring the interval between adjacent bonding wires 23 again after the repairing step of the bonding wires 23. That is, in the same manner as the first operation control example, a wire bonding step (S201) and a step (S202) of measuring a gap (clearance) between adjacent bonding wires 23 are performed. Next, the measurement result of the interval and the set value (threshold value) are compared. If the measurement result is less than the set value, the bonding wire 23 to be repaired is selected (S203). A step (S204) of moving the welding pin 8 toward the vicinity of the bonding wire 23 that is determined to be repaired (S204), and a step of repairing the bonding wire 23 by the front end 9 of the welding pin 8 (S205) are performed. After the repairing step (S205) of the bonding wire 23 is performed, the interval between the bonding wires 23 is measured again (S202). Next, the measurement result of the interval is compared with the set value (threshold value), and the repairing step of the bonding wire 23 is repeatedly performed until all the measurement results exceed the set value. By implementing the above steps, even if the interval between the adjacent bonding wires 23 is not sufficiently enlarged in one repair step, the interval between all the adjacent bonding wires 23 can still be made to exceed the set value. Therefore, the yield of the semiconductor device can be further improved. Next, a third operation control example of the semiconductor manufacturing apparatus 1 will be described with reference to a flowchart shown in FIG. 10. The third operation control example includes the following operations (steps) before the repairing step of the bonding wire 23: the bonding wire 11 is held and raised by the clamp 14, and the leading end of the bonding wire 11 is stored in the welding pin 8. After the wire bonding step is performed, the front end of the bonding wire 11 protrudes from the front end of the solder pin 8. If the repairing step of the bonding wire 23 is performed in this state, there is a possibility that a bending or the like may occur in the protruding portion, and an abnormality may occur in the next wire bonding step. In this case, since the leading end of the bonding wire 11 is housed in the welding needle 8 before the repairing step of the bonding wire 23, the protruding portion can be prevented from being bent or the like. That is, as in the second operation control example, the wire bonding step (S301), the step (S302) of measuring the interval (clearance) between adjacent bonding wires 23, the measurement result of the interval, and the set value (threshold value) are performed. After the comparison step (selection step of the bonding wire 23 to be repaired) (S303), a step of storing the front end of the bonding wire 11 in the solder pin 8 is performed (S304). Next, as in the second operation control example, the moving step (S305) of the welding needle 8, the repairing step (S306) of the bonding wire 23, and the re-measurement step (S302) of the interval between adjacent bonding wires 23 are performed. Repeat the repair steps of the bonding wire 23 until all the measurement results exceed the set value. By performing the above steps, the repairing step of the bonding wire 23 can be performed without adversely affecting the wire bonding step. Next, a fourth operation control example of the semiconductor manufacturing apparatus 1 will be described with reference to a flowchart shown in FIG. 11. The fourth operation control example includes an operation (step) of measuring only the interval of the repaired bonding wire 23 after the repairing step of the bonding wire 23. In this way, by limiting the interval measurement object after the repair step to the repaired bonding wire 23, it is possible to shorten the time required for re-measurement of the interval. That is, the wire bonding step (S401), the measurement step (S402) of the interval between adjacent bonding wires 23, and the comparison step of the measurement result of the interval and the set value (threshold value) are performed in the same manner as the third operation control example (repair is required) Step of selecting the bonding wire 23) (S403), Step of moving the welding pin 8 (S404), and Step of repairing the bonding wire 23 (S405). After that, a step of measuring the line interval of the repaired bonding wire 23 is performed (S407). The repairing step of the bonding wire 23 is repeatedly performed until the measurement result exceeds the set value. By implementing the above steps, it is possible to further improve the yield while shortening the manufacturing steps of the semiconductor device. The second to fourth motion controls described above can be used in combination. For example, FIG. 12 is a flowchart of a fifth operation control example in which a third operation control example and a fourth operation control example of the semiconductor manufacturing apparatus 1 are combined. That is, the fifth operation control example includes a step (S504) of storing the leading end of the bonding wire 11 in the welding pin 8, and a step (S508) of measuring the line interval of the repaired bonding wire 23. At this time, as shown in FIG. 13, a step (S605) of storing the front end of the bonding wire 11 in the welding pin 8 may be performed after the moving step (S604) of the welding pin 8. In addition, although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other ways, and various omissions, substitutions, and changes can be made without departing from the spirit of the invention. These embodiments and variations are included in the scope or gist of the invention, and are included in the invention described in the scope of patent application and its equivalent scope. [Related Applications] This case has priority over Japanese Patent Application No. 2016-53320 (application date: March 17, 2016). This case contains all the contents of the basic application by referring to the basic application.

1‧‧‧半導體製造裝置
2‧‧‧X-Y平台
3‧‧‧接合頭
4‧‧‧接合臂
5‧‧‧接合平台
6‧‧‧半導體晶片
7‧‧‧電路基板
8‧‧‧銲針
9‧‧‧前端部
10‧‧‧貫通孔
11、23‧‧‧接合線
13‧‧‧超聲振子
14‧‧‧線夾
15‧‧‧開合機構
16‧‧‧相機
17‧‧‧控制部
21‧‧‧電極墊
21a‧‧‧第1電極墊
22‧‧‧接合墊
22a‧‧‧第1接合墊
23a‧‧‧第1接合線
231‧‧‧接合線
232‧‧‧接合線
H‧‧‧瓶頸高度
S101~S608‧‧‧步驟
T‧‧‧前端直徑
1‧‧‧Semiconductor manufacturing equipment
2‧‧‧XY Stage
3‧‧‧ joint head
4‧‧‧Joint arm
5‧‧‧Joint Platform
6‧‧‧ semiconductor wafer
7‧‧‧circuit board
8‧‧‧welding pin
9‧‧‧ front end
10‧‧‧through hole
11, 23‧‧‧ bonding wire
13‧‧‧ Ultrasonic Oscillator
14‧‧‧clip
15‧‧‧ opening and closing agency
16‧‧‧ Camera
17‧‧‧Control Department
21‧‧‧electrode pad
21a‧‧‧1st electrode pad
22‧‧‧Joint pad
22a‧‧‧The first joint pad
23a‧‧‧The first bonding wire
231‧‧‧ bonding wire
232‧‧‧bonding wire
H‧‧‧ Bottleneck height
S101 ~ S608‧‧‧step
T‧‧‧ front diameter

圖1係表示實施形態之半導體製造裝置之剖視圖。 圖2係表示圖1所示之半導體製造裝置中所使用之銲針之一例之圖。 圖3係表示使用圖1所示之半導體製造裝置實施打線接合步驟之半導體零件之一例之圖。 圖4係表示圖1所示之半導體製造裝置之動作控制之第1例之流程圖。 圖5係表示使用圖1所示之半導體製造裝置進行線修復步驟之圖。 圖6係表示使用圖1所示之半導體製造裝置進行線修復步驟之圖。 圖7係表示使用圖1所示之半導體製造裝置進行線修復步驟之圖。 圖8係表示使用圖1所示之半導體製造裝置實施線修復步驟後之接合線之圖。 圖9係表示圖1所示之半導體製造裝置之動作控制之第2例之流程圖。 圖10係表示圖1所示之半導體製造裝置之動作控制之第3例之流程圖。 圖11係表示圖1所示之半導體製造裝置之動作控制之第4例之流程圖。 圖12係表示圖1所示之半導體製造裝置之動作控制之第5例之流程圖。 圖13係表示圖1所示之半導體製造裝置之動作控制之第5例之變化例之流程圖。FIG. 1 is a sectional view showing a semiconductor manufacturing apparatus according to the embodiment. FIG. 2 is a diagram showing an example of a solder pin used in the semiconductor manufacturing apparatus shown in FIG. 1. FIG. FIG. 3 is a diagram showing an example of a semiconductor component that is subjected to a wire bonding step using the semiconductor manufacturing apparatus shown in FIG. 1. FIG. FIG. 4 is a flowchart showing a first example of operation control of the semiconductor manufacturing apparatus shown in FIG. 1. FIG. FIG. 5 is a diagram showing a line repair procedure using the semiconductor manufacturing apparatus shown in FIG. 1. FIG. FIG. 6 is a diagram showing a line repair procedure using the semiconductor manufacturing apparatus shown in FIG. 1. FIG. FIG. 7 is a diagram showing a line repair procedure using the semiconductor manufacturing apparatus shown in FIG. 1. FIG. FIG. 8 is a view showing a bonding wire after a line repair step is performed using the semiconductor manufacturing apparatus shown in FIG. 1. FIG. 9 is a flowchart showing a second example of the operation control of the semiconductor manufacturing apparatus shown in FIG. 1. FIG. FIG. 10 is a flowchart showing a third example of the operation control of the semiconductor manufacturing apparatus shown in FIG. 1. FIG. FIG. 11 is a flowchart showing a fourth example of the operation control of the semiconductor manufacturing apparatus shown in FIG. 1. FIG. FIG. 12 is a flowchart showing a fifth example of operation control of the semiconductor manufacturing apparatus shown in FIG. 1. FIG. FIG. 13 is a flowchart showing a modification example of the fifth example of the operation control of the semiconductor manufacturing apparatus shown in FIG. 1. FIG.

6‧‧‧半導體晶片 6‧‧‧ semiconductor wafer

7‧‧‧電路基板 7‧‧‧circuit board

9‧‧‧前端部 9‧‧‧ front end

21‧‧‧電極墊 21‧‧‧electrode pad

22‧‧‧接合墊 22‧‧‧Joint pad

23‧‧‧接合線 23‧‧‧ bonding wire

231‧‧‧接合線 231‧‧‧ bonding wire

232‧‧‧接合線 232‧‧‧bonding wire

Claims (8)

一種半導體裝置之製造方法,其包括以下步驟: 使用插通有接合線之銲針,以上述接合線分別將設置於第1裝置構成零件之複數個第1接合部、與設置於第2裝置構成零件之複數個第2接合部之間電性連接; 於連接上述複數個第1接合部與上述複數個第2接合部之複數個上述接合線中,測定相鄰之上述接合線間之間隙; 選擇所測定之上述相鄰之接合線間之間隙為設定值以下之一組接合線;及 於所選擇之上述一組接合線間配置上述銲針,使上述銲針一面與上述接合線之至少一者接觸、一面沿上述接合線之接線方向移動,而擴大上述一組接合線間之間隙。A method for manufacturing a semiconductor device includes the following steps: using a solder pin inserted with a bonding wire, using the bonding wire to respectively form a plurality of first bonding portions provided on a first device component and a second device configuration Electrical connection between a plurality of second joints of the part; and measuring a gap between the adjacent joint lines among the plurality of joint lines connecting the plurality of first joint portions and the plurality of second joint portions; Select the measured gap between the adjacent bonding wires to be a set of bonding wires below the set value; and arrange the welding pin between the selected group of bonding wires so that one side of the welding pin and at least the bonding wire One touches and one side moves along the wiring direction of the bonding wires, thereby increasing the gap between the above-mentioned group of bonding wires. 如請求項1之半導體裝置之製造方法,其進而包括以下步驟: 擴大上述一組接合線間之間隙後,再次測定上述一組接合線間之間隙;及 於上述再次測定之一組接合線間之間隙之測定值為設定值以下之上述一組接合線間,配置上述銲針,使上述銲針一面與上述接合線之至少一者接觸、一面沿上述接合線之接線方向移動,而再次擴大上述一組接合線間之間隙。For example, the method for manufacturing a semiconductor device according to claim 1, further comprising the steps of: after expanding the gap between the group of bonding wires, measuring the gap between the group of bonding wires again; and measuring the group of bonding wires between the two groups again. The measured value of the gap is between the set of bonding wires below the set value. The welding pin is arranged so that one side of the welding pin is in contact with at least one of the bonding wires, and the other side moves in the wiring direction of the bonding wire, and is enlarged again. The gap between the above set of bonding wires. 如請求項2之半導體裝置之製造方法,其中於再次測定上述間隙之步驟中,僅再次測定上述間隙經擴大之一組接合線間之間隙。For example, in the method for manufacturing a semiconductor device according to claim 2, in the step of measuring the gap again, only the gap between the group of bonding wires in which the gap is enlarged is measured again. 一種半導體裝置之製造方法,其包括以下步驟: 使用插通有接合線之銲針,以上述接合線分別將設置於第1裝置構成零件之複數個第1接合部、與設置於第2裝置構成零件之複數個第2接合部之間電性連接; 於連接上述複數個第1接合部與上述複數個第2接合部之複數個上述接合線中,測定一上述接合線偏離設定軌跡之量; 當所測定之一上述接合線偏離設定軌跡之量為設定值以上時,選擇偏離設定軌跡之量為設定值以上之第1接合線、與於上述第1接合線偏離設定軌跡之方向相鄰之第2接合線,作為一組接合線;及 於所選擇之上述一組接合線間配置上述銲針,使上述銲針一面與上述接合線之至少一者接觸、一面沿上述接合線之接線方向移動,而擴大上述一組接合線間之間隙。A method for manufacturing a semiconductor device includes the following steps: using a solder pin inserted with a bonding wire, using the bonding wire to respectively form a plurality of first bonding portions provided on a first device component and a second device configuration Electrical connection between the plurality of second joints of the part; and measuring the amount of deviation of the one joint line from the set trajectory among the plurality of joint lines connecting the plurality of first joint portions and the plurality of second joint portions; When one of the measured joint lines deviates from the set trajectory by more than a set value, the first joint line deviated from the set trajectory by more than the set value is selected to be adjacent to the direction in which the first joint line deviates from the set trajectory. The second bonding wire is used as a group of bonding wires; and the solder pin is arranged between the selected group of bonding wires, so that one side of the solder pin is in contact with at least one of the bonding wires, and one side is along the wiring direction of the bonding wire. Move to expand the gap between the set of bonding wires. 如請求項4之半導體裝置之製造方法,其進而包括以下步驟: 擴大上述一組接合線間之間隙後,再次測定上述第1接合線偏離設定軌跡之量;及 於包括上述再次測定之上述第1接合線偏離設定軌跡之量為設定值以上之上述第1接合線在內之上述一組接合線間配置上述銲針,使上述銲針一面接觸上述接合線之至少一者、一面沿上述接合線之接線方向移動,而再次擴大上述一組接合線間之間隙。If the method for manufacturing a semiconductor device according to claim 4, further comprising the steps of: expanding the gap between the set of bonding wires, and measuring the amount of deviation of the first bonding wire from the set trajectory again; and 1 The bonding wire is deviated from the set trajectory by the above-mentioned first bonding wire, and the welding pin is arranged between the group of bonding wires, so that the welding pin is in contact with at least one of the bonding wires and the welding line is along the bonding. The wiring direction of the wire moves, and the gap between the above-mentioned set of bonding wires is enlarged again. 如請求項5之半導體裝置之製造方法,其中於上述再次測定步驟中,僅對上述間隙經擴大之一組接合線再次測定偏離設定軌跡之量。For example, the method for manufacturing a semiconductor device according to claim 5, wherein in the above-mentioned re-measurement step, the amount of deviation from the set trajectory is re-measured only for the group of bonding wires whose gaps are enlarged. 如請求項1至6中任一項之半導體裝置之製造方法,其中於上述所選擇之一組接合線間配置上述銲針之前,進而包括以下步驟:使插通於上述銲針中之上述接合線上升,將上述接合線之前端收納於上述銲針內。The method for manufacturing a semiconductor device according to any one of claims 1 to 6, wherein before the above-mentioned solder pins are arranged between the selected one of the bonding wires, the method further includes the following steps: making the above-mentioned bonding inserted in the aforementioned solder pins. The wire rises, and the leading end of the bonding wire is housed in the solder pin. 如請求項1至6中任一項之半導體裝置之製造方法,其中上述銲針具有瓶頸構造之前端部,使大於上述前端部之前端徑、且低於瓶頸高度之部分接觸上述接合線。The method for manufacturing a semiconductor device according to any one of claims 1 to 6, wherein the solder pin has a front end portion of a bottleneck structure, and a portion larger than a front end diameter of the front end portion and lower than a height of the bottleneck contacts the bonding wire.
TW106104198A 2016-03-17 2017-02-09 Semiconductor device manufacturing method TWI647768B (en)

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