JP6348626B2 - Manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device manufacturing technique, for example, a technique effective when applied to the assembly of a semiconductor device having a semiconductor chip on which a through electrode is formed.

  A structure in which an alignment mark is formed on a surface of a semiconductor chip on which a pad is formed, and this alignment mark is a test-dedicated pad to which a probe or the like hits is disclosed in, for example, Japanese Unexamined Patent Application Publication No. 2009-260373 (Patent Document 1). Has been.

  Further, an alignment mark formed in the same process as the process of forming the through electrode and having the same structure is formed on the substrate, and the alignment between the semiconductor chip to be stacked and the substrate is performed using the alignment mark. The technique is disclosed in, for example, Japanese Patent Laid-Open No. 2005-175263 (Patent Document 2).

  In addition, a structure in which a plurality of circuit regions are formed on the upper surface of the wafer and alignment marks are provided inside each circuit region is disclosed in, for example, Japanese Patent Application Laid-Open No. 2011-49318 (Patent Document 3). Further, Patent Document 3 describes that the tip of a through electrode formed on a wafer can be used as an alignment mark.

  In addition, with respect to the semiconductor wafer, with reference to the alignment mark, elements such as transistors and resistors constituting the semiconductor circuit and wirings to be connected to the elements are sequentially formed, and through holes are formed in the semiconductor wafer. For example, Japanese Patent Application Laid-Open No. 2008-153499 (Patent Document 4) discloses the formation of an electrode and a through electrode.

JP 2009-260373 A JP 2005-175263 A JP 2011-49318 A JP 2008-153499 A

  In the flow of technology for downsizing and high-density mounting of semiconductor devices (semiconductor packages), development of three-dimensional mounting technology for SIP (System In Package) with a three-dimensional structure is being actively conducted. Among the three-dimensional mounting technologies, TSV (Through Silicon) is used to form a through hole in a chip in a wafer state, bury a conductive material to form a through electrode, and electrically connect the stacked chips via the through electrode. Via (silicon through electrode)) technology is effective for miniaturization while stacking many chips.

  As an example of a semiconductor device using the TSV technology, a first semiconductor chip (for example, a logic chip) having a through electrode is flip-chip mounted on a wiring board (package substrate), and further on the back surface of the first semiconductor chip. And a second semiconductor chip (for example, a memory chip) provided with a protruding electrode is mounted (laminated). An electrode pad corresponding to the through electrode is provided on the back surface of the first semiconductor chip, and the second semiconductor chip is electrically connected to the first semiconductor chip through the above-described protruding electrode, electrode pad, and through electrode. Has been.

  Such a semiconductor device is often assembled by the following procedure.

  1) The alignment mark formed on the wiring board is recognized by the recognition unit of the chip mounting machine.

  2) Mount the first semiconductor chip on the wiring board based on the recognition result of 1).

  3) The alignment mark formed again on the wiring board is recognized by the recognition unit of the chip mounting machine.

  4) The second semiconductor chip is mounted on the first semiconductor chip based on the recognition result of 3).

  However, when the inventor of the present application uses the alignment mark formed on the wiring board as described above in the steps 1) and 3), the first semiconductor chip is displaced from the wiring board (mounting error, It has been found that the mounting accuracy variation is added to the positional deviation of the second semiconductor chip relative to the first semiconductor chip. That is, the steps 3) and 4) for recognizing the alignment mark formed on the wiring board and mounting the second semiconductor chip on the first semiconductor chip are only the positions of the second semiconductor chip and the wiring board. However, the accuracy of the positions of the second semiconductor chip and the first semiconductor chip cannot be guaranteed. In addition, in recent years, the adjacent pitch between the plurality of through-electrodes formed in the first semiconductor chip has become as narrow as about 50 μm, and the adjacent pitch of the plurality of electrode pads corresponding to each through-electrode has become the same. ing. For this reason, when a slight displacement occurs between the electrode pad of the first semiconductor chip and the protruding electrode of the second semiconductor chip, stable connection between the first semiconductor chip and the second semiconductor chip (the electrode pad and the protruding electrode and Stable connection) cannot be ensured.

  Accordingly, the inventor of the present application provides an alignment mark used in the step 3) on the back surface of the first semiconductor chip in order to improve (stabilize) the alignment accuracy between the first semiconductor chip and the second semiconductor chip. It was considered to be installed in. However, the inventor of the present application has found a further problem that, depending on the pattern of the alignment mark, it approximates the arrangement pattern of a plurality of electrode pads, and erroneous recognition occurs during recognition.

  An object of the embodiment disclosed in the present application is to provide a technique capable of improving the assembling property of a semiconductor device.

  Other problems and novel features will become apparent from the description of the specification and the accompanying drawings.

  A method of manufacturing a semiconductor device according to an embodiment includes a step of mounting a second semiconductor chip on a first semiconductor chip, and a plurality of electrode pads and a recognition mark are disposed on the main surface of the first semiconductor chip. When mounting the second semiconductor chip, the recognition range including the recognition mark of the first semiconductor chip is imaged to recognize the pattern of the recognition range. Further, the second semiconductor chip is mounted on the first semiconductor chip by aligning the plurality of electrode pads of the first semiconductor chip and the plurality of protruding electrodes of the second semiconductor chip based on the recognition result. At this time, the pattern of the recognition range is different from any part of the array pattern of the plurality of electrode pads.

  According to the one embodiment, the assembling property of the semiconductor device can be improved.

It is sectional drawing which shows an example of the structure of the semiconductor device of embodiment. FIG. 2 is a partial cross-sectional view illustrating an example of a structure after element formation to wiring formation in the assembly of the semiconductor device of FIG. 1. It is a fragmentary sectional view showing an example of the structure after copper post bump formation of the assembly of the semiconductor device of FIG. It is a fragmentary sectional view which shows an example of the structure after wafer support attachment-back surface grinding | polishing of the assembly of the semiconductor device of FIG. FIG. 2 is a partial cross-sectional view illustrating an example of a structure after a back surface bump is formed in the assembly of the semiconductor device of FIG. 1. It is a fragmentary sectional view which shows an example of the structure after tape sticking of assembly of the semiconductor device of FIG. 1-carrier removal. It is a fragmentary sectional view which shows an example of the structure after the dicing of the assembly of the semiconductor device of FIG. FIG. 2 is a partial cross-sectional view showing an example of a structure after flip-chip mounting of the lower chip in the assembly of the semiconductor device of FIG. 1. FIG. 2 is a partial cross-sectional view showing an example of a structure at the time of alignment in assembling the semiconductor device of FIG. 1. FIG. 2 is a partial cross-sectional view showing an example of a structure after flip-chip mounting of the upper chip in the assembly of the semiconductor device of FIG. 1. It is a conceptual diagram which shows an example of the structure of the prober which compared and examined. It is the top view which shows the structure of the surface side of the wafer mounted in the prober of FIG. 11, and an enlarged plan view. It is a top view which shows the structure of the back surface side of the wafer mounted in the prober of FIG. It is the top view which shows the structure of the A section of FIG. 13, and a partial enlarged plan view. It is a conceptual diagram which shows the alignment method which performed comparative examination. It is the top view which shows the recognition range recognized at the time of the alignment shown in FIG. 15, and an enlarged partial plan view. FIG. 2 is a conceptual diagram showing an example of a state at the time of alignment in a flip chip process of assembling the semiconductor device of FIG. 1. FIG. 2 is a conceptual diagram illustrating an example of a structure after flip chip mounting in a flip chip process of assembling the semiconductor device of FIG. 1. It is sectional drawing which shows an example of the structure at the time of the alignment of FIG. It is sectional drawing which shows an example of the structure after the flip chip mounting shown in FIG. It is a top view which shows the structure of the surface side of the wafer used by this Embodiment. FIG. 22 is a plan view and a partially enlarged plan view showing the structure of part A in FIG. 21. It is the top view of the semiconductor chip which performed comparative examination, and the partial expanded plan view of a pattern. It is a block diagram which shows an example of the structure of the chip mounting machine used at the flip chip process of the assembly of the semiconductor device of FIG. FIG. 2 is a block diagram showing an example of a structure of a prober device used in an inspection process for assembling the semiconductor device of FIG. 1. It is a fragmentary sectional view which shows an example of the holding state of the wafer at the time of an inspection in the prober apparatus of FIG. It is sectional drawing which shows an example of the formation process of the recognition mark in the semiconductor chip integrated in the semiconductor device of FIG. It is sectional drawing which shows an example of the formation process of the recognition mark in the semiconductor chip integrated in the semiconductor device of FIG. It is sectional drawing which shows the 1st modification of the formation process of the recognition mark in the semiconductor chip integrated in the semiconductor device of FIG. It is a conceptual diagram which shows an example of the pitch and magnitude | size of a pattern by the penetration electrode of FIG. FIG. 2 is a plan view showing an example of a structure on the back side of a logic chip incorporated in the semiconductor device of FIG. 1. It is the top view which shows the pattern of the recognition range of a 2nd modification, and an enlarged partial plan view. It is the top view which shows the pattern of the recognition range of a 3rd modification, and an enlarged partial plan view. It is the top view and enlarged partial plan view which show the pattern of the recognition range of a 4th modification. It is the top view which shows the pattern of the recognition range of a 5th modification, and an enlarged partial plan view. It is the top view which shows the pattern of the recognition range of a 6th modification, and an enlarged partial plan view. It is the top view and enlarged partial plan view which show the pattern of the recognition range of a 7th modification. It is an enlarged plan view which shows the pattern of the recognition range of an 8th modification. It is an enlarged plan view which shows the pattern of the recognition range of a 9th modification. It is an enlarged plan view which shows the pattern of the recognition range of a 10th modification. It is sectional drawing which shows the structure of the semiconductor device of the 11th modification of embodiment. It is an expanded partial sectional view which shows the structure of the semiconductor device of the 12th modification of embodiment. It is sectional drawing which shows the structure of the semiconductor device of the 13th modification of embodiment. It is sectional drawing which shows the structure of the semiconductor device of the 14th modification of embodiment.

  In the following embodiments, the description of the same or similar parts will not be repeated in principle unless particularly necessary.

  Further, in the following embodiment, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments, but they are not irrelevant to each other unless otherwise specified. The other part or all of the modifications, details, supplementary explanations, and the like are related.

  Also, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), particularly when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and it may be more or less than the specific number.

  Further, in the following embodiments, the constituent elements (including element steps) are not necessarily indispensable unless otherwise specified and clearly considered essential in principle. Needless to say.

  Further, in the following embodiments, regarding constituent elements and the like, when “consisting of A”, “consisting of A”, “having A”, and “including A” are specifically indicated that only those elements are included. It goes without saying that other elements are not excluded except in the case of such cases. Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numerical values and ranges.

  Hereinafter, embodiments will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof will be omitted. Further, even a plan view may be hatched for easy understanding of the drawing.

(Embodiment)
FIG. 1 is a cross-sectional view showing an example of the structure of the semiconductor device of the embodiment.

  As shown in FIG. 1, the semiconductor device of the present embodiment is a semiconductor package in which a plurality of semiconductor chips are stacked on a package substrate (wiring substrate) 3 on which wiring is formed. As an example of the semiconductor package, a BGA (Ball Grid Array) 6 in which a plurality of ball electrodes 9 serving as external connection terminals are provided in a grid on the lower surface (back surface) 3b side of the package substrate 3 will be described. The ball electrode 9 is, for example, a solder ball.

  The detailed structure of the BGA 6 will be described. The BGA 6 is mounted with two semiconductor chips stacked. Of these two semiconductor chips, the semiconductor chip arranged on the lower side is a logic chip (semiconductor chip equipped with a microcomputer, microcomputer chip) 1, while the upper side semiconductor chip stacked on the logic chip 1. Is a memory chip 2. The logic chip 1 and the memory chip 2 are electrically connected, and the upper memory chip 2 is controlled by the lower logic chip 1. Therefore, it can be said that the BGA 6 of the present embodiment is a SIP (System In Package) type semiconductor package.

  The logic chip 1 is flip-chip mounted on the package substrate 3 via a plurality of copper (Cu) post bumps (copper pillar bumps, metal bumps, metal bump electrodes) 5 that are bump electrodes. That is, as shown in FIG. 8 to be described later, the logic chip 1 has a surface (first main surface) 1a on which an element is formed and a plurality of copper post bumps 5 are arranged. It is arranged so as to face 3 a and is mounted on the upper surface 3 a of the package substrate 3.

  Further, the logic chip 1 is formed with a plurality of through electrodes 1c. The through electrode 1c is formed through the silicon base portion and is electrically connected to electrodes formed on the front and back surfaces of the chip.

  As shown in FIG. 8, the through electrode 1 c in the logic chip 1 of the BGA 6 has one end of the wiring portion 1 g formed on the insulating layer 1 f on the surface layer on the surface (element formation surface, lower surface) 1 a side of the logic chip 1. It is electrically connected to one end. Furthermore, the other end of the wiring part 1 g is electrically connected to a pad 1 d formed on the surface 1 a of the logic chip 1. Furthermore, the pad 1 d is electrically connected to the copper post bump 5. Further, the other end of the through electrode 1c is electrically connected to a bump (electrode pad) 1e provided on the back surface (second main surface, top surface) 1b side opposite to the surface 1a of the logic chip 1. . That is, the bump 1 e provided on the back surface 1 b of the logic chip 1 is electrically connected to the through electrode 1 c, the wiring portion 1 g, the pad 1 d, and the copper post bump 5 from the back surface 1 b to the front surface 1 a of the logic chip 1. It will be.

  Further, as shown in FIG. 8, the bumps 1e provided on the back surface 1b of the logic chip 1 and the pads 2d provided on the front surface 2a of the memory chip 2 are electrically connected, whereby the logic chip 1 and the logic chip 1 are connected. The memory chip 2 stacked on the back surface 1b of the chip 1 is electrically connected.

  Specifically, as shown in FIG. 10, a plurality of bumps (electrode pads) 1e arranged in a matrix are formed on the back surface 1b of the logic chip 1, while the front surface 2a of the memory chip 2 is formed. On the top, a plurality of bumps 2e corresponding to the plurality of bumps 1e are disposed, and the memory chip 2 and the logic chip 1 are flip-chip connected via the bumps 2e connected to the bumps 1e.

  In addition, a plurality of bumps 1 e are formed on the back surface 1 b of the logic chip 1. Furthermore, a recognition mark 1h for chip position recognition used for alignment in the probe inspection process and the flip chip mounting process in the assembly process of the BGA 6 is formed.

  That is, the recognition mark 1h recognizes the recognition mark 1h formed on the back surface (upper surface) 1b of the logic chip 1 in the probe inspection process and the flip chip mounting process in the assembly process of the BGA 6, and aligns the logic chip 1. Is to do.

  Further, the BGA 6 is configured to supply power, GND, and signals from the package substrate 3 to the upper memory chip 2 via the logic chip 1.

  As an example, the pitch of the copper post bumps 5 is about 100 μm or less, while the pitch of the bumps 1e on the opposite side is around 50 μm. In these ranges, the electrode pitch of the copper post bumps 5> the bumps The electrode pitch is 1e. Further, the pitch in plan view of the plurality of through electrodes 1c arranged immediately below each of the plurality of bumps 1e is about 50 μm, similarly to the electrode pitch of the bumps 1e. The package substrate 3 and the logic chip 1 are electrically connected via a plurality of copper post bumps 5.

  As shown in FIG. 8, a plurality of lands (first pad electrodes) 3i and a solder resist film (insulating film) 3k covering the outer periphery of the lands 3i are formed on the upper surface 3a of the package substrate 3. The copper post bumps 5 are electrically connected to the exposed portions of the lands 3i through, for example, solder 7 that is a conductive material.

  On the other hand, on the lower surface 3b of the package substrate 3, a plurality of lands 3j and a solder resist film (insulating film) 3k covering the outer periphery of the lands 3j are formed. Ball electrodes 9 serving as external connection terminals are electrically connected.

  The plurality of lands 3i on the upper surface 3a of the package substrate 3 and the plurality of lands 3j on the lower surface 3b are electrically connected via the internal wiring 3g and the through-hole wiring 3h.

  As shown in FIG. 1, the logic chip 1 and the memory chip 2 stacked on the package substrate 3 are sealed with a sealing body 4 made of, for example, an epoxy resin.

  Next, a method for manufacturing the semiconductor device of the present embodiment will be described.

  2 is a partial cross-sectional view showing an example of the structure after element formation to wiring formation in the assembly of the semiconductor device of FIG. 1, and FIG. 3 is a portion showing an example of the structure after copper post bump formation in the assembly of the semiconductor device of FIG. 4 is a partial cross-sectional view showing an example of the structure after wafer support attachment to back surface polishing in the assembly of the semiconductor device of FIG. 5 is a partial cross-sectional view showing an example of the structure after the back surface bump formation in the assembly of the semiconductor device of FIG. 1, and FIG. 6 shows an example of the structure after the tape is attached to the carrier of the assembly of the semiconductor device in FIG. FIG. 7 is a partial sectional view showing an example of the structure after dicing for assembling the semiconductor device of FIG. 8 is a partial cross-sectional view showing an example of the structure after flip-chip mounting of the lower chip of the semiconductor device assembly of FIG. 1, and FIG. 9 shows an example of the structure during alignment of the semiconductor device assembly of FIG. FIG. 10 is a partial cross-sectional view, and FIG. 10 is a partial cross-sectional view showing an example of the structure after flip-chip mounting of the upper chip in the assembly of the semiconductor device of FIG.

  First, the element formation shown in step S1 of FIG. 2 is performed. Here, the element 1 s is formed on the surface 8 a of a semiconductor wafer (hereinafter simply referred to as a wafer) 8 which is a semiconductor substrate. That is, an element 1s such as a transistor is formed on a surface layer made of an insulating layer 1p and a protective film 1q on a base substrate 1r made of silicon.

Next, the penetration electrode formation of step S2 is performed. Here, first, a metal layer 1 m is formed on the surface 8 a of the wafer 8, and then a plurality of through electrodes 1 c electrically connected to the metal layer 1 m are formed in the wafer 8. Note that the surface of each through electrode 1c is covered with an insulating film 1t such as SiO ₂ (including TiN), thereby preventing the through electrode 1c from diffusing. Here, the inter-electrode pitch of the plurality of through electrodes 1c is, for example, about 50 μm.

  Next, wiring formation in step S3 is performed. Here, first, the metal layer 1n is formed on the insulating layer 1f on the surface (first surface) 8a. That is, the metal layer 1n electrically connected to the plurality of through electrodes 1c is formed on the metal layer 1m. The metal layer 1n is composed of a plurality of wiring layers, and an interlayer insulating film is formed between each wiring layer.

  Further, a plurality of pads 1d electrically connected to the metal layer 1n are formed on the insulating layer 1f. The pad 1d is, for example, a pad made of aluminum (Al) here.

  Next, the copper post bump formation in step S4 of FIG. 3 is performed. Here, the copper post bumps 5 which are a plurality of protruding electrodes electrically connected to the metal layer 1n are formed on the metal layer 1n. That is, the copper post bumps 5 serving as protruding electrodes are formed on the plurality of pads 1d formed on the insulating layer 1f and electrically connected to the metal layer 1n. Further, solder 7 is formed on each copper post bump 5. Here, a post bump made of copper (Cu) is described as an example, but the present invention is not limited to this, and another metal post bump may be used.

  In addition, a plurality of copper post bumps 5 are provided here at a pitch of, for example, 100 μm or less. Since the number of terminals of the through electrode 1c required on the memory chip side is larger than the number of copper post bumps connected to the package substrate side, each electrode pitch of the plurality of copper post bumps 5> each of the plurality of through electrodes 1c. Of the electrode pitch.

  Next, a probe inspection is performed. That is, after the copper post bumps 5 are formed, the plurality of copper post bumps 5 are probed (by applying a test probe (not shown)), and a first probe inspection which is an electrical test is performed. The first probe inspection is performed to determine whether the logic chip 1 formed on the wafer 8 is good or not, and is performed on the plurality of logic chips 1 formed in the chip region of the wafer 8.

  Next, wafer support attachment shown in step S5 of FIG. 4 is performed. Here, the surface 8 a side of the wafer 8 is attached to the carrier 11 via the adhesive 12. The carrier 11 is a glass carrier made of, for example, quartz glass. The adhesive 12 is, for example, an organic adhesive. However, the adhesive 12 is not limited to an organic adhesive, and a conductive adhesive or the like may be used.

  Next, back surface polishing (grinding, back grinding) shown in step S6 of FIG. 4 is performed. Here, the back surface 8b opposite to the front surface 8a of the wafer 8 is polished (ground) to expose the tips (parts) of the plurality of through-electrodes 1c previously formed in step S2. The polishing at this time is, for example, polishing and chemical etching.

Next, back surface bump formation shown in step S7 of FIG. 5 is performed. Here, first, the insulating film 1 u is formed around the tips of the plurality of through electrodes 1 c exposed on the back surface 8 b of the wafer 8. The insulating film 1u is, for example, a SiO ₂ (including TiN) film. Further, bumps 1e are formed on the respective tips exposed on the back surface 8b side of the plurality of through electrodes 1c. The bump 1e is formed by plating, for example. The bump 1e is often made of, for example, gold (Au).

  Thereby, a plurality of bumps 1 e are formed on the back surface 8 b of the wafer 8. Since each of the plurality of bumps 1e is formed at the tip of the plurality of through electrodes 1c exposed on the back surface 8b of the wafer 8, the electrode pitch of the plurality of bumps 1e is equal to the pitch of the plurality of through electrodes 1c. The same. Therefore, on the front and back surfaces of the wafer 8, the electrode pitch of each of the plurality of copper post bumps 5 is greater than the electrode pitch of each of the plurality of bumps 1 e (through electrodes 1 c).

  Next, a probe inspection is performed. Here, a second probe inspection is performed to inspect the electrical connection state (conduction state) between the plurality of copper post bumps 5 and the plurality of bumps 1e. In the second probe inspection, the wafer 8 is supported in a state where the carrier 11 is attached to the wafer 8, and the conduction between the respective electrodes of the plurality of bumps 1e is confirmed in this state.

  In other words, the second probe inspection is performed to determine whether each of the plurality of through electrodes 1c formed in the wafer 8 (in the chip) is acceptable.

  In the second probe inspection, the recognition mark 1h formed on the back surface 1b of the logic chip 1 shown in FIG. 8 is recognized, and a probe test is performed on the plurality of bumps 1e on the back surface 1b of the logic chip 1 based on the recognition result. Probe with the needle in contact.

  After completion of the second probe inspection, tape attachment shown in step S8 in FIG. 6 is performed. Here, the back surface 8 b side of the wafer 8 subjected to the second probe inspection is attached to the dicing tape 15.

  Next, the carrier removal shown in step S9 is performed. Here, the carrier 11 bonded to the front surface 8a side with the adhesive 12 is removed from the wafer 8 with respect to the wafer 8 on which the second probe inspection has been completed and the dicing tape 15 has been bonded (removed). To do). Further, the adhesive 12 is removed by etching. At this time, the adhesive 12 is removed by etching, and other foreign matters can be removed, and the plurality of copper post bumps 5 and the element formation surface (surface 8a) can be cleaned.

  Next, dicing shown in step S10 in FIG. 7 is performed. Here, the wafer 8 supported by the dicing tape 15 is cut to obtain a plurality of non-defective semiconductor chips (here, the logic chip 1).

  Next, flip chip mounting is performed.

  Here, flip chip mounting of the logic chip (lower chip) 1 shown in step S11 of FIG. 8 is performed. First, a package substrate (wiring substrate, multiple substrate) 3 is prepared. A plurality of lands 3 i connected to the plurality of copper post bumps 5 of the logic chip 1 are formed on the upper surface 3 a of the package substrate 3, while the lower surface 3 b opposite to the upper surface 3 a of the package substrate 3. Are formed with a plurality of lands 3j electrically connected to the plurality of lands 3i.

  In addition, a solder resist film 3k is formed on the upper and lower surfaces of the package substrate 3, and a part of each land 3i, 3j is exposed.

  After the package substrate 3 is prepared, the solder 7 formed on the copper post bumps 5 is mounted on the upper surface 3a of the package substrate 3 by heating and pressurizing the logic chip 1 that has become non-defective in the second probe inspection. The package substrate 3 and the plurality of copper post bumps 5 are electrically connected to each other. Thereafter, an underfill 10 that is a liquid sealing resin is injected and filled in the gap between the logic chip 1 and the package substrate 3. For this, the underfill 10 which is a liquid sealing resin is applied on the package substrate 3 in advance, and the logic chip 1 is mounted to electrically connect the copper post bumps 5 and the package substrate 3. And filling the resin in the gap between the logic chip 1 and the package substrate 3 may be performed simultaneously.

  Next, a probe inspection is performed. Here, a third probe inspection for inspecting the electrical connection state between the logic chip 1 and the package substrate 3 is performed. In this third probe inspection, the recognition mark 1h formed on the back surface 1b of the logic chip 1 is recognized, and the probe test needle is brought into contact with the plurality of bumps 1e on the back surface 1b of the logic chip 1 based on the recognition result. And conduct a continuity test.

  By this third probe inspection, it can be confirmed whether or not the conduction between the logic chip 1 and the package substrate 3 is ensured.

  Next, the memory chip (upper chip) 2 shown in step S12 of FIG. 9 is stacked.

  First, the logic chip 1 and the memory chip 2 are aligned. Here, based on the recognition result of the recognition mark 1h on the back surface 1b of the logic chip 1 recognized at the time of the third probe inspection, a plurality of bumps 1e on the back surface 1b of the logic chip 1 and a plurality of the front surfaces 2a of the memory chip 2 are obtained. Alignment with the bump 2e is performed. Then, after the alignment is completed, the memory chip 2 is flip-chip mounted on the logic chip 1 as shown in FIG.

  Here, the plurality of bumps 1e of the logic chip 1 and the plurality of bumps 2e of the memory chip 2 are aligned so that the back surface 1b of the logic chip 1 and the front surface 2a of the memory chip 2 face each other. A memory chip 2 is mounted on 1 and flip chip mounting is performed. Thereafter, the underfill 10 is filled in the gap between the logic chip 1 and the memory chip 2.

  Next, in the resin sealing step, the logic chip 1, the memory chip 2, the plurality of copper post bumps 5, the plurality of bumps 2 e, etc. are covered with a sealing resin to form a sealing body 4, and the external connection terminals The ball electrode 9 is mounted. After mounting, the package substrate 3 is cut into individual pieces, and the assembly of the BGA 6 shown in FIG. 1 is completed.

  Next, a semiconductor wafer alignment method performed by the probe inspection of the present embodiment and a semiconductor chip alignment method performed by flip chip mounting will be described. 11 is a conceptual diagram showing an example of the structure of a prober that has been compared, FIG. 12 is a plan view and an enlarged plan view showing the structure of the front side of the wafer mounted on the prober of FIG. 11, and FIG. 13 is a plan view of FIG. FIGS. 14A and 14B are a plan view and a partially enlarged plan view, respectively, showing the structure of part A in FIG. 13. FIG. 15 is a conceptual diagram showing a registration method that has been compared and FIG. 16 is a plan view and an enlarged partial plan view showing a recognition range recognized at the time of registration shown in FIG.

  The prober 30 shown in FIG. 11 performs probe inspection of the wafer 31, takes out the wafer 31 conveyed to the loader / unloader 30d, and places it on a stage 30a movable in the X, Y, and Z directions. A plurality of probe needles 30c provided on the test head 30b of the prober 30 are brought into contact with the electrodes of the wafer 31 to conduct continuity inspection, electrical characteristic inspection, and the like.

  At this time, in the probe inspection, it is necessary to accurately contact the probe needle 30c with a test unit (pad or bump) in a chip unit to inspect the characteristics. Therefore, the prober 30 that moves the wafer 31 in units of chips needs to recognize one chip and move it with high accuracy. Accordingly, it is possible to move one chip by recognizing a specified alignment mark such as a unique pattern in the chip.

  FIG. 12 shows the structure on the surface 31a side of the wafer 31 on which a plurality of through electrodes 31d are formed. On the surface 31a side, a scribe line other than the terminals of the plurality of through electrodes 31d shown in the enlarged view is shown. 31c is formed so that the section of the chip can be recognized. In the chip region 31e, a unique pattern composed of the above-described terminals and the like is repeated, and the pattern of the unique portion is recognized and aligned at the time of alignment. In addition, alignment marks 31f for alignment are also formed at the corners of the chip region 31e, and are used for alignment of the semiconductor 31 during the probe inspection.

  On the other hand, FIG. 13 shows a structure on the back surface 31b side of the wafer 31, and only a plurality of bumps 31g connected to the through electrode 31d can be seen. Therefore, in the wafer state, when the probe inspection is performed by bringing the probe needle 30c into contact with the bump 31g on the back surface 31b side, a mark for alignment is required, but as described above, a plurality of marks are provided on the back surface 31b side. Since only the bump 31g is visible, it is difficult to bring the probe needle 30c into contact with the bump 31g in the probe inspection. For example, if the prober 30 recognizes the rear surface 31b of the wafer 31 for alignment, the recognition range C and the image captured by the camera are captured as shown in A and B in the enlarged view of FIG. Since the pattern is the same in the range D, it is determined that the pattern is similar and the probability that the prober 30 erroneously recognizes increases.

  This problem also occurs when the upper semiconductor chip (for example, the memory chip 2 shown in FIG. 9) is aligned during chip stacking in the chip mounting process. For example, the chip 32 is flip-chip mounted on the wiring board 3 shown in FIG. 15, and the recognition for alignment of the upper semiconductor chip stacked on the chip 32 is recognized, and the plurality of through electrodes 31d are recognized by the camera 34. In this case, as in the case of the above-described probe inspection, the pattern is the same in the recognition range C and the imaging range D in FIG.

  As for the mounting of the lower chip 32, the pitch between the electrodes for flip chip connection (the pitch between the pads 1d in FIG. 8, for example, about 100 μm or less) is the pitch between the through electrodes 31d (for example, around 50 μm). Therefore, the positioning can be performed by recognizing the positioning mark formed on the wiring board 3.

  However, since the semiconductor chip stacked on the upper stage side is flip-chip mounted on the plurality of through-electrodes 31d arranged in a narrow pitch on the lower stage chip 32, the position for securing the positional accuracy on the back surface of the chip 32 is also provided. A mark for alignment is required.

  As shown in FIG. 16, even if the alignment mark 35 made of a dot image is formed in the chip region 31e, the pattern of the recognition range C by the alignment mark 35 is compared with the arrangement pattern of the plurality of bumps 31g. Since the pattern of the imaging range D by the bump 31g is similar, there is a high possibility of erroneous recognition.

  Next, features of the present embodiment will be described.

  17 is a conceptual diagram showing an example of a state during alignment in the flip chip process of assembling the semiconductor device of FIG. 1, and FIG. 18 is an example of a structure after flip chip mounting in the flip chip process of assembling the semiconductor device of FIG. FIG. 19 is a sectional view showing an example of the structure at the time of alignment in FIG. 17, and FIG. 20 is a sectional view showing an example of the structure after flip-chip mounting shown in FIG. 21 is a plan view showing the structure of the front side of the wafer used in the present embodiment, FIG. 22 is a plan view and a partially enlarged plan view showing the structure of part A in FIG. 21, and FIG. It is the top view which shows the structure of a part, and a partial enlarged plan view. 24 is a block diagram showing an example of the structure of a chip mounting machine used in the flip chip process for assembling the semiconductor device in FIG. 1, and FIG. 25 is a diagram of a prober device used in the inspection process for assembling the semiconductor device in FIG. FIG. 26 is a partial cross-sectional view showing an example of a wafer holding state at the time of inspection in the prober apparatus of FIG. 25.

  In this embodiment, as shown in FIGS. 17 and 18, a recognition mark 1 h for alignment is formed on the back surface 1 b of the logic chip 1. Then, when the memory chip 2 is flip-chip mounted on the back surface 1b of the logic chip 1, the pattern within the recognition range including the recognition mark 1h is recognized and the memory chip 2 is aligned.

  In this manner, by providing the alignment recognition mark 1h on the back surface 1b of the logic chip 1, it is possible to reduce erroneous recognition as compared to recognizing a part of the plurality of through electrodes 1c. Further, as shown in FIGS. 19 and 20, when the memory chip 2 is mounted on the logic chip 1, the plurality of through electrodes 1c of the logic chip 1 and the plurality of bumps 2e of the memory chip 2 are aligned with high accuracy. can do. Here, FIG. 21 shows the back surface 8b side of the wafer 8 on which the recognition mark 1h as shown in FIG. 22 is formed, and a plurality of bumps 1e are provided in each chip region on the back surface 8b side. In addition, as shown in FIG. 22, a recognition mark 1h is formed at the corner of the chip.

  Note that the recognition mark 1h shown in FIG. 22 is a stipple by the bump 1e connected to each of the plurality of through electrodes 1c, and when viewed from above, it is seen as a so-called L shape.

  Thereby, in the flip chip connecting step, first, the recognition range C including the recognition mark 1h on the back surface 1b of the logic chip 1 is imaged by the camera 14 shown in FIG. 19 to recognize the pattern of the recognition range C shown in FIG. To do.

  Here, the pattern of the recognition range C is different from any part of the arrangement pattern of the plurality of bumps 1e. That is, on the back surface 1b side of the logic chip 1, the pattern of the recognition range C to be recognized by the camera 14 is not the same as the pattern of the imaging range D in the arrangement of the plurality of bumps 1e.

  Note that “the pattern is different” means that the pattern of the recognition range C including the recognition mark 1 h is different from any part of the arrangement pattern of the plurality of bumps 1 e on the back surface 1 b of the logic chip 1. Alternatively, when the pattern of the recognition range C including the recognition mark 1h is overlaid on the area where the plurality of bumps 1e are arranged, the patterns do not match (does not match).

  In the example shown in FIG. 22, the recognition mark 1h is composed of an assembly of a plurality of patterns 1ha, and the recognition range C including the recognition mark 1h includes a first region 1i in which a plurality of patterns 1ha are arranged, and a pattern 1ha. The second region 1j is not disposed.

  On the other hand, the imaging range D has only an area (corresponding to the first area 1i) where the plurality of bumps 1e are arranged, and does not have an area corresponding to the second area 1j.

  Therefore, the pattern of the recognition range C formed on the chip and the array pattern of the imaging range D are definitely different, and they are not similar patterns (similar patterns).

  Therefore, when the camera 14 images the back surface 1b of the logic chip 1, it is possible to reduce erroneous recognition of the arrangement pattern of the imaging range D as the pattern of the recognition range C to be recognized.

  In a recognition unit such as a chip mounting machine, when recognizing a mark at a predetermined location, an approximate recognition position (design value) is stored in the apparatus, and the (X, Y) coordinates of the mark are set. In many cases, an operation for searching for a mark is performed. However, if a similar pattern is formed around the coordinates, the recognition unit may erroneously recognize the similar pattern as a mark. Therefore, it is preferable to dispose the similar pattern and the recognition pattern as far apart as possible.

  Here, FIG. 23 shows one solution to the problem of the present invention (if the pattern of the alignment mark approximates the arrangement pattern of a plurality of electrode pads, erroneous recognition occurs during recognition). . 23A shows a case where the vicinity of the central portion, which is relatively misrecognized, of the arrangement of the bumps 1e is imaged. The arrangement pattern of the bumps 1e in the imaging range D and the arrangement of the recognition marks 1h in the recognition range C are shown. Due to the approximation, there is a high possibility of erroneous recognition.

  Therefore, by disposing the recognition marks 1h at the corners on the back surface of the semiconductor chip, the positions of the plurality of bumps 1e and the recognition marks 1h can be separated, and as a result, erroneous recognition can be prevented.

  However, disposing the recognition mark 1h at a position away from the bump 1e causes an increase in the area of the semiconductor chip.

  Therefore, as in the present invention shown in FIG. 22, the recognition mark 1h in the recognition range C is surely different from the arrangement pattern in the imaging range D, thereby bringing the recognition mark 1h closer to the plurality of bumps 1e. As a result, the area of the semiconductor chip can be reduced. Furthermore, it is possible to suppress an increase in the size of the semiconductor wafer forming the semiconductor chip (an increase in wafer size).

  Next, a detailed method when the memory chip 2 is flip-chip connected to the logic chip 1 on which the recognition mark 1h shown in FIG. 22 is formed will be described.

  First, the chip mounting machine 13 shown in FIG. 24 used for flip chip connection will be described. The chip mounting machine 13 stores a camera 14 that captures a pattern in the recognition range C including the recognition mark 1h of the logic chip 1 shown in FIG. 22, and recognition that stores image data captured by the camera 14 and processes the image data. Part 16 and a chip mounting part 17 for positioning and mounting the upper memory chip 2 based on the image data processed by the recognition part 16.

  At the time of flip chip connection, first, the camera 14 of the chip mounting machine 13 captures the recognition range C including the recognition mark 1h on the back surface 1b of the logic chip 1 in FIG. At this time, the pattern image data of the recognition range C stored in the recognition unit 16 in advance and the pattern image data of the recognition range C newly captured by the camera 14 are compared. At this time, since the pattern of the recognition range C is different from any part of the arrangement pattern in the pattern of the recognition range C and the arrangement pattern of the imaging range D of the plurality of bumps 1e, the arrangement pattern of the imaging range D is changed. The pattern of the recognition range C can be reliably recognized by the recognition unit 16 without being erroneously recognized as the pattern of the recognition range C to be recognized.

  Next, based on the result of recognizing the pattern in the recognition range C by the chip mounting unit 17, a plurality of bumps 1e of the logic chip 1 and a bump 2e which is a plurality of protruding electrodes of the memory chip 2, as shown in FIG. Align with.

  Further, after the alignment, the memory chip 2 is mounted on the logic chip 1 by the chip mounting unit 17, and the plurality of bumps 1 e of the logic chip 1 and the plurality of bumps 2 e of the memory chip 2 are electrically connected. This completes the flip chip connection.

  In this way, the recognition mark 1h that forms a pattern different from the arrangement pattern of the bumps 1e is formed on the back surface 1b of the logic chip 1, so that the recognition mark 1h in the pattern of the recognition range C can be reliably recognized. Thus, alignment between the plurality of bumps 1e of the logic chip 1 and the plurality of bumps 2e of the memory chip 2 can be performed with high accuracy.

  As a result, the reliability of flip chip connection can be improved, and the assemblability of the semiconductor device (BGA 6) can be improved.

  Next, at the time of probe inspection (second probe inspection or third probe inspection) in the assembly process of the BGA 6 of this embodiment, the logic chip 1 (semiconductor wafer 8) on which the recognition mark 1h shown in FIG. A detailed method for performing the alignment with will be described.

  First, the prober device 18 shown in FIG. 25 used in the probe inspection will be described. The prober device 18 includes a camera 19 that captures a pattern of the recognition range C including the recognition mark 1h, a recognition unit 20 that stores image data captured by the camera 19, and processes the image data. A plurality of probe needles 21 that contact the semiconductor chip based on the image data and a measurement unit 22 that measures the electrical characteristics of the semiconductor chip via the plurality of probe needles 21 are provided.

  At the time of probe inspection, first, the camera 19 of the prober device 18 captures the recognition range C including the recognition mark 1h on the back surface 1b of the logic chip 1 in FIG. At this time, the pattern image data of the recognition range C stored in the recognition unit 20 in advance and the pattern image data of the recognition range C newly captured by the camera 19 are compared. At this time, since the pattern of the recognition range C is different from any part of the arrangement pattern in the pattern of the recognition range C and the arrangement pattern of the imaging range D of the plurality of bumps 1e, the arrangement pattern of the imaging range D is changed. The pattern of the recognition range C can be reliably recognized by the recognition unit 20 without being erroneously recognized as the pattern of the recognition range C to be recognized.

  Thereafter, based on the result of recognizing the pattern in the recognition range C, the plurality of bumps 1e of the logic chip 1 shown in FIG. 9 (or the plurality of bumps 1e on the back surface 8b of the wafer 8 in FIG. 5) and the plurality of bumps 1e in FIG. Positioning with the probe needle 21 is performed.

  After the alignment, a plurality of probe needles 21 are brought into contact with each of the plurality of bumps 1 e of the logic chip 1, and the electrical characteristics of the logic chip 1 are measured by the measuring unit 22.

  In this way, the recognition mark 1h that forms a pattern different from the arrangement pattern of the bumps 1e is formed on the back surface 1b of the logic chip 1, so that the recognition mark 1h in the pattern of the recognition range C can be reliably recognized. Thus, the alignment between the plurality of bumps 1e of the logic chip 1 and the probe needle 21 of the prober device 18 can be performed with high accuracy.

  As a result, the reliability of the inspection in the probe inspection can be improved, and the assemblability of the semiconductor device (BGA 6) can be improved.

  In the case of performing the second probe inspection after forming the bump 1e in the back surface bump forming process in step S7 shown in FIG. 5, the probe inspection is performed in the state of the wafer 8 attached to the carrier 11. In the probe inspection in the wafer state, as shown in FIG. 26, the probe inspection is performed with the wafer 8 held on the stage 23 of the prober device 18 via the carrier 11.

  When the probe inspection is performed in this wafer state, after the probe inspection, the wafer 8 is diced as shown in FIG. 7 to obtain the logic chip 1 that is a non-defective product by the probe inspection (second probe inspection). Thereafter, the good logic chip 1 is mounted on the package substrate 3 as shown in FIG.

  In the assembly of the BGA 6 of the present embodiment, the second and third probe inspections are not necessarily performed. Further, only one of the second and third probe inspections may be performed, or both may be performed.

  Also, in the flip chip connection of the upper memory chip 2 shown in FIG. 9, the alignment performed by imaging the recognition mark 1h is not necessarily performed. However, in that case, in at least one of the second and third probe inspections, alignment with the probe needle 21 performed by imaging the recognition mark 1h is performed.

  The pattern of the recognition range C including the recognition mark 1h imaged in the first probe inspection or the second probe inspection includes the recognition mark 1h imaged in the flip chip connection of the upper memory chip 2 shown in FIG. It may be shared with the pattern of the recognition range C. That is, it is preferable to use a common recognition mark 1h that is imaged for alignment by probe inspection and flip chip connection.

  Thereby, it can avoid forming the separate recognition mark 1h for every process on a chip | tip back surface, and can use the area | region in a semiconductor chip efficiently.

  Next, a method for forming the recognition mark 1h according to the present embodiment will be described.

  27 is a cross-sectional view showing an example of the formation process of the recognition mark in the semiconductor chip incorporated in the semiconductor device of FIG. 1, and FIG. FIGS. 29 and 29 are cross-sectional views showing a first modification of the formation process of the recognition mark in the semiconductor chip incorporated in the semiconductor device of FIG.

  30 is a conceptual diagram showing an example of the pitch and size of the pattern formed by the through electrodes of FIG. 22, and FIG. 31 is a plan view showing an example of the structure on the back side of the logic chip incorporated in the semiconductor device of FIG. .

  First, the case where the recognition mark is formed in a process different from the through electrode forming process will be described. As shown in step S <b> 21 of FIG. 27, first, an element 1 s is formed on the surface 8 a of the wafer 8. That is, an element 1s such as a transistor is formed on a surface layer made of an insulating layer 1p and a protective film 1q on a base substrate 1r made of silicon.

Next, a through electrode is formed. Here, first, a metal layer 1 m is formed on the surface 8 a of the wafer 8, and then a plurality of through electrodes 1 c electrically connected to the metal layer 1 m are formed in the wafer 8. Note that the surface of each through electrode 1c is covered with an insulating film 1t such as SiO ₂ (including TiN), thereby preventing the through electrode 1c from diffusing.

  Next, after forming the copper post bump 5 on the pad 1 d, the carrier 11 is attached to the wafer 8 via the adhesive 12. Further, back surface polishing shown in step S22 is performed. That is, the back surface 8b of the wafer 8 held by the carrier 11 is polished to protrude the tip portions of the plurality of through electrodes 1c.

  Next, back surface bump formation shown in step S23 of FIG. 28 is performed. Here, bumps 1e are formed at the respective tips of the respective through electrodes 1c.

  Next, mark formation shown in step S24 is performed. For example, the recognition mark 1k is formed on the back surface 8b of the wafer 8 by plating or the like.

  In this manner, by forming the recognition mark 1k in a process different from the through electrode forming process, it is possible to form the recognition mark 1k with a pattern completely different from the arrangement pattern of the through electrodes 1c. In other words, the recognition mark 1h can be formed by completely changing the size, shape, pitch, and the like.

  As shown in FIG. 30, the plurality of through electrodes 1c arranged in a matrix form have a pitch X between adjacent electrodes of X = 50 μm and a pitch Y according to JEDEC (Joint Electron Device Engineering Council standards). It is determined that Y = 40 μm and the electrode diameter φ is φ = 20 μm.

  Therefore, when the recognition mark 1k is formed in a process different from the through electrode forming process, the recognition mark 1k may be formed by changing the pitch, size, shape, etc. without being limited to these numerical values. Alternatively, they may be formed with the same pitch, diameter and shape.

  On the other hand, the 1st modification shown in FIG. 29 is a figure which shows the case where the recognition mark 1h is formed simultaneously in a penetration electrode formation process.

  First, the element 1 s is formed on the surface 8 a of the wafer 8. That is, an element 1s such as a transistor is formed on a surface layer made of an insulating layer 1p and a protective film 1q on a base substrate 1r made of silicon.

Next, as shown in step S31, a plurality of through electrodes 1v for the recognition mark 1h are formed together with the through electrode 1c in the through electrode forming step. First, the metal layer 1 m is formed on the surface 8 a of the wafer 8, and then a plurality of through electrodes 1 c and 1 v electrically connected to the metal layer 1 m are formed in the wafer 8. The surface of each through electrode 1c, 1v is covered with an insulating film 1t such as SiO ₂ (including TiN), thereby preventing the through electrodes 1c, 1v from diffusing.

  Further, after forming the copper post bump 5 on the pad 1 d, the carrier 11 is attached to the wafer 8 via the adhesive 12. Then, back surface polishing shown in step S32 is performed. That is, the back surface 8b of the wafer 8 held by the carrier 11 is polished to project the tip portions of the plurality of through electrodes 1c, 1v.

  Next, mark formation (back bump formation) shown in step S33 is performed. Here, bumps 1e are formed at the respective tips of the plurality of through electrodes 1c protruding from the back surface 8b of the wafer 8, and recognition marks 1h are formed at the tips of the plurality of through electrodes 1v. The plurality of bumps 1e and the recognition mark 1h are formed by, for example, plating.

  In the case where the recognition mark 1h is simultaneously formed in the through electrode forming process, the recognition mark 1h is an aggregate of point images (pattern 1ha) or a single point image.

  By simultaneously forming the recognition mark 1h in the through electrode forming step in this way, the through electrode 1v for the recognition mark can be formed at the same time as the through electrode 1c using a single mask. The recognition mark 1h can be formed.

  Furthermore, the process for forming the recognition mark 1h can be omitted, and as a result, the recognition mark 1h can be formed efficiently.

  Even when the recognition mark 1h is formed at the same time in the through electrode forming process, the pitch and size of the adjacent through electrodes 1v can be changed, and the shape can be changed from that of the through electrodes 1c. For example, only the pitch X may be changed, only the pitch Y may be changed, or both the pitch X and Y may be changed.

  However, the plurality of through electrodes 1v may be formed with the same pitch, diameter, and shape as the plurality of through electrodes 1c.

  Next, the formation position of the recognition mark 1h when the shape of the back surface 1b of the logic chip 1 is substantially square will be described with reference to FIG.

  In the logic chip 1, a plurality of through electrodes 1c are arranged in a matrix at the center of the back surface 1b. Therefore, it is necessary to secure a cell region around the plurality of through electrodes 1c. Therefore, as shown in FIG. 31, the recognition mark 1h is preferably formed at a position away from the region where the plurality of through electrodes 1c on the back surface 1b are arranged. For example, it is an end region such as a corner of the back surface 1b.

  As a result, a sufficient cell area can be secured.

  Furthermore, the recognition rate of the recognition mark 1h can be increased by forming the recognition mark 1h at a position (an end portion of the back surface 1b) away from the region where the plurality of through electrodes 1c are disposed on the back surface 1b. That is, since the recognition mark 1h is formed at a position sufficiently away from the bump 1e connected to the plurality of through electrodes 1c, the recognition mark 1h can be easily recognized when captured by the cameras 14 and 19, The recognition rate of the recognition mark 1h can be increased.

  However, as shown in the logic chip 1 of FIG. 22, when the recognition mark 1h is formed at a position close to the region where the plurality of bumps 1e (through electrodes 1c) are arranged, the bump 1e, the recognition mark 1h, Therefore, the chip mounting accuracy when performing flip chip connection can be increased.

  Accordingly, in order to increase the recognition rate of the recognition mark 1h, it is preferable that the recognition mark 1h is formed at a position away from the plurality of bumps 1e (through electrodes 1c), but the chip mounting accuracy at the time of flip chip connection is increased. If necessary, the recognition mark 1h may be formed at a position close to the plurality of bumps 1e (through electrodes 1c).

  Next, another modification will be described.

  32 is a plan view and an enlarged partial plan view showing a recognition range pattern of the second modification, FIG. 33 is a plan view and an enlarged partial plan view showing a recognition range pattern of the third modification, and FIG. 34 is a fourth modification. FIG. 35 is a plan view and an enlarged partial plan view showing the pattern of the recognition range of the fifth modification, and FIG. 36 is a pattern of the recognition range of the sixth modification. They are a top view and an enlarged partial plan view. 37 is a plan view and an enlarged partial plan view showing the recognition range pattern of the seventh modification, FIG. 38 is an enlarged plan view showing the recognition range pattern of the eighth modification, and FIG. 39 is the ninth modification example. FIG. 40 is an enlarged plan view showing the recognition range pattern of the tenth modification. 41 is a sectional view showing the structure of a semiconductor device according to an eleventh modification of the embodiment, FIG. 42 is an enlarged partial sectional view showing the structure of a semiconductor device according to the twelfth modification of the embodiment, and FIG. FIG. 44 is a cross-sectional view showing the structure of a semiconductor device according to a fourteenth modification of the embodiment.

  32 to 37, for the sake of convenience, the case where the shape of the back surface of the chip is rectangular and the recognition mark 1h is formed at a position close to the area where the plurality of bumps 1e are arranged will be taken up. As will be described, it goes without saying that the shape of the back surface of the chip and the positional relationship between the recognition mark 1h and the plurality of bumps 1e may be a shape close to a square as in the logic chip 1 shown in FIG.

  The second modification shown in FIG. 32 shows a modification of the recognition mark 1h. The recognition mark 1h is composed of an assembly of a plurality of patterns 1ha and has a + shape in plan view. The recognition range C including 1h has the second regions 1j where the pattern 1ha is not arranged at four places (four corners).

  On the other hand, since the imaging range D does not have an area corresponding to the second area 1j, the pattern of the recognition range C and the arrangement pattern of the imaging range D are definitely different. It is not a pattern.

  As a result, when the camera 14 of FIG. 24 or the camera 19 of FIG. 25 captures the back surface 1b of the logic chip 1, it is possible to reduce erroneous recognition of the arrangement pattern of the imaging range D as the pattern of the recognition range C to be recognized. can do.

  The third modification shown in FIG. 33 also shows a modification of the recognition mark 1h. The recognition mark 1h is composed of a single first pattern 1hb and is circular in plan view. Furthermore, although the area of each of the plurality of bumps 1e is equal, the area of the first pattern 1hb is different from the area of each of the plurality of bumps 1e, and the area of the first pattern 1hb is more than the area of each of the bumps 1e. It is much bigger.

  Note that also in the third modification, the recognition range C including the recognition mark 1h has the second region 1j in which the first pattern 1hb is not arranged.

  On the other hand, since the imaging range D does not have an area corresponding to the second area 1j, the pattern of the recognition range C and the arrangement pattern of the imaging range D are definitely different. It is not a pattern.

  As a result, when the camera 14 of FIG. 24 or the camera 19 of FIG. 25 captures the back surface 1b of the logic chip 1, it is possible to reduce erroneous recognition of the arrangement pattern of the imaging range D as the pattern of the recognition range C to be recognized. can do.

  Further, the area of the first pattern 1hb is much larger than the area of each bump 1e, and the sizes of the first pattern 1hb and the bump 1e are clearly different, so that the recognition range C including the recognition mark 1h is included. The recognition rate can be further increased.

  The fourth modification shown in FIG. 34 also shows a modification of the recognition mark 1h. The recognition mark 1h includes a first pattern 1hb, a second pattern 1hc, a third pattern 1hd, and a fourth pattern 1he. Have. Here, when the first pattern 1hb is used as a reference, the second pattern 1hc is arranged along the first direction 1w, and the third pattern 1hd is arranged along the second direction 1x orthogonal to the first direction 1w. Has been. Further, the fourth pattern 1he is arranged along the first direction 1w with the third pattern 1hd as a reference.

  The first pattern 1hb, the second pattern 1hc, the third pattern 1hd, and the fourth pattern 1he are each circular in plan view, and the areas of the patterns are equal, and each of the plurality of bumps 1e is further equal. It is different from the area.

  That is, the circular areas (sizes) of the first pattern 1hb, the second pattern 1hc, the third pattern 1hd, and the fourth pattern 1he are clearly different from the areas (sizes) of the plurality of bumps 1e. ing. That is, the area of each pattern is clearly larger than the area (size) of each of the plurality of bumps 1e.

  Further, the pitch distance P1 between the first pattern 1hb and the second pattern 1hc is larger than the pitch distance P2 of each of the plurality of bumps 1e, and the relation of P1> P2 is established. Further, the inter-pitch distance P3 between the first pattern 1hb and the third pattern 1hd is larger than the inter-pitch distance P2 of each of the plurality of bumps 1e, and the relationship P3> P2.

  That is, in the fourth modification, the sizes of the individual patterns and the respective bumps 1e are completely different, and the arrangement pitch between the adjacent patterns (bumps 1e) is also completely different. This is definitely different from the arrangement pattern of the imaging range D, and in the fourth modification example, both are more clearly different patterns.

  Therefore, when the camera 14 in FIG. 24 or the camera 19 in FIG. 25 images the back surface 1b of the logic chip 1, it is further ensured that the arrangement pattern of the imaging range D is erroneously recognized as the pattern of the recognition range C to be recognized. Can be reduced.

  A fifth modification shown in FIG. 35 also shows a modification of the recognition mark 1h. The recognition mark 1h is composed of a single first pattern 1hb and has a circular shape in plan view. Furthermore, although the area of each of the plurality of bumps 1e is equal, the area of the first pattern 1hb is different from the area of each of the plurality of bumps 1e, and the area of the first pattern 1hb is more than the area of each of the bumps 1e. It is much bigger.

  Therefore, the pattern of the recognition range C and the arrangement pattern of the imaging range D are definitely different, and they are not similar patterns (similar patterns).

  As a result, when the camera 14 of FIG. 24 or the camera 19 of FIG. 25 captures the back surface 1b of the logic chip 1, it is possible to reduce erroneous recognition of the arrangement pattern of the imaging range D as the pattern of the recognition range C to be recognized. can do.

  Furthermore, the recognition range C of the fifth modified example of FIG. 35 is one area of the first pattern 1hb, and is much smaller than the recognition range C of FIG.

  Therefore, by reducing the recognition range C, it is possible to ensure a large cell area.

  A sixth modification shown in FIG. 36 also shows a modification of the recognition mark 1h. The recognition mark 1h is composed of a plurality of first patterns 1hb and is L-shaped in plan view. Furthermore, although the area of each of the plurality of first patterns 1hb is the same, it is different from the area of each of the plurality of bumps 1e, and the area of the first pattern 1hb is much smaller than the area of each of the bumps 1e. .

  Further, the arrangement pitch of the plurality of first patterns 1hb is different from the arrangement pitch of the plurality of bumps 1e, and the arrangement pitch of the plurality of first patterns 1hb is much smaller than the arrangement pitch of the plurality of bumps 1e.

  Note that also in the sixth modification, the recognition range C including the recognition mark 1h has the second region 1j in which the first pattern 1hb is not disposed.

  Therefore, the pattern of the recognition range C and the arrangement pattern of the imaging range D are definitely different, and they are not similar patterns (similar patterns).

  As a result, when the camera 14 of FIG. 24 or the camera 19 of FIG. 25 captures the back surface 1b of the logic chip 1, it is possible to reduce erroneous recognition of the arrangement pattern of the imaging range D as the pattern of the recognition range C to be recognized. can do.

  Furthermore, also in the sixth modified example, since the recognition range C is narrow, it is possible to secure a large area of the cell region.

  The seventh modified example shown in FIG. 37 also shows a modified example of the recognition mark 1h. The recognition mark 1h includes a plurality of first patterns 1hb and second patterns 1hc, and the first pattern 1hb and the first pattern 1hb. Two patterns 1hc are alternately arranged in a staggered arrangement in the first direction 1w and the second direction 1x.

  The areas of the first pattern 1hb and the second pattern 1hc are equal, and the areas of the first pattern 1hb and the second pattern 1hc are also equal to the areas of the plurality of bumps 1e.

  However, the plurality of first patterns 1hb and the second pattern 1hc are alternately arranged in a staggered arrangement, and the arrangement pitch of the first pattern 1hb and the second pattern 1hc is about twice as large as the arrangement pitch of the plurality of bumps 1e. It has become.

  Therefore, since the arrangement pitch of the two is completely different, the pattern of the recognition range C and the arrangement pattern of the imaging range D are definitely different, and they are not similar patterns (similar patterns).

  As a result, when the camera 14 of FIG. 24 or the camera 19 of FIG. 25 captures the back surface 1b of the logic chip 1, it is possible to reduce erroneous recognition of the arrangement pattern of the imaging range D as the pattern of the recognition range C to be recognized. can do.

  Next, the modified examples shown in FIGS. 38 to 40 show modified examples of the shape in plan view of one pattern 1ha of the recognition mark 1h. First, the eighth modified example shown in FIG. 38 is a case where the shape of one pattern 1ha of the recognition mark 1h is an octagon in plan view. The ninth modification shown in FIG. 39 is a case where the shape of one pattern 1ha of the recognition mark 1h is a + shape in plan view. Furthermore, the 10th modification shown in FIG. 40 is a case where the shape of one pattern 1ha of the recognition mark 1h is a negative shape in plan view.

  Thus, even if the shape of one pattern 1ha of the recognition mark 1h is the shape of the modification shown in FIGS. 38 to 40, the same effect as in the case of the circle shown in FIG. 22 can be obtained.

  Next, the modification shown in FIGS. 41 to 44 is a modification related to the structure of the semiconductor device.

  First, an eleventh modification shown in FIG. 41 shows a BGA (semiconductor device) 25 in which the logic chip 1 and the memory chip 2 stacked thereon are sealed by a case 24 instead of resin sealing. It is. Also in this BGA 25, the recognition range C including the recognition mark 1h as shown in FIG. 22 is recognized in the flip chip connection process and the probe inspection process in the assembly, thereby narrowing the memory chip 2 to be stacked when the flip chip is connected. The alignment of the pitch electrode and the alignment of the probe needle 21 (see FIG. 25) with the narrow pitch electrode during probe inspection can be performed with high accuracy. Thereby, the assemblability of the BGA 25 can be improved.

  42 shows a semiconductor device in which a plurality of memory chips 2 are stacked on a logic chip 1. That is, the logic chip 1 is mounted on the package substrate 3 via the copper post bumps 5, and a plurality of memory chips 2 are stacked on the logic chip 1.

  At this time, a plurality of through electrodes 1c and 2c are formed in each of the logic chip 1 and the plurality of memory chips 2 stacked thereon. The through electrodes 1c and 2c are via wirings that are formed through the silicon base portion and electrically connect the electrodes on the front and back surfaces of the chip. In other words, it is an electrode formed by opening a through hole in a chip in a wafer state and embedding a conductive material, and is effective for laminating a large number of semiconductor chips while maintaining a narrow pad pitch.

  Therefore, the through electrode 1c in the logic chip 1 is formed by forming a copper post bump 5 connected to the pad 1d on the front surface 1a and a bump 1e provided on the opposite back surface 1b side on the insulating layer 1f on the surface layer. They are electrically connected via the wiring part 1g.

  On the other hand, the through electrode 2c in the memory chip 2 has a wiring portion in which a pad 2d provided on the front surface 2a and a bump 2e provided on the opposite back surface 2b side are similarly formed on the insulating layer 2f of the surface layer. It is electrically connected via 2g.

  In the stacking of the logic chip 1 and a plurality of memory chips 2 (second semiconductor chip, third semiconductor chip) on the upper side, bumps 1e directly connected to the through electrodes 1c of the logic chip 1 and the memory chip 2 The pad 2d on the surface 2a side is electrically connected. Further, the upper surface side bump 2e directly connected to the through electrode 2c of the second-stage memory chip 2 and the lower surface side pad 2d of the third-stage memory chip 2 are electrically connected. Yes. The second-stage memory chip 2 and the third-stage memory chip 2 are the same chip.

  For example, when the third-stage memory chip 2 is stacked on the second-stage memory chip 2, the alignment mark 2h formed on the back surface 2b of the second-stage memory chip 2 is recognized and aligned. As a result, the second-stage memory chip 2 and the third-stage memory chip 2 can be aligned with high accuracy.

  Here, as an example of a semiconductor device in which the structure shown in FIG. 42 is sealed by resin sealing, a BGA 26 of the thirteenth modification shown in FIG. 43 is shown.

  In addition, as an example of a semiconductor device in which the structure shown in FIG.

  The BGA 26 shown in FIG. 43 and the BGA 27 shown in FIG. 44 are stacked by recognizing the recognition range C including the recognition mark 1h as shown in FIG. 22 in the flip chip connection process and the probe inspection process in each assembly. The alignment of the narrow pitch electrodes when the memory chip 2 is flip-chip connected can be performed with high accuracy. Further, the probe needle 21 (see FIG. 25) at the time of probe inspection can be aligned with the narrow pitch electrode with high accuracy. As a result, the assemblability of the BGAs 26 and 27 can be improved.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the above embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  For example, in the above-described embodiments and modifications, a BG tape other than the carrier may be used as a support member that supports the wafer in the assembly process.

  In the above-described embodiment and modification, the case where the semiconductor device is a BGA has been described. However, if the semiconductor device has a structure in which a plurality of semiconductor chips are stacked on a wiring board, the BGA is used. For example, an LGA (Land Grid Array) may be used.

  The following embodiments may also be included.

(Appendix)
[Claim 1]
(A) a first semiconductor chip having a first main surface and a second main surface opposite to the first main surface; a first main surface; and a first main surface opposite to the first main surface. Preparing a second semiconductor chip having two main surfaces;
(B) mounting the second semiconductor chip on the first semiconductor chip such that the second main surface of the first semiconductor chip and the first main surface of the second semiconductor chip face each other; Have
On the second main surface of the first semiconductor chip, a plurality of electrode pads and recognition marks arranged in a matrix are arranged,
A plurality of protruding electrodes corresponding to the plurality of electrode pads of the first semiconductor chip are disposed on the first main surface of the second semiconductor chip,
The step (b)
(B1) capturing a recognition range including the recognition mark on the second main surface of the first semiconductor chip and recognizing the pattern of the recognition range;
(B2) aligning the plurality of electrode pads of the first semiconductor chip and the plurality of protruding electrodes of the second semiconductor chip based on the result of recognizing the pattern of the recognition range;
(B3) A step of mounting the second semiconductor chip on the first semiconductor chip and electrically connecting the plurality of electrode pads of the first semiconductor chip and the plurality of protruding electrodes of the second semiconductor chip. And having
The method of manufacturing a semiconductor device, wherein the pattern of the recognition range is different from any part of the array pattern of the plurality of electrode pads.
[Section 2]
In the method for manufacturing a semiconductor device according to Item 1,
A manufacturing method of a semiconductor device, wherein the first semiconductor chip is a logic chip including a microcomputer, and the second semiconductor chip is a memory chip.
[Section 3]
In the method for manufacturing a semiconductor device according to Item 2,
A method for manufacturing a semiconductor device, wherein a third semiconductor chip is mounted on the second semiconductor chip.
[Claim 4]
In the method for manufacturing a semiconductor device according to Item 3,
A method of manufacturing a semiconductor device, wherein the second semiconductor chip and the third semiconductor chip are the same chip.
[Section 5]
In the method for manufacturing a semiconductor device according to Item 4,
The method for manufacturing a semiconductor device, wherein the third semiconductor chip is a memory chip.
[Claim 6]
In the method for manufacturing a semiconductor device according to Item 1,
After the step (b),
A method for manufacturing a semiconductor device, comprising: a sealing step of sealing the first semiconductor chip, the second semiconductor chip, and the plurality of protruding electrodes.

1 Logic chip (first semiconductor chip)
1a Surface (first main surface)
1b Back surface (second main surface)
1c Through electrode 1d Pad 1e Bump (electrode pad)
1f Insulating layer 1g Wiring part 1h Recognition mark 1ha Pattern 1hb First pattern 1hc Second pattern 1hd Third pattern 1he Fourth pattern 1i First region 1j Second region 1k Recognition mark 1m Metal layer 1n Metal layer 1p Insulating layer 1q Protective film 1r base substrate 1s element 1t insulating film 1u insulating film 1v through electrode 1w first direction 1x second direction 2 memory chip (second semiconductor chip)
2a Surface (first main surface)
2b Back surface (second main surface)
2c Penetration electrode 2d Pad 2e Bump 2f Insulating layer 2g Wiring part 2h Recognition mark 3 Package substrate (wiring substrate, multiple substrate)
3a Upper surface 3b Lower surface 3g Internal wiring 3h Through-hole wiring 3i Land 3j Land 3k Solder resist film 4 Sealing body 5 Copper post bump 6 BGA (semiconductor device)
7 Solder 8 Wafer 8a Front surface 8b Back surface 9 Ball electrode 10 Underfill 11 Carrier 12 Adhesive 13 Chip mounting machine 14 Camera 15 Dicing tape 16 Recognition unit 17 Chip mounting unit 18 Prober device 19 Camera 20 Recognition unit 21 Probe needle 22 Measuring unit 23 Stage 24 Case 25 BGA (Semiconductor Device)
26 BGA (semiconductor device)
27 BGA (semiconductor device)
30 prober 30a stage 30b test head 30c probe needle 30d loader / unloader 31 wafer 31a front surface 31b back surface 31c scribe line 31d through electrode 31e chip region 31f alignment mark 31g bump 32 chip 34 camera 35 alignment mark

Claims (21)

(A) a first semiconductor chip having a first main surface and a second main surface opposite to the first main surface; a third main surface; and a first main surface opposite to the third main surface. Preparing a second semiconductor chip having four main surfaces;
(B) mounting the second semiconductor chip on the first semiconductor chip such that the second main surface of the first semiconductor chip and the third main surface of the second semiconductor chip face each other; Have
On the second main surface of the first semiconductor chip, a plurality of electrode pads and recognition marks arranged in a matrix are arranged,
The first semiconductor chip has a plurality of through electrodes, and the plurality of through electrodes are electrically connected to each of the plurality of electrode pads,
A plurality of protruding electrodes corresponding to the plurality of electrode pads of the first semiconductor chip are disposed on the third main surface of the second semiconductor chip,
The step (b)
(B1) capturing a recognition range including the recognition mark on the second main surface of the first semiconductor chip and recognizing the pattern of the recognition range;
(B2) aligning the plurality of electrode pads of the first semiconductor chip and the plurality of protruding electrodes of the second semiconductor chip based on the result of recognizing the pattern of the recognition range;
(B3) A step of mounting the second semiconductor chip on the first semiconductor chip and electrically connecting the plurality of electrode pads of the first semiconductor chip and the plurality of protruding electrodes of the second semiconductor chip. And having
The pattern of the recognition range is different from any part of the array pattern of the plurality of electrode pads,
Before the step (a),
(A1) forming the plurality of through electrodes on the first semiconductor chip;
(A2) After the step (A1), on the second main surface of the first semiconductor chip, the plurality of through electrodes are electrically separated, and in a plan view, directly on the plurality of through electrodes. Forming the recognition mark on the layer on which the plurality of through electrodes are further formed so as not to overlap, and
A method for manufacturing a semiconductor device comprising: In the manufacturing method of the semiconductor device according to claim 1,
(A3) After the step (A1) and before the step (A2), the plurality of electrode pads are electrically connected to the respective through electrodes immediately above the plurality of through electrodes. Having a process of forming,
In the step (A2), the recognition mark is a manufacturing method of a semiconductor device formed by plating. In the manufacturing method of the semiconductor device according to claim 1,
The step (A2) is a method for manufacturing a semiconductor device, which is performed in a state where a plurality of metal bumps are provided on the first main surface of the first semiconductor chip. In the manufacturing method of the semiconductor device according to claim 1,
The recognition mark has a first pattern;
The area of each electrode pad of the plurality of electrode pads is equal,
A method of manufacturing a semiconductor device, wherein an area of the first pattern is different from an area of each electrode pad of the plurality of electrode pads. In the manufacturing method of the semiconductor device according to claim 4,
The method of manufacturing a semiconductor device, wherein an area of the first pattern of the recognition mark is larger than an area of each of the plurality of electrode pads. In the manufacturing method of the semiconductor device according to claim 4,
The method of manufacturing a semiconductor device, wherein an area of the first pattern of the recognition mark is smaller than an area of each electrode pad of the plurality of electrode pads. In the manufacturing method of the semiconductor device according to claim 1,
The recognition mark has a first pattern and a second pattern, and a distance between pitches of the first pattern and the second pattern is larger than a distance between pitches of the electrode pads of the plurality of electrode pads. Device manufacturing method. In the manufacturing method of the semiconductor device according to claim 7,
The recognition mark has a third pattern, and a pitch distance between the first pattern and the third pattern is larger than a pitch distance between the electrode pads of the plurality of electrode pads. In the manufacturing method of the semiconductor device according to claim 8,
The method of manufacturing a semiconductor device, wherein the second pattern is arranged in a first direction when the first pattern is used as a reference, and the third pattern is arranged in a second direction orthogonal to the first direction. In the manufacturing method of the semiconductor device according to claim 7,
The areas of the first and second patterns of the recognition mark are equal,
The method of manufacturing a semiconductor device, wherein the areas of the first and second patterns are different from the areas of the plurality of electrode pads. In the manufacturing method of the semiconductor device according to claim 7,
The areas of the first and second patterns of the recognition mark are equal,
The method of manufacturing a semiconductor device, wherein the areas of the first and second patterns are equal to the areas of the plurality of electrode pads. In the manufacturing method of the semiconductor device according to claim 1,
The method for manufacturing a semiconductor device, wherein the recognition range including the recognition mark includes a first region in which a plurality of patterns are arranged and a second region in which no patterns are arranged. In the manufacturing method of the semiconductor device according to claim 12,
A method of manufacturing a semiconductor device, wherein the areas of the plurality of patterns of the recognition mark are equal and different from the areas of the plurality of electrode pads. In the manufacturing method of the semiconductor device according to claim 1,
In the step (b), a camera that captures a pattern of the recognition range including the recognition mark, a recognition unit that stores image data captured by the camera, and processes the image data, and a processing performed by the recognition unit Performed by a chip mounting machine having a chip mounting portion for positioning and mounting a semiconductor chip based on the image data,
The step (b2) is a method of manufacturing a semiconductor device including a step of comparing the image data of the pattern of the recognition range stored in the recognition unit in advance with the image data of the pattern of the recognition range newly captured. (A) a first semiconductor chip having a first main surface and a second main surface opposite to the first main surface; a third main surface; and a first main surface opposite to the third main surface. Preparing a second semiconductor chip having four main surfaces;
(B) measuring electrical characteristics of the first semiconductor chip;
(C) mounting the second semiconductor chip on the first semiconductor chip that has become non-defective in the step (b),
On the second main surface of the first semiconductor chip, a plurality of electrode pads and recognition marks arranged in a matrix are arranged,
The first semiconductor chip has a plurality of through electrodes, and the plurality of through electrodes are electrically connected to each of the plurality of electrode pads,
The step (b)
(B1) capturing a recognition range including the recognition mark on the second main surface of the first semiconductor chip and recognizing the pattern of the recognition range;
(B2) a step of aligning the plurality of electrode pads and the plurality of probe needles of the first semiconductor chip based on a result of recognizing the pattern of the recognition range;
(B3) contacting the plurality of probe needles with each of the plurality of electrode pads of the first semiconductor chip, and measuring the electrical characteristics of the first semiconductor chip;
The pattern of the recognition range is different from any part of the array pattern of the plurality of electrode pads,
Before the step (a),
(A1) forming the plurality of through electrodes on the first semiconductor chip;
(A2) After the step (A1), on the second main surface of the first semiconductor chip, the plurality of through electrodes are electrically separated, and in a plan view, directly on the plurality of through electrodes. Forming the recognition mark on the layer on which the plurality of through electrodes are further formed so as not to overlap, and
A method for manufacturing a semiconductor device comprising: In the manufacturing method of the semiconductor device according to claim 15,
(A3) After the step (A1) and before the step (A2), the plurality of electrode pads are electrically connected to the respective through electrodes immediately above the plurality of through electrodes. Having a process of forming,
In the step (A2), the recognition mark is a manufacturing method of a semiconductor device formed by plating. In the manufacturing method of the semiconductor device according to claim 15,
The step (A2) is a method for manufacturing a semiconductor device, which is performed in a state where a plurality of metal bumps are provided on the first main surface of the first semiconductor chip. In the manufacturing method of the semiconductor device according to claim 15,
The step (b) is a method for manufacturing a semiconductor device performed in a wafer state. In the manufacturing method of the semiconductor device according to claim 18,
(D) A semiconductor device further comprising a step of dicing the wafer after the step (b) and before the step (c), and obtaining the first semiconductor chip that is a non-defective product in the step (b). Production method. In the manufacturing method of the semiconductor device according to claim 15,
(E) A method for manufacturing a semiconductor device, comprising a step of mounting the first semiconductor chip on a wiring board before the step (a). In the manufacturing method of the semiconductor device according to claim 15,
In the step (b), a camera that captures the pattern of the recognition range including the recognition mark, an image data captured by the camera, a recognition unit that processes the image data, and the image that is processed by the recognition unit Performed by a prober device having a plurality of probe needles that contact a semiconductor chip based on data, a measurement unit that measures the electrical characteristics of the semiconductor chip via the plurality of probe needles,
The step (b2) is a method of manufacturing a semiconductor device including a step of comparing the image data of the pattern of the recognition range stored in the recognition unit in advance with the image data of the pattern of the recognition range newly captured.

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