TW201806149A - 半導體裝置及用以形成其的方法 - Google Patents

半導體裝置及用以形成其的方法 Download PDF

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TW201806149A
TW201806149A TW106106977A TW106106977A TW201806149A TW 201806149 A TW201806149 A TW 201806149A TW 106106977 A TW106106977 A TW 106106977A TW 106106977 A TW106106977 A TW 106106977A TW 201806149 A TW201806149 A TW 201806149A
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channel
layer
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semiconductor device
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TW106106977A
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TWI728060B (zh
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喬治 A. 凱特爾
洪俊九
馬克 S. 羅德爾
達爾門達 雷迪 帕勒
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三星電子股份有限公司
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    • H01L29/76—Unipolar devices, e.g. field effect transistors
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    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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Abstract

本發明揭露一種半導體裝置及一種用以形成所述半導體裝置的方法。半導體裝置的n通道組件包含第一水平奈米片（hNS）堆疊，且p通道組件包含第二hNS堆疊。第一hNS堆疊包含具有多個第一閘極層及至少一個第一通道層的第一閘極結構。第一內部間隙壁安置於至少一個第一閘極層與第一源極/汲極結構之間，其中第一內部間隙壁具有第一長度。第二hNS堆疊包含具有多個第二閘極層及至少一個第二通道層的第二閘極結構。第二內部間隙壁安置於至少一個第二閘極層與第二源極/汲極結構之間，其中第二內部間隙壁具有大於第一長度的第二長度。

Description

半導體裝置及用以形成其的方法
本發明大體上是有關於半導體裝置，且更具體言之，是有關於用以形成具有變化的通道應變的奈米尺度場效電晶體（field effect transistor；FET）裝置的方法。
半導體裝置的一個基本組件為電晶體，通常稱作FET。存在各種類型的FET裝置，且FET裝置的功能、組成物以及用途各不相同。通常用於半導體裝置中的一種類型的FET裝置為金屬氧化物半導體場效電晶體（metal-oxide-semiconductor field effect transistor；MOSFET）。MOSFET裝置通常呈現為以下兩種相異類型：p通道MOSFET（p-channel MOSFET；pMOS）裝置以及n通道MOSFET（n-channel MOSFET；nMOS）裝置。數位資料處理裝置可包含pMOS裝置與nMOS裝置的組合，其以互補金屬氧化物半導體（complimentary metal-oxide-semiconductor；CMOS）配置進行配置。先進半導體裝置中的電晶體大小約束（constraints）需要更緊湊的電晶體設計及拓撲。一種此類設計包含具有經組合以提供用於數位應用的可縮放（scalable）CMOS電路的多閘極結構的電晶體裝置。
一些半導體裝置將水平奈米片（horizontal nanosheets；hNS）形狀或水平奈米線（horizontal nanowires；hNW）形狀的通道用於電晶體裝置，其將在本文中分別被稱作hNS裝置或hNW裝置。在hNS裝置中，裝置的通道中的至少一些通道經塑形為由環閘極結構（gate-all around structure）圍繞的奈米片。奈米片為具有通常在約2 nm至約10 nm範圍內的一個經按比例縮放尺寸的結構，而其他尺寸可更大（例如，在約10 nm至約100 nm的範圍內）。當用於由環閘極結構圍繞的MOS裝置的通道中時，hNS可具有通常具有較小尺寸（例如，約2 nm至約10 nm）及較大尺寸（例如，約10 nm至約100 nm）的剖面（其正交於通道中的電流流動的方向）。當hNS的剖面的所述二個尺寸類似（例如，兩者皆在約2 nm至約10 nm的範圍內時），其被稱為NW。儘管主要結合hNS裝置來描述本發明實施例，但應理解，本文中所揭露的實施例可同樣適用於hNW裝置。在製造hNS結構或hNW結構的程序期間，可將應變引入於裝置的一個或多個通道中。應變可為在製造所述結構時所使用的材料及程序順序的物理或機械結果。再者，變化的應變可由hNS或hNW結構的實體尺寸的變化引起。應變參數的變化可能影響裝置的效能。效果可能不利，或可能增強裝置的效能，此取決於裝置組態及應變參數的值。
呈現用於在奈米尺度hNS或hNW半導體裝置上形成變化的應變的方法。在一實施例中，一種半導體裝置包含：n通道組件，其可包含第一水平奈米片（hNS）堆疊及第一源極/汲極結構，其中所述第一hNS堆疊可在底層上包含具有多個第一閘極層及至少一個第一通道層的第一閘極結構，第一閘極層可與所述底層接觸，且各第一通道層可與至少一個第一閘極層接觸，所述第一源極/汲極結構可安置於由所述第一hNS堆疊形成的通道長度的一個末端處，第一內部間隙壁可安置於至少一個第一閘極層與所述第一源極/汲極結構之間，其中所述第一內部間隙壁具有第一長度；以及p通道組件，其可包含第二hNS堆疊及第二源極/汲極結構，其中所述第二hNS堆疊可在所述底層上包含具有多個第二閘極層及至少一個第二通道層的第二閘極結構，第二閘極層可與所述底層接觸且各第二通道層可與至少一個第二閘極層接觸，所述第二源極/汲極結構可安置於由所述第二hNS堆疊形成的通道長度的一個末端處，且第二內部間隙壁可安置於至少一個第二閘極層與所述第二源極/汲極結構之間，其中所述第二內部間隙壁具有大於所述第一長度的第二長度。在一個實施例中，所述第一長度可比所述第二長度小約2 nm至約5 nm（包含2 nm及5 nm）。在另一實施例中，各第一通道層中的應變可包含拉伸應變，且各第二通道層中的應變可包含中性應變或壓縮應變。
在一實施例中，一種用以形成半導體裝置的方法可包含：形成n通道組件的第一水平奈米片（hNS）堆疊，其中所述第一hNS堆疊可在底層上包含多個第一犧牲層及至少一個第一通道層，其中第一犧牲層可與所述底層接觸，各第一通道層可與至少一個第一犧牲層接觸，所述第一犧牲層可由SiGe形成，且所述至少一個第一通道層可由Si形成；形成p通道組件的第二hNS堆疊，其中所述第二hNS堆疊可在所述底層上包含多個第二犧牲層及至少一個第二通道層，第二犧牲層可與所述底層接觸，其中各第二通道層可與至少一個第二犧牲層接觸，且所述第二犧牲層可由SiGe形成，且所述至少一個第二通道層可由Si形成；形成第一源極/汲極凹槽及第二源極/汲極凹槽，其中所述第一源極/汲極凹槽可安置於由所述第一hNS堆疊形成的通道的末端處，且所述第二源極/汲極凹槽可安置於由所述第二hNS堆疊形成的通道的末端處；在所述第一犧牲層與所述第一通道層之間，在所述第一源極/汲極凹槽中的至少一者內形成第一內部間隙壁凹槽，其中所述第一內部間隙壁凹槽具有第一長度；以及在所述第二犧牲層與所述第二通道層之間，在所述第二源極/汲極凹槽中的至少一者內形成第二內部間隙壁凹槽，其中所述第二內部間隙壁凹槽具有大於所述第一長度的第二長度。
在一實施例中，一種用以形成半導體裝置的方法可包含：形成n通道組件的第一水平奈米片（hNS）堆疊，其中所述第一hNS堆疊可在底層上包含多個第一犧牲層及至少一個第一通道層，且第一犧牲層可與所述底層接觸，各第一通道層可與至少一個第一犧牲層接觸，且所述第一犧牲層可由SiGe形成，且所述至少一個第一通道層可由Si形成，其中各第一犧牲層可包含第一Ge含量百分比；形成p通道組件的第二hNS堆疊，其中所述第二hNS堆疊可在所述底層上包含多個第二犧牲層及至少一個第二通道層，且第二犧牲層可與所述底層接觸，各第二通道層可與至少一個第二犧牲層接觸，所述第二犧牲層可由SiGe形成，且所述至少一個第二通道層可由Si形成，其中各第二犧牲層具有第二Ge含量百分比，其中所述第二Ge含量百分比可小於或等於所述第一Ge含量百分比；形成第一源極/汲極凹槽及第二源極/汲極凹槽，其中所述第一源極/汲極凹槽可安置於由所述第一hNS堆疊形成的通道的末端處，且所述第二源極/汲極凹槽可安置於由所述第二hNS堆疊形成的通道的末端處；在所述第一犧牲層與所述第一通道層之間，在所述第一源極/汲極凹槽中的至少一者內形成至少一個第一內部間隙壁凹槽；以及在所述第二犧牲層與所述第二通道層之間，在所述第二源極/汲極凹槽中的至少一者內形成至少一個第二內部間隙壁凹槽。
本文中描述用於製造具有hNS通道或hNW通道的半導體裝置的方法及系統的實施例。所揭露實施例可適用於諸多不同通道材料系統，但尤其適用於矽（Si）通道hNS裝置或矽通道hNW裝置。有利地，所揭露實施例可允許CMOS裝置的pMOS組件及nMOS組件中的不同應變。在一個特定實施例中，pMOS組件中的應變可接近中性或可為壓縮的，而nMOS組件中的應變可為拉伸的。在一個實施例中，實質上相同的通道材料可用於nMOS組件及pMOS組件兩者，但兩個組件中的應變可由於用以形成內部間隙壁的犧牲層的凹槽的不同厚度而不同。舉例而言，拉伸應變在nMOS組件中可比在pMOS組件中大。類似地，壓縮應變在pMOS組件中可比在nMOS組件中大。在又另一個實施例中，nMOS組件可具有拉伸通道應變，且pMOS組件可具有中性或壓縮通道應變。
圖1描繪根據本文中所揭露的標的物的用以形成具有變化的通道應變的奈米尺度半導體裝置的方法100的一個實施例的流程圖。在一實施例中，方法100可包含形成半導體裝置的hNS堆疊，其中hNS堆疊包含至少一個通道層及至少一個犧牲層，如在區塊101處所指示。在區塊102處，可圖案化及蝕刻hNS堆疊以界定hNS裝置的寬度（意即，如沿著如在圖2A至圖6B中描繪之進入紙面的j軸所量測）。在區塊103處，可在經圖案化hNS堆疊上形成虛設閘極結構。另外，在區塊104處，可在鄰近於閘極結構的一或多個區中移除hNS堆疊的一部分，以形成一或多個源極及/或汲極空腔。在區塊105處，可選擇性地蝕刻hNS堆疊的犧牲層的一部分以在犧牲層中形成凹槽，其中凹槽的深度可界定hNS結構的應變參數。另外，在區塊106處，可將間隙壁材料沈積於凹槽中，藉此在犧牲層為凹入式的區中形成間隙壁（在本文中被稱作「內部間隙壁」）。方法100可併入於hNS或hNW裝置的製造流程中，且因而可在額外操作及/或程序之前及/或之後。舉例而言，可用以完成hNS裝置的製造的操作及/或程序可包含再生源極-汲極區及替換閘極程序。在替換閘極程序期間，可自通道層選擇性地移除保留在結構中的犧牲層的部分。儘管在所述方法中描述對於本文中所揭露的標的物切合的關鍵操作，但在所揭露操作之間可使用如適於製造hNS裝置的額外操作及/或程序。
應理解，圖1中所描繪的方法的詳細實施可視方法是用以形成pMOS組件還是nMOS組件且視是形成hNW還是hNS而變化。設計特定處理參數及材料可視待形成的半導體裝置的特定應用及特性而變化。分別結合圖2A至圖6A針對nMOS裝置及圖2B至圖6B針對pMOS裝置描述方法100的其他實施例。應理解，產生圖2A至圖6B中所描繪的結構的某些操作可針對nMOS組件及pMOS組件兩者同時執行，而其他操作可針對nMOS組件及針對pMOS組件單獨地執行。實際上，通常獨立於pMOS組件的處理流程而執行nMOS組件的處理流程的一些操作，這是因為用以製造nMOS組件的材料及處理參數可能不同於用於製造pMOS組件的材料及處理參數。
圖2A及圖2B分別描繪根據本文中所揭露的標的物的在一個製造階段處的nMOS組件的hNS堆疊的實施例的剖面圖及pMOS組件的hNS堆疊的實施例的剖面圖。更具體言之，圖2A中所描繪的hNS堆疊的實施例表示可用以製造半導體裝置的nMOS組件的hNS堆疊。在一實施例中，圖2A的hNS堆疊可形成於基底或底層201上。在一實施例中，圖2A的hNS堆疊可包含多個犧牲層202、犧牲層206以及犧牲層210，以及穿插在多個犧牲層202、犧牲層206以及犧牲層210之間的多個通道層204及通道層208。犧牲層202、犧牲層206以及犧牲層210與通道層204及通道層208可以交替順序形成，其中犧牲層直接形成於基底或底層201上。如圖2A中所描繪，犧牲層202、犧牲層206以及犧牲層210與通道層204及通道層208各自實質上平行於由i軸及j軸形成的平面。犧牲層202、犧牲層206以及犧牲層210與通道層204及通道層208中的每一者具有在實質上平行於k軸的方向上所量測的厚度。在一個實施例中，犧牲層202、犧牲層206以及犧牲層210可由矽鍺（Si 1-x Ge x ）材料形成。在此類實施例中，通道層204及通道層208可由Si材料形成。應理解，儘管在圖2A中僅將三個犧牲層及兩個通道層描繪為形成nMOS組件的hNS堆疊，但根據本文中所揭露的標的物的hNS堆疊可包含比圖2A中所描繪的更多或更少的犧牲層及通道層。
圖2B中所描繪的hNS堆疊的實施例表示可用以製造半導體裝置的pMOS組件的hNS堆疊。在一實施例中，堆疊形成於基底或底層201上。在一實施例中，圖2B的hNS堆疊可包含多個犧牲層212、犧牲層216以及犧牲層220，以及穿插在多個犧牲層212、犧牲層216以及犧牲層220之間的多個通道層214及通道層218。犧牲層212、犧牲層216以及犧牲層220與通道層214及通道層218可以交替順序形成，其中犧牲層直接形成於基底或底層201上。如圖2B中所描繪，犧牲層212、犧牲層216以及犧牲層220與通道層214及通道層218各自實質上平行於由i軸及j軸形成的平面。犧牲層212、犧牲層216以及犧牲層220與通道層214及通道層218中的每一者具有在實質上平行於k軸的方向上所量測的厚度。在一個實施例中，犧牲層212、犧牲層216以及犧牲層220可由矽鍺（Si 1-y Ge y ）材料形成。在此類實施例中，通道層214及通道層218可由Si材料形成。應理解，儘管在圖2B中僅將三個犧牲層及兩個通道層描繪為形成pMOS組件的hNS堆疊，但根據本文中所揭露的標的物的hNS堆疊可包含比圖2B中所描繪的更多或更少的犧牲層及通道層。
在一些實施例中，可能僅存在一個堆疊沈積，意即，同一堆疊可經沈積用於nFET裝置及pFET裝置。在將矽鍺犧牲層用於nMOS hNS堆疊及pMOS hNS堆疊兩者的一些實施例中，可能存在多於一個堆疊沈積，以使得至少一些nFET裝置在犧牲層中具有與pFET裝置不同（意即，更大）的Ge含量。在此類實施例中，在製造流程中的不同步驟處遮蔽且執行堆疊沈積。在一些實施例中，形成圖2A的nFET堆疊及圖2B的pFET堆疊的材料可包含上文所描述的材料組成物，其中x可不同於y，且其中x可大於y。對x及y的選擇可在nFET裝置的通道中比在pFET裝置的通道中引起更大的拉伸應變。
在圖3A及圖3B中所描繪的製造階段處，閘極結構314a、314b、314c及閘極結構334a、334b、334c分別形成於nMOS組件的hNS堆疊及pMOS組件的hNS堆疊上方。在此類實施例中，閘極結構314a至閘極結構314c及閘極結構334a至閘極結構334c可為虛設閘極。圖3A中所描繪的第一組閘極結構314a至閘極結構314c可包含絕緣層302（諸如氧化物材料）、多晶矽層308以及罩蓋層312（諸如氮化Si材料）。閘極結構314a至閘極結構314c亦可包含間隙壁304。類似地，圖3B中所描繪的閘極結構334a至閘極結構334c可包含絕緣層322、多晶矽層328、罩蓋層332以及間隙壁324。
在一些實施例中，將相同程序應用於nFET裝置及pFET裝置。在其他實施例中，用於nFET的程序與用於pFET的程序可不同，且在製造期間在不同操作點處加以應用（意即，遮蔽另一類型的裝置）。在一些實施例中，必要時，間隙壁304的厚度與間隙壁324的厚度可在nFET或pFET中不同（例如，以匹配hNS堆疊中的內部間隙壁厚度）。
在圖4A及圖4B中所描繪的製造階段處，分別在鄰近於閘極結構314a至閘極結構314c及閘極結構334a至閘極結構334c的區中蝕刻空腔或凹槽402。意即，分別在k軸方向上蝕刻hNS堆疊以形成凹槽402。可在稍後製造操作中使用凹槽402形成源極/汲極區。在一些實施例中，凹槽402可到達基底或底層201。如圖4A及圖4B中可見，在i軸方向上量測hNS堆疊的通道長度。
在使用具有Si通道層及矽鍺犧牲層的hNS堆疊的實施例中，可在形成源極及汲極空腔或凹槽402期間在通道層中藉由犧牲層誘發拉伸應變。源極及汲極凹槽402的形成可引起堆疊的彈性鬆弛，此在通道層中引起拉伸應變。
在一實施例中，如圖5A及圖5B中所描繪，可在i軸方向上選擇性地回蝕nMOS組件的犧牲層202、犧牲層206以及犧牲層210與pMOS組件的犧牲層212、犧牲層216及犧牲層220，以在通道層之間的犧牲層中形成凹槽502。如在i軸方向上所量測的凹槽502的長度或深度可與通道層204、通道層208、通道層214以及通道層218在i軸方向上的長度與相對應的經蝕刻犧牲層202、經蝕刻犧牲層206、經蝕刻犧牲層210、經蝕刻犧牲層212、經蝕刻犧牲層216以及經蝕刻犧牲層220在i軸方向上的長度的差相關。在一實施例中，圖5A的nMOS組件中的凹槽502沿著i軸方向的長度或深度504可小於圖5B的pMOS組件中的凹槽502沿著i軸方向的長度或深度506。
可在nFET裝置及pFET裝置的流程的不同操作處執行用於內部間隙壁形成的犧牲層凹槽502。pMOS組件的犧牲層凹槽502的較長長度或深度506可有助於部分地釋放pFET組件的通道中的非所要拉伸應變。nMOS組件的犧牲層凹槽502的減小的長度或深度504可引起對nFET組件的通道中的拉伸應變的相對較小釋放，從而使得nFET組件具有比pFET組件高的拉伸應變。
圖6A及圖6B分別描繪根據本文中所揭露的標的物的在內部間隙壁已形成於凹槽502中之後的nMOS組件的hNS堆疊的實施例的剖面圖及pMOS組件的hNS堆疊的實施例的剖面圖。在圖6A中，nMOS間隙壁602可形成為在凹槽502中具有如在i軸方向上所量測的第一厚度（或「長度」）604。類似地，在圖6B中描繪pMOS間隙壁612，其具有如在i軸方向上所量測的大於nMOS間隙壁602的第一厚度604的第二厚度（或「長度」）606。在一個實施例中，藉由回蝕nMOS間隙壁602，間隙壁的厚度604可小於凹槽的深度504。類似地，pMOS間隙壁612可比凹槽502薄。在不執行間隙壁凹槽的實施例中，nMOS間隙壁的厚度604可實質上等於nMOS犧牲層凹槽的深度504，且pMOS間隙壁的厚度606可實質上等於pMOS犧牲層凹槽的深度506。
在所描述的實施例中，裝置的拉伸應變或壓縮應變可分別由犧牲層的Ge含量與nMOS凹槽的深度504及pMOS凹槽的深度506的組合調整或預定義。在一實施例中，犧牲層中的Ge含量在nFET裝置中可比在pFET裝置中高至少5%。在一實施例中，深度504與深度506的差可在約1 nm至約5 nm的範圍內。
在所描述的操作之後，用以製造hNS裝置的製造流程如所已知地繼續。後續操作包含在源極空腔及汲極空腔內形成源極結構及汲極結構。此可在一些實施例中藉由源極空腔及汲極空腔內的源極及汲極的磊晶再生而得以實現，且在一些實施例中藉由超出此等空腔的源極結構及汲極結構的過度生長而得以實現。在一些實施例中，源極結構及汲極結構可生長鬆弛，以使得在源極及汲極生長期間可不改變通道中的應變。在其他實施例中，當在通道中添加應變有利於特定裝置時，源極及汲極再生可經設計以在通道中添加應變。
製造流程可包含後續操作中的替換閘極程序，在此期間可自通道層選擇性地移除犧牲層（所謂的「奈米片釋放」程序）。在奈米片釋放程序期間，通道中的應變中的一小部分應變可能由於源極結構及汲極結構的重佈而丟失，但維持通道應變中的一大部分通道應變。奈米片釋放之後可圍繞通道層形成閘極堆疊。可包含額外製造步驟以完成hNS裝置及電路的製造。
圖7描繪根據本文中所揭露的標的物的包含hNS堆疊的實施例的電子系統700的方塊圖。參考圖7，電子系統700可包含控制器710、輸入/輸出（input/output；I/O）裝置704、記憶體裝置706、介面708以及匯流排702。控制器710、I/O裝置704、記憶體裝置706以及/或介面708可藉由匯流排702彼此連接。匯流排702可作為用於傳輸資料的路徑。
控制器710可包含微處理器、數位訊號處理器、微控制器、以及能夠執行與微處理器、數位訊號處理器以及微控制器的彼等功能類似的功能的邏輯裝置中的至少一者。I/O裝置704可包含小鍵盤、鍵盤以及顯示裝置。記憶體裝置706可儲存資料及/或命令。介面708可用以將資料傳輸至通訊網路或自通訊網路接收資料。介面708可為有線或無線介面。在一實例中，介面708可包含天線或有線或無線收發器。
儘管未在圖示中說明，但電子系統700可為用於改良控制器710的操作的操作記憶體，且亦可包含高速動態隨機存取記憶體（Dynamic Random Access Memory；DRAM）或靜態隨機存取記憶體（Static Random Access Memory；SRAM）。在此處，根據本發明概念的上述實施例的半導體裝置中的任一者可用作操作記憶體。此外，根據上述實施例的半導體裝置中的任一者可提供於記憶體裝置706中、介面708中、控制器710中或I/O裝置704中。
電子系統700可應用於能夠在無線環境中傳輸或接收資訊的幾乎所有類型的電子產品，諸如個人資料助理（personal data assistant；PDA）、攜帶型電腦、網路平板電腦、無線電話、行動電話、數位音樂播放器、記憶卡等。
儘管在本文中參考特定實施例描述本文中所揭露的標的物，但可在不背離申請專利範圍的範疇的情況下進行各種修改及改變，如下文所闡述。因此，應將本說明書及諸圖視為說明性而非限制性意義，且所有此等修改意欲包含於所主張標的物的範疇內。並不意欲將本文中關於特定實施例所描述的任何益處、優點或問題的解決方案理解為任何或所有申請專利範圍的關鍵、所需或基本特徵或元件。
除非另外說明，否則諸如「第一」及「第二」的術語用以任意地區分開此等術語描述的元件。因此，此等術語未必意欲指示此等元件的時間或其他優先排序。術語「耦接」或「以可操作方式耦接」定義為連接，但不必直接連接且不必以機械方式連接。除非另外說明，否則術語「一（a/an）」定義為一或多個。術語「包括（comprise）」（及包括的任何形式，諸如「包括（comprises」及「包括（comprising）」）、「具有（have）」（及具有的任何形式，諸如「具有（has」及「具有（having）」）、「包含（include）」（及包含的任何形式，諸如「包含（includes」及「包含（including）」）以及「含有（contain）」（及含有的任何形式，諸如「含有（contains）」及「含有（containing）」）為開放式連系動詞。結果，「包括」、「具有」、「包含」或「含有」一或多個元件的系統、裝置或設備擁有彼等一或多個元件，但不限於僅擁有彼等一或多個元件。類似地，「包括」、「具有」、「包含」或「含有」一或多個操作的方法或程序擁有彼等一或多個操作，但不限於僅擁有彼等一或多個操作。
100‧‧‧方法
101、102、103、104、105、106‧‧‧區塊
201‧‧‧底層
202、206、210、212、216、220‧‧‧犧牲層
204、208、214、218‧‧‧通道層
302、322‧‧‧絕緣層
304、324‧‧‧間隙壁
308、328‧‧‧多晶矽層
312、332‧‧‧罩蓋層
314a、314b、314c、334a、334b、334c‧‧‧閘極結構
402‧‧‧凹槽
502‧‧‧凹槽
504、506‧‧‧深度
602‧‧‧間隙壁
604‧‧‧厚度
606‧‧‧厚度
612‧‧‧間隙壁
700‧‧‧電子系統
702‧‧‧匯流排
704‧‧‧輸入/輸出（I/O）裝置
706‧‧‧記憶體裝置
708‧‧‧介面
710‧‧‧控制器
i‧‧‧軸
j‧‧‧軸
k‧‧‧軸
圖1描繪根據本文中所揭露的標的物的用以形成具有變化的通道應變的奈米尺度半導體裝置的方法的一個實施例的流程圖。 圖2A及圖2B分別描繪根據本文中所揭露的標的物的在一個製造階段處的nMOS組件的hNS堆疊的實施例的剖面圖及pMOS組件的hNS堆疊的實施例的剖面圖。 圖3A及圖3B分別描繪根據本文中所揭露的標的物的在另一製造階段處的nMOS組件的hNS堆疊的實施例的剖面圖及pMOS組件的hNS堆疊的實施例的剖面圖。 圖4A及圖4B分別描繪根據本文中所揭露的標的物的在又一製造階段處的nMOS組件的hNS堆疊的實施例的剖面圖及pMOS組件的hNS堆疊的實施例的剖面圖。 圖5A及圖5B分別描繪根據本文中所揭露的標的物的在另一製造階段處的nMOS組件的hNS堆疊的實施例的剖面圖及pMOS組件的hNS堆疊的實施例的剖面圖。 圖6A及圖6B分別描繪根據本文中所揭露的標的物的在又另一製造階段處的nMOS組件的hNS堆疊的實施例的剖面圖及pMOS組件的hNS堆疊的實施例的剖面圖。 圖7描繪根據本文中所揭露的標的物的包含hNS堆疊的實施例的電子系統的方塊圖。
201‧‧‧底層
202、206、210‧‧‧犧牲層
204、208‧‧‧通道層
302‧‧‧絕緣層
304‧‧‧間隙壁
308‧‧‧多晶矽層
312‧‧‧罩蓋層
314a、314b、314c‧‧‧閘極結構
602‧‧‧間隙壁
604‧‧‧厚度
i‧‧‧軸
j‧‧‧軸
k‧‧‧軸

Claims (20)

  1. 一種半導體裝置，其包括： n通道組件，其包括第一水平奈米片堆疊及第一源極/汲極結構，所述第一水平奈米片堆疊在底層上包括具有多個第一閘極層及至少一個第一通道層的第一閘極結構，所述多個第一閘極層中的一者與所述底層接觸，所述至少一個第一通道層中的每一者與所述多個第一閘極層中的至少一者接觸，所述第一源極/汲極結構安置於由所述第一水平奈米片堆疊形成的通道長度的一個末端處，第一內部間隙壁安置於所述多個所述第一閘極層中的至少一者與所述第一源極/汲極結構之間，所述第一內部間隙壁包括第一長度；以及 p通道組件，其包括第二水平奈米片堆疊及第二源極/汲極結構，所述第二水平奈米片堆疊在所述底層上包括具有多個第二閘極層及至少一個第二通道層的第二閘極結構，所述多個第二閘極層中的一者與所述底層接觸，所述至少一個第二通道層中的每一者與所述多個第二閘極層中的至少一者接觸，所述第二源極/汲極結構安置於由所述第二水平奈米片堆疊形成的通道長度的一個末端處，第二內部間隙壁安置於所述多個第二閘極層中的至少一者與所述第二源極/汲極結構之間，所述第二內部間隙壁包括大於所述第一長度的第二長度。
  2. 如申請專利範圍第1項所述的半導體裝置，其中所述第一長度比所述第二長度小約2 nm至約5 nm。
  3. 如申請專利範圍第1項所述的半導體裝置，其中所述至少一個第一通道層中的每一者中的應變包括拉伸應變，且 其中所述至少一個第二通道層中的每一者中的應變包括中性應變或壓縮應變。
  4. 如申請專利範圍第1項所述的半導體裝置，其中所述至少一個第二通道層中的每一者中的拉伸應變小於所述至少一個第一通道層中的每一者中的拉伸應變。
  5. 一種用以形成半導體裝置的方法，所述方法包括： 形成n通道組件的第一水平奈米片堆疊，所述第一水平奈米片堆疊在底層上包括多個第一犧牲層及至少一個第一通道層，所述多個第一犧牲層中的至少一者與所述底層接觸，所述至少一個第一通道層中的每一者與所述多個第一犧牲層中的至少另一者接觸，所述多個第一犧牲層由SiGe形成，且所述至少一個第一通道層由Si形成； 形成p通道組件的第二水平奈米片堆疊，所述第二水平奈米片堆疊在所述底層上包括多個第二犧牲層及至少一個第二通道層，所述多個第二犧牲層中的至少一者與所述底層接觸，所述至少一個第二通道層中的每一者與所述多個第二犧牲層中的至少另一者接觸，所述多個第二犧牲層由SiGe形成，且所述至少一個第二通道層由Si形成； 形成第一源極/汲極凹槽及第二源極/汲極凹槽，所述第一源極/汲極凹槽安置於由所述第一水平奈米片堆疊形成的通道的末端處，且所述第二源極/汲極凹槽安置於由所述第二水平奈米片堆疊形成的通道的末端處； 在所述多個第一犧牲層中的一者與所述至少一個第一通道層中的一者之間，在所述第一源極/汲極凹槽中的至少一者內形成第一內部間隙壁凹槽，所述第一內部間隙壁凹槽包括第一長度；以及 在所述多個第二犧牲層中的一者與所述至少一個第二通道層中的一者之間，在所述第二源極/汲極凹槽中的至少一者內形成第二內部間隙壁凹槽，所述第二內部間隙壁凹槽包括大於所述第一長度的第二長度。
  6. 如申請專利範圍第5項所述的用以形成半導體裝置的方法，其進一步包括： 在所述第一內部間隙壁凹槽中形成第一內部間隙壁；以及 在所述第二內部間隙壁凹槽中形成第二內部間隙壁。
  7. 如申請專利範圍第6項所述的用以形成半導體裝置的方法，其進一步包括： 用第一閘極結構替換所述多個第一犧牲層；以及 用第二閘極結構替換所述多個第二犧牲層。
  8. 如申請專利範圍第7項所述的用以形成半導體裝置的方法，其中所述至少一個第一通道層中的每一者中的應變包括拉伸應變，且 其中所述至少一個第二通道層中的每一者中的應變包括中性應變或壓縮應變。
  9. 如申請專利範圍第7項所述的用以形成半導體裝置的方法，其中所述至少一個第二通道層中的每一者中的拉伸應變小於所述至少一個第一通道層中的每一者的拉伸應變。
  10. 如申請專利範圍第5項所述的用以形成半導體裝置的方法，其中所述第一長度比所述第二長度小約2 nm至約5 nm。
  11. 如申請專利範圍第10項所述的用以形成半導體裝置的方法，其中所述多個第一犧牲層的Ge含量百分比大於或等於所述多個第二犧牲層的Ge含量百分比。
  12. 如申請專利範圍第11項所述的用以形成半導體裝置的方法，其中所述第一犧牲層的所述Ge含量百分比比所述第二犧牲層的所述Ge含量百分比大至少5%。
  13. 一種用以形成半導體裝置的方法，所述方法包括： 形成n通道組件的第一水平奈米片堆疊，所述第一水平奈米片堆疊在底層上包括多個第一犧牲層及至少一個第一通道層，所述多個第一犧牲層中的一者與所述底層接觸，所述至少一個第一通道層中的每一者與所述多個第一犧牲層中的至少另一者接觸，所述多個第一犧牲層由SiGe形成，且所述至少一個第一通道層由Si形成，所述多個第一犧牲層中的每一者包括第一Ge含量百分比； 形成p通道組件的第二水平奈米片堆疊，所述第二水平奈米片堆疊在所述底層上包括多個第二犧牲層及至少一個第二通道層，所述多個第二犧牲層中的一者與所述底層接觸，所述至少一個第二通道層中的每一者與所述多個第二犧牲層中的至少另一者接觸，所述多個第二犧牲層由SiGe形成，且所述至少一個第二通道層由Si形成；所述多個第二犧牲層中的每一者包括第二Ge含量百分比，所述第二Ge含量百分比小於或等於所述第一Ge含量百分比； 形成第一源極/汲極凹槽及第二源極/汲極凹槽，所述第一源極/汲極凹槽安置於由所述第一水平奈米片堆疊形成的通道的末端處，且所述第二源極/汲極凹槽安置於由所述第二水平奈米片堆疊形成的通道的末端處； 在所述第一犧牲層與所述第一通道層之間，在所述第一源極/汲極凹槽中的至少一者內形成至少一個第一內部間隙壁凹槽；以及 在所述第二犧牲層與所述第二通道層之間，在所述第二源極/汲極凹槽中的至少一者內形成至少一個第二內部間隙壁凹槽。
  14. 如申請專利範圍第13項所述的用以形成半導體裝置的方法，其進一步包括： 在所述第一內部間隙壁凹槽中形成第一內部間隙壁；以及 在所述第二內部間隙壁凹槽中形成第二內部間隙壁。
  15. 如申請專利範圍第14項所述的用以形成半導體裝置的方法，其進一步包括： 用第一閘極結構替換所述多個第一犧牲層；以及 用第二閘極結構替換所述多個第二犧牲層。
  16. 如申請專利範圍第13項所述的用以形成半導體裝置的方法，其中所述第一犧牲層的所述第一Ge含量百分比比所述第二犧牲層的所述第二Ge含量百分比大至少約5%。
  17. 如申請專利範圍第16項所述的用以形成半導體裝置的方法，其中所述第一內部間隙壁凹槽的第一長度比所述第二內部間隙壁凹槽的第二長度小約2 nm至約5 nm。
  18. 如申請專利範圍第13項所述的用以形成半導體裝置的方法，其中所述第一內部間隙壁凹槽的第一長度比所述第二內部間隙壁凹槽的第二長度小約2 nm至約5 nm。
  19. 如申請專利範圍第13項所述的用以形成半導體裝置的方法，其中所述第一通道層中的每一者中的應變包括拉伸應變，且 其中所述第二通道層中的每一者中的應變包括中性應變或壓縮應變。
  20. 如申請專利範圍第13項所述的用以形成半導體裝置的方法，其中所述第二通道層中的每一者中的拉伸應變小於所述第一通道層中的每一者中的拉伸應變。
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US20170263704A1 (en) 2017-09-14
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