TW201802973A - Sheet for producing three-dimensional integrated laminated circuit and method for producing three-dimensional integrated laminated circuit - Google Patents

Sheet for producing three-dimensional integrated laminated circuit and method for producing three-dimensional integrated laminated circuit Download PDF

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TW201802973A
TW201802973A TW106105694A TW106105694A TW201802973A TW 201802973 A TW201802973 A TW 201802973A TW 106105694 A TW106105694 A TW 106105694A TW 106105694 A TW106105694 A TW 106105694A TW 201802973 A TW201802973 A TW 201802973A
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adhesive layer
layer
dimensional
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circuit manufacturing
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TWI722115B (en
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根津裕介
杉野貴志
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琳得科股份有限公司
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    • CCHEMISTRY; METALLURGY
    • C09DYES; PAINTS; POLISHES; NATURAL RESINS; ADHESIVES; COMPOSITIONS NOT OTHERWISE PROVIDED FOR; APPLICATIONS OF MATERIALS NOT OTHERWISE PROVIDED FOR
    • C09JADHESIVES; NON-MECHANICAL ASPECTS OF ADHESIVE PROCESSES IN GENERAL; ADHESIVE PROCESSES NOT PROVIDED FOR ELSEWHERE; USE OF MATERIALS AS ADHESIVES
    • C09J5/00Adhesive processes in general; Adhesive processes not provided for elsewhere, e.g. relating to primers
    • CCHEMISTRY; METALLURGY
    • C09DYES; PAINTS; POLISHES; NATURAL RESINS; ADHESIVES; COMPOSITIONS NOT OTHERWISE PROVIDED FOR; APPLICATIONS OF MATERIALS NOT OTHERWISE PROVIDED FOR
    • C09JADHESIVES; NON-MECHANICAL ASPECTS OF ADHESIVE PROCESSES IN GENERAL; ADHESIVE PROCESSES NOT PROVIDED FOR ELSEWHERE; USE OF MATERIALS AS ADHESIVES
    • C09J11/00Features of adhesives not provided for in group C09J9/00, e.g. additives
    • C09J11/02Non-macromolecular additives
    • C09J11/04Non-macromolecular additives inorganic
    • CCHEMISTRY; METALLURGY
    • C09DYES; PAINTS; POLISHES; NATURAL RESINS; ADHESIVES; COMPOSITIONS NOT OTHERWISE PROVIDED FOR; APPLICATIONS OF MATERIALS NOT OTHERWISE PROVIDED FOR
    • C09JADHESIVES; NON-MECHANICAL ASPECTS OF ADHESIVE PROCESSES IN GENERAL; ADHESIVE PROCESSES NOT PROVIDED FOR ELSEWHERE; USE OF MATERIALS AS ADHESIVES
    • C09J201/00Adhesives based on unspecified macromolecular compounds
    • CCHEMISTRY; METALLURGY
    • C09DYES; PAINTS; POLISHES; NATURAL RESINS; ADHESIVES; COMPOSITIONS NOT OTHERWISE PROVIDED FOR; APPLICATIONS OF MATERIALS NOT OTHERWISE PROVIDED FOR
    • C09JADHESIVES; NON-MECHANICAL ASPECTS OF ADHESIVE PROCESSES IN GENERAL; ADHESIVE PROCESSES NOT PROVIDED FOR ELSEWHERE; USE OF MATERIALS AS ADHESIVES
    • C09J7/00Adhesives in the form of films or foils
    • C09J7/20Adhesives in the form of films or foils characterised by their carriers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/34Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367Cooling facilitated by shape of device
    • H01L23/3672Foil-like cooling fins or heat sinks
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/27Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • CCHEMISTRY; METALLURGY
    • C09DYES; PAINTS; POLISHES; NATURAL RESINS; ADHESIVES; COMPOSITIONS NOT OTHERWISE PROVIDED FOR; APPLICATIONS OF MATERIALS NOT OTHERWISE PROVIDED FOR
    • C09JADHESIVES; NON-MECHANICAL ASPECTS OF ADHESIVE PROCESSES IN GENERAL; ADHESIVE PROCESSES NOT PROVIDED FOR ELSEWHERE; USE OF MATERIALS AS ADHESIVES
    • C09J2203/00Applications of adhesives in processes or use of adhesives in the form of films or foils
    • C09J2203/326Applications of adhesives in processes or use of adhesives in the form of films or foils for bonding electronic components such as wafers, chips or semiconductors
    • CCHEMISTRY; METALLURGY
    • C09DYES; PAINTS; POLISHES; NATURAL RESINS; ADHESIVES; COMPOSITIONS NOT OTHERWISE PROVIDED FOR; APPLICATIONS OF MATERIALS NOT OTHERWISE PROVIDED FOR
    • C09JADHESIVES; NON-MECHANICAL ASPECTS OF ADHESIVE PROCESSES IN GENERAL; ADHESIVE PROCESSES NOT PROVIDED FOR ELSEWHERE; USE OF MATERIALS AS ADHESIVES
    • C09J2301/00Additional features of adhesives in the form of films or foils
    • C09J2301/30Additional features of adhesives in the form of films or foils characterized by the chemical, physicochemical or physical properties of the adhesive or the carrier
    • C09J2301/312Additional features of adhesives in the form of films or foils characterized by the chemical, physicochemical or physical properties of the adhesive or the carrier parameters being the characterizing feature

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Organic Chemistry (AREA)
  • Manufacturing & Machinery (AREA)
  • Inorganic Chemistry (AREA)
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  • Adhesives Or Adhesive Processes (AREA)
  • Adhesive Tapes (AREA)

Abstract

This sheet 1 for producing a three-dimensional integrated laminated circuit, which is interposed between a plurality of semiconductor chips having through-electrodes and is used to adhere the semiconductor chips to each other and obtain a three-dimensional integrated laminated circuit, is provided with at least a curable adhesive layer 13, wherein the adhesive layer 13 includes a thermally conductive filler and the standard deviation of the thickness (T2) of the adhesive layer 13 is 2.0 [mu]m or less. This sheet 1 for producing a three-dimensional integrated laminated circuit can be used to produce a three-dimensional integrated laminated circuit having excellent heat dissipation properties.

Description

三次元積體積層電路製造用板片以及三次元積體積層電路之製造方法 Plate for manufacturing three-dimensional product volume layer circuit and method for manufacturing three-dimensional product volume layer circuit

本發明係有關於一種適合於製造三次元積體積層電路之板片、及使用該板片之三次元積體積層電路之製造方法。 The present invention relates to a plate suitable for manufacturing a three-dimensional bulk-layer circuit and a method for manufacturing a three-dimensional bulk-layer circuit using the same.

近年來,從電子電路的大容量化、高功能化的觀點而言,將複數個半導體晶片立體地層積而成之三次元積體積層電路(以下有稱為「積層電路」之情形)的開發係進展中。在此種積層電路,為了小型化.高功能化,係使用具有從電路形成面起貫穿至其相反面的貫穿電極(TSV)之半導體晶片。此時,被層積的半導體晶片之間,係藉由各自所具備的貫穿電極(或設置在貫穿電極的端部之凸塊)彼此的接觸而被電性連接。 In recent years, from the viewpoint of increasing the capacity and function of electronic circuits, the development of a three-dimensional multi-layer volume layer circuit (hereinafter referred to as a "multi-layer circuit") in which a plurality of semiconductor wafers are three-dimensionally laminated is developed. Department in progress. In this kind of multilayer circuit, in order to miniaturize. It is highly functional and uses a semiconductor wafer having a through electrode (TSV) penetrating from the circuit formation surface to the opposite surface. At this time, the stacked semiconductor wafers are electrically connected by contact between the through-electrodes (or bumps provided at the ends of the through-electrodes) provided in each of them.

製造此種積層電路時,為了確保上述的電性連接及機械強度,係使用樹脂組成物將貫穿電極彼此電性連接,且同時將半導體晶片彼此接著。例如,特許文獻1係提案揭示一種方法,其係使通常被稱為非導電性膜(Non-Conductive Film,NCF)之膜狀接著劑介於半導體晶片之間,而將半導體晶片彼此接著之方法。 When manufacturing such a laminated circuit, in order to ensure the above-mentioned electrical connection and mechanical strength, a resin composition is used to electrically connect the through electrodes to each other, and at the same time, the semiconductor wafers are bonded to each other. For example, Patent Document 1 proposes a method in which a film-shaped adhesive, commonly referred to as a non-conductive film (NCF), is interposed between semiconductor wafers, and the semiconductor wafers are adhered to each other. .

然而,在上述的積層電路,因為將複數個半導體 晶片層積,所以使電流流動於電路時非常容易發熱。積層電路的發熱,會引起演算處理能力低落或錯誤操作,而成為積層電路性能低落的原因。又,積層電路過度地發熱時,積層電路亦有產生變形、破損或故障之情形。因此,上述的積層電路被要求具有較高的放熱性,以確保可靠性。 However, in the above-mentioned multilayer circuit, since a plurality of semiconductors The wafers are laminated, so it is very easy to generate heat when a current flows through the circuit. The heat generation of the multilayer circuit may cause a decrease in the calculation processing capability or an erroneous operation, which may cause the performance of the multilayer circuit to be deteriorated. In addition, when the laminated circuit generates excessive heat, the laminated circuit may be deformed, damaged, or malfunctioned. Therefore, the above-mentioned laminated circuit is required to have high heat dissipation to ensure reliability.

[先前技術文獻] [Prior technical literature] [專利文獻] [Patent Literature]

[專利文獻1]日本特開2010-010368號公報 [Patent Document 1] Japanese Patent Laid-Open No. 2010-010368

但是,在使用先前的接著劑而製造的積層電路,有未必能夠達成良好的放熱性之問題。 However, in a multilayer circuit manufactured using a conventional adhesive, there is a problem that it is not always possible to achieve good heat dissipation.

本發明係鑒於此種實際情況而進行,其目的係提供一種能夠製造具有優異的放熱性之三次元積體積層電路製造用板片。又,本發明之目的,係提供此種三次元集積體積層電路之製造方法。 The present invention has been made in view of such an actual situation, and an object thereof is to provide a plate for manufacturing a three-dimensional bulk volume circuit having excellent heat release properties. Another object of the present invention is to provide a method for manufacturing such a three-dimensional integrated volume layer circuit.

為了達成上述目的,本發明第1係提供一種三次元積體積層電路製造用板片,其係介於具有貫穿電極的複數個半導體晶片之間,為了將前述複數個半導體晶片相互接著而成為三次元積體積層電路所使用之三次元積體積層電路製造用板片,其特徵在於:前述三次元積體積層電路製造用板片係至少具備硬化性的接著劑層,前述接著劑層係含有熱傳導性填料,且前述接著劑層的厚度(T2)之標準偏差為2.0μm以下(發明 1)。 In order to achieve the above object, the first system of the present invention provides a three-dimensional bulk-layer circuit manufacturing plate, which is interposed between a plurality of semiconductor wafers having a through electrode, and the three semiconductor wafers are bonded to each other to form a three-dimensional circuit. The three-dimensional bulk-layer circuit manufacturing plate used for the three-dimensional bulk-layer circuit is characterized in that the above-mentioned three-dimensional bulk-layer circuit manufacturing plate has at least a hardenable adhesive layer, and the adhesive layer contains Thermally conductive filler, and the standard deviation of the thickness (T2) of the adhesive layer is 2.0 μm or less (invention 1).

上述發明(發明1)之三次元積體積層電路製造用板片,因為接著劑層包含具有較高的熱傳導性之熱傳導性填料,且接著劑層的厚度(T2)之標準偏差為上述範圍,使用該板片而製造的積層電路係成為放熱優異性者。因此,藉由使用上述發明(發明1)之三次元積體積層電路製造用板片,能夠製造具有較高的可靠性之積層電路。 In the above-mentioned invention (Invention 1), the sheet for manufacturing a three-dimensional bulk-layer circuit is because the adhesive layer contains a thermally conductive filler having high thermal conductivity, and the standard deviation of the thickness (T2) of the adhesive layer is in the above range. The multilayer circuit system manufactured using this plate is excellent in heat radiation. Therefore, by using the plate for manufacturing a three-dimensional multilayer volume circuit of the above invention (Invention 1), a multilayer circuit having high reliability can be manufactured.

在上述發明(發明1),前述熱傳導性填料,係以由選自金屬氧化物、碳化矽、碳化物、氮化物及金屬氫氧化物之材料所構成為佳(發明2)。 In the above invention (Invention 1), the thermally conductive filler is preferably composed of a material selected from a metal oxide, silicon carbide, carbide, nitride, and metal hydroxide (Invention 2).

在上述發明(發明1、2),在前述接著劑層之前述熱傳導性填料的含量,係以35質量%以上、95質量%以下為佳(發明3)。 In the above invention (Inventions 1, 2), the content of the thermally conductive filler in the adhesive layer is preferably 35% by mass or more and 95% by mass or less (Invention 3).

在上述發明(發明1~3),前述熱傳導性填料在23之熱傳導率,係以10W/m.K以上為佳(發明4)。 In the above invention (Inventions 1 to 3), the thermal conductivity of the thermally conductive filler at 23 is 10 W / m. K or higher is preferred (Invention 4).

在上述發明(發明1~4),前述熱傳導性填料的平均粒徑,係以0.01μm以上、20μm以下為佳(發明5)。 In the above invention (Inventions 1 to 4), the average particle diameter of the thermally conductive filler is preferably 0.01 μm or more and 20 μm or less (Invention 5).

在上述發明(發明1~5),前述接著劑層硬化後的熱傳導率,係以0.5W/m.K以上、8.0W/m.K以下為佳(發明6)。 In the above invention (Inventions 1 to 5), the thermal conductivity of the adhesive layer after curing is 0.5 W / m. Above K, 8.0W / m. K is preferred (invention 6).

在上述發明(發明1~6),構成前述接著劑層之材料,係以含有熱硬化性成分、高分子量成分及硬化觸媒為佳(發明7)。 In the above inventions (Inventions 1 to 6), it is preferable that the material constituting the adhesive layer contains a thermosetting component, a high molecular weight component, and a curing catalyst (Invention 7).

在上述發明(發明1~7),前述高分子量成分的玻璃轉移溫度係以50℃以上為佳(發明8)。 In the above inventions (Inventions 1 to 7), the glass transition temperature of the high molecular weight component is preferably 50 ° C or higher (Invention 8).

在上述發明(發明1~8),構成前述接著劑層之材料係以含有助焊劑成分為佳(發明9)。 In the above inventions (Inventions 1 to 8), the material constituting the adhesive layer is preferably a flux-containing component (Invention 9).

在上述發明(發明1~9),前述接著劑層的厚度係以2μm以上、500μm以下為佳(發明10)。 In the above invention (Inventions 1 to 9), the thickness of the adhesive layer is preferably 2 μm or more and 500 μm or less (Invention 10).

在上述發明(發明1~10),前述三次元積體積層電路製造用板片,較佳是進一步具備:黏著劑層,其係層積在前述接著劑層的一面側;及基材,其係層積在前述黏著劑層之與前述接著劑層為相反的面側(發明11)。 In the above invention (Inventions 1 to 10), the plate for manufacturing a three-dimensional bulk volume circuit preferably further includes: an adhesive layer, which is laminated on one side of the adhesive layer; and a substrate, which The layer is laminated on the opposite side of the adhesive layer from the adhesive layer (Invention 11).

在上述發明(發明11),前述基材的厚度係以10μm以上、500μm以下為佳(發明12)。 In the above invention (Invention 11), the thickness of the substrate is preferably 10 μm or more and 500 μm or less (Invention 12).

在上述發明(發明11或12),前述接著劑層的厚度(T2)對前述基材的厚度(T1)之比(T2/T1),係以0.01以上、5.0以下為佳(發明13)。 In the above invention (Invention 11 or 12), the ratio (T2 / T1) of the thickness (T2) of the adhesive layer to the thickness (T1) of the substrate is preferably 0.01 or more and 5.0 or less (Invention 13).

在上述發明(發明10、11),前述黏著劑在23℃之儲存彈性模數,係以1×103Pa以上、1×109Pa以下為佳(發明14)。 In the above inventions (Inventions 10 and 11), the storage elastic modulus of the adhesive at 23 ° C is preferably 1 × 10 3 Pa or more and 1 × 10 9 Pa or less (Invention 14).

在上述發明(發明11~14),前述基材在23℃之拉伸彈性模數,係以100MPa以上、5000MPa以下為佳(發明15)。 In the above inventions (Inventions 11 to 14), the tensile elastic modulus of the substrate at 23 ° C is preferably 100 MPa or more and 5000 MPa or less (Invention 15).

本發明第2係提供一種三次元積體積層電路之製造方法,其特徵在於包含下列步驟:將前述三次元積體積層電路製造用板片(發明1~10)之前述接著劑層的一面或前述三次元積體積層電路製造用板片(發明11~15)之前述接著劑層之與前述黏著劑層為相反的面、與具備貫穿電極之半導體晶圓的至少一面貼合之步驟;將前述半導體晶圓與前述三次元積體積層電路製造用板片的前述接著劑層同時切割,而個片化成為附接 著劑層之半導體晶片之步驟;將經個片化之複數個前述附接著劑層之半導體晶片,以將前述貫穿電極彼此電性連接且將前述接著劑層與前述半導體晶片交替地配置之方式複數層層積,而得到半導體晶片積層體之步驟;及使在前述半導體晶片積層體之前述接著劑層硬化,而將構成前述半導體晶片積層體之前述半導體晶片彼此接著之步驟(發明16)。 The second aspect of the present invention provides a method for manufacturing a three-dimensional bulk-layer circuit, which includes the following steps: one side of the adhesive layer of the aforementioned three-dimensional bulk-layer circuit manufacturing plate (Inventions 1 to 10) or The step of bonding the adhesive layer on the opposite side of the adhesive layer to at least one side of the semiconductor wafer having a through electrode; The semiconductor wafer is cut simultaneously with the adhesive layer of the three-dimensional bulk-layer circuit manufacturing sheet, and the individual pieces are attached. A step of applying a semiconductor wafer with an adhesive layer; a method of electrically connecting the through electrodes to each other and alternately disposing the adhesive layer and the semiconductor wafer by singulating the plurality of semiconductor wafers with the adhesive layer A step of laminating a plurality of layers to obtain a semiconductor wafer laminate; and a step of hardening the adhesive layer on the semiconductor wafer laminate and adhering the semiconductor wafers constituting the semiconductor wafer laminate to each other (Invention 16).

使用本發明之三次元積體積層電路製造用板片時,能夠製造具有優異的放熱性之三次元積體積層電路。又,使用本發明的製造方法時,能夠製造此種三次元積體積層電路。 When the plate for manufacturing a three-dimensional bulk-layer circuit of the present invention is used, a three-dimensional bulk-layer circuit having excellent heat release properties can be manufactured. When the manufacturing method of the present invention is used, it is possible to manufacture such a three-dimensional product volume layer circuit.

1、2‧‧‧三次元積體積層電路製造用板片 1、2‧‧‧Three-dimensional multi-layer circuit board manufacturing

11‧‧‧基材 11‧‧‧ Substrate

12‧‧‧黏著劑層 12‧‧‧ Adhesive layer

13‧‧‧接著劑層 13‧‧‧ Adhesive layer

14‧‧‧剝離板片 14‧‧‧ peeling sheet

第1圖係本發明的第1實施形態之三次元積體積層電路製造用板片的剖面圖。 FIG. 1 is a cross-sectional view of a plate for manufacturing a three-dimensional multi-layer bulk-layer circuit according to the first embodiment of the present invention.

第2圖係本發明的第2實施形態之三次元積體積層電路製造用板片的剖面圖。 Fig. 2 is a cross-sectional view of a plate for manufacturing a three-dimensional multi-layer bulk circuit in a second embodiment of the present invention.

[用以實施發明之形態] [Forms for Implementing Invention]

以下,說明本發明的實施形態。 Hereinafter, embodiments of the present invention will be described.

[三次元積體積層電路製造用板片] [Three-dimensional product volume layer circuit manufacturing plate]

第1圖係顯示第1實施形態之三次元積體積層電路製造用板片1之剖面圖。如第1圖所顯示,本實施形態之三次元積體積層電路製造用板片1(以下有稱為「製造用板片1」之情形), 係具備接著劑層13、及層積在該接著劑層13的至少一面之剝離板片14。又,亦可將剝離板片14省略。 Fig. 1 is a cross-sectional view showing a plate 1 for manufacturing a three-dimensional multi-layer bulk-layer circuit of the first embodiment. As shown in FIG. 1, the plate 1 for manufacturing a three-dimensional bulk volume circuit of the present embodiment (hereinafter referred to as “manufacturing plate 1”), The adhesive layer 13 is provided with a release sheet 14 laminated on at least one side of the adhesive layer 13. The release sheet 14 may be omitted.

又,第2圖係顯示第2實施形態之三次元積體積層電路製造用板片2之剖面圖。如第2圖所顯示,本實施形態之三次元積體積層電路製造用板片2(以下,有稱為「製造用板片2」之情形),係具備基材11、層積在基材11的至少一面側之黏著劑層12、層積在黏著劑層12之與基材11為相反側之接著劑層13。又,在接著劑層13之與黏著劑層12為相反面,亦可層積剝離板片14。 Fig. 2 is a cross-sectional view showing a plate 2 for manufacturing a three-dimensional multi-layered bulk circuit of the second embodiment. As shown in FIG. 2, the plate 2 for manufacturing a three-dimensional multilayer volume circuit for the present embodiment (hereinafter, referred to as a “manufacturing plate 2”) is provided with a base material 11 and laminated on the base material. An adhesive layer 12 on at least one side of 11 and an adhesive layer 13 laminated on the adhesive layer 12 on the side opposite to the substrate 11. In addition, the release sheet 14 may be laminated on the surface of the adhesive layer 13 opposite to the adhesive layer 12.

在本實施形態之三次元積體積層電路製造用板片1、2,接著劑層13含有具有高熱傳導率之熱傳導性填料。又,在本實施形態之三次元積體積層電路製造用板片1、2,接著劑層13的厚度(T2)之標準偏差為2.0μm以下。 In the three-dimensional multi-layer bulk-layer circuit manufacturing plates 1 and 2 of this embodiment, the adhesive layer 13 contains a thermally conductive filler having a high thermal conductivity. In addition, in the three-dimensional multi-layer bulk-layer circuit manufacturing plates 1 and 2 of this embodiment, the standard deviation of the thickness (T2) of the adhesive layer 13 is 2.0 μm or less.

通常,因為積層電路係將複數個半導體晶片層積而成者,所以大量地含有成為熱源的電路,且同時具有不容易放熱之構造。因此,使電流在積層電路流動時,積層電路容易發熱,同時所產生的熱量不容易往外部逸散。 Generally, since a multilayer circuit is a laminate of a plurality of semiconductor wafers, it contains a large amount of circuits that serve as heat sources, and also has a structure that does not easily release heat. Therefore, when the current flows in the multilayer circuit, the multilayer circuit is liable to generate heat, and at the same time, the generated heat is not easily dissipated to the outside.

但是,在使用本實施形態之三次元積體積層電路製造用板片1、2而製造的積層電路,藉由含有熱傳導性填料而放熱性優異的接著劑層13將半導體晶片彼此接著,所以熱量容易從該接著劑層13端部放出。又,藉由接著劑層13的厚度(T2)之標準偏差為上述範圍,構成積層電路之接著劑13的厚度成為均勻,同時積層電路本身的厚度亦成為均勻,其結果,係成為在積層電路內熱傳導優異者。藉由以上,積層電路 全體的放熱性優異,而且即便使電流流動時,亦能夠抑制過度地變為高溫。其結果,能夠製造具有高可靠性之積層電路。 However, in the multilayer circuit manufactured using the three-dimensional multilayer bulk circuit circuit manufacturing plates 1 and 2 of this embodiment, the semiconductor wafers are bonded to each other by the adhesive layer 13 containing a thermally conductive filler and having excellent heat release properties, so the heat is It is easy to release from the end of this adhesive layer 13. In addition, since the standard deviation of the thickness (T2) of the adhesive layer 13 is in the above range, the thickness of the adhesive 13 constituting the multilayer circuit becomes uniform, and the thickness of the multilayer circuit itself becomes uniform. As a result, the multilayer circuit Excellent internal heat conduction. With the above, the laminated circuit The overall exothermic property is excellent, and it is possible to suppress excessive temperature rise even when a current is caused to flow. As a result, a laminated circuit having high reliability can be manufactured.

另一方面,積層電路係將複數個半導體晶片層積而成者,所以通常將積層電路製成均勻的厚度係困難的。這是因為即便構成積層電路之半導體晶片或接著劑層的厚度從所需要的厚度只有稍微的偏差,由於將半導體晶片及接著劑層層積,所以該偏移係被累積,其結果,成為使積層電路從所需要的厚度大幅偏移的重要原因之一。又,在將半導體晶圓的貫穿電極或凸塊埋入至接著劑層時有產生空隙之情形,由於該空隙,在積層電路之接著劑層的厚度有部分地產生變化之情形。特別是在積層電路,因為具有複數個可能產生空隙之半導體晶圓與接著劑層之界面,所以產生空隙之概率較高,使積層電路的厚度均勻係變得更加困難。但是,在本實施形態之三次元積體積層電路製造用板片1、2,藉由接著劑層13的厚度(T2)之標準偏差為上述範圍,而能夠抑制接著劑層13的厚度從所需要的厚度偏移,藉此,能夠將積層電路製成均勻的厚度。而且,藉由接著劑層13的厚度(T2)之標準偏差為上述範圍,將半導體晶圓的貫穿電極或凸塊埋入至接著劑層13時,能夠抑制產生空隙,而能夠良好地埋入,藉此,亦能夠將積層電路製成均勻的厚度。 On the other hand, since a multilayer circuit is a laminate of a plurality of semiconductor wafers, it is generally difficult to make the multilayer circuit a uniform thickness. This is because even if the thickness of the semiconductor wafer or the adhesive layer constituting the laminated circuit is slightly different from the required thickness, the semiconductor wafer and the adhesive layer are laminated, so the offset is accumulated, and as a result, One of the important reasons that the laminated circuit deviates greatly from the required thickness. In addition, when a through electrode or a bump of a semiconductor wafer is buried in an adhesive layer, a void may be generated. Due to the void, a thickness of an adhesive layer of a laminated circuit may be partially changed. Especially in the multilayer circuit, because there are interfaces between the semiconductor wafer and the adhesive layer that may generate voids, the probability of voids is high, making the thickness of the multilayer circuit even more difficult. However, in the three-dimensional bulk-layer circuit manufacturing plates 1 and 2 of this embodiment, the standard deviation of the thickness (T2) of the adhesive layer 13 is within the above range, and the thickness of the adhesive layer 13 can be suppressed from being changed. The required thickness is offset, whereby the laminated circuit can be made uniform in thickness. In addition, since the standard deviation of the thickness (T2) of the adhesive layer 13 is within the above range, when a through-electrode or bump of a semiconductor wafer is buried in the adhesive layer 13, generation of voids can be suppressed, and it can be embedded well. Therefore, the laminated circuit can also be made into a uniform thickness.

本實施形態之三次元積體積層電路製造用板片1、2,係介於具有貫穿電極之複數個半導體晶片之間,為了將該複數個半導體晶片相互接著成為三次元積體積層電路而使用。貫穿電極之一端或兩端亦可從半導體晶片的表面突出。 又,半導體晶片亦可進一步具備凸塊,此時,該凸塊亦可設置在貫穿電極的一端或兩端。 The plates 1 and 2 for manufacturing a three-dimensional bulk-layer circuit in this embodiment are interposed between a plurality of semiconductor wafers having a through electrode, and are used to connect the plurality of semiconductor wafers to each other to form a three-dimensional bulk-layer circuit. . One or both ends of the through electrode may also protrude from the surface of the semiconductor wafer. Further, the semiconductor wafer may further include a bump, and in this case, the bump may be provided at one end or both ends of the through electrode.

在本實施形態之三次元積體積層電路用板片1、2,接著劑層13係具有硬化性。在此,所謂具有硬化性,係指接著劑層13能夠藉由加熱等而硬化。亦即,接著劑層13係在構成製造用板片1、2之狀態為未硬化。接著劑層13可為熱硬化性,或是亦可為能量線硬化性。但是,從將製造用板片1、2使用在積層電路的製造方法時,能夠良好地進行硬化的觀點而言,接著劑層13係以熱硬化性為佳。具體而言,將製造用板片1、2使用在積層電路的製造方法時,係如後述,接著劑層13以被貼附在半導體晶圓之狀態被個片化。藉此,能夠得到半導體晶片與經個片化的接著劑層13之積層體。該積層體係其接著劑層13側的面為貼附在半導體晶片的積層體上,而在該狀態下進行接著劑層13的硬化。通常,半導體晶片係不具有對能量線之透射性,或是多半的情況該透射性為非常低,即便是此種情況,若接著劑層13具有熱硬化性,就能夠使接著劑層13迅速地硬化。 In the three-dimensional multi-layer circuit board 1 and 2 of this embodiment, the adhesive layer 13 is hardenable. Here, the term “having a hardening property” means that the adhesive layer 13 can be hardened by heating or the like. That is, the adhesive layer 13 is unhardened in the state which comprises the manufacturing plates 1 and 2. The adhesive layer 13 may be thermosetting or energy ray-curable. However, the adhesive layer 13 is preferably thermosetting because it can harden well when the manufacturing plates 1 and 2 are used in a laminated circuit manufacturing method. Specifically, when the manufacturing plates 1 and 2 are used in a manufacturing method of a laminated circuit, as described later, the adhesive layer 13 is singulated in a state where it is attached to a semiconductor wafer. Thereby, a laminated body of the semiconductor wafer and the individualized adhesive layer 13 can be obtained. In this multilayer system, the surface on the side of the adhesive layer 13 is a laminated body attached to a semiconductor wafer, and the adhesive layer 13 is hardened in this state. In general, semiconductor wafers do not have transmittance to energy rays, or in most cases, the transmittance is very low. Even in this case, if the adhesive layer 13 has thermosetting properties, the adhesive layer 13 can be quickly made. To harden.

1.接著劑層 Adhesive layer

(1)材料 (1) Materials

在本實施形態之三次元積體積層電路製造用板片1、2,構成接著劑層13之材料係含有熱傳導性填料。又,該材料係以進一步含有熱硬化性成分、硬化劑、硬化觸媒、高分子量成分、具有助焊劑功能之成分等為佳。 In the three-dimensional bulk-layer circuit manufacturing plates 1 and 2 of this embodiment, the material constituting the adhesive layer 13 contains a thermally conductive filler. In addition, it is preferable that the material further contain a thermosetting component, a curing agent, a curing catalyst, a high molecular weight component, a component having a flux function, and the like.

(1-1)熱傳導性填料 (1-1) Thermally conductive filler

構成接著劑層13之材料係含有熱傳導性填料。在此,所謂熱傳導性填料,係指具有較高的熱傳導率之填料,例如,係指在25℃之熱傳導率為10W/m.K以上的填料,係指較佳為20W/m.K以上的填料,係指特佳為30W/m.K以上的填料。又,熱傳導性填料在25℃的熱傳導率之上限值,係沒有限定,通常為300W/m.K以下。 The material constituting the adhesive layer 13 contains a thermally conductive filler. Here, the so-called thermally conductive filler means a filler having a high thermal conductivity, for example, a thermal conductivity of 10 W / m at 25 ° C. A filler of K or higher means preferably 20 W / m. Fillers above K refer to a particularly good 30 W / m. Fillers above K. The upper limit of the thermal conductivity of the thermally conductive filler at 25 ° C is not limited, but is usually 300 W / m. K or less.

如前述,接著劑層13含有熱傳導性填料時,藉由與積層電路具有均勻的厚度之相互作用,接著劑層13顯示優異的放熱性。又,藉由接著劑層13含有熱傳導性填料,在所得到的積層電路,其剛性變高之同時,不容易產生因環境變化引起的尺寸變化。 As described above, when the adhesive layer 13 contains a thermally conductive filler, the adhesive layer 13 exhibits excellent heat release properties by interacting with the laminated circuit with a uniform thickness. In addition, since the adhesive layer 13 contains a thermally conductive filler, the obtained laminated circuit has higher rigidity and is less likely to undergo dimensional changes due to environmental changes.

作為上述熱傳導性填料,係以使用選自由氧化鋅、氧化鎂、氧化鋁、氧化鈦、氧化鐵等的金屬氧化物、碳化矽、碳酸鈣等的碳化物、氮化硼、氮化鋁等的氮化物、氫氧化鎂等的金屬氫氧化物、及滑石之材料所構成之填料為佳。該等之中,從能夠達成更優異的放熱性的觀點而言,以使用選自由氧化鋅、氧化鎂、氧化鋁、氧化鈦、氧化鐵等的金屬氧化物、碳化矽、碳酸鈣等的碳化物、氮化硼、氮化鋁等的氮化物、及氫氧化鎂等的金屬氫氧化物之材料所構成之填料為佳。該等材料,可將其粉末使用作為填料,亦可使用球形化而成為珠粒狀者作為填料,或者亦可使用其單結晶纖維作為填料。從上述材料所得到的熱傳導性填料,係能夠單獨使用1種或組合2種以上而使用。又,熱傳導性填料係以不具有導電性為佳。 As the thermally conductive filler, a material selected from the group consisting of metal oxides such as zinc oxide, magnesium oxide, aluminum oxide, titanium oxide, and iron oxide, carbides such as silicon carbide, calcium carbonate, boron nitride, and aluminum nitride is used. Fillers composed of metal hydroxides such as nitrides and magnesium hydroxide, and talc materials are preferred. Among these, from the viewpoint of achieving more excellent heat release properties, carbonization selected from the group consisting of metal oxides such as zinc oxide, magnesium oxide, aluminum oxide, titanium oxide, and iron oxide, silicon carbide, and calcium carbonate is used. Fillers made of materials such as nitrides, nitrides such as boron nitride, aluminum nitride, and metal hydroxides such as magnesium hydroxide are preferred. For these materials, powders may be used as fillers, or spheroidized beads may be used as fillers, or single crystal fibers may be used as fillers. The thermally conductive fillers obtained from the above materials can be used alone or in combination of two or more. The thermally conductive filler is preferably non-conductive.

熱傳導性填料的形狀係沒有特別限定,例如,可 具有選自粒狀、針狀、板狀及不定型之至少1種形狀。該等之中,以使用粒狀熱傳導性填料為佳。藉由熱傳導性填料為粒狀,在接著劑層13之熱傳導性填料的填充率提升,而在接著劑層13形成有效率的熱傳導路徑,其結果,接著劑層13係成為具有更良好的放熱性者。 The shape of the thermally conductive filler is not particularly limited. It has at least one shape selected from the group consisting of granular, needle-like, plate-like, and amorphous. Among these, it is preferable to use a granular heat conductive filler. When the thermally conductive filler is granular, the filling rate of the thermally conductive filler in the adhesive layer 13 is increased, and an efficient heat conduction path is formed in the adhesive layer 13. As a result, the adhesive layer 13 has a better heat release. Sex.

熱傳導性填料為粒狀時,其平均粒徑之下限值係以0.01μm以上為佳,以0.05μm以上為更佳,以0.1μm以上為特佳。又,上述熱傳導性填料的平均粒徑,上限值係以20μm以下為佳,以5μm以下為更佳,以1μm以下為特佳。藉由熱傳導性填料的平均粒徑為上述範圍,接著劑層13係成為放熱性更優異者,同時接著劑層13的製膜性變為良好,而且,能夠提高在接著劑層13之熱傳導性填料的填充率。又,在本說明書之熱傳導性填料的平均粒徑,係指使用電子顯微鏡測定隨意選擇的20個熱傳導性填料之的長軸徑,且設為其算術平均值而算出之粒徑。 When the thermally conductive filler is granular, the lower limit of the average particle diameter is preferably 0.01 μm or more, more preferably 0.05 μm or more, and particularly preferably 0.1 μm or more. The upper limit of the average particle diameter of the thermally conductive filler is preferably 20 μm or less, more preferably 5 μm or less, and particularly preferably 1 μm or less. When the average particle diameter of the thermally conductive filler is in the above range, the adhesive layer 13 is more excellent in heat release, and at the same time, the film forming property of the adhesive layer 13 is good, and the thermal conductivity in the adhesive layer 13 can be improved. Filling rate of the filler. In addition, the average particle diameter of the thermally conductive filler in the present specification refers to a particle diameter calculated by measuring the major axis diameter of 20 thermally selected fillers arbitrarily selected using an electron microscope, and calculating the arithmetic mean thereof.

又,熱傳導性填料為粒狀時,該熱傳導性填料的最大粒徑係以50μm以下為佳,以25μm以下為更佳。藉由熱傳導性填料的最大粒徑為50μm以下,容易將熱傳導性填料填充至接著劑層13中,其結果,接著劑層13成為具有更良好的放熱性者。又,藉由無機填料的最大粒徑為50μm以下,在積層電路之貫穿電極(或設置在貫穿電極的端部之凸塊)彼此容易進行電性連接,而能夠有效地製造具有較高的可靠性之積層電路。 When the thermally conductive filler is granular, the maximum particle diameter of the thermally conductive filler is preferably 50 μm or less, and more preferably 25 μm or less. When the maximum particle diameter of the thermally conductive filler is 50 μm or less, it is easy to fill the thermally conductive filler into the adhesive layer 13. As a result, the adhesive layer 13 has a better heat release property. In addition, since the maximum particle diameter of the inorganic filler is 50 μm or less, the through electrodes (or bumps provided at the ends of the through electrodes) of the multilayer circuit are easily electrically connected to each other, and can be efficiently manufactured with high reliability. Layered circuit of sex.

熱傳導性填料為粒狀時,熱傳導性填料的粒徑分 布(CV值),係以15%以上為佳,特別是以30%以上為佳。又,該粒徑分布(CV值),係以80%以下為佳,特別是以60%以下為佳。藉由將熱傳導性填料的粒徑分布設為上述範圍,能夠有效率地達成均勻的放熱性。又,CV值是粒徑的偏差之指標,這意味著CV值越大,粒徑的偏差越大。因此,特別是藉由CV值為15%以上,粒徑的偏差變為良好,具有較小的尺寸之粒子容易進入粒子與粒子之間隙。藉此,能夠有效地填充熱傳導性填料,而容易得到顯示較高的放熱性之接著劑層13。又,藉由CV值為80%以下,能夠抑制熱傳導性填料的粒徑變得比接著劑層13的厚度更大。其結果,能夠抑制在接著劑層13之與接著劑層12為相反側的面產生凹凸,而容易得到良好的接著性。而且,藉由CV值為80%以下,容易形成具有均勻的性能之接著劑層13。又,熱傳導性填料的粒徑分布(CV值),係能夠藉由進行熱傳導性填料的電子顯微鏡觀察,針對200個以上的粒子測定長軸徑,求取長軸徑的標準偏差,且設為將該標準偏差除以上述的平均粒徑之值而得到。 When the thermally conductive filler is granular, the particle size of the thermally conductive filler is The cloth (CV value) is preferably 15% or more, especially 30% or more. The particle size distribution (CV value) is preferably 80% or less, and particularly preferably 60% or less. By setting the particle size distribution of the thermally conductive filler to the above range, it is possible to efficiently achieve uniform heat release. The CV value is an index of variation in particle size, which means that the larger the CV value, the larger the variation in particle size. Therefore, especially with a CV value of 15% or more, the variation in the particle diameter becomes good, and particles having a small size easily enter the gap between the particles. Thereby, the thermally conductive filler can be efficiently filled, and the adhesive layer 13 exhibiting high heat release properties can be easily obtained. In addition, when the CV value is 80% or less, the particle diameter of the thermally conductive filler can be suppressed from becoming larger than the thickness of the adhesive layer 13. As a result, it is possible to suppress the occurrence of unevenness on the surface of the adhesive layer 13 opposite to the adhesive layer 12, and it is easy to obtain good adhesiveness. In addition, when the CV value is 80% or less, it is easy to form the adhesive layer 13 having uniform performance. The particle size distribution (CV value) of the thermally conductive filler can be measured by electron microscope observation of the thermally conductive filler, and the major axis diameter can be measured for 200 or more particles, and the standard deviation of the major axis diameter can be determined as This standard deviation is obtained by dividing the value of the above average particle diameter.

熱傳導性填料的形狀為針狀時,在該熱傳導性填料之平均軸長(長軸方向的平均軸長),係以0.01μm以上為佳,特別是以0.05μm以上為佳,進一步以0.1μm以上為佳。又,該平均軸長係以10μm以下為佳,特別是以5μm以下為佳,進一步以1μm以下為佳。 When the shape of the thermally conductive filler is acicular, the average axial length (average axial length in the long axis direction) of the thermally conductive filler is preferably 0.01 μm or more, particularly preferably 0.05 μm or more, and further 0.1 μm. The above is better. The average axial length is preferably 10 μm or less, particularly preferably 5 μm or less, and further preferably 1 μm or less.

熱傳導性填料的縱橫比(aspect ratio)係以1以上為佳,特別是以5以上為佳。又,該縱橫比係以20以下為佳,特別是以15以下為佳。藉由熱傳導性填料的縱橫比為上述範 圍,係在接著劑層13形成有效率的熱傳導路徑,而使接著劑層13成為具有更良好的放熱性者。又,縱橫比係能夠設為將熱傳導性填料的短軸數量平均徑除以長軸數量平均徑之值。在此,所謂短軸數量平均徑及長軸數量平均徑,係指透過電子顯微鏡照相測定隨意選擇的20個熱傳導性填料之短軸徑及長軸徑,且設為各自的算術平均值而算出之個數平均粒徑。 The aspect ratio of the thermally conductive filler is preferably 1 or more, and particularly preferably 5 or more. The aspect ratio is preferably 20 or less, and particularly preferably 15 or less. The aspect ratio of the thermally conductive filler is the above-mentioned range It is because an efficient heat conduction path is formed in the adhesive layer 13 so that the adhesive layer 13 has a better heat radiation property. The aspect ratio can be a value obtained by dividing the average diameter of the minor axis number of the thermally conductive filler by the average diameter of the major axis number. Here, the average number of minor axes and the average number of major axes refer to the measurement of the minor axis and major axis diameters of 20 thermally conductive fillers arbitrarily selected by electron microscope photography, and are calculated by setting their respective arithmetic mean values. The number average particle size.

熱傳導性填料的比重係以1g/cm3以上為佳,特別是以3g/cm3以上為佳。又,該比重係以10g/cm3以下為佳,特別是以6g/cm3以下為佳。藉由該比重為上述範圍,接著劑層13的放熱性係成為更優異者。 The specific gravity of the thermally conductive filler is preferably 1 g / cm 3 or more, and particularly preferably 3 g / cm 3 or more. The specific gravity is preferably 10 g / cm 3 or less, and particularly preferably 6 g / cm 3 or less. When the specific gravity is in the above range, the exothermic property of the adhesive layer 13 becomes more excellent.

又,在接著劑層13之熱傳導性填料的含量,係將構成接著劑層13之材料的合計量作為基準,下限值係以35質量%以上為佳,以40質量%以上為更佳,以50質量%以上為特佳。又,上述熱傳導性填料的含量之上限值係以95質量%以下為佳,以90質量%以下為更佳。在構成接著劑層13之材料,藉由熱傳導性填料的含量為35質量%以上,接著劑層13係成為具有更良好的放熱性者,使用本實施形態之三次元積體積層電路製造用板片1、2,能夠有效地製造具有優異的放熱性之積層電路。又,藉由該含量為95質量%以下,在構成接著劑層13之材料中之熱傳導性填料以外的成分之含量為相對地變高,使得接著劑層13能夠發揮更良好的接著性。 The content of the thermally conductive filler in the adhesive layer 13 is based on the total amount of the materials constituting the adhesive layer 13, and the lower limit value is preferably 35% by mass or more, and more preferably 40% by mass or more. It is particularly preferred to be 50% by mass or more. The upper limit of the content of the thermally conductive filler is preferably 95% by mass or less, and more preferably 90% by mass or less. The material constituting the adhesive layer 13 has a thermally conductive filler content of 35% by mass or more, and the adhesive layer 13 has a better heat release property, and the three-dimensional multi-layer bulk-layer circuit manufacturing board of this embodiment is used. Sheets 1 and 2 can efficiently produce a multilayer circuit having excellent heat release properties. In addition, when the content is 95% by mass or less, the content of components other than the thermally conductive filler in the material constituting the adhesive layer 13 becomes relatively high, so that the adhesive layer 13 can exhibit better adhesiveness.

(1-2)熱硬化性成分 (1-2) Thermosetting ingredients

構成接著劑層13之材料,係以含有熱硬化性成分為佳。熱硬化性成分係只要通常被使用在半導體晶片的連接用之接 著劑成分,就只要沒有特別限定。具體而言可舉出環氧樹脂、酚樹脂、三聚氰胺樹脂、尿素樹脂、聚酯樹脂、胺甲酸酯樹脂、丙烯酸樹脂、聚醯亞胺樹脂、苯并

Figure TW201802973AD00001
嗪樹脂、苯氧基樹脂等,該等能夠單獨使用1種或組合2種以上而使用。該等之中,從接著性等的觀點而言,係以環氧樹脂及酚樹脂為佳,以環氧樹脂為特佳。 The material constituting the adhesive layer 13 is preferably one containing a thermosetting component. The thermosetting component is not particularly limited as long as it is an adhesive component generally used for connection of semiconductor wafers. Specific examples include epoxy resin, phenol resin, melamine resin, urea resin, polyester resin, urethane resin, acrylic resin, polyimide resin, and benzo
Figure TW201802973AD00001
A azine resin, a phenoxy resin, etc. can be used individually by 1 type or in combination of 2 or more types. Among these, epoxy resins and phenol resins are preferable, and epoxy resins are particularly preferable from the viewpoint of adhesiveness and the like.

環氧樹脂係具有受到加熱時進行三次元網狀化而形成堅固的硬化物之性質。作為此種環氧樹脂,能夠使用先前習知的各種環氧樹脂,具體而言,能夠舉出雙酚A、雙酚F、間苯二酚、苯酚酚醛清漆、甲酚酚醛清漆等的酚類的環氧丙基醚;丁二醇、聚乙二醇、聚丙二醇等的醇類的環氧丙基醚;鄰苯二甲酸、間苯二甲酸、四氫鄰苯二甲酸等羧酸的環氧丙基醚;將鍵結在苯胺異三聚氰酸酯等的氮原子之活性氫使用環氧丙基取代而成之環氧丙基型或烷基環氧丙基型的環氧樹脂;將如乙烯基環己烷二環氧化物、3,4-環氧環己基甲基-3,4-二環己烷羧酸酯、2-(3,4-環氧)環己基-5,5-螺(3,4-環氧)環己烷-間-二

Figure TW201802973AD00002
烷等之分子內的碳-碳雙鍵藉由例如氧化而導入環氧基而成之所謂脂環型環氧化物。此外,亦能夠使用具有聯苯骨架、二環己二烯骨架、萘骨架等之環氧樹脂。該等環氧樹脂可單獨1種、或組合2種以上而使用。 Epoxy resins have the property of undergoing three-dimensional network formation upon heating to form a solid hardened product. As such an epoxy resin, various conventionally known epoxy resins can be used, and specific examples include phenols such as bisphenol A, bisphenol F, resorcinol, phenol novolac, and cresol novolac. Glycidyl ether; Glycidyl ethers of alcohols such as butanediol, polyethylene glycol, and polypropylene glycol; Rings of carboxylic acids such as phthalic acid, isophthalic acid, and tetrahydrophthalic acid Oxypropyl ether; epoxy-type or alkyl-epoxy-type epoxy resin in which active hydrogen bonded to a nitrogen atom such as aniline isocyanurate is substituted with glycidyl group; For example, vinyl cyclohexane diepoxide, 3,4-epoxycyclohexylmethyl-3,4-dicyclohexanecarboxylate, 2- (3,4-epoxy) cyclohexyl-5, 5-spiro (3,4-epoxy) cyclohexane-m-di
Figure TW201802973AD00002
A carbon-carbon double bond in a molecule such as an alkane is a so-called alicyclic epoxide in which an epoxy group is introduced by oxidation, for example. In addition, an epoxy resin having a biphenyl skeleton, a dicyclohexadiene skeleton, a naphthalene skeleton, or the like can also be used. These epoxy resins can be used individually by 1 type or in combination of 2 or more types.

在構成接著劑層13的材料之上述熱硬化性成分的含量,係將構成接著劑層13的材料之合計量作為基準,其下限值係以5質量%以上為佳,以10質量%以上為更佳。又,上述熱硬化性成分的含量之上限值係以75質量%以下為佳,以 55質量%以下為更佳。藉由上述熱硬化性成分的含量為上述範圍,將前述的發熱起始溫度及發熱尖峰溫度調整成為前述的範圍係變得容易。 The content of the thermosetting component in the material constituting the adhesive layer 13 is based on the total amount of the material constituting the adhesive layer 13, and the lower limit value thereof is preferably 5 mass% or more, and 10 mass% or more. For the better. The upper limit of the content of the thermosetting component is preferably 75% by mass or less. 55 mass% or less is more preferred. When the content of the thermosetting component is in the above range, it becomes easy to adjust the aforementioned exothermic onset temperature and exothermic peak temperature to the aforementioned range.

(1-3)硬化劑.硬化觸媒 (1-3) Hardener. Hardening catalyst

構成接著劑層13之材料係含有前述的熱硬化性成分時,該材料係以進一步含有硬化劑及硬化觸媒為佳。 When the material constituting the adhesive layer 13 contains the aforementioned thermosetting component, it is preferable that the material further contains a curing agent and a curing catalyst.

作為硬化劑,係沒有特別限定,可舉出酚類、胺類、硫醇類等,能夠按照前述熱硬化成分的種類而適當地選擇。例如,使用環氧樹脂作為硬化性成分時,從與環氧樹脂的反應性等的觀點而言,以酚類為佳。 The curing agent is not particularly limited, and examples thereof include phenols, amines, and thiols, and can be appropriately selected according to the type of the thermosetting component. For example, when an epoxy resin is used as the curable component, phenols are preferred from the viewpoint of reactivity with the epoxy resin and the like.

作為酚類,例如能夠舉出雙酚A、四甲基雙酚A、二烯丙基雙酚A、聯苯酚、雙酚F、二烯丙基雙酚F、三苯基甲烷型苯酚、四酚、酚醛清漆型苯酚、甲酚酚醛清漆樹脂等,該等係能夠單獨使用1種或組合2種以上而使用。 Examples of the phenols include bisphenol A, tetramethyl bisphenol A, diallyl bisphenol A, biphenol, bisphenol F, diallyl bisphenol F, triphenylmethane-type phenol, tetrakis Phenol, novolac-type phenol, cresol novolac resin, etc. can be used alone or in combination of two or more.

又,作為硬化觸媒,係沒有特別限定,可舉出咪唑系、磷系、胺系等,能夠按照前述熱硬化成分等的種類而適當地選擇。又,作為硬化觸媒,以使用潛在性硬化觸媒為佳,其在預定條件下不產生活性化,但被加熱至使焊料熔融之高溫的壓黏溫度以上時產生活性化。而且,該潛在性硬化觸媒,亦以使用作為經微膠囊化的潛在性硬化觸媒為佳。 The curing catalyst is not particularly limited, and examples thereof include imidazole-based, phosphorus-based, amine-based, and the like, and they can be appropriately selected according to the types of the aforementioned thermosetting components and the like. As the hardening catalyst, it is preferable to use a latent hardening catalyst, which does not activate under predetermined conditions, but activates when it is heated to a temperature higher than the sticking temperature at which the solder melts. The latent curing catalyst is also preferably used as a microencapsulated latent curing catalyst.

例如,使用環氧樹脂作為硬化性成分時,從與環氧樹脂的反應性、保存安定性、硬化物的物性、硬化速度等的觀點而言,作為硬化觸媒,係以使用咪唑系硬化觸媒為佳。作為咪唑系硬化觸媒,能夠使用習知物,但是從優異的硬化性、 保存安定性及接續可靠性的觀點而言,係以具有三嗪骨架之咪唑觸媒為佳。該等可單獨使用、或併用2種以上而使用。又,該等亦可使用作為經微膠囊化的潛在性硬化觸媒。咪唑系硬化觸媒的熔點,係從優異的硬化性、保存安定性及接續可靠性的觀點而言,以200℃以上為佳,特別是以250℃以上為佳。 For example, when an epoxy resin is used as a hardening component, an imidazole-based hardening catalyst is used as a hardening catalyst from the viewpoints of reactivity with the epoxy resin, storage stability, physical properties of hardened materials, and hardening speed. Media is better. As imidazole-based curing catalysts, known substances can be used, but from excellent curing properties, In terms of preservation stability and connection reliability, an imidazole catalyst having a triazine skeleton is preferred. These can be used individually or in combination of 2 or more types. Moreover, these can also be used as a microencapsulated latent hardening catalyst. The melting point of the imidazole-based hardening catalyst is preferably 200 ° C or higher, and particularly preferably 250 ° C or higher, from the viewpoint of excellent hardenability, storage stability, and connection reliability.

在本實施形態,在構成接著劑層13的材料之硬化觸媒的含量,係將構成接著劑層13的材料之合計量設為基準,下限值係以0.1質量%以上為佳,以0.2質量%以上為更佳,以0.4質量%以上為特佳。又,上述硬化觸媒的含量之上限值,係以10質量%以下為佳,以5質量%以下為更佳,以3質量%以下為特佳。在構成接著劑層13之材料,硬化觸媒的含量為上述下限值以上時,能夠使熱硬化性成分充分地硬化。另一方面,硬化觸媒的含量為上述上限值以下時,接著劑層13的保存安定性係變為良好。 In this embodiment, the content of the hardening catalyst of the material constituting the adhesive layer 13 is based on the total amount of the material constituting the adhesive layer 13, and the lower limit value is preferably 0.1% by mass or more, and 0.2 A mass% or more is more preferred, and a mass of 0.4 mass% or more is particularly preferred. The upper limit of the content of the hardening catalyst is preferably 10% by mass or less, more preferably 5% by mass or less, and particularly preferably 3% by mass or less. When the material constituting the adhesive layer 13 has a content of the curing catalyst of at least the above-mentioned lower limit value, the thermosetting component can be sufficiently cured. On the other hand, when the content of the curing catalyst is equal to or less than the above-mentioned upper limit value, the storage stability of the adhesive layer 13 becomes good.

(1-4)高分子量成分 (1-4) High molecular weight ingredients

上述構成接著劑層13之材料,係以含有前述熱硬化性成分以外的高分子量成分為佳。藉由含有該高分子量成分,該材料的90℃熔融黏度與平均線膨脹係數係容易滿足後述的數值範圍,且所得到的積層電路之接續可靠性成為較高了。 The material constituting the adhesive layer 13 is preferably a high molecular weight component other than the thermosetting component. By including the high molecular weight component, the material's 90 ° C. melt viscosity and average linear expansion coefficient easily meet the numerical ranges described below, and the reliability of the obtained multilayer circuit is higher.

作為高分子量成分,例如,可舉出(甲基)丙烯酸系樹脂、苯氧基樹脂、聚酯樹脂、聚胺酯樹脂、聚醯亞胺樹脂、聚醯胺醯亞胺樹脂、矽氧烷改性聚醯亞胺樹脂、聚丁二烯樹脂、聚丙烯樹脂、苯乙烯-丁二烯-苯乙烯共聚物、苯乙烯-乙烯-丁烯-苯乙烯共聚物、聚縮醛樹脂、以聚乙烯縮丁醛樹脂為首 之聚乙烯縮醛樹脂、丁基橡膠、氯丁二烯橡膠、聚醯胺樹脂、丙烯腈-丁二烯共聚物、丙烯腈-丁二烯-丙烯酸共聚物、丙烯腈-丁二烯-苯乙烯共聚物、聚乙酸乙烯酯、耐綸等,而且能夠單獨使用1種或組合2種以上而使用。 Examples of the high molecular weight component include (meth) acrylic resins, phenoxy resins, polyester resins, polyurethane resins, polyimide resins, polyimide resins, and siloxane-modified polyimide resins. Fluorene imine resin, polybutadiene resin, polypropylene resin, styrene-butadiene-styrene copolymer, styrene-ethylene-butene-styrene copolymer, polyacetal resin, polyethylene butyral Led by aldehyde resin Polyvinyl acetal resin, butyl rubber, chloroprene rubber, polyamide resin, acrylonitrile-butadiene copolymer, acrylonitrile-butadiene-acrylic acid copolymer, acrylonitrile-butadiene-benzene Ethylene copolymer, polyvinyl acetate, nylon, etc. can be used alone or in combination of two or more.

又,在本說明書之「(甲基)丙烯酸」係意味著丙烯酸及甲基丙烯酸之雙方。針對「(甲基)丙烯酸系樹脂」等其它的類似用語亦同樣。 In addition, "(meth) acrylic acid" in this specification means both acrylic acid and methacrylic acid. The same applies to other similar terms such as "(meth) acrylic resin".

前述高分子量成分之中,以使用選自由聚乙烯縮醛樹脂、及聚酯樹脂、苯氧基樹脂所組成群組之1種以上為佳。構成上述製造用板片之材料,係藉由含有該等高分子量成分,90℃熔融黏度及平均線膨脹係數均成為較低的值,其結果,使該等值成為後述的數值範圍內變得容易。 Among the high molecular weight components, it is preferable to use one or more members selected from the group consisting of a polyvinyl acetal resin, a polyester resin, and a phenoxy resin. The material constituting the above-mentioned manufacturing sheet is made to contain these high molecular weight components, and both the 90 ° C. melt viscosity and the average linear expansion coefficient become lower values. As a result, these values fall within the numerical range described later. easily.

在此,聚乙烯縮醛樹脂,係能夠使用醛將聚乙烯醇進行縮醛化得到者,其中該聚乙烯醇係藉由將聚乙酸乙烯酯皂化而得到。作為在縮醛化所使用的醛,可舉出正丁醛、正己醛、正戊醛等。作為聚乙烯縮醛樹脂,採用使用正丁醛進行縮醛化而成之聚乙烯縮丁醛樹脂亦佳。 Here, the polyvinyl acetal resin is obtained by acetalizing polyvinyl alcohol using an aldehyde, and the polyvinyl alcohol is obtained by saponifying polyvinyl acetate. Examples of the aldehyde used in the acetalization include n-butyraldehyde, n-hexanal, and n-valeraldehyde. As the polyvinyl acetal resin, a polyvinyl butyral resin obtained by acetalization using n-butyraldehyde is also preferred.

作為聚酯樹脂,例如將聚對苯二甲酸乙二酯樹脂、聚對苯二甲酸丁二酯樹脂、聚草酸乙二酯樹脂等的二羧酸成分及二醇成分進行聚縮合而得到之聚酯樹脂;使聚異氰酸酯化合物對該等反應而得到之胺甲酸酯改性聚酯樹脂等的改性聚酯樹脂;將丙烯酸樹脂及/或乙烯基樹脂接枝化而成之聚酯樹脂等,而且能夠單獨使用1種或組合2種以上而使用。 Examples of the polyester resin include a polymer obtained by polycondensing a dicarboxylic acid component and a diol component such as polyethylene terephthalate resin, polybutylene terephthalate resin, and polyethylene oxalate resin. Ester resins; modified polyester resins such as urethane-modified polyester resins obtained by reacting polyisocyanate compounds with these; polyester resins obtained by grafting acrylic resins and / or vinyl resins, etc. Moreover, it can be used individually by 1 type or in combination of 2 or more types.

又,構成接著劑層13之材料,係含有聚乙烯縮醛 樹脂、或聚酯樹脂作為上述高分子量成分時,係以進一步含有苯氧基樹脂為特佳。進一步含有苯氧基樹脂時,構成接著劑層13之材料,其90℃熔融黏度及平均線膨脹係數係更容易滿足後述的數值範圍。 The material constituting the adhesive layer 13 contains polyvinyl acetal. When a resin or a polyester resin is used as the high-molecular weight component, it is particularly preferred that the resin further contains a phenoxy resin. When a phenoxy resin is further contained, the material constituting the adhesive layer 13 has a 90 ° C melt viscosity and an average linear expansion coefficient that more easily satisfy the numerical ranges described later.

作為苯氧基樹脂,係沒有特別限定,例如能夠例示雙酚A型、雙酚F型、雙酚A/雙酚F共聚合型、聯苯酚型、聯苯型等。 The phenoxy resin is not particularly limited, and examples thereof include bisphenol A type, bisphenol F type, bisphenol A / bisphenol F copolymerization type, biphenol type, and biphenyl type.

上述高分子量成分之軟化點的下限值,係以50℃以上為佳,以100℃以上為更佳,以120℃以上為特佳。又,上述高分子量成分之軟化點的上限值,係以200℃以下為佳,以180℃以下為更佳,以150℃以下為特佳。藉由含有軟化點為上述下限值以上之高分子量成分,能夠減低構成接著劑層13之材料的平均線膨脹係數,而容易滿足後述的數值範圍。又,軟化點為上述上限值以下時,能夠抑制接著劑層13的脆化。又,軟化點係設為依據ASTM D1525所測得的值。 The lower limit of the softening point of the high molecular weight component is preferably 50 ° C or higher, more preferably 100 ° C or higher, and particularly preferably 120 ° C or higher. The upper limit of the softening point of the high molecular weight component is preferably 200 ° C or lower, more preferably 180 ° C or lower, and particularly preferably 150 ° C or lower. By including a high molecular weight component having a softening point of the above lower limit value or more, the average linear expansion coefficient of the material constituting the adhesive layer 13 can be reduced, and it is easy to satisfy a numerical range described later. When the softening point is equal to or less than the above-mentioned upper limit value, embrittlement of the adhesive layer 13 can be suppressed. The softening point is a value measured in accordance with ASTM D1525.

上述高分子量成分之玻璃轉移溫度的下限值,係以50℃以上為佳,以60℃以上為更佳,以80℃以上為特佳。又,上述高分子量成分之玻璃轉移溫度的上限值,係以250℃以下為佳,以200℃以下為更佳,以180℃以下為特佳。藉由含有玻璃轉移溫度為上述下限值以上之高分子量成分,能夠減低構成接著劑層13之材料的平均線膨脹係數,而容易滿足後述的數值範圍。又,玻璃轉移溫度為上述上限值以下時,與其它材料的相溶性係變為優異。又,高分子量成分的玻璃轉移溫度,係使用差示掃描熱量分析計而測得的值。 The lower limit of the glass transition temperature of the high molecular weight component is preferably 50 ° C or higher, more preferably 60 ° C or higher, and particularly preferably 80 ° C or higher. The upper limit of the glass transition temperature of the high molecular weight component is preferably 250 ° C or lower, more preferably 200 ° C or lower, and particularly preferably 180 ° C or lower. By including a high molecular weight component having a glass transition temperature of the above lower limit value or more, the average linear expansion coefficient of the material constituting the adhesive layer 13 can be reduced, and the numerical range described later can be easily satisfied. When the glass transition temperature is equal to or lower than the above upper limit, the compatibility with other materials becomes excellent. The glass transition temperature of the high molecular weight component is a value measured using a differential scanning calorimeter.

上述高分子量成分之重量平均分子量,係以1萬以上為佳,以3萬以上為更佳,以5萬以上為特佳。又,上限值係以100萬以下為佳,以70萬以下為更佳,以50萬以下為特佳。重量平均分子量為上述下限值以上時,因為維持薄膜形成性之同時,亦能夠使熔融黏度降低,乃是較佳。又,重量平均分子量為上述上限值以下時,因為與熱硬化性成分等的低分子量成分之相溶性提升,乃是較佳。又,在本說明書之重量平均分子量,係藉由凝膠滲透層析法(GPC)法而測定之標準聚苯乙烯換算之值。 The weight average molecular weight of the high molecular weight component is preferably 10,000 or more, more preferably 30,000 or more, and particularly preferably 50,000 or more. The upper limit value is preferably 1 million or less, more preferably 700,000 or less, and particularly preferably 500,000 or less. When the weight-average molecular weight is equal to or more than the above-mentioned lower limit value, it is preferable because the melt viscosity can be reduced while maintaining the film forming property. When the weight-average molecular weight is equal to or less than the above-mentioned upper limit, it is preferable because the compatibility with low-molecular-weight components such as thermosetting components is improved. In addition, the weight average molecular weight in this specification is a standard polystyrene conversion value measured by the gel permeation chromatography (GPC) method.

在構成接著劑層13之材料之上述高分子量成分的含量,係將構成接著劑層13之材料的合計量設為基準,下限值係以3質量%以上為佳,以5質量%以上為更佳,以7質量%以上為特佳。又,上述高分子量成分的含量之上限值,係以95質量%以下為佳,以90質量%以下為更佳,以80質量%以下為特佳。上述高分子量成分的含量為上述下限值以上時,能夠使構成接著劑層13之材料的90℃熔融黏度成為更低的值,而容易滿足前述的數值範圍。另一方面,上述高分子量成分的含量為上述上限值以下時,能夠進一步減低構成接著劑層13之材料的平均線膨脹係數,而容易滿足後述的數值範圍。 The content of the high molecular weight component in the material constituting the adhesive layer 13 is based on the total amount of the material constituting the adhesive layer 13, and the lower limit value is preferably 3% by mass or more, and 5% by mass or more. More preferably, it is especially preferable that it is 7 mass% or more. The upper limit of the content of the high molecular weight component is preferably 95% by mass or less, more preferably 90% by mass or less, and particularly preferably 80% by mass or less. When the content of the high-molecular-weight component is greater than or equal to the above-mentioned lower limit value, the 90 ° C. melt viscosity of the material constituting the adhesive layer 13 can be made lower, and the aforementioned numerical range can be easily satisfied. On the other hand, when the content of the high-molecular-weight component is equal to or less than the above-mentioned upper limit value, the average linear expansion coefficient of the material constituting the adhesive layer 13 can be further reduced, and the numerical range described later can be easily satisfied.

(1-5)具有助焊劑功能之成分 (1-5) Ingredients with flux function

在本實施形態,藉由焊料將半導體晶片的貫穿電極或凸塊接合時,構成接著劑層13之材料係以含有具有助焊劑功能的成分(以下有稱為「助焊劑成分」之情形)為佳。助焊劑成分係具有將在電極表面所形成的金屬氧化膜除去的作用之物,能夠 使藉由焊料之電極之間的電性連接成為更確實者,而能夠提高在焊接部之接續可靠性。 In this embodiment, when the through-electrodes or bumps of a semiconductor wafer are bonded by solder, the material constituting the adhesive layer 13 contains a component having a flux function (hereinafter referred to as a "flux component") as good. The flux component is a substance having a function of removing a metal oxide film formed on an electrode surface, and is capable of By making the electrical connection between the electrodes of the solder more reliable, the connection reliability at the soldered portion can be improved.

作為助焊劑成分,係沒有特別限定,以具有酚性羥基及/或羧基之成分為佳,以具有羧基之成分為特佳。具有羧基之成分,係具有助焊劑功能之同時,將後述的環氧樹脂使用作為熱硬化性成分時,亦具有作為硬化劑之作用。因此,具有羧基之成分,因為焊接完成之後,係作為硬化劑而被消耗,所以能夠抑制起因於過剩的助焊劑成分之不良。 The flux component is not particularly limited, and a component having a phenolic hydroxyl group and / or a carboxyl group is preferred, and a component having a carboxyl group is particularly preferred. The component having a carboxyl group has a flux function, and when a later-described epoxy resin is used as a thermosetting component, it also functions as a hardener. Therefore, the component having a carboxyl group is consumed as a hardener after the soldering is completed, so it is possible to suppress a defect caused by an excessive flux component.

作為具體的助焊劑成分,例如,可舉出戊二酸、2-甲基戊二酸、鄰大茴香酸、二酚酸、己二酸、乙醯柳酸、苯甲酸、二苯羥乙酸、壬二酸、苄基苯甲酸、丙二酸、2,2-雙(羥甲基)丙酸、枊酸、鄰-甲氧基苯甲酸、間-羥基苯甲酸、琥珀酸、2,6-二甲氧基甲基對甲酚、苯甲酸醯肼、卡肼(carbohydrazide)、丙二酸二醯肼、琥珀酸二醯肼、戊二酸二醯肼、枊酸醯肼、亞胺二乙酸二醯肼、伊康酸二醯肼、檸檬酸三醯肼、硫卡肼(thiocarbohydrazide)、二苯甲酮腙(Benzophenone hydrazone)、4,4’-氧雙苯磺醯肼、己二酸二醯肼、松香衍生物等,該等係能夠單獨使用1種或組合2種以上而使用。 Specific examples of the flux component include glutaric acid, 2-methylglutaric acid, o-antanilic acid, diphenolic acid, adipic acid, ossalic acid, benzoic acid, diphenylglycolic acid, Azelaic acid, benzylbenzoic acid, malonic acid, 2,2-bis (hydroxymethyl) propionic acid, gallic acid, o-methoxybenzoic acid, m-hydroxybenzoic acid, succinic acid, 2,6- Dimethoxymethyl p-cresol, hydrazine benzoate, carbohydrazide, dihydrazine malonate, dihydrazine succinate, dihydrazine glutarate, hydrazine oxalate, imine diacetic acid Dihydrazine, dihydrazine iconate, trihydrazine citrate, thiocarbohydrazide, bezophenone hydrazone, 4,4'-oxodisulfenazine, adipic acid A hydrazine, a rosin derivative, etc. can be used individually by 1 type or in combination of 2 or more types.

作為松香衍生物,可舉出松脂膠(gum rosin)、妥爾松香(tall rosin)、木松香、聚合松香、氫化松香、甲醯化松香、松香酯、松香改性順丁烯二酸樹脂、松香改性酚樹脂、松香改性醇酸樹脂等。 Examples of the rosin derivative include gum rosin, tall rosin, wood rosin, polymerized rosin, hydrogenated rosin, methylated rosin, rosin ester, rosin-modified maleic acid resin, Rosin modified phenol resin, rosin modified alkyd resin, etc.

該等之中,以使用選自由2-甲基戊二酸、己二酸及松香衍生物之至少1種為特佳。2-甲基戊二酸及己二酸,係 因為在構成接著劑層13之材料,雖然分子量較小,但是在分子內具有2個羧基,所以即便少量添加亦具有優異的助焊劑功能,而能夠特別適合在本實施形態。松香衍生物係軟化點較高,因為在維持低線膨脹係數化之同時,能夠賦予助焊劑性,所以能夠特別適合在本實施形態。 Among these, it is particularly preferable to use at least one selected from the group consisting of 2-methylglutaric acid, adipic acid, and rosin derivatives. 2-methylglutaric acid and adipic acid The material constituting the adhesive layer 13 has a small molecular weight but has two carboxyl groups in the molecule. Therefore, even if it is added in a small amount, it has an excellent flux function, and is particularly suitable for this embodiment. The rosin derivative has a high softening point, and can maintain a low linear expansion coefficient while imparting flux properties, and is therefore particularly suitable for this embodiment.

助焊劑成分的熔點及軟化點之至少一方,係以80℃以上為佳,以110℃以上為較佳,以130℃以上為更佳。助焊劑成分的熔點及軟化點之至少一方為上述範圍時,能夠得到更優異的助焊劑功能,也能夠減低排氣等,乃是較佳。又,助焊劑成分的熔點及軟化點之上限值係沒有特別限定,例如焊料的熔點以下即可。 At least one of the melting point and the softening point of the flux component is preferably 80 ° C or higher, more preferably 110 ° C or higher, and more preferably 130 ° C or higher. When at least one of the melting point and the softening point of the flux component is within the above-mentioned range, it is preferable to obtain more excellent flux function and reduce exhaust gas. The upper limit of the melting point and softening point of the flux component is not particularly limited, and may be, for example, less than the melting point of the solder.

在本實施形態,構成接著劑層13的材料之助焊劑成分的含量,係將構成接著劑層13的材料之合計量設為基準,其下限值係以0.1質量%以上為佳,以0.2質量%以上為更佳,以0.3質量%以上為特佳。又,上述助焊劑成分的含量之上限值,係以20質量%以下為佳,以15質量%以下為更佳,以10質量%以下為特佳。在構成接著劑層13之材料,助焊劑成分的含量為上述下限值以上時,能夠使藉由焊料之電極之間的電性連接成為更確實者,而能夠進一步提高在焊接部之接續可靠性。另一方面,助焊劑成分的含量為上述上限值以下時,能夠防止起因於過剩的助焊劑成分之離子遷移等的不良。 In this embodiment, the content of the flux component of the material constituting the adhesive layer 13 is based on the total amount of the material constituting the adhesive layer 13, and the lower limit thereof is preferably 0.1% by mass or more, and 0.2 A mass% or more is more preferable, and 0.3 mass% or more is particularly preferable. The upper limit of the content of the flux component is preferably 20% by mass or less, more preferably 15% by mass or less, and particularly preferably 10% by mass or less. When the material constituting the adhesive layer 13 and the content of the flux component is equal to or more than the above-mentioned lower limit value, the electrical connection between the electrodes by the solder can be made more reliable, and the connection reliability at the soldered portion can be further improved Sex. On the other hand, when the content of the flux component is equal to or less than the above-mentioned upper limit value, defects such as ion migration caused by the excessive flux component can be prevented.

(1-6)其它成分 (1-6) Other ingredients

接著劑層13,亦可進一步含有可塑劑、安定劑、黏著賦予劑、著色劑、偶合劑、抗靜電劑、抗氧化劑、導電性粒子、前 述熱傳導性填料以外的無機填料等作為構成該接著劑層13之材料。 The adhesive layer 13 may further contain a plasticizer, a stabilizer, an adhesion-imparting agent, a coloring agent, a coupling agent, an antistatic agent, an antioxidant, a conductive particle, and a An inorganic filler other than the thermally conductive filler is used as a material constituting the adhesive layer 13.

例如,構成接著劑層13之材料係藉由含有導電性粒子,而能夠對三次元積體積層電路製造用板片1、2賦予異方導電性時,在補助焊接之態樣、或是在與焊接不同的態樣,能夠將半導體晶片彼此進行電性連接。 For example, when the material constituting the adhesive layer 13 contains conductive particles and can provide anisotropic conductivity to the three-dimensional bulk-layer circuit manufacturing plates 1 and 2, it may be in a state of supporting welding or in Unlike soldering, semiconductor wafers can be electrically connected to each other.

(2)物性(2-1)熱傳導率 (2) Physical properties (2-1) Thermal conductivity

在本實施形態之三次元積體積層電路製造用板片1、2,接著劑層13硬化後的熱傳導率係以0.5W/m.K以上為佳,特別是以0.7W/m.K以上為佳,進一步以1.0W/m.K以上為佳。又,該熱傳導率係以8.0W/m.K以下為佳,特別是以4.0W/m.K以下為佳,進一步以3.0W/m.K以下為佳。藉由該熱傳導率為0.5W/m.K以上,接著劑層13係容易顯現良好的放熱性,使用本實施形態之三次元積體積層電路製造用板片1、2,能夠有效地製造具有較高的可靠性之積層電路。另一方面,藉由該熱傳導率為8.0W/m.K以下,在接著劑層13之熱傳導性填料的含量不過度地增多,其結果,容易兼具在接著劑層13之良好的放熱性、與接著劑層13的接著性及板片加工性。又,接著劑層13的熱傳導率的測定方法,係如後述的試驗例所顯示。 In the three-dimensional bulk-layer circuit manufacturing plates 1 and 2 of this embodiment, the thermal conductivity of the adhesive layer 13 after curing is 0.5 W / m. Above K is preferred, especially 0.7W / m. Above K is preferred, further at 1.0 W / m. Above K is preferred. The thermal conductivity is 8.0 W / m. Below K is preferred, especially at 4.0 W / m. Below K is preferred, further at 3.0 W / m. K is preferred. With this thermal conductivity being 0.5W / m. Above K, the adhesive layer 13 is easy to exhibit good heat dissipation properties. By using the three-dimensional multilayer volume circuit manufacturing plates 1 and 2 of this embodiment, it is possible to efficiently manufacture a multilayer circuit having high reliability. On the other hand, the thermal conductivity is 8.0 W / m. Below K, the content of the thermally conductive filler in the adhesive layer 13 does not increase excessively. As a result, it is easy to have both good heat release property in the adhesive layer 13, adhesiveness with the adhesive layer 13, and sheet workability. The method for measuring the thermal conductivity of the adhesive layer 13 is as shown in a test example described later.

(2-2)熔融黏度 (2-2) Melt viscosity

在本實施形態之三次元積體積層電路製造用板片1、2,構成接著劑層13之材料在硬化前之90℃的熔融黏度(以下,有稱為「90℃熔融黏度」之情形),其上限值以5.0×105Pa.s以下為佳,特別是以1.0×105Pa.s以下為佳,進一步以5.0×104Pa.s 以下為佳。90℃熔融黏度為上述上限值以下時,在使接著劑層13介於電極之間時,能夠良好地追隨在半導體晶片表面之起因於貫穿電極或凸塊之凹凸,而能夠防止在半導體晶片與接著劑層13之界面產生空隙。又,90℃熔融黏度之下限值以1.0×100Pa.s以上為佳,特別是以1.0×101Pa.s以上為佳,進一步以1.0×102Pa.s以上為佳。90℃熔融黏度為上述下限值以上時,構成接著劑層13之材料不會過度流動,在接著劑層13貼附時或半導體晶片層積時,能夠防止裝置的污染。因此,本實施形態之三次元積體積層電路製造用板片1、2,係藉由構成的材料之90℃熔融黏度為上述範圍,而成為具有較高的可靠性者。 In the three-dimensional bulk-layer circuit manufacturing plates 1 and 2 of this embodiment, the melt viscosity of the material constituting the adhesive layer 13 before curing at 90 ° C (hereinafter referred to as "90 ° C melt viscosity") , Its upper limit is 5.0 × 10 5 Pa. It is preferably below s, especially 1.0 × 10 5 Pa. It is preferably below s, and further preferably 5.0 × 10 4 Pa. s is preferred. When the melt viscosity at 90 ° C is equal to or less than the above upper limit value, when the adhesive layer 13 is interposed between the electrodes, the unevenness on the surface of the semiconductor wafer due to the penetration electrode or the bump can be well followed, and the semiconductor wafer can be prevented. A void is generated at the interface with the adhesive layer 13. The lower limit of the melt viscosity at 90 ° C is 1.0 × 10 0 Pa. Above s is preferred, especially 1.0 × 10 1 Pa. s or more is preferred, further 1.0 × 10 2 Pa. Above s is preferred. When the melt viscosity at 90 ° C. is equal to or more than the above-mentioned lower limit value, the material constituting the adhesive layer 13 does not flow excessively, and contamination of the device can be prevented when the adhesive layer 13 is attached or the semiconductor wafer is laminated. Therefore, the three-dimensional multi-layer bulk layer circuit manufacturing plates 1 and 2 of this embodiment are those having a higher reliability because the constituent material has a 90 ° C melt viscosity within the above range.

在此,構成接著劑層13的材料之90℃熔融黏度,係能夠使用流量測試器而測定。具體而言,能夠針對厚度15mm的接著劑層13,使用流量測試器(島津製作所公司製、CFT-100D),在荷重50kgf、溫度範圍50~120℃、升溫速度10℃/min的條件下測定熔融黏度。 Here, the 90 ° C melt viscosity of the material constituting the adhesive layer 13 can be measured using a flow tester. Specifically, it is possible to measure the adhesive layer 13 having a thickness of 15 mm using a flow tester (manufactured by Shimadzu Corporation, CFT-100D) under a load of 50 kgf, a temperature range of 50 to 120 ° C, and a heating rate of 10 ° C / min. Melt viscosity.

(2-3)平均線膨脹係數 (2-3) Average linear expansion coefficient

在本實施形態,構成接著劑層13之材料,其硬化物在0~130℃之平均線膨脹係數(以下,有簡稱為「平均線膨脹係數」之情形),上限值係以45ppm以下為佳,特別是以35ppm以下為佳,進一步以25ppm以下為佳。平均線膨脹係數為上述上限值以下時,由硬化物所構成的接著劑層13與半導體晶片之線膨脹係數之差變小,基於此種差,能夠減低在接著劑層13與半導體晶片之間可能產生之應力。藉此,本實施形態之三次元積體積層電路製造用板片1、2,係能夠使半導體晶片彼此的接 續可靠性成為較高者,特別是在實施例顯示之溫度循環試驗,成為顯示較高的接續可靠性者。 In this embodiment, the material constituting the adhesive layer 13 has an average linear expansion coefficient (hereinafter referred to as the "average linear expansion coefficient" for short) of the hardened material at 0 to 130 ° C, and the upper limit value is 45 ppm or less. It is particularly preferred that it is preferably 35 ppm or less, and more preferably 25 ppm or less. When the average linear expansion coefficient is equal to or less than the above-mentioned upper limit value, the difference between the linear expansion coefficient of the adhesive layer 13 and the semiconductor wafer composed of the hardened material becomes small. Based on this difference, the gap between the adhesive layer 13 and the semiconductor wafer can be reduced. Possible stress. As a result, the three-dimensional multi-layer bulk-layer circuit manufacturing plates 1 and 2 of this embodiment can connect semiconductor wafers to each other. The continuous reliability becomes higher, especially the temperature cycle test shown in the examples, and it becomes the one with higher continuous reliability.

另一方面,平均線膨脹係數的下限值係沒有特別限制,從薄膜形成性的觀點而言,以5ppm以上為佳,以10ppm以上為較佳。 On the other hand, the lower limit value of the average linear expansion coefficient is not particularly limited, and from the viewpoint of film formability, it is preferably 5 ppm or more, and more preferably 10 ppm or more.

在此,構成接著劑層13之材料的平均線膨脹係數,係能夠使用熱機械分析裝置而測定。具體而言,係針對在基材上形成厚度45μm的接著劑層13之後,藉由在160℃進行處理1小時使接著劑層13硬化而得到的硬化物,使用熱機械分析裝置(Bruker AXS公司製、TMA4030SA),在荷重2g、溫度範圍0~300℃、升溫速度5℃/min的條件下測定線膨脹係數。從該測定結果,能夠算出在0~130℃的平均線膨脹係數。 Here, the average linear expansion coefficient of the material constituting the adhesive layer 13 can be measured using a thermomechanical analysis device. Specifically, a cured product obtained by forming a 45 μm thick adhesive layer 13 on a substrate and curing the adhesive layer 13 by treating at 160 ° C. for one hour was performed using a thermomechanical analysis device (Bruker AXS Corporation). Co., Ltd., TMA4030SA), the linear expansion coefficient was measured under the conditions of a load of 2 g, a temperature range of 0 to 300 ° C, and a temperature increase rate of 5 ° C / min. From this measurement result, the average linear expansion coefficient at 0 to 130 ° C can be calculated.

(2-4)玻璃轉移溫度 (2-4) Glass transition temperature

在本實施形態,構成接著劑層13之材料,其硬化物的玻璃轉移溫度(Tg)之下限值,係以150℃以上為佳,以200℃以上為更佳,以240℃以上為特佳。硬化物的玻璃轉移溫度為上述下限值以上時,因為在溫度循環試驗時硬化物不變形且不容易產生應力,乃是較佳。另一方面,硬化物的玻璃轉移溫度之上限值係沒有特別限制,從抑制硬化物脆化的觀點而言,係以350℃以下為佳,以300℃以下為較佳。 In this embodiment, the lower limit of the glass transition temperature (Tg) of the material constituting the adhesive layer 13 is preferably 150 ° C or higher, more preferably 200 ° C or higher, and 240 ° C or higher. good. When the glass transition temperature of the cured product is equal to or higher than the above-mentioned lower limit value, it is preferable because the cured product does not deform and does not easily generate stress during the temperature cycle test. On the other hand, the upper limit of the glass transition temperature of the hardened material is not particularly limited. From the viewpoint of suppressing embrittlement of the hardened material, it is preferably 350 ° C or lower, and more preferably 300 ° C or lower.

在此,構成接著劑層13之材料的硬化物之玻璃轉移溫度,係使用動態黏彈性測定機器(TA Instruments公司製、DMA Q800),在頻率11Hz、振幅10μm且以升溫速度3℃/分鐘,測定使其從0℃起升溫至300℃為止且依照拉伸模式時的黏彈 性時之tanδ(損失彈性模數/儲存彈性模數)最大點的溫度。 Here, the glass transition temperature of the hardened material of the material constituting the adhesive layer 13 is a dynamic viscoelasticity measuring device (manufactured by TA Instruments, DMA Q800) at a frequency of 11 Hz, an amplitude of 10 μm, and a heating rate of 3 ° C./minute. Measure the viscoelasticity when the temperature is raised from 0 ° C to 300 ° C and the tensile mode is followed. The temperature at the maximum point of tan δ (loss modulus / storage modulus).

(2-5)5%質量減少溫度 (2-5) 5% mass reduction temperature

在本實施形態之三次元積體積層電路製造用板片1、2,構成接著劑層13之材料的硬化物,藉由熱重量測定之5%質量減少溫度,係以350℃以上為佳,特別是以360℃以上為佳。藉由該5%質量減少溫度為350℃以上,接著劑層13的硬化物係成為對高溫的耐性優異者。因此,在積層電路的製造等,即便該硬化物被曝露在高溫時,亦能夠抑制伴隨著該硬化物的含有成分分解而產生揮發成分等,而能夠良好地維持積層電路的性能。又,該5%質量減少溫度的上限係沒有特別限定,但是該5%質量減少溫度,係通常以500℃以下為佳。 In the three-dimensional bulk layer circuit manufacturing plates 1 and 2 of this embodiment, the hardened material of the material constituting the adhesive layer 13 is 5% by mass weight reduction temperature measured by thermogravimetry, which is preferably 350 ° C or higher. In particular, 360 ° C or higher is preferred. When the 5% mass reduction temperature is 350 ° C. or higher, the hardened material of the adhesive layer 13 is excellent in resistance to high temperatures. Therefore, even when the cured product is exposed to a high temperature during the manufacture of the multilayer circuit, the generation of volatile components and the like due to the decomposition of the contained components of the cured product can be suppressed, and the performance of the multilayer circuit can be favorably maintained. The upper limit of the 5% mass reduction temperature is not particularly limited, but the 5% mass reduction temperature is usually preferably 500 ° C or lower.

在此,5%質量減少溫度,係能夠使用差示熱.熱重量同時測定裝置而測定。具體而言,係能夠針對在基材上形成厚度45μm的接著劑層13之後,藉由將所得到的試樣在160℃處理1小時使接著劑層13硬化而得到的硬化物,依據JIS K7120:1987且使用差示熱.熱重量同時測定裝置(島津製作所公司製、DTG-60),將氮氣作為流入氣體,以氣體流入速度100ml/min、升溫速度20℃/min使其從40℃起升溫至550℃為止,而進行熱重量測定。基於所得到的熱重量曲線,而求取相對於在溫度100℃的質量,質量減少5%之溫度(減少5%質量之溫度)。 Here, a 5% mass reduction temperature allows differential heat to be used. Thermogravimetric simultaneous measurement device. Specifically, the cured product can be obtained by forming a 45 μm thick adhesive layer 13 on a substrate, and then curing the adhesive layer 13 by treating the obtained sample at 160 ° C. for 1 hour, in accordance with JIS K7120. : 1987 and using differential heat. Simultaneous thermogravimetric measurement device (DTG-60, manufactured by Shimadzu Corporation), using nitrogen as the inflow gas, and increasing the temperature from 40 ° C to 550 ° C at a gas inflow rate of 100 ml / min and a temperature increase rate of 20 ° C / min. Thermogravimetric determination. Based on the obtained thermogravimetric curve, a temperature at which the mass is reduced by 5% relative to the mass at a temperature of 100 ° C. (a temperature at which the mass is reduced by 5%) is determined.

(2-6)儲存彈性模數 (2-6) Storage modulus

在本實施形態之三次元積體積層電路製造用板片1、2,接著劑層13硬化後之在23℃之儲存彈性模數,係以1.0×102MPa 以上為佳,特別是以1.0×103MPa以上為佳。又,該儲存彈性模數係以1.0×105MPa以下為佳,特別是以1.0×104MPa以下為佳。藉由該儲存彈性模數為上述範圍,在製造積層電路時,將半導體晶片與經個片化的接著劑層13交替地層積而成之積層體,係成為具有良好的強度者。其結果,即便進一步層積半導體晶片時或操作該積層體時,均能夠良好地維持積層體的狀態,而能夠製造具有優異的品質之積層電路。 In the three-dimensional bulk-layer circuit manufacturing plates 1 and 2 of this embodiment, the storage elastic modulus at 23 ° C. after the adhesive layer 13 is hardened is preferably 1.0 × 10 2 MPa or more, particularly 1.0 × 10 3 MPa or more is preferred. The storage elastic modulus is preferably 1.0 × 10 5 MPa or less, and particularly preferably 1.0 × 10 4 MPa or less. With the storage elastic modulus in the above range, a laminated body obtained by alternately laminating a semiconductor wafer and an individualized adhesive layer 13 when manufacturing a laminated circuit has a good strength. As a result, even when the semiconductor wafer is further laminated or the laminated body is operated, the state of the laminated body can be maintained well, and a laminated circuit having excellent quality can be manufactured.

在此,接著劑層13硬化後之在23℃之儲存彈性模數,係能夠使用動態黏彈性測定機器而測定。具體而言,係針對在基材上形成厚度45μm的接著劑層13之後,藉由在160℃處理1小時使接著劑層13硬化而得到的硬化物,使用動態黏彈性測定機器(TA Instruments公司製、DMA Q800),測定在頻率11Hz、振幅10μm,以升溫速度3℃/分鐘,使其從0℃升溫至300℃為止時之藉由拉伸模式所得的黏彈性。能夠從該測定結果,讀取接著劑層硬化後之在23℃之儲存彈性模數(MPa)。 Here, the storage elastic modulus at 23 ° C. after the adhesive layer 13 is hardened can be measured using a dynamic viscoelasticity measuring device. Specifically, a cured product obtained by forming an adhesive layer 13 having a thickness of 45 μm on a substrate and curing the adhesive layer 13 by treating at 160 ° C. for 1 hour was measured using a dynamic viscoelasticity measuring instrument (TA Instruments Corporation). Co., Ltd., DMA Q800), and measured the viscoelasticity obtained by the tensile mode at a frequency of 11 Hz, an amplitude of 10 μm, and a temperature increase rate of 3 ° C./minute to raise the temperature from 0 ° C. to 300 ° C. From this measurement result, the storage elastic modulus (MPa) at 23 ° C. after the adhesive layer is hardened can be read.

(2-7)藉由差示掃描熱量分析法之發熱起始溫度及發熱尖峰溫度 (2-7) Heating start temperature and heating peak temperature by differential scanning calorimetry

在本實施形態之三次元積體積層電路製造用板片1、2,在硬化前之接著劑層13,藉由差示掃描熱量分析(DSC)法,以升溫速度10℃/分鐘所測定的發熱起始溫度(TS),係以70℃~150℃的範圍為佳,特別是以100℃~150℃的範圍為佳,進一步以120℃~150℃的範圍為佳。藉由該發熱起始溫度(TS)為上述範圍,例如,能夠抑制在接受使用切割刀片切割半導體晶圓時所產生的熱量時於未蓄意的階段引起接著劑層13產生硬化,同 時製造用板片1、2的保存安定性亦優異。特別是為了製造積層電路,將複數個半導體晶片層積之後,將存在於半導體晶片之間之複數層的接著劑層13總括地使其硬化時,能夠抑制在半導體晶片積層完成前於未蓄意的階段引起接著劑層13產生硬化。 In the three-dimensional bulk layer circuit manufacturing plates 1 and 2 of this embodiment, the adhesive layer 13 before curing is measured by a differential scanning calorimetry (DSC) method at a heating rate of 10 ° C / min. The exothermic onset temperature (TS) is preferably in the range of 70 ° C to 150 ° C, particularly in the range of 100 ° C to 150 ° C, and more preferably in the range of 120 ° C to 150 ° C. By setting the heat generation temperature (TS) to the above range, for example, it is possible to prevent the adhesive layer 13 from being hardened at an unintended stage when the heat generated when the semiconductor wafer is cut using a dicing blade is received. The manufacturing sheets 1 and 2 are also excellent in storage stability. In particular, in order to manufacture a laminated circuit, after a plurality of semiconductor wafers are laminated, a plurality of layers of the adhesive layer 13 existing between the semiconductor wafers are collectively hardened, and it is possible to suppress unintended before the completion of the semiconductor wafer lamination. This stage causes the adhesive layer 13 to harden.

在本實施形態之三次元積體積層電路製造用板片1、2,在硬化前之接著劑層13,藉由差示掃描熱量分析(DSC)法,以升溫速度10℃/分鐘所測定的發熱尖峰溫度(TP),係以發熱起始溫度(TS)+5~60℃為佳,特別是以TS+5~50℃為佳,進一步以TS+10~40℃為佳。藉由該發熱尖峰溫度(TP)為上述範圍,在使接著劑層13硬化時,從硬化的開始至完成為止的時間係成為較短的時間。通常,使用NCF之接著劑而製造積層電路時,接著劑的硬化是需要時間的。因此,在積層電路的製造之生產作業時間(tact time),多半是依照接著劑的硬化時間來規定。因而,如上述藉由至接著劑層13硬化為止之時間為較短,能夠有效地縮短生產作業時間。特別是製造積層電路時,為了製程的效率化,係有將複數個半導體晶片層積(暫時放置)之後,最後總括地使存在於半導體晶片之間之複數層的接著劑層13硬化之情形。即便是此種情況,藉由該發熱尖峰溫度(TP)為上述範圍,能夠抑制在半導體晶片積層完成前於未蓄意的階段,引起存在於製程初期所層積的半導體晶片之間的接著劑層13產生硬化。 In the three-dimensional bulk layer circuit manufacturing plates 1 and 2 of this embodiment, the adhesive layer 13 before curing is measured by a differential scanning calorimetry (DSC) method at a heating rate of 10 ° C / min. The fever peak temperature (TP) is preferably the fever start temperature (TS) + 5 ~ 60 ° C, especially TS + 5 ~ 50 ° C, and more preferably TS + 10 ~ 40 ° C. When the heat generation peak temperature (TP) is in the above range, when the adhesive layer 13 is hardened, the time from the start to completion of the hardening becomes shorter. Generally, when a laminated circuit is manufactured using an NCF adhesive, it takes time to harden the adhesive. Therefore, the tact time in the manufacture of the multilayer circuit is mostly determined in accordance with the curing time of the adhesive. Therefore, as described above, since the time until the adhesive layer 13 is hardened is short, the production work time can be effectively shortened. In particular, when manufacturing a multilayer circuit, in order to improve the efficiency of the process, after laminating (temporarily placing) a plurality of semiconductor wafers, a plurality of layers of the adhesive layer 13 existing between the semiconductor wafers are finally hardened. Even in this case, by setting the heating peak temperature (TP) to the above-mentioned range, it is possible to prevent an adhesive layer existing between the semiconductor wafers laminated at the beginning of the process from occurring in an unintended stage before the semiconductor wafers are laminated. 13 produces hardening.

在此,上述發熱起始溫度及上述發熱尖峰溫度,係能夠使用差示掃描熱量計而測定。具體而言,係將厚度15mm 的接著劑層13使用差示掃描熱量計(TA Instruments公司製、Q2000),以升溫速度10℃/分鐘,從常溫起加熱至300℃為止。能夠從藉此而得到的DSC曲線求取發熱開始之溫度(發熱起始溫度)(TS)、及發熱尖峰溫度(TP)。 Here, the exothermic onset temperature and the exothermic peak temperature can be measured using a differential scanning calorimeter. Specifically, the thickness is 15mm The adhesive layer 13 was heated from normal temperature to 300 ° C. using a differential scanning calorimeter (TA 2000, Q2000) at a temperature increase rate of 10 ° C./minute. From the DSC curve obtained in this way, it is possible to obtain the temperature at which the heat starts (heating start temperature) (TS) and the heat peak temperature (TP).

(2-8)接著劑層的厚度等 (2-8) thickness of adhesive layer, etc.

在本實施形態之三次元積體積層電路製造用板片1、2,接著劑層13的厚度(T2)係以2μm以上為佳,特別是以5μm以上為佳,進一步以10μm以上為佳。又,該厚度(T2)係以500μm以下為佳,特別是以300μm以下為佳,進一步以100μm以下為佳。藉由接著劑層13的厚度(T2)為2μm以上,能夠將存在於半導體晶片之貫穿電極或凸塊良好地埋入至接著劑層13。又,藉由接著劑層13的厚度(T2)為500μm以下,在將具有貫穿電極之半導體晶片透過接著劑層13而接著時,接著劑層13不會過度地在側面滲出,而能夠製造可靠性較高的半導體裝置。又,接著劑層13的厚度(T2),係設定為在製造用板片1以50mm間隔、合計測定100點時之平均值。 In the three-dimensional bulk-layer circuit manufacturing plates 1 and 2 of this embodiment, the thickness (T2) of the adhesive layer 13 is preferably 2 μm or more, particularly preferably 5 μm or more, and further preferably 10 μm or more. The thickness (T2) is preferably 500 μm or less, particularly 300 μm or less, and further preferably 100 μm or less. When the thickness (T2) of the adhesive layer 13 is 2 μm or more, the through-electrodes or bumps existing in the semiconductor wafer can be favorably buried in the adhesive layer 13. In addition, when the thickness (T2) of the adhesive layer 13 is 500 μm or less, when a semiconductor wafer having a through electrode is passed through the adhesive layer 13 and then bonded, the adhesive layer 13 does not excessively ooze on the side surface, and can be manufactured reliably High-performance semiconductor device. The thickness (T2) of the adhesive layer 13 is set to an average value when 100 points are measured at a total interval of 50 mm at the manufacturing sheet 1.

在本實施形態之三次元積體積層電路製造用板片1、2,接著劑層13的厚度(T2)之標準偏差為2.0μm以下,以1.8μm以下為佳,特別是以1.6μm以下為佳。該標準偏差大於2.0μm時,在使用製造用板片1、2而將半導體晶圓的貫穿電極或凸塊埋入接著劑層13時,容易產生空隙,同時也使構成積層電路之接著劑層13的厚度及積層電路本身的厚度均勻化變得困難,其結果,積層電路的放熱性變成不充分。特別是因為積層電路係將半導體晶片及接著劑層13複數層積而得到 者,所以接著劑層13之厚度(T2)的標準偏差大於2.0μm時,所得到之有關積層電路厚度的均勻性受到損害,且該積層電路無法達成良好的放熱性。又,接著劑層13的厚度(T2)的標準偏差之測定方法,係如後述之試驗例所顯示。 The standard deviation of the thickness (T2) of the adhesive layer 13 in the three-dimensional bulk-layer circuit manufacturing plates 1 and 2 of this embodiment is 2.0 μm or less, preferably 1.8 μm or less, and particularly 1.6 μm or less. good. When the standard deviation is greater than 2.0 μm, when the through-electrodes or bumps of the semiconductor wafer are embedded in the adhesive layer 13 using the manufacturing plates 1 and 2, voids are likely to occur, and at the same time, the adhesive layer constituting the laminated circuit The thickness of 13 and the thickness of the multilayer circuit itself become difficult to uniformize, and as a result, the heat dissipation of the multilayer circuit becomes insufficient. In particular, the laminated circuit is obtained by laminating a semiconductor wafer and an adhesive layer 13 in plural. Therefore, when the standard deviation of the thickness (T2) of the adhesive layer 13 is greater than 2.0 μm, the uniformity of the thickness of the obtained multilayer circuit is impaired, and the multilayer circuit cannot achieve good heat dissipation. The method for measuring the standard deviation of the thickness (T2) of the adhesive layer 13 is shown in the test example described later.

在具備基材11之第2實施形態之三次元積體積層電路製造用板片2,接著劑層13的厚度(T2)對基材11的厚度(T1)之比(T2/T1),係以0.01以上為佳,特別是以0.1以上為佳,進一步以0.4以上為佳。又,該比(T2/T1)係以1.5以下為佳,特別是以1.0以下為佳,進一步以0.9以下為佳。藉由該比(T2/T1)為上述範圍,基材11與接著劑層13的厚度平衡係成為良好者,將製造用板片2貼附在半導體晶圓時的操作性優異,同時調整該貼附時的貼附適合性係變得容易。其結果,能夠良好地進行該貼附,且能夠製造具有優異的品質之積層電路。特別是藉由該比(T2/T1)為0.01以上,基材11在製造用板片1的相對厚度係成為較小者,能夠將製造用板片1的相對剛性抑制成為較低。其結果,在將製造用板片1貼附在半導體晶圓時,將存在於半導體晶圓的貫穿電極或凸塊良好地埋入至接著劑層13係變得容易。另一方面,藉由該比(T2/T1)為1.5以下,基材11在製造用板片1之相對厚度係成為較大者,且能夠將製造用板片1的相對剛性維持為較高。其結果,製造用板片1的操作性係成為優異者且容易將製造用板片1貼附在半導體晶圓。又,基材11的厚度(T1)係設為在製造用板片1以50mm間隔、合計測定100點時之平均值。 The ratio (T2 / T1) of the thickness (T2) of the adhesive layer 13 to the thickness (T1) of the substrate 11 in the three-dimensional bulk-layer circuit manufacturing sheet 2 having the second embodiment of the substrate 11 is It is preferably 0.01 or more, particularly preferably 0.1 or more, and further preferably 0.4 or more. The ratio (T2 / T1) is preferably 1.5 or less, particularly preferably 1.0 or less, and more preferably 0.9 or less. When the ratio (T2 / T1) is within the above range, the thickness balance between the substrate 11 and the adhesive layer 13 is good, and the workability when attaching the manufacturing sheet 2 to a semiconductor wafer is excellent. Applicability is easy when attaching. As a result, the lamination can be performed well and a laminated circuit having excellent quality can be manufactured. In particular, when the ratio (T2 / T1) is 0.01 or more, the relative thickness of the substrate 11 in the manufacturing sheet 1 becomes smaller, and the relative rigidity of the manufacturing sheet 1 can be suppressed low. As a result, when the manufacturing sheet 1 is attached to a semiconductor wafer, it becomes easy to embed the penetration electrodes or bumps existing in the semiconductor wafer in the adhesive layer 13 system. On the other hand, when the ratio (T2 / T1) is 1.5 or less, the relative thickness of the substrate 11 in the manufacturing sheet 1 becomes larger, and the relative rigidity of the manufacturing sheet 1 can be maintained high. . As a result, the operability of the manufacturing sheet 1 is excellent, and the manufacturing sheet 1 can be easily attached to a semiconductor wafer. The thickness (T1) of the base material 11 is an average value when a total of 100 points are measured at a 50 mm interval between the manufacturing sheet 1.

2.黏著劑層 2. Adhesive layer

(1)材料 (1) Materials

在具備黏著劑層12之第2實施形態之三次元積體積層電路製造用板片2,黏著劑層12可由非硬化性黏著劑所構成,或者亦可由硬化性黏著劑所構成。如後述,將本實施形態之三次元積體積層電路製造用板片2使用在積層電路的製造方法時,係將接著劑層13從基材11與黏著劑層12之積層體剝離。因此,從容易進行該剝離的觀點而言,黏著劑層12係以由硬化性黏著劑所構成且藉由硬化而黏著力降低者為佳。 In the plate 2 for manufacturing a three-dimensional bulk volume circuit of the second embodiment including the adhesive layer 12, the adhesive layer 12 may be made of a non-hardening adhesive or may be made of a hardening adhesive. As will be described later, when the three-dimensional multilayer bulk circuit circuit manufacturing sheet 2 of this embodiment is used in a multilayer circuit manufacturing method, the adhesive layer 13 is peeled from the laminated body of the substrate 11 and the adhesive layer 12. Therefore, from the viewpoint of facilitating the peeling, the adhesive layer 12 is preferably composed of a curable adhesive and the adhesive force is reduced by curing.

黏著劑層12係由硬化性黏著劑所構成時,該黏著劑可為能量線硬化性黏著劑,或者亦可為熱硬化性黏著劑。在此,為了使黏著劑層12與接著劑層13在不同的階段硬化,接著劑層13係具有熱硬化性時,黏著劑層12係以由能量線硬化性黏著劑所構成為佳,接著劑層13係具有能量線硬化性時,黏著劑層12係以由熱硬化性黏著劑所構成為佳。但是,因為接著劑層13係基於前述的理由而以具有熱硬化性為佳,所以黏著劑層12係以由能量線硬化性黏著劑所構成為佳。 When the adhesive layer 12 is composed of a hardenable adhesive, the adhesive may be an energy ray hardenable adhesive or a thermosetting adhesive. Here, in order to harden the adhesive layer 12 and the adhesive layer 13 at different stages, when the adhesive layer 13 is thermosetting, the adhesive layer 12 is preferably composed of an energy ray-curable adhesive. When the agent layer 13 is energy ray-curable, the adhesive layer 12 is preferably composed of a thermosetting adhesive. However, since the adhesive layer 13 is preferably thermosetting for the reasons described above, the adhesive layer 12 is preferably composed of an energy ray-curable adhesive.

作為上述非硬化性黏著劑,係以具有所需要的黏著力及再剝離性者為佳,例如能夠使用丙烯酸系黏著劑、橡膠系黏著劑、聚矽氧系黏著劑、胺甲酸酯系黏著劑、聚酯系黏著劑、聚乙烯醚系黏著劑等。該等之中,從有效地抑制在切割步驟於未蓄意的階段在黏著劑層12與接著劑層13之界面產生剝離的觀點而言,係以丙烯酸系黏著劑為佳。 The non-hardening adhesive is preferably one having a required adhesive force and re-peelability. For example, an acrylic adhesive, a rubber adhesive, a silicone adhesive, or a urethane adhesive can be used. Agents, polyester-based adhesives, polyvinyl ether-based adhesives, and the like. Among these, from the viewpoint of effectively suppressing peeling at the interface between the adhesive layer 12 and the adhesive layer 13 at an unintended stage of the cutting step, an acrylic adhesive is preferred.

作為上述能量線硬化性黏著劑,可為以具有能量線硬化性的聚合物作為主成分者,亦可為以非能量線硬化性聚 合物(不具有能量線硬化性之聚合物)與至少1種以上之具有能量線硬化性基的單體及/或寡聚物之混合物作為具有主成分者。又,亦可為具有能量線硬化性的聚合物與非能量線硬化性聚合物之混合物,亦可為具有能量線硬化性之聚合物與至少1種以上之具有能量線硬化性基的單體及/或寡聚物之混合物,亦可為該等3種的混合物。 The energy-ray-curable adhesive may be a polymer having energy-ray-curable polymer as a main component, or a polymer having non-energy-ray-curable polymer. A compound (a polymer having no energy ray curability) and a mixture of at least one or more monomers and / or oligomers having an energy ray curable group are those having a main component. Also, it may be a mixture of an energy ray-curable polymer and a non-energy ray-curable polymer, or may be an energy ray-curable polymer and at least one or more monomers having an energy ray-curable group. A mixture of oligomers and / or oligomers may also be a mixture of these three types.

上述具有能量線硬化性之聚合物,係以在側鏈導入有具有能量線硬化性的官能基(能量線硬化性基)之(甲基)丙烯酸酯(共)聚合物為佳。該聚合物係以使具有含官能基的單體單元之丙烯酸系共聚物、與具有鍵結在該官能基的官能基之不飽和基含有化合物反應而得到者為佳。 The polymer having energy ray curability is preferably a (meth) acrylate (co) polymer having a functional group (energy ray curable group) having energy ray curability introduced into a side chain. The polymer is preferably obtained by reacting an acrylic copolymer having a functional unit-containing monomer unit and an unsaturated group-containing compound having a functional group bonded to the functional group.

作為上述至少1種以上之具有能量線硬化性基的單體及/或寡聚物,例如能,夠使用多元醇與(甲基)丙烯酸的酯等。 As the at least one or more of the monomers and / or oligomers having an energy ray-curable group, for example, an ester of a polyhydric alcohol and (meth) acrylic acid can be used.

作為非能量線硬化性聚合物成分,例如,能夠使用具有前述之含官能基的聚合物單元之丙烯酸系共聚物。 As the non-energy-ray-curable polymer component, for example, an acrylic copolymer having the aforementioned functional unit-containing polymer unit can be used.

(2)物性等 (2) Physical properties, etc.

在本實施形態之三次元積體積層電路製造用板片2,黏著劑層12在23℃之儲存彈性模數,係以1×103Pa以上為佳,以1×104Pa以上為特佳。又,該儲存彈性模數係以1×109Pa以下為佳,以1×108Pa以下為特佳。又,黏著劑層12由硬化性黏著劑所構成時,係將該儲存彈性模數設為硬化前的儲存彈性模數。藉由黏著劑層12在23℃之儲存彈性模數為上述範圍,在將製造用板片2貼附在半導體晶圓時,能夠將存在於半導體晶 圓之貫穿電極或凸塊良好地埋入至接著劑層13。又,使用製造用板片1、2而將半導體晶圓之不形成凸塊的面進行背面研磨時,能夠抑制半導體晶圓產生翹曲或凹陷(dimple)。又,黏著劑層12在23℃之儲存彈性模數,係能夠使用,例如,動態黏彈性測定裝置(TA Instruments公司製、ARES),在頻率1Hz、測定溫度範圍-50~150℃、升溫速度3℃/min的條件下測定。 In the plate 2 for manufacturing a three-dimensional bulk-layer circuit of the present embodiment, the storage elastic modulus of the adhesive layer 12 at 23 ° C. is preferably 1 × 10 3 Pa or more, and 1 × 10 4 Pa or more is special good. The storage elastic modulus is preferably 1 × 10 9 Pa or less, and particularly preferably 1 × 10 8 Pa or less. When the adhesive layer 12 is composed of a curable adhesive, the storage elastic modulus is set to the storage elastic modulus before curing. When the storage elastic modulus of the adhesive layer 12 at 23 ° C. is in the above range, when the manufacturing plate 2 is attached to the semiconductor wafer, the penetration electrodes or bumps existing in the semiconductor wafer can be well embedded. To the adhesive layer 13. In addition, when the non-bumped surface of the semiconductor wafer is polished on the back surface using the manufacturing plates 1 and 2, it is possible to suppress the semiconductor wafer from being warped or dimpled. The storage elastic modulus of the adhesive layer 12 at 23 ° C can be used. For example, a dynamic viscoelasticity measuring device (manufactured by TA Instruments, ARES) can be used at a frequency of 1 Hz, a measurement temperature range of -50 to 150 ° C, and a temperature increase rate. Measured at 3 ° C / min.

黏著劑層12的厚度,係沒有特別限定,例如,以1μm以上為佳,以10μm以上為特佳。又,該厚度係例如,以100μm以下為佳,以50μm以下為特佳。藉由黏著劑層12的厚度為1μm以上,黏著劑層12能夠發揮良好的黏著力。又,藉由該厚度為100μm以下,能夠抑制黏著劑層12成為不需要的厚度,而能夠減低成本。 The thickness of the adhesive layer 12 is not particularly limited. For example, it is preferably 1 μm or more, and particularly preferably 10 μm or more. The thickness is, for example, preferably 100 μm or less, and particularly preferably 50 μm or less. When the thickness of the adhesive layer 12 is 1 μm or more, the adhesive layer 12 can exhibit good adhesion. In addition, when the thickness is 100 μm or less, the adhesive layer 12 can be prevented from becoming an unnecessary thickness, and the cost can be reduced.

3.基材 3. Substrate

(1)材料 (1) Materials

在具備基材11之第2實施形態之三次元積體積層電路製造用板片2,作為構成基材11之材料,係沒有特別限定。但是,將製造用板片2設為切割板片一體型接著板片(切割.晶片接合板片)時,構成基材11之材料,係以在構成切割板片之基材通常被使用的材料為佳。例如作為此種基材11的材料,可舉出聚乙烯、聚丙烯、聚丁烯、聚丁二烯、聚甲基戊烯、聚氯乙烯、氯乙烯共聚物、聚對苯二甲酸乙二酯、聚對苯二甲酸丁二酯、聚胺酯、乙烯乙酸乙烯酯共聚物、離子聚合物、乙烯.(甲基)丙烯酸共聚物、乙烯.(甲基)丙烯酸酯共聚物、聚苯乙烯、乙烯基聚異戊二烯、聚碳酸酯、聚烯烴等,該等之中,能夠使用1 種或2種以上的混合物。 As the material constituting the base material 11 in the three-dimensional multi-layer bulk-layer circuit manufacturing sheet 2 provided with the second embodiment of the base material 11, there is no particular limitation. However, when the manufacturing plate 2 is a dicing plate-integrated type bonding plate (cutting, wafer bonding plate), the material constituting the base material 11 is a material generally used for the base material constituting the dicing plate. Better. Examples of the material of the substrate 11 include polyethylene, polypropylene, polybutene, polybutadiene, polymethylpentene, polyvinyl chloride, vinyl chloride copolymer, and polyethylene terephthalate. Ester, polybutylene terephthalate, polyurethane, ethylene vinyl acetate copolymer, ionic polymer, ethylene. (Meth) acrylic copolymer, ethylene. (Meth) acrylate copolymer, polystyrene, vinyl polyisoprene, polycarbonate, polyolefin, etc. Among these, 1 can be used One or a mixture of two or more.

又,將製造用板片2設為背面研磨板片一體型接著板片時,構成基材11之材料,係以在構成背面研磨板片之基材通常被使用的材料為佳。例如作為此種基材11的材料,可舉出由聚對苯二甲酸乙二酯、聚乙烯、聚丙烯、乙烯.乙酸乙烯酯共聚物等的樹脂所構成者,該等之中,能夠使用一種或2種以上的混合物。 When the manufacturing plate 2 is a back-grinding plate integrated type bonding plate, the material constituting the base material 11 is preferably a material usually used for the base material constituting the back-grinding plate. Examples of the material of such a substrate 11 include polyethylene terephthalate, polyethylene, polypropylene, and ethylene. Among resins such as a vinyl acetate copolymer, one or a mixture of two or more of them can be used.

基材11之黏著劑層12側的面,亦可施行底漆處理、電暈處理、電漿處理等的表面處理,用以提高與黏著劑層12的密著性。 The surface on the side of the adhesive layer 12 of the base material 11 may also be subjected to surface treatments such as a primer treatment, a corona treatment, and a plasma treatment to improve the adhesion with the adhesive layer 12.

(2)物性等 (2) Physical properties, etc.

在本實施形態之三次元積體積層電路製造用板片2,基材11在23℃之拉伸彈性模數,係以100MPa以上為佳,特別是以200MPa以上為佳,進一步以300MPa以上為佳。又,該拉伸彈性模數係以5000MPa以下為佳,特別是以1000MPa以下為佳,進一步以400MPa以下為佳。藉由基材11在23℃之拉伸彈性模數為上述範圍內,將製造用板片2貼附在半導體晶圓時,能夠將存在於半導體晶圓之貫穿電極或凸塊良好地埋入至接著劑層13。又,將製造用板片2設為切割板片一體型接著板片時,藉由基材11在23℃之拉伸彈性模數為上述範圍內,在將製造用板片2擴展而擴大半導體晶片彼此的間隔時,因為基材11不容易斷裂,乃是較佳。又,基材11在23℃之拉伸彈性模數,能夠依據JISK 7127:1999,使用拉伸試驗機而測定。 In the plate 2 for manufacturing a three-dimensional bulk-layer circuit of this embodiment, the tensile elastic modulus of the substrate 11 at 23 ° C is preferably 100 MPa or more, particularly 200 MPa or more, and further 300 MPa or more. good. The tensile elastic modulus is preferably 5,000 MPa or less, particularly preferably 1000 MPa or less, and further preferably 400 MPa or less. When the substrate 11 has a tensile elastic modulus at 23 ° C within the above range, when the manufacturing sheet 2 is attached to a semiconductor wafer, the through-electrodes or bumps existing in the semiconductor wafer can be well embedded. To the adhesive layer 13. In addition, when the manufacturing sheet 2 is a cut-to-piece integrated type bonding sheet, the substrate 11 is stretched at 23 ° C. and the modulus of elasticity is within the above range, and the manufacturing sheet 2 is expanded to expand the semiconductor. When the wafers are spaced from each other, it is preferable because the substrate 11 is not easily broken. The tensile elastic modulus of the base material 11 at 23 ° C can be measured using a tensile tester in accordance with JISK 7127: 1999.

基材11的厚度(T1)係沒有特別限定,例如,以10μm 以上為佳,特別是以15μm以上為佳。又,該厚度(T1)係例如,以500μm以下為佳,特別是以100μm以下為佳。藉由基材11的厚度(T1)為上述範圍,能夠容易地將前述之接著劑層12的厚度(T2)對基材11的厚度(T1)之比(T2/T1)的值,設定在前述範圍,而且在將製造用板片1、2貼附在半導體晶圓時具有優異的操作性。其結果,能夠有效地製造品質優異的積層電路。 The thickness (T1) of the substrate 11 is not particularly limited. For example, the thickness (T1) is 10 μm. The above is preferable, and especially 15 μm or more is preferable. The thickness (T1) is, for example, preferably 500 μm or less, and particularly preferably 100 μm or less. When the thickness (T1) of the substrate 11 is in the above range, the value (T2 / T1) of the ratio (T2 / T1) of the thickness (T2) of the adhesive layer 12 to the thickness (T1) of the substrate 11 can be easily set at The aforementioned range also has excellent operability when attaching the manufacturing plates 1 and 2 to a semiconductor wafer. As a result, it is possible to efficiently manufacture a multilayer circuit having excellent quality.

4.剝離板片 4. Peel off the sheet

剝離板片14的構成為任意,例如,可舉出聚對苯二甲酸乙二酯、聚對苯二甲酸丁二酯、聚萘二甲酸乙二酯等的聚酯膜、聚丙烯、聚乙烯等的聚烯烴膜等的塑膠膜。該等的剝離面(與接著劑層13接觸之面)係以經施行剝離處理為佳。作為在剝離處理所使用的剝離劑,例如,可舉出聚矽氧系、氟系、長鏈烷基系等的剝離劑。 The configuration of the release sheet 14 is arbitrary, and examples thereof include polyester films such as polyethylene terephthalate, polybutylene terephthalate, and polyethylene naphthalate, polypropylene, and polyethylene. Polyolefin film and other plastic films. Such a release surface (a surface in contact with the adhesive layer 13) is preferably subjected to a release treatment. Examples of the release agent used in the release treatment include a release agent such as a silicone-based, fluorine-based, or long-chain alkyl-based release agent.

針對剝離板片的厚度,係沒有特別限制,通常為20μm以上、250μm以下。 The thickness of the release sheet is not particularly limited, but is usually 20 μm or more and 250 μm or less.

5.三次元積體積層電路製造用板片之製造方法 5. Manufacturing method of plate for manufacturing three-dimensional product volume layer circuit

第1實施形態之三次元積體積層電路製造用板片1,係能夠與先前的三次元積體積層電路製造用板片同樣地製造。例如,製造具備剝離板片14之三次元積體積層電路製造用板片1時,能夠藉由調製含有前述的熱傳導性填料、其它構成接著劑層13之材料、及依照需要而進一步含有溶劑或分散介質之塗佈液,使用模塗佈器、簾流塗佈器、噴霧塗佈器、狹縫塗佈器、刮刀塗佈器等將該塗佈液塗佈在剝離板片14的剝離面上而形成塗膜,使該塗膜乾燥,以製造製造用板片2。塗佈液係只要 能夠進行塗佈,其性狀就沒有特別限定,有將用以形成接著劑層13之成分以溶質的方式含有之情形,亦有以分散質的方式含有之情形。剝離板片14亦可剝離作為製程材料,亦可在直到貼附於半導體晶圓之期間,保護接著劑層13。 The three-dimensional bulk-layer circuit manufacturing sheet 1 of the first embodiment can be manufactured in the same manner as the conventional three-dimensional bulk-layer circuit manufacturing sheet. For example, when manufacturing the three-dimensional bulk-layer circuit manufacturing sheet 1 provided with the peeling sheet 14, it is possible to further contain a solvent or The coating liquid for the dispersion medium is coated on the release surface of the release sheet 14 using a die coater, a curtain coater, a spray coater, a slit coater, a blade coater, or the like. A coating film is formed thereon, and the coating film is dried to manufacture a manufacturing sheet 2. Coating liquid as long as The coating can be applied, and its properties are not particularly limited, and there may be a case where the component for forming the adhesive layer 13 is contained as a solute, or a case where it is contained as a dispersant. The release sheet 14 may be peeled as a process material, and the adhesive layer 13 may be protected until it is attached to the semiconductor wafer.

又,作為在三次元積體積層電路製造用板片1的兩面各自層積2層的剝離板片14而成之積層體的製造方法,能夠將塗佈液塗佈前述的剝離板片14之剝離面上而形成塗膜,使其乾燥而形成由接著劑層13及剝離板片14所構成之積層體,將該積層體在接著劑層13之與剝離板片14為相反的面,貼附在其它剝離板片14的剝離面,而得到由剝離板片14/接著劑層13/剝離板14所構成之積層體。在該積層體之剝離板片14亦可剝離作為製程材料,亦可在直到貼附於半導體晶圓之期間,保護接著劑層13。 In addition, as a method for producing a laminated body in which two layers of release sheets 14 are laminated on both sides of the three-dimensional multilayer circuit manufacturing sheet 1, a coating solution can be applied to the aforementioned release sheet 14. A coating film is formed on the peeling surface, and it is dried to form a laminate composed of the adhesive layer 13 and the release sheet 14. The laminate is applied to the surface of the adhesive layer 13 which is opposite to the release sheet 14 and is applied. It is attached to the release surface of the other release sheet 14 to obtain a laminated body composed of the release sheet 14 / adhesive layer 13 / release sheet 14. The release sheet 14 of the laminate may be peeled as a process material, and the adhesive layer 13 may be protected until it is attached to the semiconductor wafer.

第2實施形態之三次元積體積層電路製造用板片2,係能夠與先前的三次元積體積層電路製造用板片2同樣地製造。例如,能夠藉由各自製造接著劑層13與剝離板片14的積層體、及黏著劑層12與基材11的積層體,以接著劑層13與黏著劑層12接觸之方式將該等積層體貼合,以得到製造用板片2。 The plate 2 for manufacturing a three-dimensional bulk-layer circuit of the second embodiment can be manufactured in the same manner as the plate 2 for manufacturing a three-dimensional bulk-layer circuit. For example, the laminated body of the adhesive layer 13 and the release sheet 14 and the laminated body of the adhesive layer 12 and the base material 11 can be manufactured by making the laminated layer of the adhesive layer 13 and the adhesive layer 12 in contact with each other. Body-fitted to obtain a manufacturing sheet 2.

接著劑層13與剝離板片14之積層體,係能夠藉由調製用以形成接著劑層13之前述的塗佈液,使用前述的塗佈方法塗佈在剝離板片14的剝離面上而形成塗膜,使該塗膜乾燥而得到。 The laminated body of the adhesive layer 13 and the release sheet 14 can be prepared by applying the aforementioned coating solution to form the adhesive layer 13 and applying the aforementioned coating method to the release surface of the release sheet 14. A coating film is formed, and this coating film is dried and obtained.

作為上述溶劑,可舉出甲苯、乙酸乙酯、甲基乙 基酮的有機溶劑等。藉由調配該等有機溶劑而成為適當的固體成分濃度之溶液,能夠更加抑制接著劑層13的厚度(T2)的偏差,而且針對厚度(T2),能夠有效地形成具有前述的標準偏差之接著劑層13。從使塗佈液均勻地塗佈的觀點而言,特別是塗佈液的固體成分濃度,係以5質量%以上為佳,特別是以10質量%以上為佳。又,從同樣的觀點而言,該固體成分濃度係以55質量%以下為佳,以50質量%以下為佳。藉由該固體成分濃度為5質量%以上,在形成塗膜時能夠抑制收縮等的發生,同時容易使溶劑充分地乾燥,且更容易抑制接著劑層13的厚度或物性的偏差。其結果,將接著劑層13的厚度(T2)的標準偏差調整在前述的範圍之內係變得容易。又,藉由該固體成分濃度為55質量%以下,能夠抑制塗佈液中的填料產生凝聚,而容易將塗佈液送液,且能夠抑制在對塗佈方向為垂直的方向連續地產生塗佈不均(橫向波狀不均),且能夠抑制接著劑層13的厚度偏差的發生。上述塗佈液之使用B型黏度計所測定之在25℃的黏度,係以20mPa.s以上為佳,特別是以25mPa.s以上為佳。又,該黏度係以500mPa.s以下為佳,特別是以100mPa.s以下為佳。 Examples of the solvent include toluene, ethyl acetate, and methyl ethyl. Organic solvents such as ketones. By formulating these organic solvents to a solution having an appropriate solid content concentration, it is possible to further suppress the variation in the thickness (T2) of the adhesive layer 13 and to effectively form an adhesive having the aforementioned standard deviation for the thickness (T2).剂 层 13。 Agent layer 13. From the viewpoint of uniformly applying the coating liquid, the solid content concentration of the coating liquid is particularly preferably 5% by mass or more, and particularly preferably 10% by mass or more. From the same viewpoint, the solid content concentration is preferably 55% by mass or less, and more preferably 50% by mass or less. When the solid content concentration is 5% by mass or more, it is possible to suppress the occurrence of shrinkage and the like when forming a coating film, to easily dry the solvent sufficiently, and to more easily suppress variations in the thickness or physical properties of the adhesive layer 13. As a result, it becomes easy to adjust the standard deviation of the thickness (T2) of the adhesive layer 13 within the aforementioned range. In addition, when the solid content concentration is 55% by mass or less, it is possible to suppress the agglomeration of the filler in the coating liquid, facilitate the feeding of the coating liquid, and suppress the continuous generation of coating in a direction perpendicular to the coating direction. The cloth is uneven (transverse wave-like unevenness), and the occurrence of thickness deviation of the adhesive layer 13 can be suppressed. The viscosity of the coating liquid at 25 ° C measured with a B-type viscometer was 20 mPa. Above s is preferred, especially 25mPa. Above s is preferred. The viscosity is 500 mPa. Below s is preferred, especially 100mPa. The following s is preferred.

黏著劑層12與基材11的積層體,係能夠藉由調製含有構成黏著劑層12的材料、及依照需要而進一步含有溶劑或分散介質之塗佈液,依照前述的塗佈方法塗佈在基材11的一面而形成塗膜,使該塗膜乾燥而得到。又,作為黏著劑層12與基材11的積層體之另外的製造方法,係將黏著劑層12形成在製程用剝離板片的剝離面上,隨後將該黏著劑層12轉 印至基材11的一面,將製程用剝離板片從黏著劑層12剝離,以得到黏著劑層12與基材11之積層體。 The laminated body of the adhesive layer 12 and the base material 11 can be prepared by preparing a coating liquid containing a material constituting the adhesive layer 12 and further containing a solvent or a dispersion medium as required, and applying the coating solution in accordance with the aforementioned coating method. A coating film is formed on one surface of the base material 11, and the coating film is obtained by drying. As another method for manufacturing a laminated body of the adhesive layer 12 and the base material 11, the adhesive layer 12 is formed on a release surface of a release sheet for a manufacturing process, and then the adhesive layer 12 is rotated. After printed on one side of the substrate 11, the release sheet for the process is peeled from the adhesive layer 12 to obtain a laminated body of the adhesive layer 12 and the substrate 11.

[三次元積體積層電路之製造方法] [Manufacturing method of three-dimensional product volume layer circuit]

使用本實施形態之三次元積體積層電路製造用板片1、2,能夠製造三次元積體積層電路。以下,說明其製造方法的例子。 By using the three-dimensional multi-layered circuit manufacturing plates 1 and 2 of this embodiment, a three-dimensional multi-layered circuit can be manufactured. An example of the manufacturing method will be described below.

首先,將本實施形態之三次元積體積層電路製造用板片1、2貼附在具有貫穿電極之半導體晶圓的一面。具體而言,係將三次元積體積層電路製造用板片1、2之接著劑層13側的面貼附在半導體晶圓的一面。 First, the three-dimensional bulk-layer circuit manufacturing plates 1 and 2 of this embodiment are attached to one side of a semiconductor wafer having a through electrode. Specifically, the surface on the side of the adhesive layer 13 of the three-dimensional bulk-layer circuit manufacturing plates 1 and 2 is attached to one surface of the semiconductor wafer.

又,具有貫穿電極之半導體晶圓,係有強度較弱的情況。因此,亦可藉由透過暫時固定材而固定在支撐玻璃等的支撐物,以補強半導體晶圓。此時,係將該積層體上之半導體晶圓側的面與三次元積體積層電路製造用板片1、2貼合之後,將支撐物與暫時固定材同時剝離。 In addition, a semiconductor wafer having a through electrode may be weak. Therefore, the semiconductor wafer can be reinforced by being fixed to a support such as a support glass through a temporary fixing material. At this time, after the surface on the side of the semiconductor wafer on the laminated body is bonded to the three-dimensional stacked volume circuit manufacturing plates 1 and 2, the support and the temporary fixing material are peeled off at the same time.

使用本實施形態1之三次元積體積層電路製造用板片1時,係進一步層積切割板片。此時,可先對半導體晶圓貼附切割板片,然後將製造用板片1貼附在該半導體晶圓之與切割板片為相反側的面。又,亦可先對半導體晶圓貼附製造用板片1,然後將切割板片貼附在該半導體晶圓之與製造用板片1為相反側的面。或者,亦可在將切割板片貼附在對半導體晶圓貼附製造用板片1而得到之積層體的製造用板片1之側的面。另一方面,使用第2實施形態之三次元積體積層電路製造用板片2時,不必進一步層積切割板片,而能夠在該製造用板片2上,進行以下的切割步驟。 When the three-dimensional multi-layer bulk-layer circuit manufacturing sheet 1 of the first embodiment is used, the cutting sheet is further laminated. At this time, a dicing sheet may be attached to the semiconductor wafer, and then the manufacturing sheet 1 may be attached to a surface of the semiconductor wafer on the side opposite to the dicing sheet. Alternatively, a manufacturing wafer 1 may be attached to a semiconductor wafer, and then a dicing wafer may be attached to a surface of the semiconductor wafer opposite to the manufacturing wafer 1. Alternatively, the dicing sheet may be attached to the side of the manufacturing sheet 1 for a laminated body obtained by attaching the manufacturing sheet 1 to a semiconductor wafer. On the other hand, in the case of using the three-dimensional stacked bulk layer circuit manufacturing sheet 2 of the second embodiment, it is not necessary to further laminate the cutting sheets, and the following cutting steps can be performed on the manufacturing sheet 2.

接著,將半導體晶圓切斷成為個別的晶片(切割步驟)。此時,係在將半導體晶圓切斷之同時,亦將接著劑層13切斷。晶圓的切斷方法係沒有特別限定,能夠使用先前習知的各種切割方法來進行。例如,可舉出使用切割刀片而將半導體晶圓切斷之方法。又,亦可採用雷射切割等的其它切割方法。 Next, the semiconductor wafer is cut into individual wafers (dicing step). At this time, at the same time as the semiconductor wafer is cut, the adhesive layer 13 is also cut. The method of cutting the wafer is not particularly limited, and can be performed using various conventionally known cutting methods. For example, the method of cutting a semiconductor wafer using a dicing blade is mentioned. Alternatively, other cutting methods such as laser cutting may be used.

切割步驟之後,拾取半導體晶片。此時,該半導體晶片係在貼附有經個片化的接著劑層13之狀態下被拾取。亦即,貼附有接著劑層13之半導體晶片,係從切割板片的黏著劑層或三次元積體積層電路製造用板片2的黏著劑層12被剝離。又,黏著劑層12由能量線硬化性黏著劑所構成時,係以在拾取前對黏著劑層12照射能量線為佳。藉此,因為該黏著劑的黏著力低落,所以半導體晶片的拾取變得容易。又,亦可視需要,在拾取之前,藉由擴展切割板片或三次元積體積層電路製造用板片2,以擴大半導體晶片彼此的間隔。 After the dicing step, the semiconductor wafer is picked up. At this time, the semiconductor wafer is picked up in a state where the singulated adhesive layer 13 is attached. That is, the semiconductor wafer to which the adhesive layer 13 is attached is peeled off from the adhesive layer of the dicing sheet or the adhesive layer 12 of the three-dimensional bulk layer circuit manufacturing sheet 2. When the adhesive layer 12 is composed of an energy ray-curable adhesive, it is preferable to irradiate the adhesive layer 12 with energy rays before picking up. Thereby, since the adhesive force of this adhesive agent is low, it becomes easy to pick up a semiconductor wafer. In addition, if necessary, before picking up, the expanded cutting plate or the three-dimensional multi-layer volume circuit manufacturing plate 2 is used to expand the interval between the semiconductor wafers.

接著,將附接著劑層之半導體晶片載置在電路基板上。附接著劑層之半導體晶片,係以半導體晶片側的電極與電路基板上的電極為相向的方式對準,而被載置電路基板上。 Next, the semiconductor wafer with the adhesive layer was placed on a circuit board. The semiconductor wafer with the adhesive layer is placed on the circuit substrate so that the electrodes on the semiconductor wafer side and the electrodes on the circuit substrate face each other.

接著,將附接著劑層之半導體晶片與電路基板進行加熱.加壓後,進行冷卻。藉此,透過接著劑層13而將半導體晶片與電路基板接著,半導體晶片的電極與在電路基板之晶片搭載部的電極,係透過在半導體晶片所形成的焊料凸塊而被電性接合。焊接的條件,亦取決於所使用的金屬組成物,例如Sn-Ag時,係以在200~300℃加熱1~30秒鐘為佳。 Next, the semiconductor wafer and the circuit board with the adhesive layer are heated. After pressurizing, cooling is performed. Thereby, the semiconductor wafer and the circuit substrate are bonded through the adhesive layer 13, and the electrodes of the semiconductor wafer and the electrodes on the wafer mounting portion of the circuit substrate are electrically bonded through solder bumps formed on the semiconductor wafer. The welding conditions also depend on the metal composition used. For example, when Sn-Ag is used, it is better to heat at 200 to 300 ° C for 1 to 30 seconds.

進行焊接後,係使介於半導體晶片與電路基板之 間的接著劑層13硬化。硬化係能夠藉由,例如,在100~200℃加熱1~120分鐘來進行。又,此種硬化步驟亦可在加壓條件下進行。又,在上述的焊接步驟,接著劑層13的硬化結束之情況,此種硬化步驟亦可省略。 After soldering, the semiconductor wafer and circuit board The intermediate adhesive layer 13 is hardened. The hardening system can be performed, for example, by heating at 100 to 200 ° C for 1 to 120 minutes. Such a hardening step may be performed under pressure. In addition, in the case where the hardening of the adhesive layer 13 is completed in the aforementioned welding step, such a hardening step may be omitted.

接著,在如上述地被接著在電路基板上之半導體晶片上,層積新的附接著劑層之半導體晶片。此時,係以新的附接著劑層之半導體晶片之接著劑層13側的面、與被層積在電路基板上之半導體晶片之與電路基板為反對側的面接觸,而且以將2個半導體晶片的貫穿電極彼此電性連接之方式層積。隨後,在新被層積之半導體晶片的貫穿電極、與被層積在電路基板上之半導體晶片的貫穿電極之間進行焊接,進而使介於該等半導體晶片之間的接著劑層13硬化。此時的焊接及接著劑層13的硬化,係能夠使用上述的方法及條件而進行。藉此,能夠得到在電路基板上層積有2個半導體晶片而成之積層體。 Next, a semiconductor wafer with a new adhesive layer is laminated on the semiconductor wafer adhered to the circuit substrate as described above. At this time, the surface of the new semiconductor wafer with the adhesive layer on the side of the adhesive layer 13 and the surface of the semiconductor wafer laminated on the circuit substrate on the side opposite to the circuit substrate are contacted, and two The through electrodes of the semiconductor wafer are laminated in such a manner that they are electrically connected to each other. Subsequently, soldering is performed between the through electrodes of the newly laminated semiconductor wafer and the through electrodes of the semiconductor wafer laminated on the circuit substrate, and the adhesive layer 13 interposed between these semiconductor wafers is hardened. The welding and hardening of the adhesive layer 13 at this time can be performed using the method and conditions described above. Thereby, a laminated body in which two semiconductor wafers are laminated on a circuit board can be obtained.

重複如以上之在被層積在電路基板上的半導體晶片上,層積附接著劑層之半導體晶片、進行焊接及接著劑層13硬化之步驟,能夠得到藉由接著劑層13的硬化物將複數個半導體晶片接著而成之積層電路。在此種積層電路,藉由接著劑層13含有熱傳導性填料,同時接著劑層13的厚度(T2)之標準偏差為前述範圍,積層電路係成為放熱性優異者。因而,藉由使用本實施形態之三次元積體積層電路製造用板片1、2,能夠製造具有較高的可靠性之積層電路。 Repeating the steps of laminating a semiconductor wafer with an adhesive layer, soldering, and curing the adhesive layer 13 on the semiconductor wafer laminated on the circuit substrate as described above, the cured product of the adhesive layer 13 can be obtained. A laminated circuit formed by a plurality of semiconductor wafers. In such a laminated circuit, since the adhesive layer 13 contains a thermally conductive filler, and the standard deviation of the thickness (T2) of the adhesive layer 13 is in the aforementioned range, the laminated circuit system is excellent in heat dissipation. Therefore, by using the three-dimensional multilayer volume circuit manufacturing plates 1 and 2 of this embodiment, a multilayer circuit having high reliability can be manufactured.

又,在以上所說明的積層電路之製造方法,係每層積1個半導體晶片,就進行焊接及接著劑層13的硬化,但 是為了製程的效率化,亦可層積複數個半導體晶片之後,最後總括地進行該等半導體晶片之間的焊接、及介於該等半導體晶片之間的接著劑層13的硬化。 In the method for manufacturing a multilayer circuit described above, one semiconductor wafer is laminated for each layer, and soldering and curing of the adhesive layer 13 are performed. This is to improve the efficiency of the manufacturing process. After laminating a plurality of semiconductor wafers, the semiconductor wafers can be soldered together and the adhesive layer 13 can be hardened between the semiconductor wafers.

以上所說明的實施形態,係為了容易理解本發明而記載,而不是用以限定本發明而記載。因而,上述實施形態所揭示的各要素,係包含屬於本發明的技術範圍之全部設計變更和均等物之宗旨。 The embodiments described above are described for easy understanding of the present invention, and are not described to limit the present invention. Therefore, each element disclosed in the above-mentioned embodiment is intended to include all design changes and equivalents belonging to the technical scope of the present invention.

[實施例] [Example]

以下,揭示實施例及試驗例等而更詳細地說明本發明,但是本發明係完全不被下述試驗例等限定。 Hereinafter, the present invention will be described in more detail by revealing examples, test examples, and the like, but the present invention is not limited at all by the following test examples and the like.

[實施例1~7、比較例1] [Examples 1 to 7, Comparative Example 1]

將含有表1顯示的構成成分之組成物,使用甲基乙基酮以固體成分濃度成為40質量%的方式稀釋,而得到塗佈液。使用B型黏度計而測定該塗佈液在25℃之黏度時為50mPa.s。將該塗佈液塗佈在經聚矽氧處理之剝離膜(LINTEC公司製、SP-PET381031)上,藉由將所得到的塗膜在烘箱且於100℃乾燥1分鐘,而得到由厚度45μm的接著劑層與剝離膜所構成之第1積層體。 A composition containing the constituent components shown in Table 1 was diluted with methyl ethyl ketone so that the solid content concentration became 40% by mass to obtain a coating liquid. Using a B-type viscometer to measure the viscosity of the coating solution at 25 ° C was 50 mPa. s. This coating solution was coated on a silicone-treated release film (manufactured by LINTEC, SP-PET381031), and the obtained coating film was dried in an oven at 100 ° C. for 1 minute to obtain a thickness of 45 μm. The first laminated body composed of an adhesive layer and a release film.

將使丙烯酸2-乙基己酯80質量份、丙烯酸甲酯10質量份及丙烯酸2-羥基乙酯10質量份共聚合而成之丙烯酸共聚物(重量平均分子量:70萬)100質量份(固體成分換算值;以下相同)、與異氰酸酯系交聯劑(Polyurethane工業公司製、CORONATE L)10質量份混合,以調製黏著劑組成物。 100 parts by mass of an acrylic copolymer (weight average molecular weight: 700,000) (solid) obtained by copolymerizing 80 parts by mass of 2-ethylhexyl acrylate, 10 parts by mass of methyl acrylate, and 10 parts by mass of 2-hydroxyethyl acrylate Component conversion value; the same applies hereinafter), and 10 parts by mass of an isocyanate-based crosslinking agent (manufactured by Polyurethane Industries, CORONATE L) was mixed to prepare an adhesive composition.

將如上述而得到的黏著劑組成物,塗佈在作為基 材之乙烯-甲基丙烯酸共聚物(EMAA)膜(厚度:100μm)的一面而形成塗膜。隨後,使塗膜在100℃乾燥1分鐘。藉此,得到由厚度10μm的黏著劑層與基材所構成之第2積層體。使用後述的方法測定該黏著劑層在23℃之儲存彈性模數時為4.6×105Pa。 The adhesive composition obtained as described above was applied to one surface of an ethylene-methacrylic acid copolymer (EMAA) film (thickness: 100 μm) as a base material to form a coating film. Subsequently, the coating film was dried at 100 ° C for 1 minute. Thereby, a second laminated body composed of an adhesive layer with a thickness of 10 μm and a substrate was obtained. The storage elastic modulus of this adhesive layer at 23 ° C. was measured by a method described later to be 4.6 × 10 5 Pa.

接著,藉由將第1積層體之接著劑層側的面、與第2積層體之黏著劑層側的面貼合,而得到三次元積體積層電路製造用板片。 Next, a surface of the first multilayer body on the adhesive layer side and a surface of the second multilayer body on the adhesive layer side were bonded to obtain a three-dimensional bulk volume circuit manufacturing plate.

[比較例2] [Comparative Example 2]

將含有表1顯示的構成成分之組成物,使用甲基乙基酮以固體成分濃度成為55質量%之方式稀釋,以得到塗佈液。使用B型黏度計測定該塗佈液在25℃的黏度時為150mPa.s。使用該塗佈液形成接著劑層,除此之外,係與實施例1同樣地進行而得到三次元積體積層電路製造用板片。 A composition containing the constituent components shown in Table 1 was diluted with methyl ethyl ketone so that the solid content concentration became 55% by mass to obtain a coating liquid. The viscosity of the coating liquid at 25 ° C was 150 mPa using a B-type viscometer. s. Except having used this coating liquid to form an adhesive layer, it carried out similarly to Example 1, and obtained the board | substrate for manufacture of a three-dimensional bulk volume circuit.

在此,表1顯示之構成成分的詳細係如以下。 The details of the constituent components shown in Table 1 are as follows.

高分子量成分 High molecular weight ingredients

.雙酚A(BPA)/雙酚F(BPF)共聚合型苯氧基樹脂:東都化成公司製、製品名「ZX-1356-2」、玻璃轉移溫度71℃、重量平均分子量6萬 . Bisphenol A (BPA) / Bisphenol F (BPF) copolymerized phenoxy resin: manufactured by Toto Kasei Co., Ltd., product name "ZX-1356-2", glass transition temperature of 71 ° C, weight average molecular weight 60,000

熱硬化性成分 Thermosetting component

.環氧樹脂1:參(羥苯基)甲烷型固體環氧樹脂、JAPAN EPOXY RESINS公司製、製品名「E1032H60」、5重量%減少溫度350℃、固體、熔點60℃ . Epoxy resin 1: Ginseng (hydroxyphenyl) methane type solid epoxy resin, manufactured by JAPAN EPOXY RESINS, product name "E1032H60", 5% weight reduction temperature 350 ° C, solid, melting point 60 ° C

.環氧樹脂2:Bis-F型液狀環氧樹脂、JAPAN EPOXY RESINS公司製、製品名「YL-983U」、環氧基當量184 . Epoxy resin 2: Bis-F liquid epoxy resin, JAPAN EPOXY Manufactured by RESINS, product name "YL-983U", epoxy equivalent 184

.環氧樹脂3:長鏈Bis-F改性型環氧樹脂、JAPAN EPOXY RESINS公司製、製品名「YL-7175」 . Epoxy resin 3: Long chain Bis-F modified epoxy resin, made by JAPAN EPOXY RESINS, product name "YL-7175"

硬化觸媒 Hardening catalyst

.2MZA-PW:2,4-二胺基-6-[2’-甲基咪唑基-(1’)]-乙基-s-三嗪、四國化成工業公司製、製品名「2MZA-PW」、熔點250℃助焊劑成分 . 2MZA-PW: 2,4-diamino-6- [2'-methylimidazolyl- (1 ')]-ethyl-s-triazine, manufactured by Shikoku Chemical Industry Co., Ltd., product name "2MZA-PW "Flux composition with a melting point of 250 ° C

.松香衍生物:荒川化學工業製,軟化點124~134℃無機填料 . Rosin derivative: Arakawa Chemical Industry, softening point: 124 ~ 134 ℃ inorganic filler

填料 filler

.熱傳導性填料(球狀氧化鋁);球狀氧化鋁、電氣化學工業公司製、製品名「DAM-0」、平均粒徑3μm、熱傳導率40W/m.K . Thermally conductive filler (spherical alumina); spherical alumina, manufactured by Denki Chemical Industry Co., Ltd., product name "DAM-0", average particle size 3 μm, thermal conductivity 40 W / m. K

.熱傳導性填料(球狀氧化鋅):球狀氧化鋅、堺化學工業公司製、平均粒徑0.6μm、熱傳導率54W/m.K . Thermally conductive filler (spherical zinc oxide): spherical zinc oxide, manufactured by Sakai Chemical Industry Co., Ltd., with an average particle diameter of 0.6 μm and a thermal conductivity of 54 W / m. K

.熱傳導性填料(氮化硼):氮化硼、昭和電工公司製、製品名「UHP-2」、形狀:板狀、平均粒徑11.8μm、縱橫比11.2、長軸方向的熱傳導率200W/m.K . Thermally conductive filler (boron nitride): boron nitride, manufactured by Showa Denko Corporation, product name "UHP-2", shape: plate-like, average particle diameter 11.8 μm, aspect ratio 11.2, thermal conductivity in major axis direction 200 W / m . K

.熔融氧化矽填料:平均粒徑3μm、熱傳導率2W/m.K . Fused silica filler: average particle size 3 μm, thermal conductivity 2 W / m. K

又,在前述黏著劑層23℃之儲存彈性模數,係藉由將複數層的黏著劑層層積而製造厚度800μm的黏著劑層之積層體,針對將該黏著劑層的積層體沖切成為直徑10mm的圓形而得到的測定用試料,使用動態黏彈性測定裝置(TA Instruments公司製、ARES),在頻率1Hz、測定溫度範圍 -50~150℃、升溫速度3℃/min的條件下測定儲存彈性模數(Pa)。 In addition, the storage elastic modulus of the adhesive layer at 23 ° C. is a laminated body of an adhesive layer having a thickness of 800 μm by laminating a plurality of adhesive layers, and punching out the laminated body of the adhesive layer. A measurement sample obtained by forming a circular shape with a diameter of 10 mm was measured at a frequency of 1 Hz and a measurement temperature range using a dynamic viscoelasticity measuring device (ARES, manufactured by TA Instruments). Measure the storage elastic modulus (Pa) under the conditions of -50 ~ 150 ℃ and temperature increasing rate of 3 ℃ / min.

[試驗例1]熱傳導率的測定 [Test Example 1] Measurement of thermal conductivity

針對實施例及比較例之各自,將含有表1顯示的構成成分之組成物,使用甲基乙基酮以固體成分濃度成為40質量%之方式稀釋,塗佈在經聚矽氧處理之剝離膜(LINTEC公司製、SP-PET381031)上,藉由將所得到的塗膜在烘箱於100℃乾燥1分鐘,而形成厚度40μm的接著劑層。將依照該步驟而得到的接著劑層,以成為厚度2mm之方式層積複數層。從該厚度2mm的積層體沖切直徑5cm的圓盤狀接著劑層而作為用以測定之試料。 For each of the examples and comparative examples, the composition containing the constituent components shown in Table 1 was diluted with methyl ethyl ketone so that the solid content concentration became 40% by mass, and applied to a silicone-treated release film. (LINTEC Corporation, SP-PET381031), the obtained coating film was dried in an oven at 100 ° C. for 1 minute to form an adhesive layer having a thickness of 40 μm. A plurality of layers of the adhesive layer obtained in accordance with this step were laminated so as to have a thickness of 2 mm. A disc-shaped adhesive layer having a diameter of 5 cm was punched out from the laminated body having a thickness of 2 mm as a sample for measurement.

將該試料在130℃加熱2小時使其硬化之後,使用熱傳導率測定裝置(EKO公司製、HC-110)而測定熱傳導率(W/m.K)。將結果顯示在表2。 This sample was heated at 130 ° C for 2 hours to harden, and then the thermal conductivity (W / m · K) was measured using a thermal conductivity measuring device (EKO Corporation, HC-110). The results are shown in Table 2.

[試驗例2]接著劑層的厚度及該厚度的標準偏差之測定 [Test Example 2] Measurement of the thickness of the adhesive layer and the standard deviation of the thickness

針對實施例及比較例所製造的第1積層體,將接著劑層的厚度(T2),以50mm間隔、合計測定100點。基於該測定結果而算出厚度(T2)的平均值(μm)及厚度(T2)之標準偏差(μm)。將結果顯示在表2。 With respect to the first laminates produced in the examples and comparative examples, the thickness (T2) of the adhesive layer was measured at a total interval of 50 mm at 100 points. Based on the measurement results, the average value (μm) of the thickness (T2) and the standard deviation (μm) of the thickness (T2) were calculated. The results are shown in Table 2.

[試驗例3]藉由溫度循環試驗之放熱性的評價 [Experimental Example 3] Evaluation of heat release by temperature cycle test

準備在一面形成有凸塊、在另一面形成有襯墊之評價用晶圓,使用全自動多晶圓貼片機(LINTEC公司製、RAD-2700F/12),而將實施例及比較例所製造的三次元積體積層電路製造用板片貼附在該評價用晶圓之形成有凸塊之側的 面,而且固定在環狀框。 Evaluation wafers having bumps formed on one side and pads formed on the other side were prepared, and a fully automatic multi-wafer placement machine (manufactured by LINTEC, RAD-2700F / 12) was used. The manufactured three-dimensional bulk-layer circuit manufacturing plate is attached to the bump-formed side of the wafer for evaluation. Surface and fixed to the ring frame.

接著,使用全自動切割鋸(DISCO公司製、DFD651)同時切割接著劑層及評價用晶圓,而個片化成為具有俯視為7.3mm×7.3mm的大小之晶片。 Next, a fully automatic dicing saw (Disco 651, manufactured by DISCO Corporation) was used to simultaneously cut the adhesive layer and the wafer for evaluation, and the wafers were sliced into wafers having a size of 7.3 mm × 7.3 mm in plan view.

接著,使用覆晶接合機(TORAY Engineering公司製、FC3000W),同時拾取經個片化之接著劑層及晶片之後,覆晶接合在基板。隨後,將第2層之附接著劑層的晶片覆晶接合在暫時放置於基板上之第1層晶片上。重複該步驟而製造在基板上層積合計5層的晶片而成之半導體裝置。 Next, a flip-chip bonding machine (Toray Engineering, FC3000W) was used to pick up the sliced adhesive layer and wafer at the same time, and the flip-chip was bonded to the substrate. Subsequently, the second-layer wafer with the adhesive layer attached thereto is bonded to the first-layer wafer temporarily placed on the substrate. This step is repeated to manufacture a semiconductor device in which a total of five layers of wafers are stacked on a substrate.

將所得到的半導體裝置,於將-55℃、10分鐘及125℃、10分鐘設為1循環之環境下,進行施行1000循環之溫度循環試驗。針對該試驗前後的半導體裝置,使用數位萬用電表(digital multimeter)測定半導體晶片之間的接續電阻值,來測定在試驗後的半導體裝置之接續電阻值對在試驗前的半導體裝置之接續電阻值之變化率。而且,依照以下的評價基準而評價接續可靠性。將結果顯示在表2。 The obtained semiconductor device was subjected to a temperature cycle test of 1000 cycles under an environment where -55 ° C, 10 minutes, and 125 ° C, 10 minutes were set as one cycle. For the semiconductor devices before and after the test, a digital multimeter was used to measure the connection resistance between the semiconductor wafers to determine the connection resistance of the semiconductor device after the test and the connection resistance of the semiconductor device before the test. The rate of change of the value. The splicing reliability was evaluated in accordance with the following evaluation criteria. The results are shown in Table 2.

○:接續電阻值的變化率為20%以下。 ○: The change rate of the connection resistance value is 20% or less.

×:接續電阻值的變化率為大於20%。 ×: The change rate of the connection resistance value is more than 20%.

[試驗例4]埋入性的評價 [Test Example 4] Evaluation of embedding property

使用試驗例3所記載之方法製造複數個半導體裝置。使用數位顯微鏡觀察從該等半導體裝置隨意地選擇之5個半導體裝置的4側面,確認在凸塊有無產生龜裂、及凸塊埋入至接著劑層之狀態,同時測定在各自的面之層積方向的厚度。基於該等結果,依照以下的評價基準而評價在實施例及比較例所得到的 三次元積體積層電路製造用板片之凸塊的埋入性。將結果顯示在表2。 A plurality of semiconductor devices were manufactured by the method described in Test Example 3. A digital microscope was used to observe the four sides of five semiconductor devices arbitrarily selected from these semiconductor devices, and to confirm the occurrence of cracks in the bumps and the state where the bumps were embedded in the adhesive layer, and the layers on each side were also measured. Product direction thickness. Based on these results, the results obtained in the examples and comparative examples were evaluated in accordance with the following evaluation criteria. Embeddedness of bumps of a plate for manufacturing a three-dimensional multi-layer circuit. The results are shown in Table 2.

○:在5個半導體裝置全部,在凸塊不產生龜裂、凸塊係良好地被埋入至接著劑層,且層積方向的厚度係在4側面間為相同。 ○: In all of the five semiconductor devices, no cracks were generated in the bumps, and the bumps were well embedded in the adhesive layer, and the thickness in the lamination direction was the same across the four sides.

×:在5個半導體裝置之中,在凸塊有產生龜裂、或凸塊埋入至接著劑層為不充分、或層積方向的厚度係在4側面間為不相同者。 ×: Among the five semiconductor devices, cracks were generated in the bumps, the bumps were not sufficiently embedded in the adhesive layer, or the thickness in the lamination direction was different between the four sides.

Figure TW201802973AD00003
Figure TW201802973AD00003

Figure TW201802973AD00004
Figure TW201802973AD00004

從表2能夠得知,在實施例之三次元積體積層電路製造用板片之接著劑層,係具有0.5W/m.K以上之優異的熱 傳導率,同時接著劑層的厚度(T2)之標準偏差為2.0μm以下。而且,使用實施例所得到的三次元積體積層電路製造用板片而製成之積層電路,能夠確認放熱性優異、且溫度循環試驗的結果為良好,而且凸塊的埋入性亦優異。 It can be known from Table 2 that the adhesive layer of the plate for manufacturing a three-dimensional volumetric layer circuit of the example in the example has 0.5 W / m. Excellent heat above K The standard deviation of the conductivity and the thickness (T2) of the adhesive layer is 2.0 μm or less. In addition, it was confirmed that the multilayer circuit produced using the three-dimensional multilayer bulk circuit circuit manufacturing plate obtained in the example was excellent in heat release property, the results of the temperature cycle test were good, and the embedding property of the bumps was also excellent.

另一方面,在比較例之三次元積體積層電路製造用板片之接著劑層,熱傳導率為0.3W/m.K之不充分的值,使用該製造用板片而製成之積層電路的放熱性亦不充分。而且,針對比較例2之三次元積體積層電路製造用板片,其接著劑層的厚度(T2)之標準偏差為2.5μm,積層電路的放熱性不充分,同時凸塊的埋入性較差。 On the other hand, in the adhesive layer of the three-dimensional bulk-layer circuit manufacturing sheet of the comparative example, the thermal conductivity was 0.3 W / m. Insufficient value of K is also insufficient for heat dissipation of a multilayer circuit produced using the manufacturing sheet. Furthermore, for the plate for manufacturing a three-dimensional multi-layered multilayer circuit of Comparative Example 2, the standard deviation of the thickness (T2) of the adhesive layer was 2.5 μm, the heat dissipation of the multilayer circuit was insufficient, and the embedding of the bump was poor. .

[產業上之可利用性] [Industrial availability]

本發明之三次元積體積層電路製造用板片係具有優異的放熱性,能夠適合利用於製造具有較高的可靠性之積層電路。 The plate system for manufacturing a three-dimensional multilayer volume circuit of the present invention has excellent heat dissipation and can be suitably used for manufacturing a multilayer circuit having high reliability.

1‧‧‧三次元積體積層電路製造用板片 1‧‧‧Three-dimensional bulk layer circuit manufacturing plate

13‧‧‧接著劑層 13‧‧‧ Adhesive layer

14‧‧‧剝離板片 14‧‧‧ peeling sheet

Claims (16)

一種三次元積體積層電路製造用板片,其係介於具有貫穿電極的複數個半導體晶片之間,為了將前述複數個半導體晶片相互接著而成為三次元積體積層電路所使用之三次元積體積層電路製造用板片,其特徵在於:前述三次元積體積層電路製造用板片係至少具備硬化性的接著劑層,前述接著劑層係含有熱傳導性填料,且前述接著劑層的厚度(T2)之標準偏差為2.0μm以下。 A plate for manufacturing a three-dimensional multi-layered multilayer circuit, which is interposed between a plurality of semiconductor wafers having through electrodes. The three-dimensional multi-layered multilayer circuit used in order to connect the plurality of semiconductor wafers to each other to form a three-dimensional multi-layered multilayer circuit. The bulk layer circuit manufacturing sheet is characterized in that the three-dimensional bulk volume circuit manufacturing sheet system has at least a hardenable adhesive layer, the adhesive layer system includes a thermally conductive filler, and the thickness of the adhesive layer The standard deviation of (T2) is 2.0 μm or less. 如申請專利範圍第1項所述之三次元積體積層電路製造用板片,其中前述熱傳導性填料,係由選自金屬氧化物、碳化矽、碳化物、氮化物及金屬氫氧化物之材料所構成。 The three-dimensional bulk-layer circuit manufacturing plate as described in item 1 of the scope of patent application, wherein the thermally conductive filler is made of a material selected from the group consisting of metal oxide, silicon carbide, carbide, nitride, and metal hydroxide. Made up. 如申請專利範圍第1項所述之三次元積體積層電路製造用板片,其中在前述接著劑層之前述熱傳導性填料的含量為35質量%以上、95質量%以下。 According to the three-dimensional bulk-layer circuit manufacturing sheet described in item 1 of the scope of the patent application, the content of the thermally conductive filler in the adhesive layer is 35% by mass or more and 95% by mass or less. 如申請專利範圍第1項所述之三次元積體積層電路製造用板片,其中前述熱傳導性填料在23之熱傳導率為10W/m.K以上。 According to the three-dimensional multi-layer bulk layer circuit manufacturing plate described in the first item of the patent application scope, wherein the thermal conductivity of the aforementioned thermally conductive filler at 23 is 10 W / m. K or more. 如申請專利範圍第1項所述之三次元積體積層電路製造用板片,其中前述熱傳導性填料的平均粒徑為0.01μm以上、20μm以下。 According to the three-dimensional multi-layer bulk-layer circuit manufacturing sheet according to item 1 of the scope of the patent application, the average particle diameter of the thermally conductive filler is 0.01 μm or more and 20 μm or less. 如申請專利範圍第1項所述之三次元積體積層電路製造用板片,其中前述接著劑層硬化後的熱傳導率為0.5W/m.K以上、8.0W/m.K以下。 According to the three-dimensional multi-layer volume circuit manufacturing plate described in the first patent application range, wherein the thermal conductivity of the aforementioned adhesive layer after hardening is 0.5 W / m. Above K, 8.0W / m. K or less. 如申請專利範圍第1項所述之三次元積體積層電路製造用板片,其中構成前述接著劑層之材料,係含有熱硬化性成分、高分子量成分及硬化觸媒。 According to the three-dimensional multi-layer bulk-layer circuit manufacturing sheet described in item 1 of the scope of the patent application, the material constituting the aforementioned adhesive layer contains a thermosetting component, a high molecular weight component, and a hardening catalyst. 如申請專利範圍第1項所述之三次元積體積層電路製造用板片,其中前述高分子量成分的玻璃轉移溫度為50℃以上。 According to the three-dimensional bulk-layer circuit manufacturing sheet described in item 1 of the scope of patent application, the glass transition temperature of the high molecular weight component is 50 ° C or higher. 如申請專利範圍第1項所述之三次元積體積層電路製造用板片,其中構成前述接著劑層之材料係含有助焊劑成分。 According to the three-dimensional bulk-layer circuit manufacturing sheet described in item 1 of the scope of patent application, the material constituting the aforementioned adhesive layer contains a flux component. 如申請專利範圍第1項所述之三次元積體積層電路製造用板片,其中前述接著劑層的厚度為2μm以上、500μm以下。 According to the three-dimensional multi-layer bulk-layer circuit manufacturing sheet described in item 1 of the scope of patent application, the thickness of the aforementioned adhesive layer is 2 μm or more and 500 μm or less. 如申請專利範圍第1項所述之三次元積體積層電路製造用板片,其中前述三次元積體積層電路製造用板片進一步具備:黏著劑層,其係層積在前述接著劑層的一面側;及基材,其係層積在前述黏著劑層之與前述接著劑層為相反的面側。 The three-dimensional bulk-layer circuit manufacturing sheet described in item 1 of the scope of the patent application, wherein the three-dimensional bulk-layer circuit manufacturing sheet further includes: an adhesive layer, which is laminated on the adhesive layer. One surface side; and a substrate, which is laminated on the side of the adhesive layer opposite to the surface of the adhesive layer. 如申請專利範圍第11項所述之三次元積體積層電路製造用板片,其中前述基材的厚度為10μm以上、500μm以下。 According to the three-dimensional multi-layer bulk-layer circuit manufacturing sheet according to item 11 of the scope of the patent application, the thickness of the aforementioned substrate is 10 μm or more and 500 μm or less. 如申請專利範圍第11項所述之三次元積體積層電路製造用板片,其中前述接著劑層的厚度(T2)對前述基材的厚度(T1)之比(T2/T1)為0.01以上、5.0以下。 According to the three-dimensional bulk-layer circuit manufacturing sheet described in item 11 of the scope of patent application, the ratio (T2 / T1) of the thickness (T2) of the adhesive layer to the thickness (T1) of the substrate is 0.01 or more , Below 5.0. 如申請專利範圍第11項所述之三次元積體積層電路製造用板片,其中前述黏著劑在23℃之儲存彈性模數為1×103Pa以上、1×109Pa以下。 According to the three-dimensional multi-layer bulk-layer circuit manufacturing sheet described in item 11 of the scope of patent application, the storage elastic modulus of the aforementioned adhesive at 23 ° C. is 1 × 10 3 Pa or more and 1 × 10 9 Pa or less. 如申請專利範圍第11項所述之三次元積體積層電路製造用板片,其中前述基材在23℃之拉伸彈性模數為100MPa以 上、5000MPa以下。 According to the three-dimensional multi-layer bulk-layer circuit manufacturing sheet as described in item 11 of the scope of the patent application, the tensile elastic modulus of the aforementioned substrate at 23 ° C is 100 MPa or more. Up to 5000MPa. 一種三次元積體積層電路之製造方法,其特徵在於包含下列步驟:將如申請專利範圍第1項所述之三次元積體積層電路製造用板片之前述接著劑層的一面或如申請專利範圍第11項所述之三次元積體積層電路製造用板片之前述接著劑層之與前述黏著劑層為相反的面、與具備貫穿電極之半導體晶圓的至少一面貼合之步驟;將前述半導體晶圓與前述三次元積體積層電路製造用板片的前述接著劑層同時切割,而個片化成為附接著劑層之半導體晶片之步驟;將經個片化之複數個前述附接著劑層之半導體晶片,以將前述貫穿電極彼此電性連接且將前述接著劑層與前述半導體晶片交替地配置之方式複數層層積,而得到半導體晶片積層體之步驟;及使在前述半導體晶片積層體之前述接著劑層硬化,而將構成前述半導體晶片積層體之前述半導體晶片彼此接著之步驟。 A method for manufacturing a three-dimensional voluminous layer circuit, which comprises the following steps: one side of the aforementioned adhesive layer of the plate for manufacturing a three-dimensional voluminous layer circuit as described in item 1 of the scope of patent application or a patent application The step of bonding the adhesive layer on the opposite side to the adhesive layer of the three-dimensional multi-layer volume circuit manufacturing plate described in item 11 to at least one side of a semiconductor wafer having a through electrode; The step of cutting the aforementioned semiconductor wafer and the aforementioned adhesive layer of the three-dimensional bulk-layer circuit manufacturing plate at the same time, and singulating into a semiconductor wafer with an adhesive layer; A step of obtaining a semiconductor wafer laminate by laminating a plurality of semiconductor wafers of the agent layer in such a manner that the through electrodes are electrically connected to each other and the adhesive layer and the semiconductor wafer are alternately arranged to obtain a semiconductor wafer laminate; and The step of curing the aforementioned adhesive layer of the laminated body, and then adhering the aforementioned semiconductor wafers constituting the aforementioned semiconductor wafer laminated body to each other.
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