TW201735296A - 包括疊層之電子封裝體 - Google Patents

包括疊層之電子封裝體 Download PDF

Info

Publication number
TW201735296A
TW201735296A TW105134021A TW105134021A TW201735296A TW 201735296 A TW201735296 A TW 201735296A TW 105134021 A TW105134021 A TW 105134021A TW 105134021 A TW105134021 A TW 105134021A TW 201735296 A TW201735296 A TW 201735296A
Authority
TW
Taiwan
Prior art keywords
electronic
substrate
laminate
electronic package
package
Prior art date
Application number
TW105134021A
Other languages
English (en)
Other versions
TWI731886B (zh
Inventor
佩莫德 馬拉特卡
凱爾 耶茲
納迦 S. 耶納木錫
理查 J. 哈里斯
迪蘭 塞納維拉特納
波蘭斯 亞齊尼帕利
王雪飛
李永剛
羅伯特 L. 聖克曼
Original Assignee
英特爾公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 英特爾公司 filed Critical 英特爾公司
Publication of TW201735296A publication Critical patent/TW201735296A/zh
Application granted granted Critical
Publication of TWI731886B publication Critical patent/TWI731886B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135—Double encapsulation or coating and encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3142—Sealing arrangements between parts, e.g. adhesion promotors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/315—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the encapsulation having a cavity
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/562—Protection against mechanical damage
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/812—Applying energy for connecting
    • H01L2224/81201—Compression bonding
    • H01L2224/81203—Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1023—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the support being an insulating substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1433—Application-specific integrated circuit [ASIC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1434—Memory
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
    • H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Non-Metallic Protective Coatings For Printed Circuits (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

一種電子封裝體，其包括一基板及附接在該基板上之一電子組件。一疊層附接在該基板之一上表面上，使得該疊層覆蓋該電子組件。該電子封裝體可更包括安裝在該疊層上之一加強材，其中該加強材係在該電子組件上方。

Description

包括疊層之電子封裝體
本發明係有關於包括疊層之電子封裝體。
背景 因為對晶片及封裝體面積與高度(以及其他物理及電氣參數等)經常有嚴格之限制，所以某些電子產品(例如，行動電話、智慧型手機、平板電腦等)之可用空間通常非常有限。因此，在一基板上減少電子組件(例如，晶粒)之尺寸極為重要。
但是，當電子組件/封裝體作成非常薄以便配合電子組件減少尺寸的需要時，可能有與製造該等組件相關之困難。舉例而言，薄組件/封裝體對於半導體工業在歷史上一直是一巨大挑戰。
某些電子組件/封裝體包括一矽晶粒，該矽晶粒具有一比較低熱膨脹係數(CTE)且附接在具有一高CTE之一基板上。因此，由於該晶粒附接在製造該等組件/封裝體時隨著溫度變化而翹曲之基板上，經常發生製造困難。在該晶粒與該基板間之CTE差異使平衡一組件/封裝體中之設計與材料性質以便在(i)室溫；及(ii)焊料球熔化溫度獲得一扁平封裝體極為困難。
解決由在該晶粒與該基板間之CTE差異造成之製造困難的一方法係在該組件/封裝體中加入一模材料以便提供剛性。將一模材料加入該組件/封裝體具有數種缺點。
加入一模通常會增加該組件/封裝體之總尺寸(特別是該組件/封裝體之Z高度)。此外，某些高效能組件/封裝體通常必須移除該模之某些部分以便由該模暴露該組件/封裝體之某些部分。移除該模之某些部分會降低該模對於減少翹曲之有效性。
在一模塑程序中，該模塑材料會在它流入且通過各種孔穴及通道時硬化。因此，該模之性質會隨著位置而不同且亦會包含與位置有關之殘留應力。此外，模塑通常是一複雜製程，其中該模內之封裝體形狀及殘留應力絕大部分取決於製程條件(例如，模硬化溫度、後模硬化溫度等)。
依據本發明之一實施例，係特地提出一種電子封裝體，其包含：一基板；一電子組件，其被附接至該基板；及一疊層，其在該基板之一上表面上，使得該疊層覆蓋該電子組件。
實施例之說明 以下說明及圖充分地顯示使所屬技術領域中具有通常知識者可實施它們之特定實施例。其他實施例可加入結構、邏輯、電性、程序、及其他改變。其他實施例之部份及特徵可包含或取代某些實施例之部份及特徵。在申請專利範圍中提出之實施例包含這些申請專利範圍之所有可用等效物。
在這申請案中使用之方位用語，例如「水平」係相對平行於一晶圓或基板之習知平面或表面的一平面來定義，與該晶圓或基板之方位無關。該用語「垂直」表示垂直於如上定義之水平的一方向。介系詞，例如「在…上」、「側」(如在「側壁」中者)、「較高」、「較低」、「上方」、及「下方」係相對在該晶圓或基板之頂表面上之該習知平面或表面來定義，與該晶圓或基板之方位無關。
圖1顯示一電子封裝體10例。該電子封裝體10包括一基板11及附接在該基板11上之一電子組件12。該電子封裝體10更包括在該基板11之一上表面14上的一疊層13，使得該疊層13覆蓋該電子組件12。
在某些形態中，該電子封裝體10更包括安裝在該疊層13上之一加強材15。該加強材15係在該電子組件12上方。應注意的是該加強材15可部分地，或完全地在該電子組件12上方。
該加強材15在該電子組件12上方之程度將取決於(i)該疊層13之厚度；(ii)該電子組件12之尺寸；(iii)該加強材15之總尺寸及厚度；及/或(iv)該加強材15所使用之材料種類(以及其他因子)。該加強材15可具有在25與100微米間之一厚度。
舉例而言，該加強材15可為銅(以及許多其他種類之材料)且包括接合該疊層13之一粗化底表面16。該加強材15之粗化底表面16可依據該疊層13所使用之材料(以及其他因子)，在有或沒有一黏著劑之情形下，容許該加強材15附接在該疊層13上。
此外，該加強材15之粗化底表面16可容許該加強材15以比在該加強材15上之一平滑底表面所需壓力小之壓力安裝在該疊層上。舉例而言，在該電子組件12上方安裝該加強材15的該疊層13之厚度可為大約10至20微米。在某些形態中，可在150與200℃間之溫度烘烤該電子封裝體10以使該疊層材料硬化且亦將該加強材15及該電子組件12牢固地接合在該疊層13上。
該電子組件12可為一主動組件(例如，一晶粒)。應注意的是在該電子封裝體10中可包括任一種電子組件12。在該電子封裝體10中包括之該電子組件12的種類部分地取決於欲使用該電子封裝體10之應用(以及其他因子)。
該電子組件12可熱壓接合在該基板11上。此外，該電子封裝體10可更包括在該電子組件12與該基板11間之一底部填料17。應注意的是該電子組件12可以目前已知或在未來發現之任何方式附接在該基板11上。
在其他形態中，該疊層13可作為在該電子組件12與該基板11間之一底部填料。應注意的是圖中未顯示使用該疊層13作為一底部填料。
在圖中所示之例中，該電子封裝體10更包括附接在該基板11之上表面14上的多數焊料球18。該疊層13覆蓋該等焊料球18。
該電子封裝體10可更包括多數孔19，其穿過該疊層13延伸至在該基板11上之焊料球18。該等孔19可使用各種技術(例如，雷射鑽孔)鑽入該疊層13中以便暴露該等焊料球18之頂側。
在某些形態中，該電子封裝體10可未包括焊料球18，使得該等孔19穿過該疊層13一路延伸到該基板11之上表面14(未顯示在圖中)。若該等孔19穿過該疊層13一路延伸到該基板11之上表面14，則該電子封裝體可更包括以目前已知(例如，電解電鍍)或在未來發現之任何方式在該等孔19內產生的多數通孔。
在某些形態中，該電子封裝體10可更包括附接在該基板11之一底表面21上的多數焊料球20。該等焊料球20之數目、種類及尺寸部分地取決於欲使用該電子封裝體10之應用(以及其他因子)。
如圖3與4所示，該疊層13可具有一非平面上表面25。舉例而言，覆蓋該電子組件12的該疊層13之一部分26可比該疊層13之其他部分更遠離該基板11之上表面14。該疊層13之這特殊構態可允許該電子封裝體10附接在另一電子封裝體30(顯示於圖3與4中)，使得製成之電子系統40具有比較低之z高度(最清楚地顯示於圖4中)。
圖3顯示一第一電子封裝體10組裝至一第二電子封裝體30前之電子系統40例的一電子系統例之側視圖。圖4顯示該第一電子封裝體10組裝至該第二電子封裝體30後之圖3之電子系統40例的側視圖。
該電子系統40包括一第一電子封裝體10，該第一電子封裝體10包括一基板11、附接在該基板11上的一電子組件12及在這基板11之一上表面14上的一疊層13，使得該疊層13覆蓋該電子組件12。該電子系統40更包括附接在該第一電子封裝體10上之一第二電子封裝體30。
在某些形態中，該第二電子封裝體30附接在該基板11之一上表面14上。如圖3與4所示，該第二電子封裝體30可間接地(或在其他形態中直接地)附接在該基板之一上表面上。該第一電子封裝體10固定在該第二電子封裝體30上的方式部分地取決於在該電子系統40中使用之該等第一與第二電子封裝體10、30的種類、以及與製造該等第一與第二電子封裝體10、30及整體電子系統40相關的製造條件。
在圖3與4所示之形態例中，該電子系統40更包括安裝在一疊層13上之一加強材15。如上所述，該加強材15可在某些或全部電子組件12上方。
該第一電子封裝體10包括多數焊料球18，其附接在該基板11之上表面14上。該疊層13覆蓋該等焊料球18且包括穿過該疊層13延伸至該等焊料球18之多數孔19。該第二電子封裝體30可附接在該等孔19內之該第一電子封裝體10的焊料球18。舉例而言，該第二電子封裝體30可使用在該第二電子封裝體30之一下表面23上的多數焊料球22附接在該第一電子封裝體10的焊料球18上。
如上所述，該疊層13可具有一非平面上表面25。覆蓋該電子組件12的該疊層13之一部分26可比該疊層13之其他部分更遠離該基板11之上表面14。
該疊層13之非平面形狀結構可用以減少用以連接該等第一與第二電子封裝體10、30的該等焊料球18、22之尺寸。減少該等焊料球18、22之尺寸可降低與焊料球橋接相關之風險。
在此所述之該等電子封裝體10、30及電子系統40可使用各種不同材料作成該疊層13。舉例而言，該疊層13可為ABF-GX-T31、ABF-GX92或一阻焊薄膜(或某種其他材料)。
此外，該疊層13可在製造該等電子封裝體10、30時之各種不同時間疊在該基板11之上表面14上。舉例而言，該疊層13可在該電子封裝體10單粒化時呈帶狀地或平板狀地附接在該基板11之上表面14上。
該加強材15所使用之材料種類可依據各種製造及應用因子來改變。舉例而言，該加強材15可為銅、不鏽鋼或不同材料之一組合。
在此所述之該等電子封裝體10、30及電子系統40可使用一更簡單之製程來製造該等電子封裝體10、30。此外，如上所述，該疊層13可在該製程時之各種時間附接在該基板11之上表面14上。
在某些形態中，該疊層13可為使用習知模材料之一較低成本替代物。此外，使用一堆疊程序可達成允許更小形狀因子且可能支持更高帶寬記憶體需求的更緊密之穿模互連(TMI)。
因為在不影響室溫翹曲之情形下減少高溫翹曲是一極困難之挑戰，所以在此所述之該等電子封裝體10、30及電子系統40亦可為對習知模製架構之一改良。由於具有該加強材15，在此所述之該等電子封裝體10、30及電子系統40可在室溫及高溫下提供翹曲控制。
圖5係具有至少一在此所述之電子封裝體10、30及/或電子系統40的一電子設備500的方塊圖。電子設備500只是可使用至少一在此所述之電子封裝體10、30及/或電子系統40形態的一電子設備之一例。
一電子設備500之例子包括，但不限於，個人電腦、平板電腦、行動電話、遊戲裝置、MP3或其他數位音樂播放器等。在這例子中，電子設備500包含一資料處理系統，且該資料處理系統包括用以耦合該電子設備500之各種組件的一系統匯流排502。系統匯流排502在該電子設備500之各種組件間提供通訊鏈路且可以一單一匯流排、以一匯流排之組合、或以任何適當方式實施。
如在此所述地包括該至少一電子封裝體10、30及/或電子系統40之任一者的一電子總成510可與系統匯流排502耦合。該電子總成510可包括任一電路或電路之組合。在一實施例中，該電子總成510包括可為任一種之處理器512。在此使用之「處理器」表示任一種運算電路，例如但不限於一微處理器、一微控制器、一複雜指令集計算(CISC)微處理器、一精簡指令集計算(RISC)微處理器、一極長指令字處理器(VLIW)微處理器、一圖形處理器、一數位訊號處理器(DSP)、多核心處理器、或任何其他種類之處理器或處理電路。
在電子總成510中可包括之其他種類的電路係一定製電路、一特殊應用積體電路(ASIC)等，例如，用於如行動電話、平板電腦、筆記型電腦、雙向無線電及類似電子系統之無線裝置中的一或多數電路(例如一通訊電路514)。該IC可達成任何其他種類之功能。
該電子設備500亦可包括一外部記憶體520，而該外部記憶體520又可包括適合特定應用之一或多數記憶體元件，例如呈一隨機存取記憶體(RAM)形式之一主記憶體522、一或多數硬碟機524、及/或處理例如光碟(CD)、快閃記憶卡、數位影音光碟(DVD)等之可移除媒體526的一或多數驅動器。
該電子設備500亦可包括一顯示裝置516、一或多數揚聲器518、及一鍵盤及/或控制器530，該鍵盤及/或控制器530可包括一滑鼠、軌跡球、觸控螢幕、語音辨識裝置、或允許一系統使用者將資訊輸入該電子設備500及由該電子設備500接收資訊的任何其他裝置。 為了更佳地顯示在此揭露之電子封裝體及/或電子系統，在此提供一系列非限制實施例：
例1包括一種電子封裝體。該電子封裝體包括：一基板；一電子組件，其附接在該基板上；及一疊層，其在該基板之一上表面上，使得該疊層覆蓋該電子組件。
例2包括例1之電子封裝體，且更包括安裝在該疊層上之一加強材，其中該加強材係在該電子組件上方。
例3包括例2之電子封裝體，其中該加強材部分地在該電子組件上方。
例4包括例2至3中任一例之電子封裝體，其中該加強材係銅。
例5包括例2至4中任一例之電子封裝體，其中該加強材包括接合該疊層之一粗化底表面。
例6包括例1至5中任一例之電子封裝體，其中該電子組件係一晶粒。
例7包括例1至6中任一例之電子封裝體，其中該電子組件係熱壓接合在該基板上。
例8包括例1至7中任一例之電子封裝體，且更包括在該電子組件與該基板間之一底部填料。 例9包括例1至7中任一例之電子封裝體，其中該疊層作為在該電子組件與該基板間之一底部填料。
例10包括例1至9中任一例之電子封裝體，且更包括穿過該疊層延伸至該基板之該上表面的多數孔。
例11包括例1至10中任一例之電子封裝體，且更包括附接在該基板之一上表面上的多數焊料球，其中該疊層覆蓋該等焊料球。
例12包括例11之電子封裝體，且更包括穿過該疊層延伸至在該基板上之該等焊料球的多數孔。
例13包括例1至12中任一例之電子封裝體，且更包括附接在該基板之一底表面上的多數焊料球。
例14包括例1至13中任一例之電子封裝體，其中該疊層具有一非平面上表面。
例15包括例14之電子封裝體，其中覆蓋該電子組件的該疊層之一部分比該疊層之其他部分更遠離該基板之該上表面。
例16包括一種電子系統。該電子系統包括：一第一電子封裝體，其包括一基板、附接在該基板上之一電子組件及在該基板之一上表面上之一疊層，使得該疊層覆蓋該電子組件；及一第二電子封裝體，其附接在該第一電子封裝體上。
例17包括例16之電子系統，其中該第二電子封裝體附接在該基板之一上表面上。 例18包括例16至17中任一例之電子系統，且更包括安裝在該疊層上之一加強材，其中該加強材係在該電子組件上方。
例19包括例16至18中任一例之電子系統，其中該第一電子封裝體包括附接在該基板之一上表面上的多數焊料球，且其中該疊層覆蓋該等焊料球並且包括穿過該疊層延伸至該等焊料球之多數孔，且其中該第二電子封裝體附接在該等孔內的該第一電子封裝體之該等焊料球上。
例20包括例16至19中任一例之電子系統，其中該疊層具有一非平面上表面，其中覆蓋該電子組件的該疊層之一部分比該疊層之其他部分更遠離該基板之該上表面。
例21包括一種電子封裝體。該電子封裝體包括：一基板；一電子組件，其附接在該基板上；一疊層，其在該基板之一上表面上，使得該疊層覆蓋該電子組件；及一加強材，其安裝在該疊層上，其中該加強材係在該電子組件上方。
例22包括例21之電子封裝體，其中該加強材係銅且部分地在該電子組件上方。
例23包括例21至22中任一例之電子封裝體，其中該加強材包括接合該疊層之一粗化底表面。
例24包括例21至23中任一例之電子封裝體，其中該疊層具有一非平面上表面，且其中覆蓋該電子組件的該疊層之一部分比該疊層之其他部分更遠離該基板之該上表面。
這概要係欲提供本標的物之非限制例。它不是要提供一排他或窮舉之說明。其中包含該詳細說明以提供關於該等電子封裝體及方法之其他資訊。
以上詳細說明包括參照形成該詳細說明之一部分的附圖。藉由圖示，該等圖顯示可實施本發明之特定實施例。這些實施例在此亦被稱為「例子」。該等例子可包括所示或所述元件以外之元件。但是，本發明人亦可預期只提供所示或所述之這些元件的例子。此外，本發明人亦可預期，相對於一特定例子(或其一或多數態樣)或相對於在此所示或所述之其他例子(或其一或多數態樣)，使用這些所示或所述元件之任何組合或置換的例子(或其一或多數態樣)。
在這文獻中，如在專利文獻中常見地，在此使用之用語「一」包括一或一以上，與任何其他情形或使用「至少一」或「一或多數」無關。在這文獻中，除非另外聲明，該用語「或」係用以表示一非互斥或，使得「A或B」包括「A非B」、「B非A」、及「A與B」。在這文獻中，該等用語「包括」及「在...中」係作為各用語「包含」及「其中」之直白英語等效語使用。此外，在以下申請專利範圍中，該等用語「包括」及「包含」是開放式的，即，包括在一申請專利範圍中在該用語後列舉者以外之多數元件的一系統、裝置、物品、組成物、配方、或製程仍被視為落在該申請專利範圍之範疇內。另外，在以下申請專利範圍中，在此使用之用語「第一」、「第二」、及「第三」等只作為標示使用，且不是要在其物體上加上數值必要條件。
以上說明是說明性的而非限制性的。例如，上述例子(或其一或多數態樣)可互相組合使用。此外，在此所述之方法的順序可為允許製造一電性互連及/或包括一電性互連之封裝體的任何順序。藉由瀏覽上述說明，例如所屬技術領域中具有通常知識者可使用其他實施例。
該摘要係為讓讀者可快速地確定該技術揭示之本質。它是在了解它不會用以判讀或限制該申請專利範圍之範疇或意義之情形下提出。
此外，在以上詳細說明中，各種特徵可組合在一起以簡化該揭露內容。這不應被解讀為一未請求之揭露特徵對任一請求項是必需的意圖。相反地，本發明標的物可為比一特定揭露實施例之所有特徵少。因此，該詳細說明因而加入以下申請專利範圍，且各請求項獨立地作為一分開之實施例，並且可預期的是該等實施例可在各種組合或置換中互相組合。本發明之範疇應參照附加申請專利範圍，及該申請專利範圍給予權利之等效物的全部範疇來決定。
10‧‧‧電子封裝體 11‧‧‧基板 12‧‧‧電子組件 13‧‧‧疊層 14‧‧‧上表面 15‧‧‧加強材 16‧‧‧粗化底表面 17‧‧‧底部填料 18,20,22‧‧‧焊料球 19‧‧‧孔 21‧‧‧底表面 23‧‧‧下表面 25‧‧‧非平面上表面 26‧‧‧部分 30‧‧‧第二電子封裝體 40‧‧‧電子系統 500‧‧‧電子設備 502‧‧‧系統匯流排 510‧‧‧電子總成 512‧‧‧處理器 514‧‧‧通訊電路 516‧‧‧顯示裝置 518‧‧‧揚聲器 520‧‧‧外部記憶體 522‧‧‧主記憶體 524‧‧‧硬碟機 526‧‧‧手持式可移除媒體 530‧‧‧鍵盤及/或控制器
圖1顯示一電子封裝體例之側視圖。
圖2顯示另一電子封裝體例之側視圖。
圖3顯示在一第一電子封裝體組裝於一第二電子封裝體前之一電子系統例的側視圖。
圖4顯示在該第一電子封裝體組裝於該第二電子封裝體後之圖3之電子系統例的側視圖。
圖5係包括在此所述之電子封裝體之一電子設備的方塊圖。
10‧‧‧電子封裝體
11‧‧‧基板
12‧‧‧電子組件
13‧‧‧疊層
14‧‧‧上表面
15‧‧‧加強材
16‧‧‧粗化底表面
17‧‧‧底部填料
18,20‧‧‧焊料球
19‧‧‧孔
21‧‧‧底表面

Claims (24)

  1. 一種電子封裝體，其包含： 一基板； 一電子組件，其被附接至該基板；及 一疊層，其在該基板之一上表面上，使得該疊層覆蓋該電子組件。
  2. 如請求項1之電子封裝體，更包含被安裝在該疊層上之一加強材，其中該加強材係在該電子組件上方。
  3. 如請求項2之電子封裝體，其中該加強材係部分地在該電子組件上方。
  4. 如請求項2之電子封裝體，其中該加強材係銅。
  5. 如請求項2之電子封裝體，其中該加強材包括嚙合該疊層之一粗化底表面。
  6. 如請求項1之電子封裝體，其中該電子組件係一晶粒。
  7. 如請求項1之電子封裝體，其中該電子組件係熱壓接合至該基板。
  8. 如請求項7之電子封裝體，更包含在該電子組件與該基板間之一底部填料。
  9. 如請求項7之電子封裝體，其中該疊層作為在該電子組件與該基板間之一底部填料。
  10. 如請求項1之電子封裝體，更包含延伸穿過該疊層至該基板之該上表面的多數孔。
  11. 如請求項1之電子封裝體，更包含被附接至該基板之一上表面的多數焊料球，其中該疊層覆蓋該等焊料球。
  12. 如請求項11之電子封裝體，更包含延伸穿過該疊層至在該基板上之該等焊料球的多數孔。
  13. 如請求項1之電子封裝體，更包含附接至該基板之一底表面的多數焊料球。
  14. 如請求項1之電子封裝體，其中該疊層具有一非平面上表面。
  15. 如請求項14之電子封裝體，其中覆蓋該電子組件的該疊層之一部分比該疊層之其他部分更遠離該基板之該上表面。
  16. 一種電子系統，其包含： 一第一電子封裝體，其包括一基板、被附接至該基板的一電子組件及在該基板之一上表面上的一疊層，使得該疊層覆蓋該電子組件；及 一第二電子封裝體，其被附接至該第一電子封裝體。
  17. 如請求項16之電子系統，其中該第二電子封裝體被附接至該基板之一上表面。
  18. 如請求項16之電子系統，更包含被安裝在該疊層上之一加強材，其中該加強材係在該電子組件上方。
  19. 如請求項16之電子系統，其中該第一電子封裝體包括被附接至該基板之一上表面的多數焊料球，且其中該疊層覆蓋該等焊料球並且包括延伸穿過該疊層至該等焊料球之多數孔，並且其中該第二電子封裝體係附接至在該等孔內的該第一電子封裝體之該等焊料球。
  20. 如請求項16之電子系統，其中該疊層具有一非平面上表面，其中覆蓋該電子組件的該疊層之一部分比該疊層之其他部分更遠離該基板之該上表面。
  21. 一種電子封裝體，其包含： 一基板； 一電子組件，其被附接至該基板； 一疊層，其在該基板之一上表面上，使得該疊層覆蓋該電子組件；及 一加強材，其被安裝在該疊層上，其中該加強材係在該電子組件上方。
  22. 如請求項21之電子封裝體，其中該加強材係銅且係部分地在該電子組件上方。
  23. 如請求項21之電子封裝體，其中該加強材包括嚙合該疊層之一粗化底表面。
  24. 如請求項21之電子封裝體，其中該疊層具有一非平面上表面，且其中覆蓋該電子組件的該疊層之一部分比該疊層之其他部分更遠離該基板之該上表面。
TW105134021A 2015-11-24 2016-10-21 包括疊層之電子封裝體及電子系統 TWI731886B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
WOPCT/US15/62397 2015-11-24
PCT/US2015/062397 WO2017091211A1 (en) 2015-11-24 2015-11-24 Electronic package that includes lamination layer

Publications (2)

Publication Number Publication Date
TW201735296A true TW201735296A (zh) 2017-10-01
TWI731886B TWI731886B (zh) 2021-07-01

Family

ID=58763684

Family Applications (1)

Application Number Title Priority Date Filing Date
TW105134021A TWI731886B (zh) 2015-11-24 2016-10-21 包括疊層之電子封裝體及電子系統

Country Status (3)

Country Link
US (1) US10985080B2 (zh)
TW (1) TWI731886B (zh)
WO (1) WO2017091211A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10985080B2 (en) 2015-11-24 2021-04-20 Intel Corporation Electronic package that includes lamination layer

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002151633A (ja) 2000-11-08 2002-05-24 Citizen Watch Co Ltd 樹脂封止型半導体装置
US6512295B2 (en) 2001-03-01 2003-01-28 International Business Machines Corporation Coupled-cap flip chip BGA package with improved cap design for reduced interfacial stresses
US7332423B2 (en) * 2005-06-29 2008-02-19 Intel Corporation Soldering a die to a substrate
TWI336502B (en) * 2006-09-27 2011-01-21 Advanced Semiconductor Eng Semiconductor package and semiconductor device and the method of making the same
TWI335070B (en) * 2007-03-23 2010-12-21 Advanced Semiconductor Eng Semiconductor package and the method of making the same
US20100109169A1 (en) 2008-04-29 2010-05-06 United Test And Assembly Center Ltd Semiconductor package and method of making the same
US8115303B2 (en) 2008-05-13 2012-02-14 International Business Machines Corporation Semiconductor package structures having liquid coolers integrated with first level chip package modules
US7851894B1 (en) * 2008-12-23 2010-12-14 Amkor Technology, Inc. System and method for shielding of package on package (PoP) assemblies
TW201428905A (zh) 2013-01-04 2014-07-16 矽品精密工業股份有限公司 半導體封裝件及其製法
US8970024B2 (en) * 2013-03-14 2015-03-03 Taiwan Semiconductor Manufacturing Company, Ltd. Packages with molding material forming steps
KR102063794B1 (ko) * 2013-06-19 2020-01-08 삼성전자 주식회사 적층형 반도체 패키지
US9082766B2 (en) * 2013-08-06 2015-07-14 Google Technology Holdings LLC Method to enhance reliability of through mold via TMVA part on part POP devices
US9142523B2 (en) * 2013-11-22 2015-09-22 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor device and manufacturing method thereof
KR102424402B1 (ko) * 2015-08-13 2022-07-25 삼성전자주식회사 반도체 패키지 및 그 제조방법
WO2017091211A1 (en) 2015-11-24 2017-06-01 Pramod Malatkar Electronic package that includes lamination layer

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10985080B2 (en) 2015-11-24 2021-04-20 Intel Corporation Electronic package that includes lamination layer

Also Published As

Publication number Publication date
US20180350709A1 (en) 2018-12-06
WO2017091211A1 (en) 2017-06-01
US10985080B2 (en) 2021-04-20
TWI731886B (zh) 2021-07-01

Similar Documents

Publication Publication Date Title
TWI529904B (zh) 凹入式及嵌入式晶粒無核心封裝體
KR102165024B1 (ko) 와이어-접합 멀티-다이 스택을 구비한 집적 회로 패키지
TWI578466B (zh) 具有垂直柱之重疊堆疊的晶粒封裝
KR101652890B1 (ko) 빌드업층에 임베드된 로직 다이 및 다른 컴포넌트
TWI521667B (zh) 形成金屬填充晶粒背側薄膜以配合無核心封裝體作電磁干擾屏蔽之技術
JP6773367B2 (ja) パッケージオンパッケージのため凹型導電性コンタクトを有する集積回路構造及び方法
TWI614876B (zh) 包括堆疊電子裝置的電子總成
JP2018518835A (ja) パッケージ構造にトレンチを形成する方法及びこの方法により形成された構造
KR101912491B1 (ko) 전자 패키지 및 전자 패키지를 형성하기 위해 제1 다이를 제2 다이에 연결시키는 방법
KR101735767B1 (ko) 전자 패키지 및 전자 패키지의 형성을 위한 제 1 다이와 제 2 다이의 접속 방법
KR101754847B1 (ko) 적층된 전자 디바이스들을 포함하는 전자 어셈블리
TW201735296A (zh) 包括疊層之電子封裝體
TWI609446B (zh) 用於電子總成之加強件帶
TWI590344B (zh) 製造電子封裝體的方法