TW201733003A - 半導體裝置之形成方法 - Google Patents

半導體裝置之形成方法 Download PDF

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TW201733003A
TW201733003A TW105135667A TW105135667A TW201733003A TW 201733003 A TW201733003 A TW 201733003A TW 105135667 A TW105135667 A TW 105135667A TW 105135667 A TW105135667 A TW 105135667A TW 201733003 A TW201733003 A TW 201733003A
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layer
forming
feature
metal
contact trench
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TWI713145B (zh
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Chun-Hsien Huang
Hong-Mao Lee
Yu-Kai Chen
Hsien-Lung Yang
Wei-Jung Lin
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Taiwan Semiconductor Mfg
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Abstract

本揭露提供一種半導體裝置之形成方法，包括：形成一源極/汲極特徵於一基板之上；形成一介電層於源極/汲極特徵之上；形成一接觸溝槽穿過介電層以曝露源極/汲極特徵；以一第一原子層沉積(ALD)製程沉積一氮化鈦(TiN)層於接觸溝槽；以及沉積一鈷層於接觸溝槽中的TiN層之上。

Description

半導體裝置之形成方法
本揭露係關於半導體裝置之形成方法，且特別是有關於一種接觸金屬之形成方法。
半導體積體電路(IC)工業已歷經快速發展的階段。積體電路設計及材料在技術上的進步使得每一代生產的積體電路變得比先前生產的積體電路更小且其電路也變得更複雜。在積體電路發展的進程中，功能性密度(例如：每一個晶片區域中內連線裝置的數目)已經普遍增加，而幾何尺寸(例如：製程中所能創造出最小的元件或線路)則是普遍下降。
這種微縮化的過程通常可藉由增加生產效率及降低相關支出提供許多利益，但此種微縮化也增加了積體電路加工和製造上的複雜度。為了實現這樣的進展，積體電路加工和製造上也需要有相同的進步。其中一個領域就是位於電晶體和其他裝置之間的佈線(wiring)或內連線。雖然現存之積體電路裝置的製造方法一般已能滿足其預期目的，但是並非在各方面都完全令人滿意。例如，期望對FinFET裝置中接觸金屬的形成製程進行改良。
根據一實施例，本揭露提供一種半導體裝置的形成方法，包括：形成一源極/汲極特徵於一基板之上；形成一 介電層於源極/汲極特徵之上；形成一接觸溝槽穿過介電層以曝露源極/汲極特徵；以一第一原子層沉積(ALD)製程沉積一氮化鈦(TiN)層於接觸溝槽；以及沉積一鈷層於接觸溝槽中的TiN層之上。
根據另一實施例，本揭露提供一種半導體裝置的形成方法，包括：形成一第一閘極堆疊和一第二閘極堆疊於一基板之上、形成一源極/汲極特徵於基板之上。源極/汲極特徵位於第一和第二閘極堆疊之間。半導體裝置的形成方法也包括：形成一介電層於源極/汲極特徵之上、形成一接觸溝槽穿過介電層以曝露源極/汲極特徵、形成一自對準矽化物層於曝露的源極/汲極特徵之上、以一第一原子層沉積(ALD)製程沉積一氮化鈦(TiN)層於接觸溝槽中，包括位於自對準矽化層之上。半導體裝置的形成方法也包括：沉積一鈷層於接觸溝槽中的TiN層之上。
又根據另一實施例，半導體裝置的形成方法包括：形成一介電層於一基板之上、形成一溝槽於介電層中、以一第一原子層沉積(ALD)製程形成一氮化鈦層於溝槽中、以及形成一鈷層於氮化鈦層之上。
為讓本揭露之上述和其他目的、特徵、和優點能更明顯易懂，下文特舉出較佳實施例，並配合所附圖式，作詳細說明如下：
100‧‧‧方法
102、104、106、107、110、112‧‧‧步驟
200‧‧‧半導體裝置
205‧‧‧初始結構
210‧‧‧基板
220‧‧‧隔離特徵
230‧‧‧鰭狀特徵
240‧‧‧第一導電特徵(HK/MG)
245‧‧‧閘極硬罩幕(HK)
250‧‧‧側壁間隔
260‧‧‧第二導電特徵(S/D特徵)
270‧‧‧介電層
310‧‧‧HM
320‧‧‧開口
410‧‧‧接觸溝槽
410U、615U‧‧‧上部分
410L、615L‧‧‧下部分
510‧‧‧矽化物層
520‧‧‧黏著層
610‧‧‧金屬層/導電層/鈷(Co)層
615‧‧‧接觸金屬
A-A‧‧‧線
本揭露最好配合圖式及詳細說明閱讀以便了解。要強調的是，依照工業上的標準實施，各個特徵並未按照比例 繪製。事實上，為了清楚之討論，可能任意的放大或縮小各個特徵的尺寸。
第1圖為根據一些實施例顯示半導體裝置之示例形成方法流程圖。
第2A圖為根據一些實施例所繪製示例半導體裝置之初始結構透視圖。
第2B圖為根據一些實施例沿著第2A圖中線A-A所繪製一示例之初始結構剖面圖。
第3A、3B、4A、4B、5A、5B、6A、6B、7A、7B、8A及8B圖為根據一些實施例沿著第2A圖中線A-A所繪製之示例半導體裝置之剖面圖。
以下揭示提供許多不同的實施方法或是例子來實行本揭露之不同特徵。以下描述具體的元件及其排列的例子以簡化本揭露。當然這些僅是例子且不該以此限定本揭露的範圍。例如，在描述中提及第一個元件形成於第二個元件之上時，其可能包括第一個元件與第二個元件直接接觸的實施例，也可能包括兩者之間有其他元件形成而沒有直接接觸的實施例。此外，在不同實施例中可能使用重複的標號及/或符號，這些重複僅為了簡單清楚地敘述本揭露，不代表所討論的不同實施例及/或結構之間有特定的關係。
此外，其中可能用到與空間相關的用詞，像是“在...下方”、“下方”、“較低的”、“上方”、“較高的”及類似的用詞，這些關係詞係為了便於描述圖式中一個(些)元 件或特徵與另一個(些)元件或特徵之間的關係。這些空間關係詞包括使用中或操作中的裝置之不同方位，以及圖式中所描述的方位。裝置可能被轉向不同方位(旋轉90度或其他方位)，則其中使用的空間相關形容詞也可相同地照著解釋。
本揭露係關於，但不限於，鰭狀場效電晶體(FinFET)裝置。此種裝置可包括P-型金氧半導體FinFET裝置或N-型金氧半導體FinFET裝置。FinFET裝置可為雙閘極裝置、三閘極裝置、塊狀(bulk)裝置、絕緣體上矽(silicon-on-insulator；SOI)裝置、及/或其他構造。本技術領域具有通常知識者可理解可從本揭露各方面獲益的其他半導體裝置實施例。例如，此處所描述的一些實施例也可應用在環繞式閘極(gate-all-around；GAA)裝置、Ω式閘極(Ω-gate)裝置、或是Π式閘極(Π-gate)裝置。以下將繼續揭露FinFET示例以說明本發明之各種實施例。然而，可了解的是，除非特別聲明，本發明不應限制於特定類型的裝置。
第1圖為根據一些實施例顯示一或多個半導體裝置之形成方法100的流程圖。以下參照第2A圖和第2B圖所示之半導體裝置200的初始結構205、以及第3A圖到第8B圖所示之半導體裝置200，詳細討論方法100。
參照第1圖、第2A圖及第2B圖，方法100始於步驟102，接收半導體裝置200的初始結構205。初始結構205包括一基板210。基板210可為一塊狀(bulk)矽基板。或者，基板210可包括一元素半導體，像是晶體結構的矽或鍺；一化合物半導體，像是矽鍺、碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦、 及/或銻化銦；或前述之組合。可能的基板210也包括絕緣體上矽(SOI)基板。利用氧植入隔離(SIMOX)、晶圓接合、及/或其他適合的方法製造SOI基板。
一些示例的基板210也包括一絕緣體層。絕緣體層包括任何合適的材料，包括氧化矽、藍寶石(sapphire)、及/或前述之組合。一示例絕緣體層可為一埋藏氧化層(BOX)。絕緣體係藉由任何合適的製程像是植入(例如：SIMOX)、氧化、沉積、及/或其他合適的製程形成。在一些示例的半導體裝置200中，絕緣體層為絕緣體上矽基板的元件(例如：層)。
基板210也可包括各種摻雜區域。摻雜區域可摻雜有p-型摻質，像是硼或BF2；n-型摻質，像是磷或砷；及/或前述之組合。摻雜區域可直接形成於基板210上、於P-井結構中、於N-井結構中、於雙井結構中、或利用凸起結構(raised structure)形成。基板210可更包括各種主動區域，像是配置為N-型金氧半電晶體裝置的區域，以及配置為P-型金氧半電晶體裝置的區域。
基板210也可包括各種隔離特徵220。隔離特徵220隔離基板210中的各種裝置區域。隔離特徵220包括利用不同製程技術形成的不同結構。例如，隔離特徵220可包括淺溝槽隔離(shallow trench isolation；STI)特徵。STI的形成可包括蝕刻基板210中的一溝槽，以及利用絕緣材料像是氧化矽、氮化矽、或氮氧化矽填充溝槽。經填充後的溝槽可具有一多層結構，像是經氮化矽填充溝槽的熱氧化襯層(thermal oxide linear layer)。可實施化學機械平坦化(chemical mechanical polishing；CMP) 以研磨背面多餘的絕緣材料，並平坦化隔離特徵220的頂表面。
初始結構205也包括形成於基板210之上的複數個鰭狀特徵230。鰭狀特徵230可包括矽(Si)、矽鍺(SiGe)、矽鍺錫(SiGeSn)、砷化鎵(GaAs)、磷化鎵(GaP)、磷化銦(InP)、砷化銦(InAs)、及/或其他合適的材料。在一些實施例中，鰭狀特徵230係藉由任何合適的製程，包括各種沉積、微影、及/或蝕刻製程形成。做為一個示例，鰭狀特徵230係藉由圖案化及蝕刻一部分的基板210形成。
初始結構205也包括位於基板210之上的複數個第一導電特徵240。在一些實施例中，第一導電特徵240可為包括包覆(wrapping over)一部分鰭狀特徵230的高介電常數/金屬閘極堆疊(HK/MGs)的閘極結構。或者，在一些實施例中，第一導電特徵240也可包括一部分的內連線結構，像是接觸(contact)、金屬導孔(via)、及/或金屬線。在一實施例中，第一導電特徵240包括電極、電容、電阻及/或一部分的電阻。為達簡潔和清晰的目的，第一導電特徵240被稱為HK/MG 240。
HK/MGs 240可包括閘極介電層及金屬閘極(MG)電極層。HK/MGs 240的閘極介電層可包括LaO、AlO、ZrO、TiO、Ta2O5、Y2O3、SrTiO3(STO)、BaTiO3(BTO)、BaZrO、HfZrO、HfLaO、HfSiO、LaSiO、AlSiO、HfTaO、HfTiO、(Ba,Sr)TiO3(BST)、Al2O3、Si3N4、氮氧化物(SiON)、或其他合適的材料。閘極介電層可藉由合適的方法沉積，像是化學氣相沉積(CVD)、原子層沉積(ALD)、熱氧化或臭氧氧化、其他合適的技術、及/或前 述之組合。
MG電極層可包括一單層或多層，像是金屬層、襯層、濕層、及黏著層。MG可包括Ti、Ag、Al、TiAlN、TaC、TaCN、TaSiN、Mn、Zr、TiN、TaN、Ru、Mo、Al、WN、Cu、W、或任何合適的材料。MG可藉由原子層沉積(ALD)、物理氣相沉積(PVD)、化學氣相沉積(CVD)、及/或其他合適的製程形成。
在一些實施例中，先形成虛設閘極堆疊，並於實施高溫製程之後，像是源極/汲極形成期間的熱製程之後，接著由HK/MGs 240所取代。虛設閘極堆疊可包括一虛設閘極介電層以及一多晶矽層，且可藉由沉積、圖案化及蝕刻製程形成。
在一些實施例中，形成一閘極硬罩幕(HM)245於每一個HK/MGs 240的頂部上，以在後續蝕刻製程中提供保護。閘極HM 245可包括鈦(Ti)、氧化鈦、氮化鈦(TiN)、鈦矽氮化物(TiSiN)、鉭(Ta)、氧化鉭、氮化鉭(TaN)、鉭矽氮化物(TaSiN)、氮化矽、氧化矽、碳化矽、氮氧化矽、錳(Mn)、鈷(Co)、釕(Ru)、氮化鎢(WN)、氮化鋁、氧化鋁、及/或其他合適的材料。閘極HM 245可藉由沉積、微影圖案化及蝕刻製程形成。
在一些實施例中，可沿著HK/MGs 240的側壁形成側壁間隔250。側壁間隔250可包括一介電材料，像是氧化矽、氮化矽、碳化矽、氮氧化矽、及/或其他合適的材料。可藉由沉積一閘極側壁間隔層，並接著以非均向(anisotropic)乾蝕刻閘極側壁間隔層來形成側壁間隔250。
初始結構205也可包括基板210之上的第二導電特徵260。在一些實施例中，第二導電特徵260為源極/汲極(S/D)特徵，其位於HK/MG 240旁且由HK/MG 240所隔離。或者，在一些實施例中，第二導電特徵260也可包括一部分的內連線結構，像是接觸(contact)、金屬導孔(via)、及/或金屬線。在一實施例中，第二導電特徵260包括電極、電容、電阻或一部分的電阻。為達簡潔和清晰的目的，第二導電特徵260此後稱為S/D特徵260。
在此，一S/D特徵260為一源極特徵，且另一S/D特徵260為一汲極特徵。如所示，S/D特徵260由HK/MG 240所隔離。在一實施例中，凹陷位於HK/MG 240旁的一部分基板210以形成S/D凹陷，並接著藉由磊晶生長製程，像是CVD、VPE及/或UHV-CVD、分子束磊晶、及/或其他合適的製程，形成S/D特徵260於S/D凹陷之上。
S/D特徵260可包括鍺(Ge)、矽(Si)、砷化鎵(GaAs)、鋁砷化鎵(AlGaAs)、鍺化矽(SiGe)、磷砷化鎵(GaAsP)、銻化鎵(GaSb)、銻化銦(InSb)、砷化鎵銦(InGaAs)、砷化銦(InAs)、或其他合適的材料。S/D特徵260可藉由磊晶生長製程，像是CVD沉積技術(例如：氣相磊晶(VPE)及/或超高真空化學氣相沉積(UHV-CVD)、分子束磊晶、及/或其他合適的製程)形成。在以S/D特徵260填充S/D凹陷之後，更進一步磊晶生長的頂層S/D特徵260水平地擴展且晶面(facets)可開始形成，像是一菱形面。S/D特徵260可在磊晶製程期間經原位(in-situ)摻雜。或者，S/D特徵260並非經原位摻雜，而是實施一植入製程(即，一接面植 入製程)以摻雜S/D特徵260。可實施一或多個退火製程以活化摻質。退火製程包括快速熱退火(RTA)及/或雷射退火製程。
在本實施例中，初始結構205包括沉積於基板210之上的一介電層270。如所示，形成介電層270以使其完全填充於HK/MGs 240之間的間隔中，並使S/D特徵260內埋於介電層270中。介電層270可包括氧化矽、具有比熱氧化矽還低的介電常數(k)的介電材料(因此被稱為低介電常數介電材料層)、及/或其他合適的介電材料層。介電層270可包括一單層或多層。可藉由CVD、ALD或旋塗式塗佈(spin-on coating)沉積第二導電特徵260。在一些實施例中，介電層270與側壁間隔250和閘極HM 245不同，以在下列更加詳述的後續蝕刻期間達到蝕刻選擇性。例如，當側壁間隔250和閘極HM 245都包括氮化矽時，介電層270包括氧化矽。
參照第1圖及第3A圖，一旦接受初始結構205，方法100進行至步驟104，形成具有開口320的HM 310於介電層270之上。指定的S/D特徵260位於開口320之中。在一些實施例中，開口320的邊緣朝向指定的S/D特徵260與側壁間隔250的每一個邊緣對齊，如第3A圖所示。或者，在一些實施例中，如第3B圖所示，開口320具有較大的寬度，以使其延伸至鄰近的HK/MGs 240(與閘極HM 245)以獲得優點，像是鬆弛(relaxing)微影製程解析度限制。
在一實施例中，HM 310為一經圖案化的光阻層。在另一實施例中，形成HM 310係藉由沉積一HM層於介電層之上、沉積光阻層於HM層之上、圖案化光阻層、接著透過圖案 化光阻層蝕刻HM層以圖案化HM層、並接著透過圖案化HM層蝕刻HM 310以於HM 310中形成開口320。
參照第1圖及第4A圖，方法100進行至步驟106，透過開口320蝕刻介電層270以形成一接觸溝槽410，且S/D特徵260曝露在接觸溝槽410中。溝槽蝕刻可包括濕蝕刻、乾蝕刻、及/或前述之組合。做為一個示例，溝槽蝕刻包括電漿乾蝕刻製程，其利用氟基化學物質(fluorine-based chemistry)，像是CF4、SF6、CH2F2、CHF3、及/或C2F6。每一個蝕刻製程可依據各蝕刻參數調整，像是所使用的摻質、蝕刻溫度、蝕刻溶液濃度、蝕刻壓力、蝕刻流速、及/或其他合適的參數。
如所示，在鄰近的閘極HM 245曝露在相同的第二開口320(如第3B圖所示)的情況下，選擇可選擇性蝕刻介電層270，而不實質地(substantially)蝕刻閘極HM 245和側壁間隔250的溝槽蝕刻製程，如第4B圖所示。據此，在蝕刻製程期間，鄰近的HK/MG240受到閘極HM 245和側壁間隔250的保護。換句話說，閘極HM 245和側壁間隔250的曝露部分做為一子蝕刻罩幕(sub-etch-mask)。因此，接觸溝槽410包括一上部分410U和一下部分410L。上部分410U比下部分410L寬。
形成接觸溝槽410之後，藉由另一個蝕刻製程移除HM 310。在HM 310為光阻圖案的實施例中，藉由濕式去光阻(wet stripping)及/或電漿灰化移除HM 310。
參照第1圖、第5A圖(結合第4A圖所述的製程)及第5B圖(結合第4B圖所述的製程)，方法100進行至步驟107，形成一矽化物層510於曝露的S/D特徵260之上以降低接觸電阻。在 一些實施例中，矽化物層510形成於S/D特徵260的頂表面之上。矽化物層510可包括這種材料，像是矽化鎳、矽化鈷、矽化鎢、矽化鉭、矽化鈦、矽化鉑、矽化鉺、矽化鈀、及/或前述之組合。可藉由矽化(silicidation)，像是自對準矽化物(金屬矽化物)形成矽化物層510，其中金屬在退火製程期間經沉積、與矽化物反應，接著藉由蝕刻移除未反應的金屬。特別地，在金屬沉積製程之後，為了退火將溫度提升以提高Si和金屬之間的反應以形成矽化物，最後可蝕刻掉未反應的金屬。退火可為單步驟或多步驟退火，取決於金屬材料或其他條件。或者，可藉由包括矽化物沉積像是CVD、PVD、或ALD之一步驟形成矽化物層510。
做為一個示例，經沉積的金屬層包括鈦(Ti)。在金屬沉積(例如：Ti)之後，運用退火製程以使金屬(例如：Ti)與S/D特徵260的矽反應，進而形成矽化物層510，像是Ti矽化物(TiSi)。接著，以一蝕刻製程移除未反應的Ti層。
一般來說，金屬層會被填充在接觸溝槽410中以形成一接觸金屬，提供與下層特徵(像是S/D特徵260)之一的電性連接。在積體電路工業的先進技術節點中，半導體裝置的關鍵尺寸變得越來越小。接觸電阻在裝置性能上扮演重要的因素，像是升壓(boosting)Ion/Ioff性能。為了降低接觸電阻，需要一種低電阻率金屬層，其與接觸溝槽的側壁/底部具有良好黏著力。做為一個示例，鈷(Co)金屬的電阻率62.4nΩ．m比鎢(W)金屬的電阻率52.8nΩ．m低得多。在接觸溝槽410中沉積這麼低電阻率的金屬層且具有良好的黏著性和良好的共形度(conformity)是 一個挑戰，且特別是在裝置尺寸下降以使得接觸溝槽410的深寬比(aspect ratio)變得越來越高的情況下。為了解決這個問題，本揭露提供在接觸溝槽中具有良好黏著力和共形度(conformity)之金屬層的形成方法。
參照第1圖、第6A圖(結合第5A圖所述的製程)及第6B圖(結合第5B圖所述的製程)，方法100進行到步驟110，沿著接觸溝槽410的側壁形成一黏著層520並朝向S/D特徵260延伸在接觸溝槽410之中。選擇對於要填充在接觸溝槽410中的金屬層具有適當黏著力的黏著層520。在本實施例中，要填充在接觸溝槽410中的金屬層包括鈷(Co)層，且Co層的黏著層520包括氮化鈦(TiN)。選擇具有相當薄的厚度的TiN黏著層520，其使得將要填充的Co層獲得較大的體積，並導致較低的接觸電阻。也選擇具有高膜密度及表面上具有低氧鈦比例的TiN黏著層520以提高與將要填充的Co層的黏著力。在一實施例中，TiN黏著層520的厚度小於30埃，密度約為4.75g/cm3，且氧鈦比例(O/Ti)小於0.5。TiN黏著層520沿著接觸溝槽410的側壁和底部共形地(comformably)形成，其共形度(conformity)大於90%。此處，共形度代表沿著溝槽底部的厚度與沿著溝槽側壁的厚度之比較。
在一實施例中，以氬氣、氦氣、及氮氣的混合前驅物載體氣體攜帶四(二甲胺基)鈦(TDMAT)/TiCl4前驅物，藉由ALD製程沉積TiN黏著層520。沉積製程包括介於200℃至450℃的製程溫度及介於0.5托至10托的沉積壓力。
黏著層520也可包括氮化鉭(TaN)、氮化鎢(WN)、 鈦矽氮化物(TiSiN)或鉭矽氮化物(TaSiN)、及/或其他材料，且可藉由CVD、PVD、金屬有機化學氣相沉積(MOCVD)、電鍍、及/或其他技術沉積。
如所示，在接觸溝槽410形成有上部分410U和下部分410L(如第4B圖所示)的情況下，黏著層520也會沿著上部分410U沉積，如第6B圖所示。
參照第1圖、第7A圖(結合第6A圖所述之製程)和第7B圖(結合第6B圖所述之製程)，方法100進行至步驟110，形成金屬層610於接觸溝槽410中的黏著層520之上。在本實施例中，導電層610包括一鈷(Co)層。在一實施例中，首先藉由ALD製程將鈷(Co)種子層沉積在TiN黏著層520之上以獲得良好的共形沉積，接著藉由塊狀-鈷PVD製程以高沉積速度填充接觸溝槽410。在一實施例中，鈷(Co)種子層具有介於5Å至100Å的一厚度。在本實施例中，TiN黏著層520對於鈷(Co)層610不只顯示了良好黏著特性，還顯示了改良的電遷移電阻(electromigration resistance)。
或者，金屬層610可包括銅(Cu)、銅錳(CuMn)、銅鋁(CuAl)或銅矽(CuSi)、鋁(Al)、鎢(W)、及/或其他合適的導電材料。金屬層610可藉由ALD、PVD、CVD、金屬有機化學氣相沉積(MOCVD)、電鍍、及/或其他技術沉積。
此外，金屬層610可凹陷，並與位於介電層270之上的黏著層520一起為後續製程(像是微影製程)提供一平坦外形，如第8A圖(結合第7A圖所述之製程)所示。在一些實施例中，實施一CMP製程以移除多餘的金屬層610和黏著層520。接觸溝 槽410中剩餘的金屬層610形成一接觸金屬615。
如所示，在接觸溝槽410形成有上部分410U和下部分410L(結合第7B圖所述之製程)的情況下，接觸金屬615具有上部分615U和下部分615L，如第8B圖所示。上部分615U的寬度比下部分615L大。
可於方法100之前、期間、及之後提供額外的步驟，且方法100的額外實施例中，前述的一些步驟可經置換、刪除、或移動。
半導體裝置200可包括額外的特徵，其可藉由後續製程形成。例如，各種導孔(via)/導線和形成於基板210之上的多層內連線特徵(例如，金屬層和內層介電質)。例如，多層內連線包括垂直內連線，像是傳統的導孔(via)或接觸(contact)，及水平內連線，像是金屬線路。各種內連線特徵可執行各種導電材料，包括銅、鎢、及/或矽化物。在一示例中，使用鑲嵌及/或雙鑲嵌製程來形成銅相關的多層內連線結構。
基於以上所述，可看到本揭露提供鈷接觸金屬的形成方法。在形成具有接觸溝槽的鈷層之前，藉由形成薄ALD TiN的方法以提高黏著力並改良電遷移電阻。本方法提供穩健對接(butted)的接觸金屬形成製程以降低接觸電阻。
本揭露提供形成半導體裝置的許多不同實施例，其對於現有的技術提供一或多種改良。在一實施例中，半導體裝置之形成方法包括：形成一源極/汲極特徵於一基板之上、形成一介電層於源極/汲極特徵之上、形成一接觸溝槽穿過介電層以曝露源極/汲極特徵、以一第一原子層沉積(ALD)製程沉 積一氮化鈦(TiN)層於接觸溝槽中、以及沉積一鈷層於接觸溝槽中的TiN層之上。
在另一實施例中，半導體裝置之形成方法包括：形成一第一閘極堆疊和一第二閘極堆疊於一基板之上、形成一源極/汲極特徵於基板之上。源極/汲極特徵位於第一和第二閘極堆疊之間。半導體裝置之形成方法也包括：形成一介電層於源極/汲極特徵之上、形成一接觸溝槽穿過介電層以曝露源極/汲極特徵、形成一自對準矽化物層於曝露的源極/汲極特徵之上、以及以一第一原子層沉積(ALD)製程沉積一氮化鈦(TiN)層於接觸溝槽中，包括位於自對準矽化層之上。半導體裝置之形成方法也包括：沉積一鈷層於接觸溝槽中的TiN層之上。
又在另一實施例中，半導體裝置之形成方法包括：形成一介電層於一基板之上、形成一溝槽於介電層中、以一第一原子層沉積(ALD)製程形成一氮化鈦層於溝槽中、以及形成一鈷層於氮化鈦層之上。
前述內文概述了許多實施例的特徵，以使本技術領域中具有通常知識者可以從各個方面更佳地了解本揭露。本技術領域中具有通常知識者應可理解，且可輕易地以本揭露為基礎來設計或修飾其他製程及結構，並以此達到相同的目的及/或達到與在此介紹的實施例等相同之優點。本技術領域中具有通常知識者也應了解這些相等的結構並未背離本揭露的發明精神與範圍。在不背離本揭露的發明精神與範圍之前提下，可對本揭露進行各種改變、置換或修改。
雖然本揭露已以數個較佳實施例揭露如上，然其 並非用以限定本揭露，任何所屬技術領域中具有通常知識者，在不脫離本揭露之精神和範圍內，當可作任意之更動與潤飾，因此本揭露之保護範圍當視後附之申請專利範圍所界定者為準。
100‧‧‧方法
102、104、106、107、110、112‧‧‧步驟

Claims (1)

  1. 一種半導體裝置之形成方法，包括：形成一源極/汲極特徵於一基板之上；形成一介電層於該源極/汲極特徵之上；形成一接觸溝槽穿過該介電層以曝露該源極/汲極特徵；以一第一原子層沉積(ALD)製程沉積一氮化鈦(TiN)層於該接觸溝槽中；以及沉積一鈷層於該接觸溝槽中的該TiN層之上。
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