TW201725719A - 磊晶再成長之異質結構奈米線側向穿隧場效電晶體 - Google Patents
磊晶再成長之異質結構奈米線側向穿隧場效電晶體 Download PDFInfo
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- TW201725719A TW201725719A TW105132367A TW105132367A TW201725719A TW 201725719 A TW201725719 A TW 201725719A TW 105132367 A TW105132367 A TW 105132367A TW 105132367 A TW105132367 A TW 105132367A TW 201725719 A TW201725719 A TW 201725719A
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- Electrodes Of Semiconductors (AREA)
Abstract
在形成位於基板上並且被閘極結構所圍繞的掩埋奈米線段之後,覆蓋該掩埋奈米線段的第二端及該閘極結構,在該掩埋奈米線段的第一端上成長磊晶源極區,隨後覆蓋該磊晶源極區及該閘極結構,在該掩埋奈米線段的第二端上成長磊晶汲極區。該磊晶源極區包括第一半導體材料以及第一導電類型的摻雜劑,而該磊晶汲極區包括與該第一半導體材料不同的第一半導體材料以及與第一導電類型相反的第二導電類型的摻雜劑。
Description
本發明係關於半導體結構,特別是關於奈米線穿隧場效電晶體。
由於亞60毫伏/十倍亞閾值斜率(sub-60mV/decade sub-threshold slope),穿隧場效電晶體(TFET)能夠降低超低功耗的供應電壓及節能計算,已逐漸形成為傳統的互補型金屬氧化物半導體(CMOS)裝置的替代物。TFET具有獨特的裝置特性,例如非對稱的源/汲的設計能引致單向傳導並提高通態(on-state)密勒電容效應(Miller capacitance effect),因此能在低電壓下陡峭的切換(steep switching)。TFET要求低帶隙材料、陡峭的穿隧接面及改進的靜電。奈米線TFET對低功耗有吸引力,因為奈米級的導線的高密度應用本身可以為裝置提供的優秀的靜電控制。因此,需要用於製造側向異質結構的奈米線TFET方法。
本發明提供奈米線的集成設計,使側向異質結構的奈米線TFET成為可行。形成位於基板上並且被閘極結構所圍繞的掩埋奈米線段之後,覆蓋該掩埋奈米線段的第二端及該閘極結構,在該掩埋奈米線段的第一端上成長磊晶源極區,隨後覆蓋該磊晶源極區及該閘極結構,在該掩埋奈米線段的第二端上成長磊晶汲極區。該磊晶源極區包括第一半導體材料以及第一導電類型的摻雜劑,而該磊晶汲極區包括與該第一半導體材料不同的第一半導體材料以及與第一導電類型相反的第二導電類型的摻雜劑。
根據本發明的一個態樣,提供一種半導體結構。該半導體結構包括:位於基板上並圍繞至少一個掩埋奈米線段的閘極結構。該至少一個掩埋奈米線段具有第一端以及與第一端相對的第二端。磊晶源極區從該至少一個掩埋奈米線段的第一端延伸。該磊晶源極區包括第一半導體材料及第一導電類型的摻雜劑。磊晶汲極區從該至少一個掩埋奈米線段的第二端延伸。該磊晶汲極區包括與該第一半導體材料不同的第二半導體材料以及與第一導電類型相反的第二導電類型的摻雜物。
根據本發明的另一個態樣,提供一種形成半導體結構的方法。該方法包括形成位於基板上並由閘極結構所圍繞的至少一個掩埋奈米線段。該至少一個掩埋奈米線段具有第一端以及與第一端相對的第二端。然後從該至少一個掩埋奈米線段的第一端磊晶形成磊晶源極區。該磊晶源極區包括第一半導體材料及第一導電類型的摻雜劑。
接著,從該至少一個掩埋奈米線段的第二端磊晶形成磊晶汲極區。該磊晶汲極區包括與該第一半導體材料不同的第二半導體材料以及與第一導電類型相反的第二導電類型的摻雜物。
10‧‧‧支持基板
20‧‧‧掩埋絕緣層
22‧‧‧凹陷表面
30‧‧‧半導體頂部
30N‧‧‧奈米線
30P1‧‧‧第一襯墊部
30P2‧‧‧第二襯墊部
30S‧‧‧掩埋奈米線段
42‧‧‧閘極介電質
42L‧‧‧閘極介電層
44‧‧‧閘極電極
44L‧‧‧閘極電極層
50‧‧‧閘極間隔物
50L‧‧‧閘極間隔層
60‧‧‧圖案化第一遮罩層
62‧‧‧第一磊晶半導體區域
70‧‧‧圖案化第二遮罩層
72‧‧‧第二磊晶半導體區域
82‧‧‧第一金屬半導體合金區域
84‧‧‧第二金屬半導體合金區域
90‧‧‧接觸層級介電層
92‧‧‧第一接觸結構
第1圖是根據本發明的實施例,形成半導體頂部之後的示例性半導體結構的橫截面圖。該半導體頂部包括通過第一襯墊部以及第二襯墊部懸浮在結構上方的奈米線。
第2圖是第1圖的示例性半導體結構在形成包括從底部到頂部的閘極介電層以及位於該半導體頂部及該基板上方的閘極電極層的閘極材料疊層之後的橫截面圖。
第3圖是第2圖的示例性半導體結構在通過圖案化閘極材料疊層形成閘極疊層于各奈米線段的部分的上方之後的橫截面圖。
第4圖是第3圖的示例性半導體結構在形成於半導體頂部、基板及閘極疊層的露出表面上的閘極間隔層之後的橫截面圖。
第5圖是第4圖的示例性半導體結構在閘極疊層的側壁上形成閘極間隔物以及移除未被閘極疊層或閘極間隔物覆蓋的半導體頂部的部分,以提供掩埋奈米線段之後的橫截面圖。
第6圖是第5圖的示例性半導體結構在覆蓋
該掩埋奈米線段的第二端並形成從該掩埋奈米線段的第一端延伸的第一磊晶半導體區域之後的橫截面圖。
第7圖是第6圖的示例性半導體結構在覆蓋該第一磊晶半導體區域並形成從該掩埋奈米線段的第二端延伸的第二磊晶半導體區域之後的橫截面圖。
第8圖是第7圖的示例性半導體結構在該第一磊晶半導體區域的頂上形成第一金屬半導體合金區域以及在該第二磊晶半導體區域的頂上形成第二金屬半導體合金區域之後的橫截面圖。
第9圖是第8圖的示例性半導體結構在形成接觸該第一金屬半導體合金區域的第一接觸結構以及接觸該第二金屬半導體合金區域的第二接觸結構之後的橫截面圖。
本發明現在將參照以下的討論及伴隨本發明的附圖作更詳細地說明。應該注意的是,本發明提供的附圖僅用於說明目的,因此,附圖不是按比例繪製的。還應該注意到的是相似及對應的組件用類似的元件符號表示。
在下面的描述中,闡述許多具體細節,例如特定的結構、部件、材料、尺寸、製程步驟及技術,以提供對本發明的各種實施例的理解。然而,本發明的各種實施例可以在沒有這些特定細節的情況下為本領域的普通技術人員所理解的。在其它實例中,為了避免模糊本發明,沒有詳細描述公知的結構或製程步驟。
參照第1圖,根據本發明的實施例的示例性半導體結構包括:形成在基板上方的半導體頂部30。該半導體頂部30包括設在一端的第一襯墊部30P1、位於相對端的第二襯墊部30P2,以及連接該第一襯墊部30P1及該第二襯墊部30P2的一或多個奈米線30N。
通過圖案化絕緣體上半導體(semiconductor-on-insulator,SOI)基板的半導體頂層可形成半導體頂部30。該SOI基板包括從底部到頂部的支持基板(handle substrate)10、掩埋絕緣層20以及導出該半導體頂部30的半導體頂層(未示出)。
該支持基板10可包括半導體材料,例如,矽(Si)、矽鍺(SiGe)、矽鍺碳化物(SiGeC)、碳化矽(SiC)、III-V族化合物半導體、II-VI族化合物半導體或者其任何組合。多層的半導體材料也可以作為支持基板10的半導體材料。在一個實施例中,支持基板10由單結晶矽所構成。支持基板10的厚度可以從50微米到2毫米,儘管更小或更大的厚度也可以使用。
掩埋絕緣層20可以包括介電材料如氧化矽、氮化矽、氧氮化矽、氮化硼或其組合。在一個實施方案中,掩埋絕緣層20可以通過傳統的沉積製程形成,例如化學氣相沉積(CVD)或物理氣相沉積(PVD)。在另一個實施方案中,掩埋絕緣層20可以使用熱成長製程形成,如熱氧化,以轉換支持基板10的表面部分。所形成的掩埋絕緣層20的厚度可以從50奈米至200奈米,儘管更小或更
大的厚度也可以使用。
該半導體頂層可以包括如上述用於支持基板10的任何半導體材料。可以用於半導體頂層的示例性的半導體材料層包括,但不限於,Si、Ge、SiGe、SiC及SiGeC以及III-V族化合物半導體,例如,InAs、GaAs、GaAsSb以及InP。該半導體頂層及該支持基板10的半導體材料可以是相同的或不同的。在一個實施方案中,該半導體頂層包括單晶半導體材料,例如,單晶矽。
半導體頂層通常提供本徵單晶半導體層,並通過傳統的沉積製程形成,例如CVD或電漿增強型化學氣相沉積(PECVD)。所形成的半導體頂層可具有從20奈米至600奈米的厚度,儘管更小或更大的厚度也可以使用。可替代地,半導體頂層可以使用兩個半導體晶圓以其間的絕緣體粘結在一起的智切(smart cut)製程形成。
該半導體頂層可以通過微影圖案化及蝕刻進行圖案化。例如,可以施加光阻層(未示出)在半導體頂層上方並且以微影曝光形成位於半導體頂層上方的翅片及連接襯墊(landing pads)的圖案。該光阻層的圖案通過非等向性蝕刻轉換到該半導體頂層,以提供含奈米線段結構(nanowire portion-containing structure)(未示出)。該非等向性蝕刻可以是乾式蝕刻,例如,反應離子蝕刻(RIE)或濕式蝕刻。該含奈米線段結構包括第一襯墊部30P1以及第二襯墊部30P2,以及連接第一襯墊部30P1及第二襯墊部30P2的一或多個奈米線段(未示出)。該奈米線3ON稍
後形成用於奈米線段。
掩埋絕緣層20通過等向性蝕刻在未被半導體頂部30所覆蓋的區域是凹陷的。當掩埋絕緣層20的物理性露出部分的凹陷過程中,該第一及第二襯墊部(30P1、30P2)可被用作蝕刻遮罩。該等向性蝕刻可以是濕式蝕刻或乾式蝕刻,其選擇性地移除該掩埋絕緣層20的介電材料至半導體頂部30的半導體材料。隨後從奈米線段的下面以及從該第一及第二襯墊部30P1、30P2的周邊部分的下面移除部分的掩埋絕緣層20。該奈米線段通過第一及第二襯墊部30P1、30P2懸浮在掩埋絕緣層20的凹陷表面22的上方。
隨著等向性蝕刻進行,該奈米線段可被平滑以形成通過第一襯墊部30P1及第二襯墊部30P2懸浮在掩埋絕緣層20上方的奈米線30N。平滑該奈米線段可通過例如在氫氣中對奈米線段退火來實行。這樣形成的各奈米線30N可具有沿平面的非矩形垂直橫截面形狀,該平面垂直於從第一襯墊部30P1朝著第二襯墊部30P2的方向。例如,該奈米線30N可具有圓形或橢圓形的垂直橫截面形狀。可執行氧化製程以縮小該奈米線30N的直徑以得到所需的尺寸。
參照第2圖,閘極材料疊層從底部到頂部包括,形成閘極介電層42L及閘極電極層44L。該閘極介電層42L被保形地沉積在該半導體頂部30的物理性暴露表面上。該閘極介電層42L可以包括高介電常數(高k)的介電材料,該介電材料的介電常數大於7.9及/或傳統的閘極
介電材料如氧化矽、氮化矽、及/或氮氧化矽。高k介電材料的實例包括,但不限於HfO2、ZrO2、La2O3、Al2O3、TiO2、SrTiO3、LaAlO3、Y2O3、HfOxNy、ZrOxNy、La2OxNy、Al2OxNy、TiOxNy、SrTiOxNy、LaAlOxNy、Y2OxNy、其矽酸鹽以及其合金。各x的值獨立地從0.5到3以及各y的值獨立地從0到2。
閘極介電層42L可以通過半導體頂部30的半導體材料的表面部分轉化為介電材料(例如介電氧化物,介電氮化物,及/或介電氮氧化物)而形成。可交換或附加地,該閘極介電層42L可以通過介電材料(如金屬氧化物,金屬氮化物及/或金屬氮氧化物)的保形沉積而形成。可以進行半導體材料的表面部分轉換成介電材料,例如,通過熱氧化,熱氮化,電漿氧化,及/或電漿氮化。能夠進行介電材料的沉積,例如,通過原子層沉積(ALD)或CVD。形成該閘極介電層42L可具有可以從0.9奈米到6奈米的厚度,儘管更小及更大的厚度也可以採用。
在閘極介電層42L上方沉積該閘極電極層44L。該閘極電極層44L填充奈米線30N及掩埋絕緣層20之間的空間。該閘極電極層44L可以包括導電材料,它可以是摻雜的半導體材料、金屬材料或是其組合。該摻雜的半導體材料,如果存在的話,可以是摻雜的多晶矽、摻雜的多晶鍺、摻雜的矽鍺合金、任何其它摻雜的元素或化合物半導體材料,或其組合。金屬材料,如果存在的話,可以是通過CVD、PVD或其組合來沉積的任何金屬材料。例
如,該金屬材料可以包括鋁及/或鎢。該閘極電極層44L的厚度可以從100奈米到500奈米,儘管更低及更高的厚度也可以使用。
參照第3圖,閘極疊層通過圖案化閘極材料疊層(42L、44L)而形成。具體地,可在閘極電極層44L上方施加硬遮罩層並微影圖案化,以形成圖案化硬遮罩層(未示出),用於定義該閘極疊層的位置、大小及形狀。該硬遮罩層可以由例如介電氮化物(如氮化矽)形成。該閘極介電層42L及閘極電極層44L未被圖案化硬遮罩層覆蓋的部分通過非等向性蝕刻移除。進行非等向性蝕刻之後,執行等向性蝕刻以移除該閘極介電層42L及閘極電極層44L的部分,其留下在奈米線30N下方並且沒有被圖案化硬遮罩層掩蔽的區域。可以執行等向性蝕刻,例如,使用稀釋的氫氟酸(DHF)。任何剩餘的圖案化硬遮罩層可通過氧基的電漿蝕刻移除。
如此形成的閘極疊層包含,來自閘極介電層42L的剩餘部分的閘極介電質42,以及來自閘極電極層44L的剩餘部分的閘極電極44。如第2圖所示,由於奈米線30已懸浮在掩埋絕緣層20上方,該閘極疊層(42,44)完全圍繞各奈米線30N的一部分。這被稱為一個全環繞閘極(gate-all-around,GAA)配置。
參照第4圖,利用CVD或ALD保形沉積介電間隔物材料,在半導體頂部30、掩埋絕緣層20以及閘極疊層(42、44)的暴露表面上形成閘極間隔層50L。示
例性介電間隔件材料可包括,但不限於,介電氮化物及介電氧化物。在一個實施方案中,閘極間隔層50L由氮化矽構成。該閘極間隔層50L的厚度可以是從3奈米到100奈米,儘管更小及更大的厚度也可以使用。
參考第5圖,執行非等向性蝕刻以移除閘極間隔層50L的水平部分。非等向性蝕刻可以是例如RIE。閘極間隔層50L剩餘的垂直部分構成位於閘極疊層(42、44)的側壁上的閘極間隔物50。該閘極疊層(42、44)及該閘極間隔物50一起定義閘極結構(42、44、50)。
隨後,可以執行選擇性蝕刻以移除該第一及第二襯墊區30P1、30P2以及未被閘極結構(42、44、50)覆蓋的奈米線30N的部分,留下掩埋奈米線段30S。該掩埋奈米線段30S是奈米線30N的剩餘部分並由該閘極結構(42、44、50)所圍繞。在一個實施方案中並如第5圖所示,掩埋區段30S的端面垂直地與閘極間隔物50的外側壁一致。該選擇性蝕刻可例如是化學HBr基的RIE,其移除該半導體材料,同時減少對介電材料(如氧化矽及氮化矽)的刻蝕。
參照第6圖,通過第一選擇性磊晶成長製程形成鄰接到該閘極結構(42、44、50)的第一側的第一磊晶半導體區域62。該第一磊晶半導體區域62合併相鄰的掩埋線段30S的第一端上。術語“磊晶成長及/或沉積”是指在半導體材料的沉積表面上成長半導體材料,其中,正在成長的半導體材料具有與半導體材料沉積表面相同的
(或幾乎相同)的結晶特性。第一磊晶半導體區域62可具有多刻面(faceted)的表面。
第一磊晶半導體區域62可以利用塊遮罩(block mask)技術形成。第一遮罩層(未示出)施加在掩埋絕緣層20、掩埋奈米線段30S及閘極結構(42、44、50)上方,然後微影圖案化,使得圖案化第一遮罩層60覆蓋掩埋奈米線段30S的第二端,同時露出掩埋奈米線段30S的第一端面,該表面將經受磊晶沉積。第一遮罩層可以是光阻層或是與硬遮罩層結合的光阻層。然後,在掩埋奈米線段30S的第一端面上方,但不能在掩埋絕緣層20及閘極間隔物50的介電表面上,通過磊晶沉積半導體材料形成第一磊晶半導體區域62。該第一磊晶半導體區域62可為n型或p型摻雜。示例性的p型摻雜劑包括,但不限於,硼(B)、鋁(Al)、鎵(Ga)及銦(In)。示例性的n型摻雜劑包括,但不限於,銻(Sb)、砷(As)及磷(P)。在該第一半導體材料的磊晶成長過程中,摻雜劑可以通過原位(in-situ)摻雜引入到該第一磊晶半導體區域62。在本發明的一個實施例中,第一磊晶半導體區域26具有p型導電性。
提供第一磊晶半導體區域62的半導體材料可以選自,但不限於,矽、鍺矽鍺、碳化矽、碳化矽鍺、化合物半導體材料、或其合金。在部分情況下,當掩埋奈米線段30S是由本徵矽構成時,第一磊晶半導體區域62可以包括p摻雜的鍺。因此,異質接面(heterojunction)存在於各掩埋奈米線段30S及第一磊晶半導體區域62之間的界
面。在部分情況下,當第一磊晶半導體區域62是由III-V族化合物半導體材料構成時,該掩埋奈米線段30S可以包括半導體材料,該半導體材料晶格匹配並且具有與該第一磊晶半導體區域62的III-V族化合物半導體材料校準的破碎隙能帶。例如當掩埋奈米線段30S包括砷化銦鎵,該第一磊晶半導體區域62可包括GaAsSb。在另一實例中,當掩埋奈米線段30S包括InAs時,該第一磊晶半導體區域62可包括GaSb。
形成第一磊晶半導體區域62之後,可以移除該圖案化第一遮罩層60,例如,通過氧基的電漿蝕刻。
參照第7圖,通過第二選擇性磊晶成長製程形成鄰接到與第一側相對的該閘極結構(42、44、50)的第二側的第二磊晶半導體區域72。該第二磊晶半導體區域72合併相鄰的與第一端相對的掩埋奈米線段30S的第二端上。第二磊晶半導體區域72可具有多刻面的表面。
通過圖案化第二遮罩層70覆蓋該第一磊晶半導體區域62以及閘極結構(42、44、50)時,在掩埋奈米線段30S的第二端面上方通過磊晶沉積第二半導體材料可以形成第二磊晶半導體區域72。該第二磊晶半導體區域72包括半導體材料,其與第一磊晶半導體區域62的半導體材料不同。該第二磊晶半導體區域72的半導體材料通常是相同于掩埋奈米線段30S的半導體材料。摻雜該第二磊晶半導體區域72的摻雜劑所具有的導電類型可與第一磊晶半導體區域62的導電類型相反。例如,如果第一磊晶半
導體區域62具有p型導電性,第二磊晶半導體區域72可以具有n型導電性,並且反之亦然。在一個實施方案中,當該第一磊晶半導體區域62由p型鍺構成及該掩埋奈米線段30S是由本徵矽構成時,該第二磊晶半導體區域72可包括n型摻雜的矽。因此,同質結存在於各掩埋奈米線段30S及第二磊晶半導體區域72之間的界面。
形成磊晶源極區之後,可以移除該圖案化第二遮罩層70,例如,通過氧基的電漿蝕刻。
對於奈米線FET,該第一磊晶半導體區域62可作為源極區,而該第二磊晶半導體區域72可作為汲極區。由於第一磊晶半導體區域62及第二磊晶半導體區域72由不同的半導體材料以及不同的導電類型所構成,因此得到具有非對稱的源極及汲極區的奈米線TFET。由於直接帶隙及較高的隧穿效率,III-V族半導體材料是奈米線TFET的源極及汲極區的優選的材料。
參照第8圖,在第一磊晶半導體區域62的頂上形成第一金屬半導體合金區域82,及在第二磊晶半導體區域72的頂上形成第二金屬半導體合金區域84。該第一及第二半導體合金區域82、84各者包括金屬矽化物或金屬鍺化物。形成該第一及第二金屬半導體合金區域82、84,可以首先在該第一及第二磊晶半導體區域62、72的表面上經由沉積金屬,例如、鎳、鉑、鈷以及合金,如NiPt。然後進行退火,令該金屬與該第一及第二磊晶半導體區域62、72之間發生反應。退火後,移除任何未反應的金屬。
在一個實施方案中,當閘極電極44是由摻雜的多晶矽構成時,也可以在閘極疊層(42、44)的頂部形成的第三金屬半導體合金區域(未示出)。
參照第9圖,在該掩埋絕緣層、該閘極結構(42、44、50)以及第一金屬半導體合金區域82,84上方形成接觸層級介電層90。該接觸層級介電層90可以包括介電材料,包括,例如,氧化物,氮化物或氧氮化物。在一個實施例中,接觸層級介電層90包括二氧化矽。例如,通過CVD或旋塗,可以形成接觸層級介電層90。接觸層級介電層90可以是自平面化,或接觸層級介電層90頂面可以被平坦化,例如,通過化學機械平坦化(CMP)。在一個實施例中,接觸層級介電層90的平面化的頂面位於該閘極電極44的頂面的上方。
在接觸層級介電層90中形成接觸結構,以提供與金屬半導體合金區域82、84的電性接觸。該接觸結構包括接觸該第一金屬半導體合金區域82的頂面的第一接觸結構92,以及接觸該第二金屬半導體合金區域84的頂面的第二接觸結構。通過由微影圖案化及非等向性蝕刻的組合,可以在接觸層級介電層90中形成接觸開口(未示出),隨後通過沉積導電材料(例如,鎢)及平坦化,該平坦化從接觸層級介電層90的頂面上方移除導電材料的多餘部分,以形成該第一及第二接觸結構。任選地,在導電材料填充到互連接觸開口之前,可以在接觸開口的側壁及底部表面上形成接觸襯墊(未示出)。接觸襯墊可包括TiN。
雖然本發明已特別地示出並相對於優選實施例描述了方法及結構,但本領域的技術人員應當理解,可以在不脫離本發明的精神及範圍的情況下作出上述及在形式與細節上的其他變化。因此,本發明的方法及結構意圖是不限定於描述及說明的確切形式及細節,而是屬於所附申請專利範圍的範圍之內。
10‧‧‧支持基板
20‧‧‧掩埋絕緣層
30S‧‧‧掩埋奈米線段
42‧‧‧閘極介電質
44‧‧‧閘極電極
50‧‧‧閘極間隔物
62‧‧‧第一磊晶半導體區域
72‧‧‧第二磊晶半導體區域
82‧‧‧第一金屬半導體合金區域
84‧‧‧第二金屬半導體合金區域
90‧‧‧接觸層級介電層
92‧‧‧第一接觸結構
Claims (20)
- 一種半導體結構,包括:閘極結構,位於基板上並圍繞至少一個掩埋奈米線段,該至少一個掩埋奈米線段具有第一端及與該第一端相對的第二端;磊晶源極區,從該至少一個掩埋奈米線段的該第一端延伸,該磊晶源極區包括第一半導體材料及第一導電類型的摻雜劑;以及磊晶汲極區,從該至少一個掩埋奈米線段的該第二端延伸,該磊晶汲極區包括與該第一半導體材料不同的第二半導體材料以及與該第一導電類型相反的第二導電類型的摻雜物。
- 如申請專利範圍第1項所述的半導體結構,其中,該至少一個掩埋奈米線段包括該第二半導體材料並且是本徵的。
- 如申請專利範圍第2項所述的半導體結構,其中,該磊晶源極區包含鍺的p型摻雜,該磊晶本徵區包括矽的n型摻雜,並且該至少一個掩埋奈米線段包括本徵矽。
- 如申請專利範圍第2項所述的半導體結構,其中,該磊晶源極區包含GaAsSb的p型摻雜,該磊晶本徵區包括InGaAs的n型摻雜,並且該至少一個掩埋奈米線段包括InGaAs。
- 如申請專利範圍第1項所述的半導體結構,其中,該至少一個掩埋奈米線段包括多個掩埋奈米線段,該第一磊 晶源極區在該第一端合併該多個掩埋奈米線段,以及該第二磊晶汲極區在該第二端合併該多個掩埋奈米線段。
- 如申請專利範圍第1項所述的半導體結構,其中,該基板包括支持基板以及在該支持基板上方的掩埋絕緣層,其中,該閘極結構存在於該掩埋絕緣層的凹陷區域上。
- 如申請專利範圍第1項所述的半導體結構,還包括:在該磊晶源極區頂上的第一金屬半導體合金區域,以及該磊晶汲極區頂上的第二金屬半導體合金區域。
- 如申請專利範圍第7項所述的半導體結構,其中,該第一金屬半導體合金及該第二金屬半導體合金區域各具有多刻面的表面。
- 如申請專利範圍第1項所述的半導體結構,其中,該閘極結構包括圍繞至少一個掩埋奈米線段的通道部分的閘極疊層,以及位於該閘極疊層的側壁上的閘極間隔物。
- 如申請專利範圍第1項所述的半導體結構,其中,該至少一個掩埋奈米線段的該第一端與該閘極結構的第一側壁垂直地對齊,並且該至少一個掩埋奈米線段的第二端與相對於該第一側壁的該閘極結構的第二側壁垂直地對齊。
- 一種形成半導體結構的方法,包括:形成至少一個掩埋奈米線段於基板上並由閘極結構所圍繞,該至少一個掩埋奈米線段具有第一端以及與 該第一端相對的第二端;形成從該至少一個掩埋奈米線段的該第一端延伸的磊晶源極區,該磊晶源極區包括第一半導體材料及第一導電類型的摻雜劑;以及形成從該至少一個掩埋奈米線段的該第二端延伸的磊晶汲極區,該磊晶汲極區包括與該第一半導體材料不同的第二半導體材料以及與該第一導電類型相反的第二導電類型的摻雜物。
- 如申請專利範圍第11項所述的方法,其中,該至少一個掩埋奈米線段包括該第二半導體材料並且是本徵。
- 如申請專利範圍第11項所述的方法,其中,該形成該至少一個掩埋奈米線段包括:形成至少一個奈米線,該至少一個奈米線通過第一襯墊部及第二襯墊部懸浮在該基板上;形成該閘極結構,該閘極結構圍繞該至少一個奈米線的部分;以及移除該第一襯墊部、該第二襯墊部及未被該閘極結構覆蓋的該至少一個奈米線的部分。
- 如申請專利範圍第13項所述的方法,其中,該基板包括支持基板以及出現在該支持基板上方的掩埋絕緣層,其中,該至少一個奈米線位於該掩埋絕緣層的凹陷區域上方。
- 如申請專利範圍第14項所述的方法,其中,形成該閘極結構包括: 形成閘極介電層,該閘極介電層在該至少一個奈米線、該第一襯墊部、該第二襯墊部及該掩埋絕緣層的該凹陷區域的表面上方;形成在該閘極介電層上方的閘極電極層,該閘極電極層填充在該至少一個奈米線及該掩埋絕緣層的該凹陷區域之間的空間;圖案化該閘極介電層及該閘極電極層,以提供閘極疊層,該閘極疊層圍繞位於該掩埋絕緣層的該凹陷區域上方的該至少一個奈米線的部分;以及形成在該閘極疊層的側壁上的閘極間隔物。
- 如申請專利範圍第11項所述的方法,其中,該至少一個掩埋奈米線段的該第一端與該閘極結構的第一側壁垂直地對齊,並且該至少一個掩埋奈米線段的第二端與相對於該第一側壁的該閘極結構的第二側壁垂直地對齊。
- 如申請專利範圍第11項所述的方法,其中,該形成該磊晶源極區包含:在該基板及該閘極結構上方形成圖案化第一遮罩層,以覆蓋該掩埋奈米線段的該第二端及該閘極結構;從未被該圖案化第一遮罩層覆蓋的該掩埋奈米線段的該第一端的表面磊晶成長摻雜的第一半導體材料;以及移除該圖案化第一遮罩層。
- 如申請專利範圍第17項所述的方法,其中,該形成該 磊晶汲極區包括:在該基板、該閘極結構及該磊晶汲極區上方形成圖案化第二遮罩層;從未被該圖案化第二遮罩層覆蓋的該掩埋奈米線段的該第二端的表面磊晶成長摻雜的第二半導體材料;以及移除該圖案化第二遮罩層。
- 如申請專利範圍第11項所述的方法,還包括,在該磊晶源極區頂上形成第一金屬半導體合金區域,以及在該磊晶汲極區頂上形成第二金屬半導體合金區域。
- 如申請專利範圍第19項所述的方法,還包括:形成接觸該第一金屬半導體合金區域的頂面的第一接觸結構以及接觸該第二金屬半導體合金區域的頂面的第二接觸結構。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US14/887,572 | 2015-10-20 | ||
US14/887,572 US9660027B2 (en) | 2015-10-20 | 2015-10-20 | Expitaxially regrown heterostructure nanowire lateral tunnel field effect transistor |
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US11723218B2 (en) * | 2020-06-29 | 2023-08-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device and method for forming the same |
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CN116072542A (zh) * | 2022-11-30 | 2023-05-05 | 中国科学院微电子研究所 | 环珊tfet器件的制备方法 |
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