TW201717393A - 具有可變覆層／核心尺寸作應力及帶隙調節的電晶體結構 - Google Patents

具有可變覆層／核心尺寸作應力及帶隙調節的電晶體結構 Download PDF

Info

Publication number
TW201717393A
TW201717393A TW105132410A TW105132410A TW201717393A TW 201717393 A TW201717393 A TW 201717393A TW 105132410 A TW105132410 A TW 105132410A TW 105132410 A TW105132410 A TW 105132410A TW 201717393 A TW201717393 A TW 201717393A
Authority
TW
Taiwan
Prior art keywords
region
band gap
cladding
core material
channel region
Prior art date
Application number
TW105132410A
Other languages
English (en)
Other versions
TWI628794B (zh
Inventor
威利 瑞奇曼第
凡 雷
拉維 皮拉瑞斯提
馬可 拉多撒福傑維克
吉伯特 狄威
尼洛依 穆可吉
傑克 卡瓦萊羅斯
羅伯特 喬
班傑明 朱功
羅沙 寇利爾
Original Assignee
英特爾股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 英特爾股份有限公司 filed Critical 英特爾股份有限公司
Publication of TW201717393A publication Critical patent/TW201717393A/zh
Application granted granted Critical
Publication of TWI628794B publication Critical patent/TWI628794B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
    • H01L29/0669—Nanowires or nanotubes
    • H01L29/0673—Nanowires or nanotubes oriented parallel to a substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
    • H01L29/0669—Nanowires or nanotubes
    • H01L29/068—Nanowires or nanotubes comprising a junction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1054—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a variation of the composition, e.g. channel with strained layer for increasing the mobility
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/161—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys
    • H01L29/165—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys in different semiconductor regions, e.g. heterojunctions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
    • H01L29/42392—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor fully surrounding the channel, e.g. gate-all-around
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
    • H01L29/512—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures the variation being parallel to the channel plane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66439—Unipolar field-effect transistors with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/775—Field effect transistors with one dimensional charge carrier gas channel, e.g. quantum wire FET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Nanotechnology (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Manufacturing & Machinery (AREA)
  • Materials Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Thin Film Transistor (AREA)

Abstract

一種設備，包含配置在基板上的異質結構且界定一通道區，該異質結構包括第一材料與第二材料，其中，第一材料具有小於基板材料之帶隙的第一帶隙，而第二材料具有大於第一帶隙之第二帶隙；以及通道區上的閘極堆疊，其中，第二材料係配置於第一材料與閘極堆疊之間。一種方法包括在基板上形成具有第一帶隙之第一材料；在第一材料上形成具有大於第一帶隙之第二帶隙之第二材料；以及，在第二材料上形成閘極堆疊。

Description

具有可變覆層/核心尺寸作應力及帶隙調節的電晶體結構
半導體裝置包括非平面式半導體裝置，其具有包括低帶隙包覆層的通道區。
過去數十年來，縮小積體電路中的特徵尺寸是半導體工業不斷成長之背後的動力。不斷縮小特徵尺寸使能夠在半導體晶片之有限的基板面上增加功能單元之密度。例如，縮小電晶體的尺寸，得以在晶片上結合更多記憶體裝置，並導致提高產能。不過，不斷推升容量並非沒有問題。使每一個裝置之性能最佳化的必要性變得愈來愈重要。
以III-V族複合半導體材料系統所形成的半導體裝置，由於低的有效質量連同雜質射散降低，因此提供電晶體通道中極高的載子移動率。III族與V族意指位於元素週期表之13-15族中的半導體材料元素(先前的III-V 族)。此等裝置提供高驅動電流的性能，且在未來的低功率、高速邏輯應用中顯然大有可為。為在矽基板上集積此等材料，典型上，要在矽與III-V族複合通道材料之間引入帶隙較寬之材料的緩衝層，以將載子限制在通道材料，並實現緩衝層中的短通道效應。
100‧‧‧結構
102‧‧‧基板
103‧‧‧絕緣層
104‧‧‧奈米帶
105‧‧‧核心材料
106‧‧‧包覆材料
108‧‧‧通道
114‧‧‧源極區
116‧‧‧汲極區
118‧‧‧閘極堆疊
120‧‧‧閘極介電質
124‧‧‧閘極電極
140‧‧‧間隔物
200‧‧‧結構
202‧‧‧基板
203‧‧‧絕緣或介電層
204‧‧‧奈米帶
205‧‧‧假閘極
206‧‧‧間隔物
207‧‧‧間隔物
208‧‧‧介電層
209‧‧‧氧化物層
210‧‧‧包覆材料
214‧‧‧源極區
216‧‧‧汲極區
217‧‧‧閘極堆疊
218‧‧‧高k介電材料
219‧‧‧金屬閘極材料
234‧‧‧接點金屬
235‧‧‧接點金屬
300‧‧‧計算裝置
302‧‧‧主機板
304‧‧‧處理器
306‧‧‧通訊晶片
圖1顯示三維電晶體結構之實施例的頂視透視圖。
圖2顯示圖1之結構通過線2-2’的橫斷面側視圖。
圖3顯示圖1之結構通過線3-3’的橫斷面視圖。
圖4係絕緣體上部分半導體結構(奈米帶)的橫斷面視圖，包括假閘極與包圍閘極的間隔物層。
圖5顯示接續於圖4在去除了假閘極後的結構。
圖6顯示接續於圖5在去除了包圍假閘極之其中一層間隔物後的結構。
圖7顯示接續於圖6在奈米帶之通道區減薄後的結構。
圖8顯示接續於圖7在通道區中之奈米帶上引進包覆材料後的結構。
圖9顯示接續於圖8在通道區上引入閘極堆疊後的結構。
圖10顯示接續於圖9在使指定之接面區(源極/汲極區)中之奈米帶從下方絕緣或介電層脫離後的結構。
圖11顯示接續於圖10在將包覆材料引入接面區中之 奈米帶並形成源極區與汲極區後的結構。
圖12顯示接續於圖11在引入到達源極區與汲極區之接點後的結構。
圖13說明按照一實施的計算裝置。
【發明內容及實施方式】
說明書中描述以可變覆層與核心尺寸來作應力及帶隙調節的半導體裝置。在一實施例中，係以通道中之第一覆層/核心尺寸與接面區(例如，源極與汲極區)中之第二不同的覆層/核心尺寸來描述電晶體裝置。藉由改變覆層/核心尺寸以提供獲致通道內之高移動率與接面區內之低接觸電阻的路徑。改變覆層/核心尺寸的方法之一係藉由改變包覆材料相對於核心材料的比率(例如，改變體積比)。改變包覆材料與核心材料之比例可調節該等材料之間的應力轉移。在一實施例中，改變核心材料橫斷面寬度，按此方式，作為電晶體導電層之包覆材料在接面區中(源極與汲極區)增加的應力，高於在通道中增加的應力。覆層中的高應力將導致帶隙變窄，且因此降低了接面區與相關之接觸金屬之間的接觸勢壘。
本文所描述的技術使能夠在矽上直接集積高移動率的半導體材料，諸如鍺(Ge)與III-V族複合半導體材料，並利用由於應力使帶隙變窄而降低裝置外部電阻的優點。
半導體裝置包括結合了閘極、通道區與接面區(源極與汲極區)的裝置。在實施例中，半導體裝置諸如但不限 於金屬氧化物半導體場效電晶體(MOSFET)或微電機系統(MEMS)裝置。在一實施例中，半導體裝置係三維MOSFET，且是孤立之裝置或一些巢狀裝置中的一個裝置。如對積體電路之理解，可以在單一基板上製造N或P通道電晶體以形成互補金屬氧化物半導體(CMOS)積體電路。此外，為了將此裝置整合到積體電路內，還要製造額外的互連。
圖1顯示三維電晶體結構之實施例的頂視透視圖。在圖1中，電晶體結構在奈米帶核心上結合了覆層。須理解，本文所描述的技術與改進不僅可應用於奈米帶或奈米結構核心裝置，也可用於其它裝置，包括但不限於三閘極電晶體裝置。
請參閱圖1，結構100包括基板102。基板102可由適合製造半導體裝置的材料構成。在一實施例中，基板102係由單晶材料所構成的大塊基板，其包括但不限於矽、鍺、矽-鍺、或III-V族複合半導體材料。在圖1所示的實施例中，基板102上配置絕緣層103。絕緣層103的材料例如可包括但不限於二氧化矽、氮化矽、或氮氧化矽。奈米帶104配置在絕緣層103上。奈米帶104係包括核心材料105與包覆材料106的異質結構。在一實施例中，核心材料105係單晶半導體材料，諸如矽，而包覆材料106係帶隙小於核心材料105的半導體材料。用於包覆材料106之材料的代表例包括鍺或III-V族複合半導體材料。奈米帶104定義具有通道108及形成在通道108相對 側之源極與汲極區114/116的三維體。覆於通道108的閘極堆疊118包括閘極電極124與閘極介電質120。間隔物140圖示於閘極堆疊118的相對側。
在一實施例中，閘極堆疊118完全包圍通道區108。在此實施例中，包覆材料106可完全包圍核心材料105。在另一實施例中，閘極堆疊118僅部分包圍通道區108，且包覆材料106也僅只部分包圍核心材料105。
在一實施例中，閘極堆疊118的閘極電極124係由金屬閘極所構成，及閘極介電質120係由介電常數大於二氧化矽介電常數之材料(高k材料)所構成。用於閘極介電質120的代表性材料包括但不限於氧化鉿、氧氮化鉿、矽化鉿、氧化鑭、氧化鋯、矽化鋯、氧化鉭、鈦酸鍶鋇、鈦酸鋇、鈦酸鍶、氧化釔、氧化鋁、氧化鉛鈧鉭、鈮酸鉛鋅、或它們的組合物。用於閘極電極124的代表性材料包括但不限於金屬氮化物、金屬碳化物、金屬矽化物、金屬鋁化物、鉿、鋯、鈦、鉭、鋁、釕、鈀、鉑、鈷、鎳、及導電金屬氧化物。
圖2顯示結構100之通過線2-2’的橫斷面側視圖。明確地說，圖2顯示奈米帶104。在此視圖中，省略了閘極堆疊118與間隔物140。圖3顯示圖1結構之通過線3-3’的橫斷面視圖。圖3說明省略了閘極堆疊118與間隔物140之奈米帶104的頂視圖。如圖2及圖3之說明，通道108之體積小於源極與汲極區114/116之體積。通道體積縮小是改進覆層與核心間之應力轉移所需。通道體積縮小 也有利於裝置的靜電控制。在一實施例中，通道之大小(例如，體積)及源極與汲極區之大小，可按需要應力轉移之每一區域的要求各自獨立地設定。
在一實施例中，奈米帶104中之包覆材料106與核心材料105間之應力的量，在源極與汲極區114/116及通道區108之間有所不同。在一實施例中，希望通道區中的移動率高。傳遞通道區108中包覆材料106中之應力或應變將可增加移動率。在實施例中，核心材料105為矽，而包覆材料106為鍺，傳遞通道區108中包覆材料106中之應力的一方法係透過包覆材料與核心材料之間的交互作用。圖2中顯示通道區108所具有之包覆材料106的體積或量，大於核心材料105的量。包覆材料(例如，鍺)的量較大將致使核心材料(例如，矽)與包覆材料的晶格結構順應。換言之，對於矽的核心材料而言，矽原子將與鍺原子的晶格對齊。在一實施例中，通道區108中之包覆材料的體積或量等於核心材料之體積或量的兩倍。此體積或量將會產生一些應力轉移到包覆材料106，其足以增加載子的移動率(例如，電洞移動率)。
如圖2中所示，在一實施例中，相對於通道區108，源極與汲極區114/116中的核心材料多於包覆材料。在一實施例中，源極與汲極區114/116中的核心材料105是此等區域中包覆材料106之體積或量的兩倍。核心材料相對於包覆材料的增加將有拉緊包覆材料之傾向而降低它的帶隙。
圖4-12描述用以於形成圖1所說明之結構的實施例。參閱圖4，圖4係部分結構的橫斷面視圖。例如，結構200包括例如單晶材料的大塊基板(諸如矽)的基板202。例如二氧化矽的絕緣或介電材料203覆蓋基板202。絕緣或介電材料203上配置例如單晶半導體材料(諸如矽)的奈米帶204。奈米帶204可形成自全覆蓋磊晶層。具代表性的方法是先將奈米帶的區域遮蔽，再去除不需要的材料以留下奈米帶。在奈米帶204上配置例如複晶矽的假閘極205，並在假閘極205四周配置第一間隔物206與第二間隔物207。間隔物206與207之材料係選擇其一相對於另一可被選擇蝕刻的材料。例如，包括二氧化矽(SiO2)、氮化矽(Si3N4)、及氮碳化矽(SiCN)。與假閘極205與間隔物206及207鄰接的是例如二氧化矽的介電層208。在一實施例中，間隔物206與207之材料選擇自相對於介電層208之材料可被選擇蝕刻的材料。在圖4所示的實施例中，假閘極205係配置在氧化物層209上。
圖5顯示接續於圖4在去除了假閘極205與下方之氧化物層209後的結構。例如，藉由諸如四甲基氫氧化銨(tetramethylammonium hydroxide；TMAH)來蝕刻以去除複晶矽的假閘極205，如有需要，接著可藉由氫氟酸(HF)去除氧化物層209。在去除了假閘極205與氧化物層209之後，即露出對應於部分通道區的部分奈米帶204。位於通道區之露出部分下方的絕緣或介電材料 203，可藉由相對於奈米帶204選擇性蝕刻絕緣或介電材料203將其除去。在一實施例中，二氧化矽的絕緣或介電材料203可使用HF蝕刻劑來選擇性地蝕刻。
圖6顯示接續於圖5在去除了間隔物206後的結構。例如，二氧化矽材料的間隔物206可使用HF蝕刻劑選擇性地去除。
圖7顯示接續於圖6在奈米帶204之通道區減薄後的結構。在一實施例中，藉由奈米帶之半導體材料的犧牲氧化，通道可相對於奈米帶之其餘部分被減薄。
圖8顯示接續於圖7在通道區中之奈米帶204上引進包覆材料後的結構。在一實施例中，例如，奈米帶204之材料為矽，包覆材料210是鍺或III-V族複合半導體材料。
圖9顯示接續於圖8在通道區上引進閘極堆疊後的結構。在一實施例中，閘極堆疊217包括在通道區材料配置高k介電材料218及在介電材料上配置金屬閘極材料219。如圖9所示，開孔或使奈米帶從絕緣或介電層203脫離以使閘極堆疊217可以完全包圍通道區。
圖10顯示接續於圖9在使指定之接面區(源極/汲極區)中之奈米帶204從下方絕緣或介電層203脫離後的結構。達成此之方法係藉由蝕刻介電層208以露出接面區中之奈米帶204，並接著相對於奈米帶材料選擇蝕刻絕緣或介電層203。
圖11顯示接續於圖10在將包覆材料引進接面區中之 奈米帶並形成源極區214與汲極區216後的結構。
圖12顯示接續於圖11在分別引進到達源極區214與汲極區216之接點後的結構。例如，圖12顯示鈦及鎢的接點金屬234包圍源極區214，以及接點金屬235包圍汲極區216。
圖13說明按照一實施的計算裝置300。計算裝置300裝有主機板302。主機板302可包括若干組件，包括但不限於處理器304及至少一個通訊晶片306。處理器304可實體及電性地耦接至主機板302。在某些實施中，至少一個通訊晶片306也實體及電性地耦接至主機板302。在另些實施中，通訊晶片306是處理器304的一部分。
視其應用而定，計算裝置300可包括其它組件，這些組件可以與也可以不與主機板302實體及電性地耦接。這些其它的組件包括但不限於揮發性記憶體(例如，DRAM)、非揮發性記憶體(例如，ROM)、快閃記憶體、圖形處理器、數位信號處理器、密碼處理器、晶片組、天線、顯示器、觸控螢幕顯示器、觸控螢幕控制器、電池、音頻編解碼器、視訊編解碼器、功率放大器、全球定位裝置(GPS)裝置、羅盤、加速儀、陀螺儀、喇叭、照相機、及大量儲存裝置(諸如硬式磁碟機、光碟(CD)、數位光碟(DVD)、等)。
通訊晶片306使往來於計算裝置300的資料傳輸能夠無線通訊。名詞“無線”及其衍生可用來描述電路、裝置、系統、方法、技術、通訊頻道等，其可透過使用經調變的 電磁輻射經由非固態媒體傳遞資料。該名詞並非暗示相關的裝置不包含任何導線，雖然在某些實施例中的確不包含。通訊晶片306可實施任何種類的無線標準或協定，包括但不限於Wi-Fi(IEEE 802.11系列)，WiMAX(IEEE 802.16系列)、IEEE 802.20，長程演進(LTE)、Ev-DO、HSPA+、HSDPA+、HSUPA+、EDGE、GSM、GPRS、CDMA、TDMA、DECT、藍牙、及它們的衍生物，以及命名為3G、4G、5G、或以上之任何其它的無線協定。計算裝置300可包括複數個通訊晶片306。例如，第一通訊晶片306可專用於較短程的無線通訊，諸如Wi-Fi及藍牙，及第二通訊晶片306可專用於較長程的無線通訊，諸如GPS、EDGE、GPRS、CDMA、WiMAX、LTE、Ev-DO及其它。
計算裝置300的處理器304包括封裝在處理器304內的積體電路晶粒。在本發明的某些實施中，處理器的積體電路晶粒包括一或多個裝置，諸如按照本發明之實施所建構的MOSFET電晶體。名詞“處理器”可指任何用來處理來自暫存器及/或記憶體之電子資料，並將該電子資料轉換成可儲存在暫存器及/或記憶體中之其它電子資料的裝置或部分裝置。
通訊晶片306也可包括封裝在通訊晶片306內的積體電路晶粒。按照本發明的另一實施，通訊晶片的積體電路晶粒包括一或多個裝置，諸如按照本發明之實施所建構的MOSFET電晶體。
在另些實施中，裝在計算裝置300內的其它組件可包含積體電路晶粒，其包括一或多個裝置，諸如按照本發明之實施所建構的MOSFET電晶體。
在各種不同的實施中，計算裝置300可以是膝上型電腦、連網小筆電、筆記型電腦、超輕薄筆電、智慧型手機、平板電腦、個人數位助理(PDA)、超行動個人電腦、行動電話、桌上型電腦、伺服器、印表機、掃瞄器、監視器、機上盒、娛樂控制單元、數位式照相機、可攜式音樂播放機、或數位式錄影機。在另些實施中，計算裝置300可以是處理資料的任何其它電子裝置。
實例
例1係一裝置，包括配置在基板上的異質結構並界定一通道區，該異質結構包括第一材料與第二材料，其中，第一材料具有小於基板材料之帶隙的第一帶隙，及第二材料具有大於第一帶隙之第二帶隙；以及通道區上的閘極堆疊，閘極堆疊包括介電材料與位於介電材料上的閘極電極，其中，第二材料係配置在第一材料與閘極堆疊之間。
在例2中，例1之設備中的第一材料包括二元III-V族半導體材料。
在例3中，例1之設備中的第一材料包括鉮化銦(InAs)。
在例4中，例1之設備中的第二材料係三元III-V族半導體材料。
在例5中，例1之設備中的第一材料與第二材料之間的過渡係緩變的。
在例6中，例1之設備中的第一材料與第二材料之間的過渡係步進的。
在例7中，例1之設備中的基板包括半導體材料及半導體材料上的絕緣層。
例8係製造半導體設備之方法，包括在基板上形成具有第一帶隙的第一材料，第一帶隙小於基板材料之帶隙；在第一二元III-V族材料上形成具有大於該第一帶隙之第二帶隙的第二III-V族材料；以及，在第二III-V族材料上形成閘極堆疊。
在例9中，例8之方法中的第一III-V族材料包括二元III-V族材料。
在例10中，例8之方法中的第一III-V族材料係鉮化銦(InAs)。
在例11中，例8之方法中的第二III-V族材料係三元III-V族材料。
在例12中，例8之方法中的第一III-V族材料與第二III-V族材料之間的過渡係緩變的。
在例13中，例8之方法中的第一二元III-V族材料與第二III-V族材料之間的過渡係步進的。
在例14中，半導體設備係藉由例8-13之任一項方法所形成。
例15係半導體設備，包括位於基板上的電晶體，該 電晶體包含位於部分基板上的通道區；第一材料，具有小於基板之半導體材料之帶隙的第一帶隙，及第二材料具有大於第一帶隙的第二帶隙；以及，位於通道區上的閘極堆疊，閘極堆疊包含介電材料與位於介電材料上的閘極電極，其中，基板與通道區相關之部分具有順應於該第一材料之晶格結構的特性。
在例16中，例15之設備中的第一材料包括二元III-V族半導體材料。
在例17中，例15之設備中的第一材料包括鉮化銦。
在例18中，例15之設備中的第二材料包括三元III-V族半導體材料。
在例19中，例15之設備中的第一材料與第二材料之間的過渡係緩變的。
在例20中，例15之設備中的第一材料與第二材料之間的過渡係步進的。
在以上的描述中，基於解釋之目的，為了提供對實施例徹底之瞭解而陳述了諸多特定的細節。不過，熟悉此方面技術之人士應明瞭，沒有某些此等特定細節，仍可實行一或多個其它的實施例。所描述的特定實施例並非對本發明之限制而是對其之說明。本發明之範圍並非由以上所提供的特定實例決定，而是由以下的申請專利範圍決定。在其它的實例中，為了避免模糊了對本描述之瞭解，習知的結構、裝置、及操作係以方塊圖的形式顯示或不詳細說明。資料參考數字或參考數字之尾端部分重複於各圖之間 用以指示對應或類似之單元被認為恰當，這些單元可以是具有類似特性的選用單元。
尚需理解，在本說明書中從頭到尾所參考之例如“一實施例”、“實施例”、“一或多個實施例”、或“不同實施例”，意指包括了實行本發明的特定特徵。同樣地，須理解，在描述中，基於有系統地揭示及有助於瞭解各不同發明態樣之目的，有時在單一個實施例、圖、或對其的描述中群集了各種不同的特徵。不過，不能將所揭示的本方法解釋成反映本發明需要比每一申請項所明確陳述之更多特徵的意圖。反之，如以下申請專利範圍所反映，各發明態樣係少於所揭示之單一實施例的所有特徵。因此，特此明確地將接續於實施方式之後的申請專利範圍併入此實施方式，且每一申請專利範圍其本身即為本發明的獨立實施例。
100‧‧‧結構
102‧‧‧基板
103‧‧‧絕緣層
104‧‧‧奈米帶
105‧‧‧核心材料
106‧‧‧包覆材料
108‧‧‧通道
114‧‧‧源極區
116‧‧‧汲極區
118‧‧‧閘極堆疊
120‧‧‧閘極介電質
124‧‧‧閘極電極
140‧‧‧間隔物

Claims (15)

  1. 一種用以調節應力及帶隙之設備，包含：位於基板上的通道區與源極區及汲極區，該源極區位於該通道區的一側上及該汲極區位於該通道區的相反側，各個該通道區與該源極區及該汲極區皆包含具有第一帶隙的核心材料以及在該核心材料上的包覆材料，該包覆材料具有與該第一帶隙不同之第二帶隙，其中該通道區的該核心材料的體積係小於在該源極區或該汲極區的任一的該核心材料的體積；及配置在該通道區上的閘極堆疊，該閘極堆疊包含閘極介電質與閘極電極。
  2. 如申請專利範圍第1項之設備，其中，該通道區中之包覆材料的量相對於核心材料的量大於該源極區與該汲極區中之包覆材料的量相對於核心材料的量。
  3. 如申請專利範圍第1項之設備，其中，該包覆材料完全包圍在該通道區中之該核心材料。
  4. 如申請專利範圍第1項之設備，其中，該包覆材料包圍在該通道區中的該核心材料的部分。
  5. 如申請專利範圍第1項之設備，其中，該包覆材料包含鍺及該核心材料包含矽。
  6. 如申請專利範圍第1項之設備，其中，該包覆材料包含III-V族化合物半導體材料。
  7. 如申請專利範圍第1項之設備，其中，該源極區與該汲極區之該包覆材料與該核心材料之間的應力，與該通 道區之該包覆材料與該核心材料之間的應力不同。
  8. 如申請專利範圍第7項之設備，其中，該源極區與該汲極區之該包覆材料中的該應力大於該通道區之該包覆材料中的應力。
  9. 如申請專利範圍第1項之設備，其中，在各個該源極區與該汲極區之中的該核心材料的體積係兩倍於在該源極區與該汲極區中的該包覆材料的體積。
  10. 一種用以調節應力及帶隙之設備，包含：位於基板上的包含有通道區與源極區及汲極區的奈米帶，該源極區位於該通道區的一側上及該汲極區位於該通道區的相反側上，各個該通道區與該源極區及該汲極區皆包含具有第一帶隙的核心材料及在該核心材料上的包覆材料，該包覆材料具有與該第一帶隙不同之第二帶隙，其中，在各個該源極區與該汲極區中的該核心材料的體積相對於該包覆材料的體積係大於在該通道區中的該核心材料的體積相對於該包覆材料的體積，配置在該通道區上的閘極堆疊，該閘極堆疊包含閘極介電質與閘極電極。
  11. 如申請專利範圍第10項之設備，其中，該包覆材料完全包圍在該通道區中之該核心材料。
  12. 如申請專利範圍第10項之設備，其中，該包覆材料包圍在該通道區中的該核心材料的部分。
  13. 如申請專利範圍第10項之設備，其中，該包覆材料包含鍺及該核心材料包含矽。
  14. 如申請專利範圍第10項之設備，其中，該包覆材料包含III-V族化合物半導體材料。
  15. 如申請專利範圍第10項之設備，其中在各個該源極區與該汲極區中的該核心材料的體積係兩倍於該源極區與該汲極區中的該包覆材料的體積。
TW105132410A 2013-09-27 2014-09-19 具有可變覆層／核心尺寸作應力及帶隙調節的電晶體結構 TWI628794B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
??PCT/US13/62468 2013-09-27
PCT/US2013/062468 WO2015047349A1 (en) 2013-09-27 2013-09-27 Transistor structure with variable clad/core dimension for stress and band gap modulation

Publications (2)

Publication Number Publication Date
TW201717393A true TW201717393A (zh) 2017-05-16
TWI628794B TWI628794B (zh) 2018-07-01

Family

ID=52744242

Family Applications (2)

Application Number Title Priority Date Filing Date
TW103132437A TWI565056B (zh) 2013-09-27 2014-09-19 具有可變覆層／核心尺寸作應力及帶隙調節的電晶體結構
TW105132410A TWI628794B (zh) 2013-09-27 2014-09-19 具有可變覆層／核心尺寸作應力及帶隙調節的電晶體結構

Family Applications Before (1)

Application Number Title Priority Date Filing Date
TW103132437A TWI565056B (zh) 2013-09-27 2014-09-19 具有可變覆層／核心尺寸作應力及帶隙調節的電晶體結構

Country Status (6)

Country Link
US (1) US9818870B2 (zh)
EP (1) EP3050113A4 (zh)
KR (1) KR102106472B1 (zh)
CN (1) CN105684154B (zh)
TW (2) TWI565056B (zh)
WO (1) WO2015047349A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI811363B (zh) * 2018-06-29 2023-08-11 美商英特爾股份有限公司 使用犧牲源極／汲極層增加的電晶體源極／汲極接觸面積

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112768508B (zh) * 2021-01-21 2023-03-28 西安电子科技大学 背栅全控型AlGaN/GaN异质结增强型功率HEMT器件及制备方法

Family Cites Families (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5081511A (en) * 1990-09-06 1992-01-14 Motorola, Inc. Heterojunction field effect transistor with monolayers in channel region
JPH07249780A (ja) * 1994-03-08 1995-09-26 Sanyo Electric Co Ltd 電界効果型半導体素子
US5479033A (en) * 1994-05-27 1995-12-26 Sandia Corporation Complementary junction heterostructure field-effect transistor
US7452778B2 (en) * 2004-06-10 2008-11-18 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor nano-wire devices and methods of fabrication
US20060267007A1 (en) * 2004-12-31 2006-11-30 Yale University Devices incorporating heavily defected semiconductor layers
WO2006132659A2 (en) * 2005-06-06 2006-12-14 President And Fellows Of Harvard College Nanowire heterostructures
US8183556B2 (en) * 2005-12-15 2012-05-22 Intel Corporation Extreme high mobility CMOS logic
US7728387B1 (en) * 2006-06-13 2010-06-01 The Board Of Trustees Of The Leland Stanford Junior University Semiconductor device with high on current and low leakage
US20080001173A1 (en) 2006-06-23 2008-01-03 International Business Machines Corporation BURIED CHANNEL MOSFET USING III-V COMPOUND SEMICONDUCTORS AND HIGH k GATE DIELECTRICS
CN101449366A (zh) * 2006-06-23 2009-06-03 国际商业机器公司 使用ⅲ-ⅴ族化合物半导体及高介电常数栅极电介质的掩埋沟道金属氧化物半导体场效应晶体管
US7948050B2 (en) * 2007-01-11 2011-05-24 International Business Machines Corporation Core-shell nanowire transistor
US7928426B2 (en) * 2007-03-27 2011-04-19 Intel Corporation Forming a non-planar transistor having a quantum well channel
KR101375833B1 (ko) * 2007-05-03 2014-03-18 삼성전자주식회사 게르마늄 나노로드를 구비한 전계효과 트랜지스터 및 그제조방법
US7632745B2 (en) * 2007-06-30 2009-12-15 Intel Corporation Hybrid high-k gate dielectric film
US8110465B2 (en) * 2007-07-30 2012-02-07 International Business Machines Corporation Field effect transistor having an asymmetric gate electrode
US8278687B2 (en) 2008-03-28 2012-10-02 Intel Corporation Semiconductor heterostructures to reduce short channel effects
US7902541B2 (en) * 2009-04-03 2011-03-08 International Business Machines Corporation Semiconductor nanowire with built-in stress
US8237150B2 (en) * 2009-04-03 2012-08-07 International Business Machines Corporation Nanowire devices for enhancing mobility through stress engineering
US8455860B2 (en) * 2009-04-30 2013-06-04 Taiwan Semiconductor Manufacturing Company, Ltd. Reducing source/drain resistance of III-V based transistors
US8178946B1 (en) * 2009-11-20 2012-05-15 Hrl Laboratories, Llc Modulation doped super-lattice base for heterojunction bipolar transistors
US8415671B2 (en) * 2010-04-16 2013-04-09 Cree, Inc. Wide band-gap MOSFETs having a heterojunction under gate trenches thereof and related methods of forming such devices
CA2819469C (en) * 2010-11-17 2019-09-10 International Business Machines Corporation Strained nanowire devices
TW201236154A (en) * 2010-12-22 2012-09-01 Ibm Semiconductor device
US8890207B2 (en) * 2011-09-06 2014-11-18 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET design controlling channel thickness
CN102683202B (zh) * 2012-05-03 2014-12-10 上海华力微电子有限公司 一种制作内建应力硅纳米线、以及制作半导体的方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI811363B (zh) * 2018-06-29 2023-08-11 美商英特爾股份有限公司 使用犧牲源極／汲極層增加的電晶體源極／汲極接觸面積

Also Published As

Publication number Publication date
EP3050113A1 (en) 2016-08-03
TWI565056B (zh) 2017-01-01
KR102106472B1 (ko) 2020-05-04
US9818870B2 (en) 2017-11-14
TW201523876A (zh) 2015-06-16
US20160240671A1 (en) 2016-08-18
CN105684154A (zh) 2016-06-15
TWI628794B (zh) 2018-07-01
CN105684154B (zh) 2019-08-20
WO2015047349A1 (en) 2015-04-02
KR20160064076A (ko) 2016-06-07
EP3050113A4 (en) 2017-05-24

Similar Documents

Publication Publication Date Title
US11139400B2 (en) Non-planar semiconductor device having hybrid geometry-based active region
US10847631B2 (en) Gate-all-around (GAA) transistors with nanowires on an isolation pedestal
US9935205B2 (en) Internal spacers for nanowire transistors and method of fabrication thereof
US9385221B2 (en) Nanowire transistor with underlayer etch stops
US10424580B2 (en) Semiconductor devices having modulated nanowire counts
KR102012114B1 (ko) 릴리스 에칭-패시베이션 표면을 갖는 게르마늄 기반 활성 영역을 구비하는 비평면 반도체 디바이스
TWI512802B (zh) 具有含低帶隙包覆層之通道區的非平面半導體裝置
TWI567990B (zh) 半導體裝置以及製造半導體裝置之方法
EP2901490B1 (en) Semiconductor device having germanium active layer with underlying parasitic leakage barrier layer
TWI565056B (zh) 具有可變覆層／核心尺寸作應力及帶隙調節的電晶體結構
EP3050114A1 (en) Methods to achieve high mobility in cladded iii-v channel materials