TW201717335A - 晶片封裝體及其形成方法 - Google Patents

晶片封裝體及其形成方法 Download PDF

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TW201717335A
TW201717335A TW105124739A TW105124739A TW201717335A TW 201717335 A TW201717335 A TW 201717335A TW 105124739 A TW105124739 A TW 105124739A TW 105124739 A TW105124739 A TW 105124739A TW 201717335 A TW201717335 A TW 201717335A
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layer
dielectric layer
semiconductor
chip package
conductive
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TW105124739A
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TWI634625B (zh
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余振華
邱文智
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台灣積體電路製造股份有限公司
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Abstract

提供了晶片封裝體之結構與形成方法。晶片封裝體包括半導體晶粒及至少部份包覆半導體晶粒之封裝層。晶片封裝體還包括位於半導體晶粒及封裝層上之高分子層。晶片封裝體更包括位於高分子層上之介電層。介電層大抵由半導體氧化物材料半導體氮氧化物材料、或半導體氮化物材料所製成。此外，晶片封裝體包括位於介電層中之導電結構，其電性連接至半導體晶粒之導電墊。

Description

晶片封裝體及其形成方法
本揭露書係有關於晶片封裝體及其形成方法，且特別是有關於系統級封裝(system in package，SiP)及其形成方法。
隨著半導體技術的演進，半導體晶粒(semiconductor dies)變得越來越小。然而，也有更多的功能需整合到這些半導體晶粒之中。因此，這些半導體晶粒具有數量越來越多的輸出/輸入墊(I/O pads)需封裝到更小的區域之中，而使得輸出/輸入墊的密度快速地成長。因此，半導體晶粒的封裝正變得更加困難。
封裝技術可區分成數個類型。這些類型之一，係將晶粒在封裝至其他晶圓上之前，先將晶粒自晶圓切下，且僅封裝其中的已知好的晶粒(known-good-dies)。此封裝技術的好處之一是具有形成扇出晶片封裝體(fan-out chip package)的可能性，這代表晶粒上的輸出/輸入墊(I/O pads)可被重新分佈(redistribute)至大於晶粒的範圍。因此，增加了封裝在晶粒表面上之輸出/輸入墊的數量。
已發展了新的封裝技術以進一步增進半導體晶粒的密度與功能。這些相對新穎的半導體晶粒封裝技術面臨著製作上之挑戰。
本揭露書之實施例提供一種晶片封裝體，包括：一半導體晶粒；一封裝層，至少部份包覆該半導體晶粒；一高分子層，位於該半導體晶粒及該封裝層之上；一介電層，位於該高分子層之上，其中該介電層大抵由一半導體氧化物材料、一半導體氮氧化物材料、或一半導體氮化物材料所製成；以及一導電結構，位於該介電層之中，其中該導電結構電性連接至該半導體晶粒之一導電墊。
本揭露書之實施例提供一種晶片封裝體，包括：一半導體晶粒；一模塑化合物層，至少部份包覆該半導體晶粒；一保護層，位於該半導體晶粒及該模塑化合物層之上；一介電層，位於該保護層之上，其中該介電層較該保護層硬；以及一導電結構，位於該介電層之中，其中該導電結構電性連接至該半導體晶粒之一導電墊。
本揭露書之實施例提供一種晶片封裝體的形成方法，包括：於一半導體晶粒之上形成一模塑化合物層以至少部分包覆該半導體晶粒；於該半導體晶粒與該模塑化合物層之上形成一高分子層；於該高分子層之上形成一介電層，其中該介電層係由一半導體氧化物材料、一半導體氧氧化物材料、或一半導體氮化物材料所製成；以及於該介電層之中形成一導電結構。
10、20‧‧‧半導體晶粒
100‧‧‧半導體基底
101‧‧‧承載基底
102‧‧‧介電層
104‧‧‧導電墊
106‧‧‧封裝層
108‧‧‧保護層
110‧‧‧介電層
112、114‧‧‧開口
116、117、118‧‧‧導電結構
119‧‧‧蝕刻停止層
120‧‧‧介電層
122‧‧‧導電結構
123‧‧‧開口
124‧‧‧導電結構
125‧‧‧開口
126‧‧‧保護層
128‧‧‧凸塊下金屬化構件
130‧‧‧導電連接結構
200‧‧‧半導體基底
202‧‧‧介電層
204‧‧‧導電墊
T1、T2‧‧‧厚度
第1A-1J圖顯示根據一些實施例之晶片封裝體的製程剖面 圖。
第2圖顯示根據一些實施例之晶片封裝體的剖面圖。
以下的揭露內容提供許多不同的實施例或範例，以實施本案的不同特徵。而本揭露書以下的揭露內容是敘述各個構件及其排列方式的特定範例，以求簡化說明。當然，這些特定的範例並非用以限定。例如，若是本揭露書以下的內容敘述了將一第一特徵形成於一第二特徵之上或上方，即表示其包含了所形成的上述第一特徵與上述第二特徵是直接接觸的實施例，亦包含了尚可將附加的特徵形成於上述第一特徵與上述第二特徵之間，而使上述第一特徵與上述第二特徵可能未直接接觸的實施例。再者，在以下敘述提及在第二製程前進行第一製程，可包括第二製程於第一製程之後立刻進行之實施例，且亦可包括附加製程於第一製程與第二製程之間進行的實施例。另外，本揭露書中不同範例可能使用重複的參考符號及/或標記。這些重複係為了簡化與清晰的目的，並非用以限定各個實施例及/或所述外觀結構之間的關係。
再者，為了方便描述圖式中一元件或特徵部件與另一(複數)元件或(複數)特徵部件的關係，可使用空間相關用語，例如“在...之下”、“下方”、“較下部”、“上方”、“較上部”及類似的用語等。除了圖式所繪示的方位之外，空間相關用語用以涵蓋使用或操作中的裝置的不同方位。所述裝置也可被另外定位(例如，旋轉90度或者位於其他方位)，並對應地解讀所使用的空間相關用語的描述。
本揭露書之一些實施例敘述如下。第1A-1J圖顯示根據一些實施例之晶片封裝體的製程剖面圖。可於第1A-1J圖所述的步驟之前、期間、及/或之後進行其他附加的處理。所敘述之一些步驟可在不同的實施例中被置換或排除。可於半導體元件結構中增加附加的構件。以下所述之一些構件，可於不同的實施例中被置換或排除。雖然，所敘述之一些實施例係具有特定的處理順序，然而這些處理亦可改以其他符合邏輯的訓續進行。
如第1A圖所示，根據一些實施例，將數個半導體晶粒(包括半導體晶粒10及20)貼合至承載基底101之上。在一些實施例中，使用黏著層(未顯示)以將半導體晶粒10及20固定在承載基底101之上。在一些實施例中，半導體晶粒10及20具有相同的功能。在一些其他實施例中，半導體晶粒10及20具有不同的功能。在一些實施例中，半導體晶粒10及20皆為已知好的晶粒(known-good-dies)。半導體晶粒10及20可由切割同一片半導體晶圓而獲得。或者，半導體晶粒10及20可由切割不同片半導體晶圓而獲得。
在一些實施例中，半導體晶粒10包括半導體基底100及形成在半導體基底100上之內連線結構(interconnection structure)。內連線結構包括多層的層間介電層及形成在多層的層間介電層中之多個導電結構(multiple conductive features)。這些導電結構包括導電線路(conductive lines)、導電插塞(conductive vias)、及導電接觸(conductive contacts)。為了簡化說明，第1A圖僅顯示其中一層間介電層(介電層102)及形成 在介電層102中及/或上之導電墊104。導電墊104可為形成在介電層102中之導電線路的一部分。導電墊104可為導電線路之較寬部分。在一些實施例中，導電墊104形成在其他導電墊上之金屬柱(metal pillars)。相似地，半導體晶粒20亦包括半導體基底200及包含介電層202及導電墊204之內連線結構。
在一些實施例中，各種元件構件(device elements)係形成在半導體基底100及200之中。這些元件構件例如包括電晶體(例如，金屬氧化物半導體場效電晶體(metal oxide semiconductor field effect transistors，MOSFET)、互補型金屬氧化半導體(complementary metal oxide semiconductor，CMOS)電晶體、雙極性接面電晶體(bipolar junction transistors，BJT)、高電壓電晶體、高頻電晶體、P通道及/或N通道場效電晶體(P-channel/N-channel field effect transistors，PFETs/NFETs)等)、二極體、或其他適合的構件。
元件構件透過半導體基底上之內連線結構而彼此相連以形成積體電路元件。積體電路元件包括邏輯元件(logic devices)、記憶體元件(memory devices)(例如，靜態隨機存取記憶體，SRAMs)、射頻(radio frequency，RF)元件、輸入/輸出(I/O)元件、單晶片系統(system-on-chip，SoC)元件、其他可應用形式之元件、或前述之組合。
在一些實施例中，承載基底101係用作暫時性支撐基底。承載基底101可由半導體材料、陶瓷材料、高分子材料、金屬材料、其他適合的材料、或前述之組合而製成。在一些實施例中，承載基底101為玻璃基底。在一些其他實施例中，承 載基底101為半導體基底，例如是矽晶圓。
如第1B圖所示，根據一些實施例，於承載基底101及半導體晶粒10及20之上形成封裝層(package layer)106。在一些實施例中，封裝層106包括高分子材料。在一些實施例中，封裝層106為模塑化合物層(molding compound layer)。模塑化合物層可包括環氧基樹脂(epoxy-based resin)。模塑化合物層可包含填充物(fillers)，例如是氧化物纖維(oxide fibers)。在一些實施例中，封裝層106包覆(encapsulate)半導體晶粒10及20，包括覆蓋其頂表面及側壁。在一些其他實施例中，封裝層106部分包覆半導體晶粒10及20。例如，半導體晶粒10及20之較上部分突出於封裝層106之頂表面。
在一些實施例中，於承載基底101及半導體晶粒10及20之上塗佈液態模塑化合物材料(liquid molding compound material)。在一些實施例中，接著採用熱製程以固化液態模塑化合物材料。因此，液態模塑化合物材料硬化並轉變形成了封裝層106。在一些實施例中，熱製程係在溫度200℃至約230℃下進行。熱製程之處理時間可為約1小時至約3小時。
如第1C圖所示，根據一些實施例，將封裝層106薄化以露出半導體晶粒之導電墊104及204。可使用平坦化製程來薄化封裝層106。平坦化製程可包括化學機械研磨(chemical mechanical polishing，CMP)製程、乾式研磨製程(dry polishing process)、研磨製程(grinding process)、蝕刻製程、其他可應用的製程、或前述之組合。
在一些實施例中，在平坦化製程之後，封裝層106 與半導體晶粒10及20之頂表面係共平面。然而，本揭露書之實施例不限於此。在一些實施例中，封裝層106之頂表面係低於半導體晶粒10及20之頂表面，如第1C圖所示。
如第1D圖所示，根據一些實施例，於半導體晶粒10及20與封裝層106之上形成保護層108。保護層108可用以緩衝產生自後續所形成之內連結構的應力。保護層108亦可用以覆蓋於平坦化製程之後形成於封裝層106上之缺陷。保護層108可提供平坦的表面以利於後續的製程。
在一些實施例中，保護層108為高分子層。在一些實施例中，高分子層可由光敏材料(photo-sensitive material)所形成，其可輕易地被圖案化以形成所需之開口。高分子層可包括聚醯亞胺(polyimide，PI)、聚苯並噁唑(polybenzoxazole，PBO)、環氧樹脂(epoxy resin)、其他適合的材料、或前述之組合。在一些實施例中，保護層108係藉著使用旋塗製程(spin-on process)、噴塗製程(spray coating process)、化學氣相沉積(chemical vapor deposition，CVD)製程、其他可應用的製程、或前述之組合而形成。
如第1D圖所示，根據一些實施例，保護層108覆蓋封裝層106之整個頂表面。在一些實施例中，保護層108直接接觸封裝層106。在一些實施例中，保護層108與封裝層106間之界面係介於保護層108與半導體晶粒10間之界面與半導體晶粒10之底部之間。保護層108可覆蓋封裝層106上之缺陷及/或顆粒。因此，避免了這些缺陷及/或顆粒對其他構件造成不利影響。
在一些實施例中，保護層108具有大抵平坦之頂表面。在一些實施例中，使用平坦化製程以提供保護層108大抵平坦之頂表面。平坦化製程可包括化學機械研磨製程、乾式研磨製程、研磨製程、蝕刻製程、其他可應用的製程、或前述之組合。
在一些實施例中，保護層108具有均一的厚度。在一些實施例中，保護層108之厚度為約3微米至約20微米。在一些其他實施例中，保護層108之厚度為約5微米至約10微米。然而，本揭露書之實施例不限於此。在一些實施例中，保護層108之厚度是不均一的，而保護層108之頂表面仍是平坦的。如第1D圖所示，保護層108之位於封裝層106上之部分具有厚度T1。保護層108之位於半導體晶粒10或20上之部分具有厚度T2。在一些實施例中，厚度T1大於厚度T2。
之後，如第1E圖所示，根據一些實施例，於保護層108上沉積介電層110。在一些實施例中，介電層110直接接觸保護層108。在一些實施例中，介電層110大抵由半導體氧化物材料(semiconductor oxide material)、半導體氧氧化物材料(semiconductor oxynitride material)、或半導體氮化物材料(semiconductor nitride material)所製成。介電層110非由高分子材料所製成。在一些實施例中，介電層110較保護層108硬。保護層108可用作介電層110下之應力緩衝。在一些實施例中，介電層110包括多層材料層之堆疊。在一些實施例中，介電層110包括氧化層及位於其下之氮化物層及/或碳化物層。氮化物層及/或碳化物層例如可用於使下方材料層(例如，導電層)免於被 氧化。
在一些實施例中，介電層110包括氧化矽、硼矽玻璃(borosilicate glass，BSG)、磷矽玻璃(phosphoric silicate glass，PSG)、硼磷矽玻璃(borophosphosilicate glass，BPSG)、氟化矽酸鹽玻璃(fluorinated silicate glass，FSG)、氮氧化矽、氮化矽、低介電常數(low-k)材料、四乙氧基矽烷(TEOS)氧化物、其他適合的材料、或前述之組合。在一些實施例中，介電層110係使用氣相沉積製程而沉積，例如化學氣相沉積製程、原子層沉積(atomic layer deposition，ALD)製程、物理氣相沉積製程、其他可應用的製程、或前述之組合。在一些其他實施例中，介電層110係使用旋塗製程、噴塗製程、其他可應用的製程、或前述之組合而沉積。
如第1F圖所示，根據一些實施例，於介電層110之中形成開口114。在一些實施例中，開口114為用以容納導電線路之溝槽。在一些實施例中，微影製程及蝕刻製程用以將介電層110圖案化。因此，形成了開口114。
之後，如第1F圖所示，根據一些實施例，於保護層108之中形成開口112。在一些實施例中，開口112為用以容納導電插塞(conductive vias)之通孔(via holes)。在一些實施例中，保護層108係藉著使用微影製程、雷射鑽孔製程(laser drilling process)、其他可應用的製程、或前述之組合而圖案化。因此，形成了開口112。
如第1G圖所示，根據一些實施例，於開口112及114之中分別形成導電結構116及118。在一些實施例中，於介電層 110之上沉積一或更多的導電材料以填充開口112及114。導電材料可包括金屬材料，包括銅(copper)、鋁(aluminum)、鎢(tungsten)、鈦(titanium)、鎳(nickel)、金(gold)、鉑(platinum)、銀(silver)、其他適合的材料、或前述之組合。在一些實施例中，一或更多的導電材料藉著使用電鍍製程(electroplating process)、物理氣相沉積、化學氣相沉積、無電鍍製程(electroless plating process)、其他可應用的製程、或前述之組合而沉積。
之後，使用平坦化製程以移除開口114外之導電材料。平坦化製程可包括化學機械研磨製程、乾式研磨製程、研磨製程、蝕刻製程、其他可應用的製程、或前述之組合。因此，導電材料在開口114中之餘留部分形成了導電結構118。導電材料在開口112中之餘留部分形成了導電結構116。在一些實施例中，導電結構118與介電層110之頂表面彼此共平面。
導電結構118可用作導電線路，而導電結構116可用作導電插塞。在一些實施例中，每一導電結構116電性連接至其中一導電墊104或204。在一些實施例中，每一導電結構116直接接觸其中一導電墊104或204。
在一些實施例中，其中亦導電結構118及一些導電結構116共同形成導電結構117，如第1G圖所示。導電結構117電性連接至半導體晶粒10之其中一導電墊104及半導體晶粒20之其中一導電墊204，如第1G圖所示。因此，可於半導體晶粒10與20之間傳送或接收電性訊號。半導晶粒10透過導電結構117而電性耦接至半導體晶粒20。
在一些實施例中，於導電結構118或117與介電層110之間形成阻障構件(barrier elements)(未顯示)。相似地，阻障構件亦可形成於導電結構116與保護層108之間。在一些實施例中，阻障構件係由氮化鈦(titanium nitride)、氮化鉭(tantalum nitride)、鈦(titanium)、鉭(tantalum)、其他適合的材料、或前述之組合所製成。在一些實施例中，在形成一或多層導電材料之前，於介電層110及開口114與112之側壁與底部上沉積阻障材料層。在用以形成導電結構118及117之平坦化製程之後，亦移除了在介電層110之頂表面上的阻障材料層。因此，阻障材料層之在開口114及112中之餘留部分形成了阻障構件。
如第1H圖所示，根據一些實施例，於介電層110及導電結構118與117之上沉積蝕刻停止層119。蝕刻停止層119用以輔助形成後續露出導電結構118及/或117之開口。蝕刻停止層119可由氮化矽、氮氧化矽、碳化矽、氮碳化矽、其他適合的材料、或前述之組合所製成。蝕刻停止層119可使用化學氣相沉積或其他可應用的製程而沉積。
可對本揭露書之實施例作出許多變化及/或修飾。在一些其他實施例中，未形成蝕刻停止層119。
之後，如第1H圖所示，根據一些實施例，於蝕刻停止層119之上沉積介電層120。在一些實施例中，介電層120之材質與形成方法相似或相同於介電層110。在一些實施例中，介電層120厚於介電層110。
如第1H圖所示，根據一些實施例，於介電層120之中形成開口125及123。在一些實施例中，開口125為溝槽，而 開口123為通孔。開口125及123彼此相連。在一些實施例中，開口125及123使用多道微影製程及蝕刻製程而形成。在一些實施例中，開口125及123係使用先通孔(via first)製程而形成。在一些其他實施例中，開口125及123係使用先溝槽(trench first)製程而形成。在一些實施例中，開口123露出蝕刻停止層119。之後，移除蝕刻停止層119之露出部分以露出導電結構118。
之後，如第1H圖所示，根據一些實施例，於開口125及123之中分別形成導電結構124及122。在一些實施例中，導電結構124及122係由銅、鋁、鎢、鈦、鎳、金、鉑、銀、其他適合的材料、或前述之組合而製成。在一些實施例中，於介電層120之上沉積一或更多的導電材料以填充開口125及123。在一些實施例中，一或更多的導電材料係使用電鍍製程、物理氣相沉積製程、化學氣相沉積製程、無電鍍製程、其他可應用的製程、或前述之組合而沉積。
之後，使用平坦化製程以移除開口125外之導電材料。平坦化製程可包括化學機械研磨製程、乾式研磨製程、研磨製程、蝕刻製程、其他可應用的製程、或前述之組合。因此，導電材料在開口125中之餘留部分形成了導電結構124。導電材料在開口123中之餘留部分形成了導電結構122。在一些實施例中，導電結構124與介電層120之頂表面係彼此共平面。
導電結構124可用作導電線路，而導電結構122可用作導電插塞。在一些實施例中，每一導電結構122電性連接至其中一導電結構118或117。在一些實施例中，每一導電結構122直接接觸其中一導電結構118或117。
在一些實施例中，導電結構124與介電層120之間形成阻障構件(未顯示)。相似地，阻障構件亦可形成於導電結構122與介電層120之間。在一些實施例中，阻障構件係由氮化鈦、氮化鉭、鈦、鉭、其他適合的材料、或前述之組合所製成。在一些實施例中，在形成一或多層導電材料之前，於介電層120及開口125與123之側壁與底部上沉積阻障材料層。在用以形成導電結構124及122之平坦化製程之後，亦移除了在介電層120之頂表面上的阻障材料層。因此，阻障材料層之在開口125及123中之餘留部分形成了阻障構件。
在一些實施例中，重複進行第1H圖所述之製程一次或多次以於第1H圖所示之結構上形成一或更多的介電層及導電結構。根據一些實施例，形成於保護層108之上的內連結構包括多層不是由高分子材料所製成之介電層。例如，介電層係由半導體氧化物材料所製成，例如是氧化矽。由於這些介電層由半導體氧化物材料所製成，其可使用微影及蝕刻製程而被圖案化，使能夠形成出次微米級的內連線(sub-micron interconnect)。
可對本揭露書之實施例作出許多的變化及/或修飾。在一些實施例中，保護層108上之內連結構係使用雙鑲嵌製程(dual damascene process)而形成。然而，本揭露書之實施例不限於此。在一些其他實施例中，內連結構係使用單鑲嵌製程(single damascene process)而形成。在一些其他實施例中，內連結構係組合使用單鑲嵌製程與雙鑲嵌製程而形成。
如第11圖所示，根據一些實施例，於包括介電層120 及110與導電結構124、122、118、及116之內連結構之上沉積保護層126。保護層126與108共同將內連結構夾置其間以緩衝應力。因此，增進了晶片封裝體之可靠度與品質。
在一些實施例中，保護層126為高分子層。在一些實施例中，高分子層可由光敏材料所形成，其可輕易地被圖案化以形成所需之開口。高分子層可包括聚醯亞胺(polyimide，PI)、聚苯並噁唑(polybenzoxazole，PBO)、環氧樹脂、其他適合的材料、或前述之組合。在一些實施例中，保護層126與108係由相同的材料所製成。在一些其他實施例中，保護層126與108係由不同的材料所製成。在一些實施例中，保護層126係藉著使用旋塗製程、噴塗製程、化學氣相沉積製程、其他可應用的製程、或前述之組合而形成。
如第1J圖所示，根據一些實施例，於保護層126之中形成凸塊下金屬化(under-bump metallurgy，UBM)構件128。在一些實施例中，將保護層126圖案化以形成露出導電結構124之開口。之後，沉積並圖案化多層材料層以形成凸塊下金屬化構件128。在一些實施例中，凸塊下金屬化構件128包括擴散阻障層(diffusion barrier layer)及晶種層(seed layer)。擴散阻障層可由氮化鉭所製成，雖然其亦可由其他材料所製成，例如是氮化鈦、鉭、鈦、或其他相似材料。晶種層可為形成在擴散阻障層上之銅晶種層。銅晶種層可由銅或其中一種銅合金所形成。銅合金可包括銀、鉻、鎳、錫、金、或前述之組合。在一些實施例中，每一凸塊下金屬化構件128包括由鈦所形成之擴散阻障層及由銅所形成之晶種層。
之後，如第1J圖所示，根據一些實施例，相應地於凸塊下金屬化構件128之上形成導電連接結構(conductive connectors)130。每一導電連接結構130透過相應的凸塊下金屬化構件而電性連接至相應的導電結構124。在一些實施例中，導電連接結構130包括焊料凸塊凸塊(solder bumps)或焊料球(solder balls)。在一些實施例中，於凸塊下金屬化構件128之上放置錫球，並回焊之以形成導電連接結構130。在一些其他實施例中，於凸塊下金屬化構件128之上電鍍錫材料以形成導電連接結構130。在一些其他實施例中，導電連接結構130係由焊錫材料(solder material)以外的金屬材料所製成。導電連接結構130可由銅、鋁、金、其他適合的材料、或前述之組合所製成。
根據一些實施例，在形成導電連接結構130之後，形成出了扇出晶圓(fan-out wafer)。之後，將扇出晶圓自承載基底101取下，並切割成數個晶片封裝體。顯示根據一些實施例，第1J圖顯示其中一晶片封裝體。晶片封裝體包括兩個半導體晶粒，其包括半導體晶粒10及20。在一些實施例中，半導體晶粒10及20具有互不相同之功能。在一些實施例中，半導體晶粒10及20透過形成在保護層108及126之間的內連結構而彼此電性交流。
可對本揭露書之實施例作出許多變化及/或修飾。在一些實施例中，晶片封裝體包括超過兩個之半導體晶粒。在一些實施例中，晶片封裝體包括一個半導體晶粒。第2圖顯示根據一些實施例之晶片封裝體的剖面圖。如第2圖所示，晶片封裝體僅包括一個半導體晶粒(半導體晶粒10)。
本揭露書之實施例提供了晶片封裝體，其包括一或更多由封裝層(例如，膜塑化合物層)所圍繞之半導體晶粒。半導體晶粒與封裝層之上形成有內連結構，其包括由半導體氧化物所製成之介電層，從而對半導體晶粒提供次微米扇出內連線。在形成內連結構之前，於半導體晶粒及封裝層形成保護層以緩衝應力。保護層亦可覆蓋封裝層之表面上的缺陷或顆粒，並提供平坦的表面以輔助內連結構的形成。因此，顯著地增進晶片封裝體的可靠度及品質。
根據一些實施例，提供一種晶片封裝體。晶片封裝體包括半導體晶粒及部份或完全包覆該半導體晶粒之封裝層。晶片封裝體還包括位於半導體晶粒及封裝層上之高分子層。晶片封裝體更包括位於高分子層上之介電層。介電層大抵由半導體氧化物材料、半導體氧氧化物材料、或半導體氮化物材料所製成。此外，晶片封裝體包括位於介電層中之導電結構，導電結構電性連接至半導體晶粒之導電墊。
根據一些實施例，提供一種晶片封裝體。晶片封裝體包括半導體晶粒及部份或完全包覆半導體晶粒之模塑化合物層。晶片封裝體還包括位於半導體晶粒及模塑化合物層之上的保護層。晶片封裝體更包括位於保護層之上的介電層，且介電層較保護層硬。此外，晶片封裝體包括位於介電層之中的導電結構，導電結構電性連接至半導體晶粒之導電墊。
根據一些實施例，提供一種晶片封裝體的形成方法。方法包括於半導體晶粒之上形成模塑化合物層以部分或完全包覆半導體晶粒。方法還包括於半導體晶粒與模塑化合物層 之上形成高分子層，並於高分子層之上形成介電層。介電層係由半導體氧化物材料、半導體氮氧化物材料、或半導體氮化物材料所製成。方法更包括於介電層之中形成導電結構。
雖然本揭露書已以數個較佳實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本揭露書之精神和範圍內，當可作任意之更動與潤飾，因此本揭露書之保護範圍當視後附之申請專利範圍所界定者為準。
10、20‧‧‧半導體晶粒
100‧‧‧半導體基底
102‧‧‧介電層
104‧‧‧導電墊
106‧‧‧封裝層
108‧‧‧保護層
110‧‧‧介電層
116、117、118‧‧‧導電結構
119‧‧‧蝕刻停止層
120‧‧‧介電層
122‧‧‧導電結構
124‧‧‧導電結構
126‧‧‧保護層
128‧‧‧凸塊下金屬化構件
130‧‧‧導電連接結構
200‧‧‧半導體基底
202‧‧‧介電層
204‧‧‧導電墊

Claims (15)

  1. 一種晶片封裝體，包括：一半導體晶粒；一封裝層，至少部份包覆該半導體晶粒；一高分子層，位於該半導體晶粒及該封裝層之上；一介電層，位於該高分子層之上，其中該介電層大抵由一半導體氧化物材料、一半導體氮氧化物材料、或一半導體氮化物材料所製成；以及一導電結構，位於該介電層之中，其中該導電結構電性連接至該半導體晶粒之一導電墊。
  2. 如申請專利範圍第1項所述之晶片封裝體，其中該高分子層直接接觸該導電結構、該封裝層、及該高分子層。
  3. 如申請專利範圍第1項所述之晶片封裝體，更包括一第二導體晶粒，其中該封裝層至少部分包覆該第二導體晶粒，且該第二半導體晶粒透過該介電層中之一第二導電結構而電性耦接至該半導體晶粒。
  4. 如申請專利範圍第3項所述之晶片封裝體，其中該介電層之頂表面與該導電結構之頂表面共平面。
  5. 如申請專利範圍第1項所述之晶片封裝體，更包括：一第二介電層，位於該介電層及該導電結構之上，其中該第二介電層包括一半導體氧化物材料；以及一第二導電結構，位於該第二介電層之中，且電性連接至該導電結構。
  6. 如申請專利範圍第5項所述之晶片封裝體，更包括一蝕刻停 止層，介於該介電層與該第二介電層之間。
  7. 如申請專利範圍第1項所述之晶片封裝體，更包括：一第二高分子層，位於該介電層之上；以及一導電連接結構，位於該第二高分子層之上，且電性連接至該導電結構。
  8. 一種晶片封裝體，包括：一半導體晶粒；一模塑化合物層，至少部份包覆該半導體晶粒；一保護層，位於該半導體晶粒及該模塑化合物層之上；一介電層，位於該保護層之上，其中該介電層較該保護層硬；以及一導電結構，位於該介電層之中，其中該導電結構電性連接至該半導體晶粒之一導電墊。
  9. 如申請專利範圍第8所述之晶片封裝體，其中該保護層具有一大抵平坦的頂表面。
  10. 如申請專利範圍第8所述之晶片封裝體，其中該保護層之於該模塑化合物層上的一第一部分較該保護層之於該半導體晶粒上的一第二部分厚。
  11. 如申請專利範圍第8所述之晶片封裝體，其中該介電層非以一高分子材料所製成。
  12. 如申請專利範圍第8所述之晶片封裝體，其中該保護層與該模塑化合物層之間的界面係介於該保護層與該半導體晶粒之間的界面與該該半導體晶粒之一底部之間。
  13. 一種晶片封裝體的形成方法，包括： 於一半導體晶粒之上形成一模塑化合物層以至少部分包覆該半導體晶粒；於該半導體晶粒與該模塑化合物層之上形成一高分子層；於該高分子層之上形成一介電層，其中該介電層係由一半導體氧化物材料、一半導體氮氧化物材料、或一半導體氮化物材料所製成；以及於該介電層之中形成一導電結構。
  14. 如申請專利範圍第13所述之晶片封裝體的形成方法，更包括在形成該介電層之前，將該高分子層平坦化。
  15. 如申請專利範圍第13所述之晶片封裝體的形成方法，其中該導電結構之形成包括：於該介電層之中形成一開口；於該介電層之上形成一導電材料以填充該開口；以及將該導電材料平坦化以移除該開口外的該導電材料，使得該導電材料之一餘留部分形成該導電結構。
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