TW201620105A - TSV structure having embedded void insulating layer and fabricating method for the same - Google Patents
TSV structure having embedded void insulating layer and fabricating method for the same Download PDFInfo
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- TW201620105A TW201620105A TW103140659A TW103140659A TW201620105A TW 201620105 A TW201620105 A TW 201620105A TW 103140659 A TW103140659 A TW 103140659A TW 103140659 A TW103140659 A TW 103140659A TW 201620105 A TW201620105 A TW 201620105A
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- air gap
- insulating layer
- dimples
- semiconductor body
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- 239000011800 void material Substances 0.000 title claims abstract description 7
- 238000000034 method Methods 0.000 title claims description 11
- 239000004065 semiconductor Substances 0.000 claims abstract description 46
- 238000011049 filling Methods 0.000 claims abstract description 14
- 239000004020 conductor Substances 0.000 claims abstract description 8
- 238000002955 isolation Methods 0.000 claims abstract description 6
- 239000010410 layer Substances 0.000 claims description 49
- 239000000463 material Substances 0.000 claims description 16
- 239000011241 protective layer Substances 0.000 claims description 10
- 239000007787 solid Substances 0.000 claims description 7
- 239000003989 dielectric material Substances 0.000 claims description 5
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 claims description 3
- 238000005530 etching Methods 0.000 claims description 3
- 229910052707 ruthenium Inorganic materials 0.000 claims description 3
- 229910000679 solder Inorganic materials 0.000 claims description 3
- 239000000945 filler Substances 0.000 abstract 2
- 238000009413 insulation Methods 0.000 description 4
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 3
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- 238000005260 corrosion Methods 0.000 description 2
- 238000000708 deep reactive-ion etching Methods 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- SIWVEOZUMHYXCS-UHFFFAOYSA-N oxo(oxoyttriooxy)yttrium Chemical compound O=[Y]O[Y]=O SIWVEOZUMHYXCS-UHFFFAOYSA-N 0.000 description 2
- 230000008054 signal transmission Effects 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 2
- 238000003466 welding Methods 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910052691 Erbium Inorganic materials 0.000 description 1
- QCEUXSAXTBNJGO-UHFFFAOYSA-N [Ag].[Sn] Chemical compound [Ag].[Sn] QCEUXSAXTBNJGO-UHFFFAOYSA-N 0.000 description 1
- 229910052797 bismuth Inorganic materials 0.000 description 1
- JCXGWMGPZLAOME-UHFFFAOYSA-N bismuth atom Chemical compound [Bi] JCXGWMGPZLAOME-UHFFFAOYSA-N 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 238000003486 chemical etching Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 238000000280 densification Methods 0.000 description 1
- UYAHIZSMUZPPFV-UHFFFAOYSA-N erbium Chemical compound [Er] UYAHIZSMUZPPFV-UHFFFAOYSA-N 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 229910052746 lanthanum Inorganic materials 0.000 description 1
- FZLIPJUXYLNCLC-UHFFFAOYSA-N lanthanum atom Chemical compound [La] FZLIPJUXYLNCLC-UHFFFAOYSA-N 0.000 description 1
- LQBJWKCYZGMFEV-UHFFFAOYSA-N lead tin Chemical compound [Sn].[Pb] LQBJWKCYZGMFEV-UHFFFAOYSA-N 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
本發明係有關於半導體晶片的縱向導通結構，特別係有關於一種具內嵌空洞絕緣層之矽穿孔結構及其製造方法。 The present invention relates to a longitudinal conduction structure of a semiconductor wafer, and more particularly to a crucible perforation structure having an in-cell void insulation layer and a method of fabricating the same.
為了縮小元件尺寸，已知矽穿孔結構作為半導體晶片內的縱向導通路徑。矽穿孔結構內有導電材料，電性導通晶片的主動面與背面，使得晶片兩表面的電極可相互導通，當晶片堆疊時，可省略習知的銲線或接合引線，故達到晶片堆疊組合的裝置微小化。然而，隨著矽穿孔結構的密集化與微孔化，將會有電阻電容延遲(RC delay)與電荷耦合(charge coupling)的問題。 In order to reduce the size of the components, the tantalum perforated structure is known as a longitudinal conduction path within the semiconductor wafer. The perforated structure has a conductive material therein, electrically conducting the active surface and the back surface of the wafer, so that the electrodes on both surfaces of the wafer can be electrically connected to each other. When the wafer is stacked, the conventional bonding wires or bonding leads can be omitted, so that the wafer stacking combination is achieved. The device is miniaturized. However, with the densification and micro-poration of the erbium perforation structure, there will be problems of RC delay and charge coupling.
為了解決上述之問題，本發明之主要目的係在於提供一種具內嵌空洞絕緣層之矽穿孔結構及其製造方法，在矽穿孔孔壁創造出非固態介電層，用以改善矽穿孔結構的電阻電容延遲(RC Delay)，進而解決矽穿孔結構的訊號傳輸時間延遲之問題。 In order to solve the above problems, the main object of the present invention is to provide a crucible perforation structure with an in-cell void insulation layer and a manufacturing method thereof, which can create a non-solid dielectric layer on the perforated hole wall to improve the perforated structure. Resistor-capacitor delay (RC Delay), which solves the problem of signal transmission time delay in the 矽-perforated structure.
本發明的目的及解決其技術問題是採用以下技術方案來實現的。本發明揭示一種具內嵌空洞絕緣層之矽穿孔結構，包含一晶片層、一介電內襯以及一導電填孔 物。該晶片層係具有一半導體主體，其中至少一孔洞係由該半導體主體之一表面凹入，由該孔洞之孔壁係更形成有複數個氣隙凹坑，該些氣隙凹坑係具有一寬度以及一不小於該寬度之深度。該介電內襯係覆蓋於該孔洞之孔壁且不填滿該些氣隙凹坑。該導電填孔物係設置於該半導體主體之該孔洞，並在該介電內襯之隔離下，該導電填孔物係不填入該些氣隙凹坑，以使該些氣隙凹坑內不被導電材料與固態介電材料填滿而構成為一介於該半導體主體與該介電內襯之間之內嵌空洞絕緣層。本發明另揭示該矽穿孔結構之製造方法。 The object of the present invention and solving the technical problems thereof are achieved by the following technical solutions. The invention discloses a crucible perforation structure with an embedded cavity insulating layer, comprising a wafer layer, a dielectric liner and a conductive filling hole Things. The wafer layer has a semiconductor body, wherein at least one hole is recessed by a surface of the semiconductor body, and a plurality of air gap pits are further formed by the hole wall of the hole, and the air gap pits have a The width and a depth not less than the width. The dielectric liner covers the hole walls of the hole and does not fill the air gap pits. The conductive fill hole is disposed in the hole of the semiconductor body, and under the isolation of the dielectric liner, the conductive fill hole does not fill the air gap pits to make the air gap pits The inner portion is not filled with the conductive material and the solid dielectric material to form a cavity insulating layer interposed between the semiconductor body and the dielectric liner. The invention further discloses a method of manufacturing the crucible perforation structure.
本發明的目的及解決其技術問題還可採用以下技術措施進一步實現。 The object of the present invention and solving the technical problems thereof can be further achieved by the following technical measures.
在前述矽穿孔結構之一較佳實施例中，可另包含有複數個內襯連接環，其係形成於該些氣隙凹坑之間，以連接該介電內襯，以避免該些內襯連接環直接接觸該半導體主體，且可在不擴大該些氣隙凹坑之寬度下加大該些氣隙凹坑之深度。 In a preferred embodiment of the foregoing damper structure, a plurality of lining connecting rings may be further formed between the air gap recesses to connect the dielectric lining to avoid the inner linings. The lining connection ring directly contacts the semiconductor body, and the depth of the air gap dimples can be increased without expanding the width of the air gap dimples.
在前述矽穿孔結構之一較佳實施例中，該些內襯連接環係可不形成於該些氣隙凹坑之底部。 In a preferred embodiment of the foregoing plenum perforation structure, the lining connection ring systems may not be formed at the bottom of the air gap dimples.
在前述矽穿孔結構之一較佳實施例中，該些氣隙凹坑之深度係具體介於該些氣隙凹坑之寬度之1~3倍之間。 In a preferred embodiment of the foregoing plethrium perforation structure, the depth of the air gap dimples is specifically between 1 and 3 times the width of the air gap dimples.
在前述矽穿孔結構之一較佳實施例中，該些氣隙凹坑之深度係具體介於60~1500奈米，該些氣隙凹坑之寬度係具體介於20~500奈米。 In a preferred embodiment of the foregoing plenum perforation structure, the depth of the air gap dimples is specifically between 60 and 1500 nm, and the width of the air gap dimples is specifically between 20 and 500 nm.
在前述矽穿孔結構之一較佳實施例中，該些氣隙凹坑內係可含有空氣，即該些氣隙凹坑不被該介電內襯填滿，以構成多環形氣泡環結構。 In a preferred embodiment of the foregoing crucible perforation structure, the air gap dimples may contain air, that is, the air gap dimples are not filled by the dielectric liner to form a multi-annular bubble ring structure.
在前述矽穿孔結構之一較佳實施例中，該導電填孔物係可更突出於該半導體主體之該表面，以形成為一凸塊部，以作為微接觸接合端。 In a preferred embodiment of the foregoing ruthenium perforation structure, the conductive hole-filling structure may protrude from the surface of the semiconductor body to form a bump portion as a micro-contact joint end.
在前述矽穿孔結構之一較佳實施例中，該凸塊部上係可設置有一銲接材料。 In a preferred embodiment of the foregoing damper structure, a solder material may be disposed on the bump portion.
在前述矽穿孔結構之一較佳實施例中，該介電內襯係可更形成於該半導體主體之該表面上，該矽穿孔結構係另包含一保護層，係形成於該半導體主體之該表面上與該介電內襯之下，並且該保護層係不形成於該孔洞內，故該保護層可作為半導體防蝕層。 In a preferred embodiment of the 矽 矽 矽 structure, the dielectric lining may be formed on the surface of the semiconductor body, the 矽 矽 structure further comprising a protective layer formed on the semiconductor body The protective layer can serve as a semiconductor anti-corrosion layer on the surface and under the dielectric liner, and the protective layer is not formed in the hole.
10‧‧‧蝕罩層 10‧‧‧ eclipse
11‧‧‧開孔 11‧‧‧Opening
100‧‧‧具內嵌空洞絕緣層之矽穿孔結構 100‧‧‧矽 Perforated structure with hollow insulation
110‧‧‧晶片層 110‧‧‧ wafer layer
111‧‧‧半導體主體 111‧‧‧Semiconductor main body
112‧‧‧表面 112‧‧‧ surface
113‧‧‧孔洞 113‧‧‧ holes
120‧‧‧氣隙凹坑 120‧‧‧ Air gap pit
121‧‧‧環形凹坑 121‧‧‧ring pit
130‧‧‧介電內襯 130‧‧‧Dielectric lining
140‧‧‧導電填孔物 140‧‧‧Electrical hole filling
141‧‧‧凸塊部 141‧‧‧Bumps
150‧‧‧內襯連接環 150‧‧‧Lined connecting ring
151‧‧‧內襯連接層 151‧‧‧ lining connection layer
160‧‧‧銲接材料 160‧‧‧Welding materials
170‧‧‧保護層 170‧‧‧Protective layer
D1‧‧‧環形凹坑之深度 D1‧‧‧Deep pit depth
D2‧‧‧氣隙凹坑之深度 D2‧‧‧ Depth of air gap pit
W1‧‧‧環形凹坑之寬度 W1‧‧‧ring pit width
W2‧‧‧氣隙凹坑之寬度 W2‧‧‧width of air gap pit
第1圖：依據本發明之一具體實施例，一種具內嵌空洞絕緣層之矽穿孔結構之局部截面示意圖。 BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a partial cross-sectional view showing a crucible structure having a cavity insulating layer embedded therein, in accordance with an embodiment of the present invention.
第2A至2E圖：依據本發明之一具體實施例，繪示該矽穿孔結構在製程之相關步驟中主元件之局部截面示意圖。 2A to 2E are diagrams showing a partial cross-sectional view of the main element of the crucible perforation structure in the relevant steps of the process according to an embodiment of the present invention.
以下將配合所附圖示詳細說明本發明之實施例，然應注意的是，該些圖示均為簡化之示意圖，僅以示意方法來說明本發明之基本架構或實施方法，故僅顯示與本案有關之元件與組合關係，圖中所顯示之元件並非以實際實施之數目、形狀、尺寸做等比例繪製，某些尺寸比例與其他相關尺寸比例或已誇張或是簡化處理，以提供更清楚的描述。實際實施之數目、形狀及尺寸比例為一種選置性之設計，詳細之元件佈局可能更為複雜。 The embodiments of the present invention will be described in detail below with reference to the accompanying drawings in which FIG. The components and combinations related to this case, the components shown in the figure are not drawn in proportion to the actual number, shape and size of the actual implementation. Some size ratios are proportional to other related sizes or have been exaggerated or simplified to provide clearer description of. The actual number, shape and size ratio of the implementation is an optional design, and the detailed component layout may be more complicated.
依據本發明之第一具體實施例，一種具內嵌空洞絕緣層之矽穿孔結構舉例說明於第1圖之局部截面示意 圖以及第2A至2E圖在製程之相關步驟中主元件之局部截面示意圖。一種具內嵌空洞絕緣層之矽穿孔結構100，包含一晶片層110、一介電內襯130以及一導電填孔物140。 According to a first embodiment of the present invention, a meandering structure having a hollow insulating layer embedded therein is illustrated in a partial cross section of FIG. Figure and Figures 2A through 2E are partial cross-sectional views of the main components in the relevant steps of the process. A crucible structure 100 having a recessed insulating layer includes a wafer layer 110, a dielectric liner 130, and a conductive via 140.
該晶片層110係為一半導體元件，具有積體電路或主動元件。該晶片層110係具有一半導體主體111，例如矽(Si)，該半導體主體111之體積佔比為該晶片層110之50%以上體積。其中至少一孔洞113係由該半導體主體111之一表面112凹入，該表面112係可為該晶片層110之主動面，或可為該晶片層110之背面。當該表面112係為主動面時，該孔洞113之深度可不超過該半導體主體111之二分之一，可利用晶背研磨，使該孔洞113為貫穿；當該表面112係為背面時，該孔洞113之深度可超過該半導體主體111之三分之二以上，或為貫穿該半導體主體111之型態。並且由該孔洞113之孔壁係更形成有複數個氣隙凹坑120。如第2D圖所示，該些氣隙凹坑120係具有一寬度W2以及一不小於該寬度W2之深度D2。該些氣隙凹坑120之深度D2係具體介於該些氣隙凹坑120之寬度W2之1~3倍之間。例如，該些氣隙凹坑120之深度係具體介於60~1500奈米，該些氣隙凹坑120之寬度係具體介於20~500奈米。該些氣隙凹坑120之深度通常地大於該晶片層110之積體電路線路厚度。 The wafer layer 110 is a semiconductor component having an integrated circuit or an active component. The wafer layer 110 has a semiconductor body 111, such as germanium (Si), which has a volume fraction of more than 50% of the wafer layer 110. At least one of the holes 113 is recessed by a surface 112 of the semiconductor body 111. The surface 112 may be the active surface of the wafer layer 110 or may be the back surface of the wafer layer 110. When the surface 112 is an active surface, the depth of the hole 113 may not exceed one-half of the semiconductor body 111, and the hole 113 may be grounded through the back grinding; when the surface 112 is a back surface, the surface 112 The depth of the hole 113 may exceed two-thirds or more of the semiconductor body 111 or may be through the semiconductor body 111. And a plurality of air gap dimples 120 are further formed by the hole wall of the hole 113. As shown in FIG. 2D, the air gap dimples 120 have a width W2 and a depth D2 not less than the width W2. The depth D2 of the air gap dimples 120 is specifically between 1 and 3 times the width W2 of the air gap dimples 120. For example, the depth of the air gap dimples 120 is specifically between 60 and 1500 nm, and the width of the air gap dimples 120 is specifically between 20 and 500 nm. The depth of the air gap dimples 120 is generally greater than the integrated circuit line thickness of the wafer layer 110.
該介電內襯130係覆蓋於該孔洞113之孔壁且不填滿該些氣隙凹坑120。該介電內襯130之材質係可為氮化矽(SiN)、氮氧化矽(SiON)與氧化矽(SiO2)之其中之一。該導電填孔物140係設置於該半導體主體111之該孔洞113，該導電填孔物140之材質係可為銅或金。較佳地，該導電填孔物140係可更突出於該半導體主體111之該表面112，以形成為一凸塊部141，以作為微接觸接合端。該 凸塊部141上係可設置有一銲接材料160，例如鉛錫或錫銀。 The dielectric liner 130 covers the hole walls of the holes 113 and does not fill the air gap dimples 120. The material of the dielectric liner 130 may be one of tantalum nitride (SiN), bismuth oxynitride (SiON) and yttrium oxide (SiO 2 ). The conductive hole-filling material 140 is disposed in the hole 113 of the semiconductor body 111. The material of the conductive hole-filling material 140 can be copper or gold. Preferably, the conductive via 140 can protrude from the surface 112 of the semiconductor body 111 to form a bump portion 141 as a micro-contact junction. A solder material 160 such as lead tin or tin silver may be disposed on the bump portion 141.
並且，在該介電內襯130之隔離下，該導電填孔物140係不填入該些氣隙凹坑120，以使該些氣隙凹坑120內不被導電材料與固態介電材料填滿而構成為一介於該半導體主體111與該介電內襯130之間之內嵌空洞絕緣層，該內嵌空洞絕緣層係由該些氣隙凹坑120的內部空間與該介電內襯130之遮蔽開口所構成，該內嵌空洞絕緣層之厚度係由該些氣隙凹坑120之深度D2所界定。該些氣隙凹坑120內係可含有空氣，即該些氣隙凹坑120不被該介電內襯130填滿，以構成多環形氣泡環結構。 Moreover, under the isolation of the dielectric liner 130, the conductive vias 140 are not filled in the air gap dimples 120, so that the air gap dimples 120 are not covered by the conductive material and the solid dielectric material. Filled and formed as a cavity insulating layer interposed between the semiconductor body 111 and the dielectric liner 130, the embedded cavity insulating layer is formed by the inner space of the air gap recess 120 and the dielectric The shadow opening of the liner 130 is formed by the depth D2 of the air gap pits 120. The air gap dimples 120 may contain air, that is, the air gap dimples 120 are not filled by the dielectric liner 130 to form a multi-annular bubble ring structure.
較佳地，該矽穿孔結構100係可另包含有複數個內襯連接環150，其係形成於該些氣隙凹坑120之間，以連接該介電內襯130，以避免該些內襯連接環150直接接觸該半導體主體111，且可在不擴大該些氣隙凹坑120之寬度下加大該些氣隙凹坑120之深度。該些內襯連接環150係可不形成於該些氣隙凹坑120之底部。 Preferably, the cymbal perforated structure 100 further includes a plurality of lining connecting rings 150 formed between the air gap dimples 120 to connect the dielectric lining 130 to avoid the inner linings 130. The lining connecting ring 150 directly contacts the semiconductor body 111, and the depth of the air gap dimples 120 can be increased without widening the width of the air gap dimples 120. The lining connecting rings 150 may not be formed at the bottom of the air gap dimples 120.
該介電內襯130係可更形成於該半導體主體111之該表面112上，該矽穿孔結構100係另包含一保護層170，係形成於該半導體主體111之該表面112上與該介電內襯130之下，並且該保護層170係不形成於該孔洞113內，故該保護層170可作為半導體防蝕層。 The dielectric liner 130 can be formed on the surface 112 of the semiconductor body 111. The germanium via structure 100 further includes a protective layer 170 formed on the surface 112 of the semiconductor body 111 and the dielectric. Below the liner 130, and the protective layer 170 is not formed in the hole 113, the protective layer 170 can serve as a semiconductor corrosion resist.
滯後係數(Time constant)為電阻與電容之乘數，該矽穿孔結構100之電容為介電常數(dielectric constant)乘以矽穿孔接觸面積(TSV contact area)並除以介電厚度(dielectric thickness)，空氣之介電常數為1，氧化物的介電常數約為4，故由該些氣隙凹坑120構成之內嵌空洞絕緣層係具有較低的電容，使得該矽穿孔結構100之 滯後係數降低。因此，本發明揭示之一種具內嵌空洞絕緣層之矽穿孔結構100係在矽穿孔孔壁創造出非固態介電層，用以改善矽穿孔結構的電阻電容延遲(RC Delay)，進而解決矽穿孔結構的訊號傳輸時間延遲之問題。 The time constant is the multiplier of the resistance and the capacitance. The capacitance of the 矽-perforated structure 100 is the dielectric constant multiplied by the TSV contact area and divided by the dielectric thickness. The dielectric constant of the air is 1, and the dielectric constant of the oxide is about 4. Therefore, the in-cell void insulating layer formed by the air gap dimples 120 has a lower capacitance, so that the crucible perforated structure 100 The hysteresis factor is reduced. Therefore, the perforated structure 100 with a recessed insulating layer is formed in the sidewall of the perforated hole to create a non-solid dielectric layer for improving the resistance and capacitance delay (RC Delay) of the perforated structure, thereby solving the problem. The problem of signal transmission time delay of the perforated structure.
第2A至2E圖係有關於該矽穿孔結構100之製程。如第2A圖所示，首先，提供一晶片層110，係具有一半導體主體111，該晶片層110係為構成於一晶圓之晶片單位，該半導體主體111之一表面112係可形成有一保護層170，該保護層170上係可先披覆一蝕罩層10，如光阻材料；經曝光顯影之後，在預定形成矽穿孔之位置，該蝕罩層10係具有一開孔11。如第2B圖所示，進行一設孔步驟，利用BOSCH(深反應性離子蝕刻)製程，形成至少一孔洞113，該孔洞113係由該半導體主體111之該表面112凹入，該孔洞113之位置對應於上述之開孔11。在形成該孔洞113之後，移除該蝕罩層10。具體地，該孔洞113之孔壁係具有一斜度，使得該孔洞113之孔壁長度大於該孔洞113之垂直深度，換言之，該孔洞113將呈開口擴大的半錐形孔，有助於前述氣隙凹坑120之深化。並且，再如第2B圖所示，該孔洞113之孔壁係形成有複數個環形凹坑121，通常該些環形凹坑121之深度D1係不大於該些環形凹坑121之寬度W1。該些環形凹坑121之深度D1係可介於20~500奈米；該些環形凹坑121之寬度W1係亦可介於20~500奈米。 2A through 2E are diagrams relating to the process of the crucible perforation structure 100. As shown in FIG. 2A, first, a wafer layer 110 is provided, which has a semiconductor body 111, which is a wafer unit formed on a wafer, and a surface 112 of the semiconductor body 111 can be formed with a protection. The layer 170, the protective layer 170 may be coated with an etch layer 10, such as a photoresist material; after exposure and development, the etch layer 10 has an opening 11 at a position where a ruthenium perforation is predetermined. As shown in FIG. 2B, a hole-forming step is performed to form at least one hole 113 by a BOSCH (deep reactive ion etching) process, the hole 113 being recessed by the surface 112 of the semiconductor body 111, the hole 113 The position corresponds to the opening 11 described above. After the hole 113 is formed, the etch layer 10 is removed. Specifically, the hole wall of the hole 113 has a slope such that the hole wall length of the hole 113 is greater than the vertical depth of the hole 113. In other words, the hole 113 will be a semi-tapered hole with an enlarged opening, which contributes to the foregoing. The deepening of the air gap dimples 120. Further, as shown in FIG. 2B, the hole walls of the hole 113 are formed with a plurality of annular recesses 121. Generally, the depth D1 of the annular recesses 121 is not greater than the width W1 of the annular recesses 121. The depth D1 of the annular recesses 121 may be between 20 and 500 nanometers; and the width W1 of the annular recesses 121 may also be between 20 and 500 nanometers.
之後，對於該孔洞113進行一半導體孔微蝕步驟，使得由該孔洞113之孔壁係更形成有複數個氣隙凹坑120，該些氣隙凹坑120係具有一寬度W2以及一不小於該寬度W2之深度D2(第2D圖所示)。如第2C圖所示，在該半導體孔微蝕步驟之前置步驟中，可利用PE-CVD(電漿輔助化學氣相沈積)製程形成一內襯連接層151在該半導體主 體111之該表面112上，並且在該孔洞113之孔壁形成複數個內襯連接環150，其係形成於該些環形凹坑121之間。該內襯連接層151與該些內襯連接環150之材質係可為氮化矽(SiN)、氮氧化矽(SiON)與氧化矽(SiO2)之其中之一，該內襯連接層151與該些內襯連接環150之沉積厚度係可介於0.05~3微米。第2D圖所示，在半導體孔微蝕步驟中，利用BOSCH(深反應性離子蝕刻)製程或化學蝕刻製程，蝕刻該孔洞113之孔壁未被保護的部位，以使得該些環形凹坑121深化以形成該些氣隙凹坑120，藉此該些氣隙凹坑120之深度D2係具體介於該些氣隙凹坑120之寬度W2之1~3倍之間。如第2E圖所示，利用低階梯覆蓋(low step coverage)的PE-CVD(電漿輔助化學氣相沈積)製程，形成一介電內襯130，該介電內襯130係覆蓋於該孔洞113之孔壁且不填滿該些氣隙凹坑120，該些內襯連接環150係連接該介電內襯130。該介電內襯130係可為單層膜或是多層膜。較佳地，該介電內襯130係可由低階梯覆蓋底層膜與高階梯覆蓋頂層膜所組成。最後，再如第1圖所示，利用UBM沉積與電鍍製程，設置一導電填孔物140，該導電填孔物140係設置於該半導體主體111之該孔洞113，並在該介電內襯130之隔離下，該導電填孔物140係不填入該些氣隙凹坑120，以使該些氣隙凹坑120內不被導電材料與固態介電材料填滿而構成為一介於該半導體主體111與該介電內襯130之間之內嵌空洞絕緣層。 Thereafter, a semiconductor hole micro-etching step is performed on the hole 113, so that a plurality of air gap pits 120 are formed from the hole wall of the hole 113, and the air gap pits 120 have a width W2 and a not less than The depth W2 of the width W2 (shown in Fig. 2D). As shown in FIG. 2C, in the pre-step of the semiconductor hole microetching step, a liner connection layer 151 may be formed on the surface of the semiconductor body 111 by a PE-CVD (plasma assisted chemical vapor deposition) process. 112, and a plurality of lining connecting rings 150 are formed in the hole walls of the holes 113, which are formed between the annular recesses 121. The material of the lining connecting layer 151 and the lining connecting ring 150 may be one of tantalum nitride (SiN), lanthanum oxynitride (SiON) and yttrium oxide (SiO 2 ), and the lining connecting layer 151 The deposition thickness with the lining connecting rings 150 may be between 0.05 and 3 microns. As shown in FIG. 2D, in the semiconductor hole micro-etching step, the unprotected portions of the hole walls of the holes 113 are etched by a BOSCH (Deep Reactive Ion Etching) process or a chemical etching process, so that the annular pits 121 are formed. The air gap dimples 120 are deepened to form the air gap dimples 120, and the depth D2 of the air gap dimples 120 is specifically between 1 and 3 times the width W2 of the air gap dimples 120. As shown in FIG. 2E, a dielectric lining 130 is formed by a low step coverage PE-CVD (plasma assisted chemical vapor deposition) process, and the dielectric liner 130 covers the hole. The hole walls of 113 do not fill the air gap dimples 120, and the lining connection rings 150 are connected to the dielectric lining 130. The dielectric liner 130 can be a single layer film or a multilayer film. Preferably, the dielectric liner 130 is comprised of a low step coverage underlying film and a high step coverage top film. Finally, as shown in FIG. 1 , a conductive fill hole 140 is disposed on the hole 113 of the semiconductor body 111 by using the UBM deposition and plating process, and the dielectric liner is disposed on the dielectric liner. The isolation hole 140 is not filled in the air gap dimples 120 so that the air gap dimples 120 are not filled with the conductive material and the solid dielectric material. A cavity insulating layer is embedded between the semiconductor body 111 and the dielectric liner 130.
以上所述，僅是本發明的較佳實施例而已，並非對本發明作任何形式上的限制，雖然本發明已以較佳實施例揭露如上，然而並非用以限定本發明，任何熟悉本項技術者，在不脫離本發明之技術範圍內，所作的任何簡單修改、等效性變化與修飾，均仍屬於本發明的技術範圍內。 The above is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the present invention. Any simple modifications, equivalent changes and modifications made without departing from the technical scope of the present invention are still within the technical scope of the present invention.
100‧‧‧具內嵌空洞絕緣層之矽穿孔結構 100‧‧‧矽 Perforated structure with hollow insulation
110‧‧‧晶片層 110‧‧‧ wafer layer
111‧‧‧半導體主體 111‧‧‧Semiconductor main body
112‧‧‧表面 112‧‧‧ surface
113‧‧‧孔洞 113‧‧‧ holes
120‧‧‧氣隙凹坑 120‧‧‧ Air gap pit
130‧‧‧介電內襯 130‧‧‧Dielectric lining
140‧‧‧導電填孔物 140‧‧‧Electrical hole filling
141‧‧‧凸塊部 141‧‧‧Bumps
150‧‧‧內襯連接環 150‧‧‧Lined connecting ring
151‧‧‧內襯連接層 151‧‧‧ lining connection layer
160‧‧‧銲接材料 160‧‧‧Welding materials
170‧‧‧保護層 170‧‧‧Protective layer
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