CN110707068B - Semiconductor interconnection structure and preparation method thereof - Google Patents
Semiconductor interconnection structure and preparation method thereof Download PDFInfo
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- CN110707068B CN110707068B CN201910849258.1A CN201910849258A CN110707068B CN 110707068 B CN110707068 B CN 110707068B CN 201910849258 A CN201910849258 A CN 201910849258A CN 110707068 B CN110707068 B CN 110707068B
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
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- H—ELECTRICITY
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
- H01L23/5283—Cross-sectional geometry
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/7682—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing the dielectric comprising air gaps
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Abstract
The invention provides a semiconductor interconnection structure and a preparation method thereof, wherein the semiconductor interconnection structure comprises: a substrate; the first insulating layer is positioned on the first surface of the substrate; a pad located within the first insulating layer and spaced from the first surface of the substrate; the annular through hole is positioned in the substrate and penetrates through the substrate along the thickness direction of the substrate; the through hole is positioned in the substrate, penetrates through the substrate along the thickness direction of the substrate and is positioned on the inner side of the annular through hole; the filling insulating layer is filled in the annular through hole and the through hole; the air gap is positioned in the filling insulating layer filled in the annular through hole; and one end of the interconnection structure is connected with the bottom of the bonding pad, and the other end of the interconnection structure at least penetrates through the first insulating layer and the filling insulating layer positioned in the through hole. The semiconductor interconnection structure can reduce the parasitic capacitance between the bonding pad and the interconnection structure and the substrate, thereby improving the input and output speed of the bonding pad during operation.
Description
Technical Field
The invention belongs to the technical field of integrated circuit design and manufacture, and particularly relates to a semiconductor interconnection structure and a preparation method thereof.
Background
In the conventional semiconductor interconnection structure, an interconnection structure connected with a pad generally penetrates through a substrate through a through hole in the substrate, and because the substrate is a whole structure (that is, a part of the substrate below the pad is integrally connected with a part of the substrate at the periphery of the pad), higher parasitic capacitance exists between the pad and the interconnection structure and the substrate, and the higher parasitic capacitance causes lower input and output speeds of the pad during operation.
Disclosure of Invention
In view of the above drawbacks of the prior art, an object of the present invention is to provide a semiconductor interconnect structure and a method for manufacturing the same, which are used to solve the problems of the semiconductor interconnect structure in the prior art that the pad and the parasitic capacitance between the interconnect structure and the substrate are high, so that the input and output speeds of the pad are low during the operation.
To achieve the above and other related objects, the present invention provides a semiconductor interconnect structure comprising:
a substrate comprising opposing first and second surfaces;
the first insulating layer is positioned on the first surface of the substrate;
a pad located within the first insulating layer and having a spacing from the first surface of the substrate;
the annular through hole is positioned in the substrate and penetrates through the substrate along the thickness direction of the substrate;
the through hole is positioned in the substrate, penetrates through the substrate along the thickness direction of the substrate and is positioned on the inner side of the annular through hole;
the filling insulation layer is filled in the annular through hole and the through hole;
the air gap is positioned in the filling insulating layer filled in the annular through hole;
and one end of the interconnection structure is connected with the bottom of the bonding pad, and the other end of the interconnection structure at least penetrates through the first insulating layer and the filling insulating layer positioned in the through hole.
Optionally, the pad is embedded in the first insulating layer, and a surface of the pad away from the substrate is flush with a surface of the first insulating layer away from the substrate.
Optionally, the number of the through holes and the number of the interconnection structures are both multiple, and the through holes and the interconnection structures are arranged in a one-to-one correspondence manner.
Optionally, the width of the through hole is smaller than the width of the annular through hole.
Optionally, the interconnect structure is isolated from the substrate by the filled insulating layer located within the via.
Optionally, the annular through hole is located at the periphery of the pad.
Optionally, the shape of the air gap comprises a ring shape.
Optionally, the semiconductor interconnect structure further comprises:
the second insulating layer is positioned on the second surface of the substrate;
one end of the interconnection structure, which is far away from the bonding pad, also penetrates through the second insulating layer to extend to the surface, which is far away from the substrate, of the second insulating layer.
The invention also provides a preparation method of the semiconductor interconnection structure, which comprises the following steps:
providing a substrate comprising opposing first and second surfaces;
forming an annular through hole and a through hole in the substrate, wherein the annular through hole and the through hole both penetrate through the substrate along the thickness direction of the substrate, and the through hole is positioned on the inner side of the annular through hole;
forming filling insulation layers in the annular through hole and the through hole, wherein an air gap is formed in the filling insulation layers in the annular through hole;
forming a first insulating layer on the first surface of the substrate;
forming a communicating hole in the first insulating layer and the filling insulating layer positioned in the through hole, and forming a groove in the first insulating layer; the communication hole is positioned on the inner side of the annular through hole and at least penetrates through the first insulating layer and the filling insulating layer positioned in the through hole along the thickness direction; the groove defines the position and the shape of a pad to be formed subsequently, is positioned on the inner side of the annular through hole and is communicated with the communication hole, and the depth of the groove is smaller than the thickness of the first insulating layer;
and forming the bonding pad in the groove and forming an interconnection structure in the communication hole.
Optionally, the surface of the pad away from the substrate is flush with the surface of the first insulating layer away from the substrate.
Optionally, the number of the through holes and the number of the interconnection structures are both multiple, and the through holes and the interconnection structures are arranged in a one-to-one correspondence manner.
Optionally, the width of the through hole is smaller than the width of the annular through hole.
Optionally, the width of the via is smaller than the width of the via, and the interconnect structure is isolated from the substrate by the filled insulating layer located within the via.
Optionally, the annular through hole is located at the periphery of the pad.
Optionally, the shape of the air gap comprises a ring shape.
Optionally, after providing the substrate and before forming the annular through hole in the substrate, the method further includes the following steps: forming a second insulating layer on the second surface of the substrate; the communication hole also penetrates through the second insulating layer in the thickness direction; the bottom of the groove is communicated with the top of the reserved communication hole; one end of the interconnection structure, which is far away from the bonding pad, extends to the surface, away from the substrate, of the second insulating layer.
As described above, the semiconductor interconnect structure and the method for manufacturing the same of the present invention have the following advantageous effects:
according to the semiconductor interconnection structure, the annular through hole is formed in the substrate on the periphery of the bonding pad, the air gap is formed in the filling insulating layer in the annular through hole, and the part of the substrate, which is positioned right below the bonding pad, can be isolated from the part of the substrate, which is positioned on the periphery of the bonding pad, through the air gap, so that parasitic capacitance among the bonding pad, the interconnection structure and the substrate is reduced, and the input and output speeds of the bonding pad during operation are improved.
Drawings
Fig. 1 is a schematic cross-sectional view of a semiconductor interconnect structure in an example.
Fig. 2 is a flowchart illustrating a method for fabricating a semiconductor interconnect structure according to a first embodiment of the present invention.
Fig. 3 is a schematic cross-sectional structure diagram of the structure obtained in step 1) of the method for manufacturing a semiconductor interconnect structure according to the first embodiment of the present invention.
Fig. 4 is a schematic cross-sectional structure diagram of the structure obtained in step 2) of the method for manufacturing a semiconductor interconnect structure provided in the first embodiment of the present invention.
Fig. 5 is a schematic cross-sectional structure diagram of the structure obtained in step 3) of the method for manufacturing a semiconductor interconnect structure according to the first embodiment of the present invention.
Fig. 6 is a schematic cross-sectional view of the structure obtained in step 4) of the method for manufacturing a semiconductor interconnect structure according to the first embodiment of the present invention.
Fig. 7 to 8 are schematic cross-sectional views of the structure obtained in step 5) of the method for manufacturing a semiconductor interconnect structure according to the first embodiment of the present invention.
Fig. 9 is a schematic cross-sectional view of the structure obtained in step 6) of the method for manufacturing a semiconductor interconnect structure provided in the first embodiment of the present invention; fig. 9 is a schematic cross-sectional view of a semiconductor interconnect structure according to a second embodiment of the present invention.
Description of the element reference numerals
11 substrate
12 through hole
13 filling the insulating layer
14 first insulating layer
15 second insulating layer
16 bonding pad
17 interconnect structure
21 substrate
22 annular through hole
23 through hole
24 filling the insulating layer
25 air gap
26 first insulating layer
27 communication hole
28 groove
29 pad
30 interconnect structure
31 second insulating layer
Detailed Description
The following description of the embodiments of the present invention is provided for illustrative purposes, and other advantages and effects of the present invention will become apparent to those skilled in the art from the present disclosure.
Please refer to fig. 1 to 9. It should be understood that the structures, ratios, sizes, and the like shown in the drawings and described in the specification are only used for matching with the disclosure of the specification, so as to be understood and read by those skilled in the art, and are not used to limit the conditions under which the present invention can be implemented, so that the present invention has no technical significance, and any structural modification, ratio relationship change, or size adjustment should still fall within the scope of the present invention without affecting the efficacy and the achievable purpose of the present invention. In addition, the terms "upper", "lower", "left", "right", "middle" and "one" used in the present specification are for clarity of description, and are not intended to limit the scope of the present invention, and the relative relationship between the terms and the terms is not to be construed as a scope of the present invention.
Referring to fig. 1, the present invention provides a semiconductor interconnect structure, which includes a substrate 11, wherein a plurality of through holes 12 penetrating through the substrate 11 along the thickness of the substrate 11 are formed in the substrate 11; a first insulating layer 14 and a second insulating layer 15 are formed on the upper and lower surfaces of the substrate respectively; a filling insulating layer 13 filled in the through hole 12; a bonding pad 16 embedded on the surface of the first insulating layer 14 far away from the substrate 11; and an interconnection structure 17 having one end connected to the bottom of the first insulating layer 14 and the other end penetrating through the first insulating layer 14, the filling insulating layer 13 located in the through hole 12 and the second insulating layer 15, and extending to a surface of the second insulating layer 15 away from the substrate 11. However, in the semiconductor interconnect structure shown in fig. 1, since the substrate 11 is a unitary structure, that is, the portion of the substrate 11 directly below the bonding pad 16 is integrally connected to the portion of the substrate 11 at the periphery of the bonding pad 16, there is a high parasitic capacitance between the bonding pad 16 and the interconnect structure 17 and the substrate 11, and the high parasitic capacitance causes the input and output rates of the bonding pad to be low when the bonding pad operates, thereby affecting the overall performance of the device.
Example one
Referring to fig. 2, the present invention further provides a method for manufacturing a semiconductor interconnect structure, which includes the following steps:
1) providing a substrate comprising opposing first and second surfaces;
2) forming an annular through hole and a through hole in the substrate, wherein the annular through hole and the through hole both penetrate through the substrate along the thickness direction of the substrate, and the through hole is positioned on the inner side of the annular through hole;
3) forming filling insulation layers in the annular through hole and the through hole, wherein an air gap is formed in the filling insulation layers in the annular through hole;
4) forming a first insulating layer on the first surface of the substrate;
5) forming a communicating hole in the first insulating layer and the filling insulating layer positioned in the through hole, and forming a groove in the first insulating layer; the communication hole is positioned on the inner side of the annular through hole and at least penetrates through the first insulating layer and the filling insulating layer positioned in the through hole along the thickness direction; the groove defines the position and the shape of a pad to be formed subsequently, is positioned on the inner side of the annular through hole and is communicated with the communication hole, and the depth of the groove is smaller than the thickness of the first insulating layer;
6) and forming the bonding pad in the groove and forming an interconnection structure in the communication hole.
In step 1), referring to step S1 in fig. 2 and fig. 3, a substrate 21 is provided, where the substrate 21 includes a first surface and a second surface opposite to each other.
By way of example, the substrate 21 may include, but is not limited to, a silicon substrate; the thickness of the substrate can be set according to actual needs, and is not limited herein.
As an example, the substrate 21 may be a bare substrate, i.e., the inside and the surface of the substrate 21 are not formed with any device structure before the subsequent steps are performed.
As an example, the following steps are also included after step 1): a second insulating layer 31 is formed on the second surface of the substrate 21, as shown in fig. 3. Specifically, the second insulating layer 31 may be formed on the second surface of the substrate 21 by a physical vapor deposition process, a chemical vapor deposition process, an atomic layer deposition process, a thermal oxidation process, or a bonding process; the second insulating layer 31 may include, but is not limited to, a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or the like.
In step 2), please refer to step S2 in fig. 2 and fig. 4, an annular through hole 22 and a through hole 23 are formed in the substrate 21, the annular through hole 22 and the through hole 23 both penetrate the substrate 21 along the thickness direction of the substrate, and the through hole 23 is located inside the annular through hole 22, that is, the annular through hole 22 is located at the periphery of the through hole 23.
As an example, the number of the through holes 23 may be set according to actual needs, for example, the number of the through holes 23 may be one, two, three or even more, and the like, which is not limited herein, and fig. 4 only illustrates three through holes.
As an example, forming the annular through hole 22 and the through hole 23 in the substrate 21 may include the following steps:
2-1) forming a mask layer (not shown) on the first surface of the substrate 21, wherein the mask layer may include, but is not limited to, a photoresist layer, and may be formed by, but is not limited to, a spin-on process;
2-2) carrying out patterning treatment on the mask layer to form a patterned mask layer (not shown), wherein an opening pattern is formed in the patterned mask layer, and the opening pattern defines the shapes and the positions of the annular through hole 22 and the through hole 23; when the mask layer is a photoresist layer, the mask layer can be subjected to graphical processing by adopting a photoetching process;
2-3) etching the substrate 21 based on the patterned mask layer to form the annular through hole 22 and the through hole 23 in the substrate; specifically, the substrate 21 may be etched by a dry etching process or a wet etching process;
2-4) removing the patterned mask layer.
As an example, the width of the through hole 23 is smaller than the width of the annular through hole 22, so that when the same process is subsequently adopted to fill the filling insulating layers in the through hole 23 and the annular through hole 22, void-free filling can be achieved in the through hole 23, and an air gap can be formed in the filling insulating layer filled in the annular through hole 22 to serve as an air gap.
In step 3), please refer to step S3 in fig. 2 and fig. 5, a filling insulation layer 24 is formed in the annular via 22 and the via 23, and an air gap 25 is formed in the filling insulation layer 24 located in the annular via 22.
For example, the annular via 22 and the via 23 may be filled with the filling insulating layer 24 by using the same process, and specifically, the annular via 22 and the via 23 may be filled with the filling insulating layer 24 by using a physical vapor deposition process, a chemical vapor deposition process, or an atomic layer deposition process. Since the width of the through hole 23 is smaller than the width of the annular through hole 23, for the through hole 23, the filling insulation layer 24 fills the through hole 23, and for the annular through hole 23, the filling insulation layer 24 is formed at the bottom and the sidewall of the annular through hole 23 first, and sealing is achieved when the annular through hole 23 is not filled in the filling process of the filling insulation layer 24; after the filling insulating layer 24 is filled in the annular via hole 22 and the via hole 23, the filling insulating layer 24 in the via hole 23 fills the via hole 23 in a void-free manner, and the air gap 25 is formed in the filling insulating layer 24 in the filling process of the filling insulating layer 24 in the annular via hole 22.
As an example, the shape of the air gap 25 may include a ring shape, specifically, the air gap 25 may surround a circle along the circumferential direction of the annular through hole 22, and the air gap 25 may also be arranged along the circumferential direction of the annular through hole 22 in a segmented and spaced manner; preferably, in this embodiment, the air gap 25 may surround the annular through hole 22.
By way of example, the filling insulating layer 24 may include, but is not limited to, a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or the like.
In step 4), referring to step S4 in fig. 2 and fig. 6, a first insulating layer 26 is formed on the first surface of the substrate 21.
As an example, the first insulating layer 26 may be formed using a physical vapor deposition process, a chemical vapor deposition process, an atomic layer deposition process, a thermal oxidation process, or a bonding process equal to the first surface of the substrate 21; the first insulating layer 26 may include, but is not limited to, a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or the like.
In step 5), referring to step S5 in fig. 2 and fig. 7 to 8, forming a communication hole 27 in the first insulating layer 26 and the filling insulating layer 24 located in the through hole 23, and forming a groove 28 in the first insulating layer 26; the communication hole 27 is located inside the annular through hole 22, and the communication hole 27 penetrates at least the first insulating layer 26 and the filling insulating layer 24 located inside the through hole 23 in the thickness direction; the groove 28 defines the position and shape of a pad to be formed later, the groove 28 is located inside the annular through hole 22, the groove 28 is communicated with the communication hole 27, and the depth of the groove 28 is smaller than the thickness of the first insulating layer 26.
When the second insulating layer 31 is formed on the second surface of the substrate 21, the communication hole 27 also penetrates the second insulating layer 31 along the thickness of the second insulating layer 31.
As an example, forming the communication hole 27 in the first insulating layer 26 and the filling insulating layer 24 located in the through hole 23, and forming the groove 28 in the first insulating layer 26 may include the following steps:
5-1) forming a first mask layer (not shown) on the surface of the first insulating layer 26 away from the substrate 21, where the first mask layer may include, but is not limited to, a photoresist layer, and may be formed by, but is not limited to, a spin-on process;
5-2) carrying out patterning treatment on the first mask layer to form a first patterned mask layer (not shown), wherein a first opening pattern is formed in the first patterned mask layer, and the shape and the position of the communication hole 27 are defined by the first opening pattern; when the first mask layer is a photoresist layer, patterning the first mask layer by adopting a photoetching process;
5-3) etching the first insulating layer 26, the filling insulating layer 24 located in the through hole 23, and the second insulating layer 31 based on the first patterned mask layer to form the communication hole 27;
5-4) removing the first patterned mask layer, wherein the structure obtained in the step is shown in FIG. 7;
5-5) forming a second mask layer (not shown) on the surface of the first insulating layer 26 away from the substrate 21, wherein the second mask layer may include, but is not limited to, a photoresist layer, and may be formed by, but is not limited to, a spin-on process;
5-6) carrying out patterning treatment on the second mask layer to form a second patterned mask layer (not shown), wherein a second opening pattern is formed in the second patterned mask layer, and the shape and the position of the groove 28 are defined by the second opening pattern; when the second mask layer is a photoresist layer, a photoetching process can be adopted to carry out graphical processing on the second mask layer;
5-7) etching the first insulating layer 26 based on the second patterned mask layer to form the groove 28 in the first insulating layer 26;
5-8) removing the second patterned mask layer, the resulting structure of this step is shown in FIG. 8.
As an example, the groove 28 is located inside the annular through hole 22 to ensure that the pad is located inside the annular through hole 22 after the pad is formed in the groove 28, that is, the annular through hole 22 is located at the periphery of the pad.
As an example, the width of the communication hole 27 is smaller than the width of the through hole 23 to ensure that the communication hole 27 is isolated from the substrate 21 by the filling insulating layer 24.
As an example, the number of the communication holes 27 may be one, two, three or more, and preferably, in this embodiment, the number of the communication holes 27 is the same as the number of the through holes 23, and the communication holes 27 are provided in one-to-one correspondence with the through holes 23.
In step 6), referring to step S6 in fig. 2 and fig. 9, the pad 29 is formed in the recess 28, and the interconnect structure 30 is formed in the via 27.
As an example, an electroplating process or a deposition process may be used to form the interconnect structure 30 in the through hole 27 before forming the pad 29 in the recess 28.
By way of example, the material of the pad 29 and the material of the interconnect structure 30 may include, but are not limited to, metals such as copper, aluminum, gold, silver, tin, and the like.
As an example, the number of the interconnect structures 30 may be one, two, three or even more, and preferably, in the present embodiment, the number of the interconnect structures 30 is the same as the number of the through holes 23, and the interconnect structures 30 are arranged in one-to-one correspondence with the through holes 23.
As an example, the surface of the pad 29 away from the substrate 21 may be flush with the surface of the first insulating layer 26 away from the substrate 21; of course, in other examples, the surface of the pad 29 away from the substrate 21 may also be higher or lower than the surface of the first insulating layer 26 away from the substrate 21; it should be noted that when the surface of the pad 29 away from the substrate 21 is lower than the surface of the first insulating layer 26 away from the substrate 21, an opening needs to be formed in the first insulating layer 26 to expose the surface of the pad 29 away from the substrate 21.
According to the preparation method of the semiconductor interconnection structure, the annular through hole 22 is formed in the substrate 21 at the periphery of the bonding pad 29, the air gap 25 is formed in the filling insulating layer 24 in the annular through hole 22, and the air gap 25 can isolate the part of the substrate 21 located right below the bonding pad 29 from the part of the substrate 21 located at the periphery of the bonding pad 29, so that the parasitic capacitance between the bonding pad 29 and the interconnection structure 30 and the substrate 21 is reduced, and the input and output speed of the bonding pad 29 during operation is improved.
Example two
With continuing reference to fig. 9 in conjunction with fig. 2-8, the present invention provides a semiconductor interconnect structure, comprising: a substrate 21, the substrate 21 comprising opposing first and second surfaces; a first insulating layer 26, wherein the first insulating layer 26 is positioned on a first surface of the substrate 21; a pad 29, the pad 29 being located within the first insulating layer 26, the pad 29 having a spacing from the first surface of the substrate 21; an annular through hole 22, the annular through hole 22 being located in the substrate 21, penetrating the substrate 21 in a thickness direction of the substrate 21; a through hole 23, the through hole 23 being located within the substrate 21, the through hole 23 penetrating the substrate 21 in a thickness direction of the substrate 21, and the through hole 23 being located inside the annular through hole 22; a filling insulation layer 24, wherein the filling insulation layer 24 is filled in the annular through hole 22 and the through hole 23; an air gap 25, the air gap 25 being located within the filling insulation layer 24 filled within the annular via hole 22; and an interconnection structure 30, wherein one end of the interconnection structure 30 is connected with the bottom of the pad 29, and the other end of the interconnection structure 30 at least penetrates through the first insulating layer 26 and the filling insulating layer 24 positioned in the through hole 23.
By way of example, the substrate 21 may include, but is not limited to, a silicon substrate; the thickness of the substrate can be set according to actual needs, and is not limited herein.
As an example, the surface of the pad 29 away from the substrate 21 may be flush with the surface of the first insulating layer 26 away from the substrate 21; of course, in other examples, the surface of the pad 29 away from the substrate 21 may also be higher or lower than the surface of the first insulating layer 26 away from the substrate 21; it should be noted that when the surface of the pad 29 away from the substrate 21 is lower than the surface of the first insulating layer 26 away from the substrate 21, an opening needs to be formed in the first insulating layer 26 to expose the surface of the pad 29 away from the substrate 21.
As an example, the annular via 22 may be located at the periphery of the pad 29.
As an example, the first insulating layer 26 may be formed using a physical vapor deposition process, a chemical vapor deposition process, an atomic layer deposition process, a thermal oxidation process, or a bonding process equal to the first surface of the substrate 21; the first insulating layer 26 may include, but is not limited to, a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or the like.
As an example, the width of the through hole 23 is smaller than the width of the annular through hole 22, so that when the same process is subsequently adopted to fill the filling insulating layers in the through hole 23 and the annular through hole 22, void-free filling can be achieved in the through hole 23, and an air gap can be formed in the filling insulating layer filled in the annular through hole 22 to serve as an air gap.
As an example, the number of the through holes 23 may be set according to actual needs, for example, the number of the through holes 23 may be one, two, three or even more, and the like, which is not limited herein, and fig. 4 only illustrates three through holes.
By way of example, the filling insulating layer 24 may include, but is not limited to, a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or the like.
As an example, the shape of the air gap 25 may include a ring shape, specifically, the air gap 25 may surround a circle along the circumferential direction of the annular through hole 22, and the air gap 25 may also be arranged along the circumferential direction of the annular through hole 22 in a segmented and spaced manner; preferably, in this embodiment, the air gap 25 may surround the annular through hole 22.
By way of example, the material of the pad 29 and the material of the interconnect structure 30 may include, but are not limited to, metals such as copper, aluminum, gold, silver, tin, and the like.
As an example, the number of the interconnect structures 30 may be one, two, three or even more, and preferably, in the present embodiment, the number of the interconnect structures 30 is the same as the number of the through holes 23, and the interconnect structures 30 are arranged in one-to-one correspondence with the through holes 23.
Illustratively, the interconnect structure 30 is isolated from the substrate 21 by the filled insulating layer 24 within the via 23.
As an example, the semiconductor interconnect structure further includes a second insulating layer 31, where the second insulating layer 31 is located on the second surface of the substrate 21; the end of the interconnect structure 30 away from the pad 29 also extends through the second insulating layer 31 to the surface of the second insulating layer 31 away from the substrate 21.
In summary, the present invention provides a semiconductor interconnect structure and a method for fabricating the same, the semiconductor interconnect structure comprising: a substrate comprising opposing first and second surfaces; the first insulating layer is positioned on the first surface of the substrate; a pad located within the first insulating layer and having a spacing from the first surface of the substrate; the annular through hole is positioned in the substrate and penetrates through the substrate along the thickness direction of the substrate; the through hole is positioned in the substrate, penetrates through the substrate along the thickness direction of the substrate and is positioned on the inner side of the annular through hole; the filling insulation layer is filled in the annular through hole and the through hole; the air gap is positioned in the filling insulating layer filled in the annular through hole; and one end of the interconnection structure is connected with the bottom of the bonding pad, and the other end of the interconnection structure at least penetrates through the first insulating layer and the filling insulating layer positioned in the through hole. According to the semiconductor interconnection structure, the annular through hole is formed in the substrate on the periphery of the bonding pad, the air gap is formed in the filling insulating layer in the annular through hole, and the part of the substrate, which is positioned right below the bonding pad, can be isolated from the part of the substrate, which is positioned on the periphery of the bonding pad, through the air gap, so that parasitic capacitance among the bonding pad, the interconnection structure and the substrate is reduced, and the input and output speeds of the bonding pad during operation are improved.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (12)
1. A semiconductor interconnect structure, comprising:
a substrate comprising opposing first and second surfaces;
the first insulating layer is positioned on the first surface of the substrate; the second insulating layer is positioned on the second surface of the substrate;
a pad located within the first insulating layer and having a spacing from the first surface of the substrate;
the annular through hole is positioned in the substrate and penetrates through the substrate along the thickness direction of the substrate; the annular through hole is positioned at the periphery of the bonding pad;
the through hole is positioned in the substrate, penetrates through the substrate along the thickness direction of the substrate and is positioned on the inner side of the annular through hole; the width of the through hole is smaller than that of the annular through hole;
the filling insulation layer is filled in the annular through hole and the through hole;
the air gap is positioned in the filling insulating layer filled in the annular through hole;
and one end of the interconnection structure is connected with the bottom of the bonding pad, and the other end of the interconnection structure at least penetrates through the first insulating layer, the filling insulating layer positioned in the through hole and the second insulating layer and extends to the surface of the second insulating layer far away from the substrate.
2. The semiconductor interconnect structure of claim 1, wherein the pad is embedded in the first insulating layer, and a surface of the pad away from the substrate is flush with a surface of the first insulating layer away from the substrate.
3. The semiconductor interconnect structure of claim 1, wherein the number of the vias and the number of the interconnect structures are both multiple, and the vias and the interconnect structures are arranged in a one-to-one correspondence.
4. The semiconductor interconnect structure of claim 1, wherein the interconnect structure is isolated from the substrate by the filled insulating layer located within the via.
5. The semiconductor interconnect structure of claim 1, wherein the shape of the air gap comprises a ring shape.
6. A preparation method of a semiconductor interconnection structure is characterized by comprising the following steps:
providing a substrate comprising opposing first and second surfaces;
forming an annular through hole and a through hole in the substrate, wherein the annular through hole and the through hole both penetrate through the substrate along the thickness direction of the substrate, and the through hole is positioned on the inner side of the annular through hole; the width of the through hole is smaller than that of the annular through hole;
forming filling insulation layers in the annular through hole and the through hole, wherein an air gap is formed in the filling insulation layers in the annular through hole;
forming a first insulating layer on the first surface of the substrate; forming a second insulating layer on the second surface of the substrate;
forming a communicating hole in the first insulating layer and the filling insulating layer positioned in the through hole, and forming a groove in the first insulating layer; the communication hole is positioned on the inner side of the annular through hole and at least penetrates through the first insulating layer, the filling insulating layer positioned in the through hole and the second insulating layer along the thickness direction; the groove defines the position and the shape of a pad to be formed subsequently, is positioned on the inner side of the annular through hole and is communicated with the communication hole, and the depth of the groove is smaller than the thickness of the first insulating layer;
and forming the bonding pad in the groove and forming an interconnection structure in the communication hole.
7. The method for manufacturing a semiconductor interconnection structure according to claim 6, wherein a surface of the pad away from the substrate is flush with a surface of the first insulating layer away from the substrate.
8. The method according to claim 6, wherein the number of the through holes and the number of the interconnection structures are both multiple, and the through holes and the interconnection structures are arranged in a one-to-one correspondence manner.
9. The method according to claim 6, wherein a width of the communicating hole is smaller than a width of the via hole, and the interconnect structure is isolated from the substrate by the filled insulating layer located within the via hole.
10. The method of claim 6, wherein the annular via is located at the periphery of the pad.
11. The method of claim 6, wherein the shape of the air gap comprises a ring shape.
12. The method for manufacturing a semiconductor interconnect structure according to any one of claims 6 to 11, wherein a bottom of the groove communicates with a top of the communicating hole that remains; one end of the interconnection structure, which is far away from the bonding pad, extends to the surface, away from the substrate, of the second insulating layer.
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| US20120013022A1 (en) * | 2010-07-16 | 2012-01-19 | Imec | Method for forming 3d-interconnect structures with airgaps |
| US20120139127A1 (en) * | 2010-12-07 | 2012-06-07 | Imec | Method for forming isolation trenches |
| WO2012089980A1 (en) * | 2010-12-31 | 2012-07-05 | Stmicroelectronics (Crolles 2) Sas | Insulated via hole |
| CN104078414A (en) * | 2013-03-28 | 2014-10-01 | 中芯国际集成电路制造(上海)有限公司 | Silicon through hole and formation method |
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| US20120013022A1 (en) * | 2010-07-16 | 2012-01-19 | Imec | Method for forming 3d-interconnect structures with airgaps |
| US20120139127A1 (en) * | 2010-12-07 | 2012-06-07 | Imec | Method for forming isolation trenches |
| WO2012089980A1 (en) * | 2010-12-31 | 2012-07-05 | Stmicroelectronics (Crolles 2) Sas | Insulated via hole |
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