WO2012089980A1 - Insulated via hole - Google Patents

Insulated via hole Download PDF

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Publication number
WO2012089980A1
WO2012089980A1 PCT/FR2011/053194 FR2011053194W WO2012089980A1 WO 2012089980 A1 WO2012089980 A1 WO 2012089980A1 FR 2011053194 W FR2011053194 W FR 2011053194W WO 2012089980 A1 WO2012089980 A1 WO 2012089980A1
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WO
WIPO (PCT)
Prior art keywords
substrate
trench
integrated circuit
upper face
electronic components
Prior art date
Application number
PCT/FR2011/053194
Other languages
French (fr)
Inventor
Alexis Farcy
Maxime Rousseau
Original Assignee
Stmicroelectronics (Crolles 2) Sas
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Stmicroelectronics (Crolles 2) Sas filed Critical Stmicroelectronics (Crolles 2) Sas
Publication of WO2012089980A1 publication Critical patent/WO2012089980A1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/7682—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing the dielectric comprising air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the present invention relates to integrated circuits and their methods of manufacture. More particularly, the invention relates to integrated circuits with electrical connections or vias substrate SEMICONDUC ⁇ tor. Such through vias are used in particular to transmit signals between stacked integrated circuits, this type of stack being known as 3D integration.
  • FIG. 1 very schematically represents, by way of example, an integrated circuit structure, comprising various electronic components.
  • This structure comprises, on a substrate 1, for example P-type lightly doped silicon (P ⁇ ), a doped P type box region 3 (P).
  • P ⁇ P-type lightly doped silicon
  • P type box region 3 P
  • Channel MOS transistor 2 is shown to include an N ⁇ ing a channel region 5, doped P-type formed in the well region 3, a gate 4, for example polycrystalline silicon flax, located above the channel region And separated therefrom by a gate oxide, a source region 6 and a drain region 7, both heavily doped N (N + ) type.
  • a gate 4 for example polycrystalline silicon flax
  • a strongly doped P-type contacting region 9 (P +), coming into contact with the P-type doped box zone 3.
  • P + strongly doped P-type contacting region 9
  • This region makes it possible to take a ohmic contact in order to measure the electric potential present in the box zone 3, particularly in the vicinity of the channel region 5 of the transistor 2.
  • a via 12 traverses the entire structure, this via being made of a conductive material formed in an opening sheathed with an insulating material 14.
  • the via is formed in a region of the integrated circuit comprising a zone 16, which is commonly used in current integrated circuit manufacturing processes to isolate neighboring transistors and is often referred to by the acronym STI, English Shallow Trench isolation.
  • the structure shown here is in fact a thinned chip at a thickness of the order of 50 to 200 ⁇ m.
  • the via is intended to transmit signals electri c ⁇ between the upper face of the IC chip and the lower face of it. Assuming that the signals transmitted by the via are of the type illustrated in FIG. 2A, namely square-wave signals, these signals induce impulses in the neighboring semiconductor regions by capacitive coupling, for example such as those illustrated in FIG. 2B. It is possible in practice to determine the influence of the signals of the via on the box 3 of the transistor by raising the voltage v BODY ⁇
  • These voltage pulses are likely to disturb the operation of components arranged in the vicinity of the via.
  • one of these components is a MOS-type field effect transistor, its threshold voltage or saturation current may be modified; and if such a transistor is part of a memory point, the stored state can be changed.
  • the through vias may have rela ⁇ tively large diameters between 5 and 100 ym and may be partially or completely filled with metal.
  • the metal mass constituting the via for example copper, is subjected, when the chip heats up or when large currents circulate in the via, to a thermal expansion which is not the same as that of the surrounding silicon and this may result in the appearance of mechanical stresses in the components located next to the via. It is well known that such mechanical stresses, by changing the carrier mobility in the channel region, interfere with the operation of chilled ⁇ twisted, and in particular by altering their threshold voltages and switching speed.
  • FIGS. 3 to 6 Various protective structures have been envisaged to reduce the influence of the through vias on the neighboring components, as illustrated in FIGS. 3 to 6.
  • the transistor 2 has been shown in a strongly schematic manner and is framed by an insulating region 20.
  • the via via is separated from the transis ⁇ tor by a guard distance d.
  • the via via is surrounded by a shallow insulating region 24 formed at the same time as the insulating regions 20 (STI) framing the various transistors of the circuit. Interposing such a dielectric region between the transistor and the upper part of the via via only partially reduces the capacitive coupling between the via and the channel region of the transistor, since the electrostatic field continues to propagate to the channel region. passing through the semiconductor substrate, under insulating regions (STI).
  • STI insulating regions
  • FIG 5 there is illustrated the insertion of heavily doped boxes 26 flanking the via via.
  • These boxes 26 are of the same type of conductivity as the semiconductor region in which the transistor is formed and are for example connected to ground to modify the lines of the electrostatic field induced by the via and thus reduce the disturbances induced on the channel of the transistor. transistor.
  • This solution gives better results than the previous ones but is not yet completely effective and in particular, if it reduces the influence of electrostatic problems, it does not solve the problem of mechanical stresses.
  • the thickness of the insulator 14 surrounding the via via 12 has been greatly increased, to interpose a thick dielectric zone between the adjacent electronic components and the via, over the entire height of the latter.
  • This solution is more efficient than the previous ones from the point of view of the reduction of electrostatic disturbances, but does not solve the problem of mechanical stresses.
  • this solution is difficult to implement in practice because it requires the use, during the manufacture of integrated circuits, a step of depositing a thick dielectric layer on an entire face of the wafer. integrated circuits. Such layers are in general highly mechanically stressed and induce a significant curvature of the platelets after deposition, which makes them fragile and makes them difficult to handle.
  • An object of embodiments of the present inven ⁇ is to provide a protective structure providing electrical isolation and mechanics of a through via.
  • Another object of embodiments of the present invention is to provide a method of manufacturing such a protective structure which involves only manufacturing steps already provided in the manufacture of a conventional integrated circuit.
  • Another object of embodiments of the present invention is to provide a protection structure whose manufacturing is compatible with the various modes of manufacturing through vias.
  • An embodiment of the present invention provides an integrated circuit comprising the side of its face EXCEED active electronic components and at least one via through the substrate, wherein the via is separated from the electronic compo ⁇ adjacent active sants by a trench vacuum extending in the substrate at least 50% of its height from said upper face, and wherein the via is separated from the empty trench by a portion of the substrate.
  • the empty trench passes through the substrate over its entire height.
  • the end of the via located on the side of the upper face is in the plane of the substrate and the via is formed of a material comprising polycrystalline silicon.
  • the end of the via located on the side of the upper face is in contact with the lower level of metallization and the via is in a material selected from the group comprising copper and
  • the section of the trench in a plane parallel to the substrate, is formed of a single element centered around said via, of a shape chosen from the circle, the square, the rectangle, the hexagon and octagon.
  • the section of the trench in a plane parallel to the substrate, is formed of a plurality of elements centered around said via, of a shape chosen from the disk and the straight strip.
  • An embodiment of the present invention pre ⁇ shows a method of making an integrated circuit comprising, on the upper face of the substrate, active electronic components and above said components, a metallization levels stack comprising at least one first insulating layer in contact with said components and at least one first level of metallization, and a via traversing the substrate, isolated from the active electronic components by an empty trench, comprising the following steps:
  • the via and the empty trench are formed in the upper face of the substrate before forming the active electronic components and the method comprises a step of thinning the substrate by its underside so as to discover the lower end of the via without discovering the lower end of the trench.
  • the via and the empty trench are formed in the upper face of the substrate after the formation of the active electronic components and the first insulating layer, and the method comprises a step of thinning the substrate by its lower face so as to discover the lower end of the via without discovering the lower end of the trench.
  • the via and the empty trench are formed in the underside of the substrate after the following steps:
  • Figure 1 previously described, is a sectional view of a portion of an integrated circuit comprising a via via and a transistor;
  • FIGS. 2A and 2B previously described, are timing diagrams illustrating the electrical disturbances brought about by the presence of a via via
  • FIGS. 3 to 6, previously described, illustrate various simple modes of protecting components of an integrated circuit with respect to the disturbances introduced by a via via;
  • Fig. 7 is a sectional view schematically showing an example of a protective structure
  • Figures 8A, 8B and 8C are top views illustrating a first type of protective structures
  • Figure 9 is a top view illustrating another method of protection vias through
  • FIGS. 10A to 10F illustrate a first method of manufacturing a protective structure
  • Figs. 11A to 11F illustrate a second method of manufacturing a protection structure
  • FIGS. 12A to 12E illustrate a third method of manufacturing a protective structure.
  • FIG. 7 is a sectional view schematically illustrating the general appearance of a protective structure, this protective structure being intended to provide the protection components disposed in the vicinity of a via relative to various types of electrical and mechanical disturbances Suspected ⁇ patible to be produced by the via during operation of the integrated circuit.
  • a via 30 surrounded by an insulating region 32 passes through the semiconductor substrate 34 of an integrated circuit chip.
  • This via is surrounded by a trench 36 which remains empty (filled with a gas and not a solid material), the upper part of this trench being occluded by a plug 38.
  • the trench 36 being made slightly away from the via 30, it is separated from the latter by a portion 35 of the semiconductor substrate 34.
  • the Profon ⁇ deur is, according to the proposed embodiments, equal to the thickness of the substrate of the chip, or slightly lower than this. Indeed, such an empty cavity (or filled with a residual gas under low pressure) represents the ideal dielectric material and provides excellent electrostatic insulation with a small footprint. Mechanical problems are also solved since any stress resulting from a thermal expansion of the via is absorbed at the cavity constituted by the empty trench.
  • Figs. 8A, 8B and 8C are top views showing a first type of trench shape in which the trench surrounds the via. Very schematically shown in these figures, a transistor neighbor of the via by the reference 40.
  • FIGS. 8A and 8B the section of the trench 36 in a plane orthogonal to the direction of the via completely surrounds the via. This section is circular in Figure 8A and square in Figure 8B. Either of these forms will be chosen based on design requirements.
  • FIG. 8C the trench 36 of FIG. 8A is shown not to be continuous but constituted by a succession of holes 42 very close to one another. If these holes are sufficiently close, the mechanical problems will be very attenuated, as well as the electrical problems.
  • Figure 9 is a top view illustrating a second type of trench form 36 adapted to the case where through vias 44 and 45 are substantially aligned and do not include them active components. In this case, it will be possible to provide only two trenches parallel to the alignment of the vias, on either side of this alignment, to protect components 40 adjacent to the influence of these vias.
  • the vias are manufactured before the production of components on a semiconductor substrate.
  • the vias are made from the upper face of an integrated circuit wafer in which components have already been formed and a first connection level intended to ensure contacts with portions of these components.
  • the vias are made while the electronic components and metallization levels coating them have already been completely formed.
  • FIGS. 10A-10F illustrate successive steps of a first embodiment in which the vias are formed prior to any embodiment of components in a semiconductor substrate.
  • FIG. 10A one starts from a semiconductor wafer 101 on which a mask 103 is formed with first openings 105 at the locations where it is desired to form vias and second openings 106 at the locations where it is desired to form a surrounding trench. or more trenches, as described with reference to FIGS. 8A-8C and 9.
  • the mask 103 was used to form openings 110 and 111 in the substrate.
  • the opening 110 has the depth and diameter that we want to have for the via. Note that by conventional methods of anisotropic etching, etching performed through an opening of smaller lateral dimension will have a lower depth ⁇ than the same etching performed simultaneously through an opening having a larger lateral dimension. In practice, it is noted that, if the side trenches have a lateral dimension which is at least three times smaller than that of the via, their depth will be 5 to 10% lower.
  • an insulating layer 113 is deposited on the upper face of the assembly of the structure, after removal of the resin layer 103.
  • the insulating coating 32 of the via and the insulating coatings 115 are thus formed on the walls of the trenches.
  • a deposition may for example be carried out according to a chemical vapor deposition process, preferably in a sub-atmospheric variant, more suitable for through vias of considerable depth. Both of these processes are well known under the respective English names of Chemical Vapor Deposition (CVD) and Sub-Atmospheric Chemical Vapor Deposition (SACVD).
  • CVD Chemical Vapor Deposition
  • SACVD Sub-Atmospheric Chemical Vapor Deposition
  • the deposition of the insulating layer 113 leads to an obstruction of the upper part of the trenches, forming plugs 38 such that the top of the cavity 36 is located under the plane of the front face 102 of the substrate 101.
  • those skilled in the art will choose a method of depositing the insulation which promotes the formation of such plugs and the maintenance of a void space in the trenches. For this, it may choose, for the first part of the deposit, operating conditions leading to a poorly compliant deposit, thus promoting the obstruction of the upper part of the trenches, then, as soon as the trenches are closed, operating conditions leading to a deposit as compliant as possible, in order to finish upholstering the walls of the via with a sufficient thickness of insulation, over the entire height of the via.
  • the vacuum 36 will be filled at low pressure with the gas mixture used during the deposition of the insulator, commonly for a silicon oxide (SiO 2) deposit. ), a mixture of argon, oxygen and a silicon precursor such as silane (S1H4) or tetra-Ethyl-Ortho-Silicate (TEOS).
  • SiO 2 silicon oxide
  • SiO 3 silicon oxide
  • a silicon precursor such as silane (S1H4) or tetra-Ethyl-Ortho-Silicate (TEOS).
  • a chemical-mechanical polishing was carried out in order to eliminate the layers 119 and 113 from the upper surface of the structure.
  • a via 30 is thus obtained, the upper face of which is in the plane of the upper side of the substrate 101, and empty trenches 36 whose upper part is obstructed by a plug 38 whose upper face is also in the plane of the upper face of the substrate 101.
  • components 2 in the upper surface of the substrate 101 are formed successively, contacts 120 in an insulating layer 121, and successive levels of metallization 122, 123, 124, 125 connected when it is necessary by vias 127 through an intermediate insulating layer.
  • contacts 120 are made with portions of semiconductor components
  • contacts 130 are made with the upper face of the via 30 to connect it via a metallization level 132.
  • the details of the connections between metallization levels n is not illustrated in Figure 10F.
  • 11A-11F illustrate steps successi ve ⁇ a second embodiment in which the vias are formed after the electronic components were formed on the side of the front face of the semiconductor wafer and that contacts were trained to elements to be connected to the integrated circuit through a first insulating layer.
  • FIG. 11A illustrates a semiconductor wafer 101 on which electronic components 2 have been made, selected portions of which are connected to contacts 120 passing through an insulating layer 121.
  • an insulating region has been formed in the upper face of the substrate 101. 200 at locations where you want to form a via and trenches protection.
  • the insulating region 200 is formed at the same time as the insulating regions (STI) generally surrounding each electronic component.
  • a mask 202 has been deposited on the structure in which a main opening 205 has been formed at the location where it is desired to form a via and openings 206 at the locations where it is desired to form the trench or trenches.
  • the mask 202 was used to successively etch the insulating layer 121, the insulating region 200 and the substrate 101, and to form openings 210 and 211.
  • This set of via openings and trenches will have the same characteristics of penetration into the substrate as the set of openings 110 and 111 described in connection with Figure 10B.
  • a diffusion barrier layer 217 has been deposited on the upper face of the entire structure.
  • the walls of the via are thus killed ⁇ dream of a diffusion barrier layer 37 deposited on the insulating layer 32. It is then proceeded to deposit on the upper face of the whole of a thick layer 219 structure in an electrically conductive material. This material completely fills the aperture 210 of the via.
  • the diffusion barrier layer 217 may for example be a stack of tantalum nitride (TaN) and tantalum deposited by a spray deposition process known as Physical Vapor Deposition (PVD).
  • the conductive thick film 219 may for example be copper (Cu) deposited as an electro ⁇ chemical process. If this type of method is used, the prior art will deposit on the barrier layer 217 a conductive layer of hooked, not shown in the figure, for example a layer of copper deposited by sputtering (PVD).
  • FIG. 11E the structure is shown after carrying out the same steps as those previously described in relation with FIG. 10E, bearing the same references or the same references incremented by a hundred. This leads to a structure whose upper surface corresponds to the upper surface of the insulating layer 121. At this upper surface, there are the plugs 38 blocking the recesses 36 of the trench or trenches and the upper surface of the conductive via 30 .
  • FIG. 11F shows the structure after carrying out the same steps as those previously described in connection with FIG. 10F, in order to achieve the successive levels of metallization then the leveling of the rear face of the semiconductor wafer to make apparent the underside 240 of the via 30 and make it a through via.
  • FIG. 12A to 12E illustrate steps successi ve ⁇ a third embodiment of a via and trench formation process. This time, the vias are formed after the components and all metallization levels have been formed on the upper surface of the wafer.
  • the back side of the thinned wafer is coated with a masking layer 303 in which openings 305 for the via and 306 for the trenches are formed.
  • anisotropic etching is carried out first of the silicon 101 of the substrate and then of the silicon oxide constituting the layers 200 and 121. It has been shown that the opening of the via reaches the metal layer 132 while those of the trenches stop a little before. In fact, this is irrelevant in this embodiment and etching could be continued until the trenches also reach the metal layer 132.
  • an insulation deposit was made in a manner similar to that described in FIG. 11C, but this time starting from the rear face of the wafer.
  • Figure 12D resumes similar steps to those described in relation to Figure 11D, but this time also from the back side of the wafer.
  • Figure 12E shows the structure after removal of the layers deposited on the back face.

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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
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Abstract

The invention relates to an integrated circuit including, on the upper surface thereof, active electronic components and at least one via (30) passing through the substrate (34), wherein the via is separated from the adjacent active electronic components by an empty trench (36) extending into the substrate over at least 50% of the height thereof starting from said upper surface.

Description

VIA TRAVERSANT ISOLE  VIA INSULATED CROSSING
Domaine de 1 ' invention Field of the invention
La présente invention concerne les circuits intégrés et leurs procédés de fabrication. Plus particulièrement, l'invention concerne les circuits intégrés présentant des liaisons électriques ou vias traversants le substrat semiconduc¬ teur. De tels vias traversants sont notamment utilisés pour transmettre des signaux entre circuits intégrés empilés, ce type d'empilement étant connu sous le vocable d'intégration 3D. The present invention relates to integrated circuits and their methods of manufacture. More particularly, the invention relates to integrated circuits with electrical connections or vias substrate SEMICONDUC ¬ tor. Such through vias are used in particular to transmit signals between stacked integrated circuits, this type of stack being known as 3D integration.
Exposé de 1 ' art antérieur Presentation of the prior art
Une voie connue de longue date pour augmenter, à en¬ combrement égal, les performances et la complexité des circuits intégrés est de miniaturiser les composants électroniques élémentaires (transistors) . One known way to increase long to ¬ equal space requirement, performance and complexity of integrated circuits is to miniaturize the basic electronic components (transistors).
Une autre voie, plus récente, consiste à réaliser des composants actifs et/ou passifs sur les deux faces d'une même puce et/ou à empiler verticalement de telles puces. Cela néces¬ site dans les deux cas de prévoir la réalisation de vias traver¬ sants le substrat des puces, liaisons bien connues sous le vocable anglo-saxon de Through Silicon Vias (TSV) . Another, more recent way is to make active and / or passive components on both sides of the same chip and / or stack vertically such chips. This neces ¬ site in both cases to provide for the realization of vias traver ¬ sants the chip substrate, well known bonds in the Anglo-Saxon term of Through Silicon Vias (TSV).
Cependant, l'intégration de tels vias traversants soulève des difficultés. En particulier, la présence de tels vias traversants et des signaux électriques qui les parcourent peut perturber le fonctionnement des composants électroniques voisins . However, the integration of such vias traverses raises difficulties. In particular, the presence of such through vias and electrical signals that run through them may interfere with the operation of neighboring electronic components.
La figure 1 représente de façon très schématique et à titre d'exemple une structure de circuit intégré, comprenant divers composants électroniques . Cette structure comprend, sur un substrat 1, par exemple en silicium faiblement dopé de type P (P~) , une zone de caisson 3 dopée de type P (P) . FIG. 1 very schematically represents, by way of example, an integrated circuit structure, comprising various electronic components. This structure comprises, on a substrate 1, for example P-type lightly doped silicon (P ~ ), a doped P type box region 3 (P).
On a représenté un transistor MOS 2 à canal N compre¬ nant une région de canal 5, dopée de type P formée dans la zone de caisson 3, une grille 4 par exemple en silicium polycristal- lin, située au dessus de la région de canal 5 et, séparée de celle-ci par un oxyde de grille, une région de source 6 et une région de drain 7, toutes deux fortement dopées de type N (N+) . Channel MOS transistor 2 is shown to include an N ¬ ing a channel region 5, doped P-type formed in the well region 3, a gate 4, for example polycrystalline silicon flax, located above the channel region And separated therefrom by a gate oxide, a source region 6 and a drain region 7, both heavily doped N (N + ) type.
En outre, à côté du transistor, à droite dans la figure, est formée une région de prise de contact 9 fortement dopée de type P (P+) , venant contacter la zone de caisson 3 dopée de type P. Cette région permet de prendre un contact ohmique afin de mesurer le potentiel électrique présent dans la zone de caisson 3, notamment au voisinage de la région de canal 5 du transistor 2.  In addition, next to the transistor, on the right in the figure, is formed a strongly doped P-type contacting region 9 (P +), coming into contact with the P-type doped box zone 3. This region makes it possible to take a ohmic contact in order to measure the electric potential present in the box zone 3, particularly in the vicinity of the channel region 5 of the transistor 2.
Un via 12 traverse toute la structure, ce via étant constitué d'un matériau conducteur formé dans une ouverture gainée d'un matériau isolant 14. De préférence, comme cela est représenté, le via est formé dans une région du circuit intégré comprenant une zone isolante 16, qui est couramment utilisée dans les processus actuels de fabrication de circuits intégrés pour isoler les transistors voisins et qui est souvent désignée par le sigle STI, de l'anglais Shallow Trench isolation. La structure représentée ici est en fait une puce amincie à une épaisseur de l'ordre de 50 à 200 um.  A via 12 traverses the entire structure, this via being made of a conductive material formed in an opening sheathed with an insulating material 14. Preferably, as shown, the via is formed in a region of the integrated circuit comprising a zone 16, which is commonly used in current integrated circuit manufacturing processes to isolate neighboring transistors and is often referred to by the acronym STI, English Shallow Trench isolation. The structure shown here is in fact a thinned chip at a thickness of the order of 50 to 200 μm.
Des contacts Vg, Vg, Vp, VgQDY et VVIA sont respecti¬ vement assurés avec la région de source 6, la grille 4, la région de drain 7, et la région de prise de contact 9 et le via 12. Vg contacts, Vg, Vp, and V VIA VgQDY its ¬ t respecti vely provided with the source region 6, the gate 4, the drain region 7, and the first contact region 9 and the via 12.
Le via est destiné à transmettre des signaux électri¬ ques entre la face supérieure de la puce de circuit intégré et la face inférieure de celle-ci. En supposant que les signaux transmis par le via sont du type illustré en figure 2A, à savoir des signaux en créneaux, ces signaux induisent dans les régions semiconductrices voisines, par couplage capacitif, des impul- sions, par exemple telles que celles illustrées en figure 2B. Il est possible en pratique de déterminer l'influence des signaux du via sur le caisson 3 du transistor en relevant la tension vBODY · The via is intended to transmit signals electri c ¬ between the upper face of the IC chip and the lower face of it. Assuming that the signals transmitted by the via are of the type illustrated in FIG. 2A, namely square-wave signals, these signals induce impulses in the neighboring semiconductor regions by capacitive coupling, for example such as those illustrated in FIG. 2B. It is possible in practice to determine the influence of the signals of the via on the box 3 of the transistor by raising the voltage v BODY ·
Ces impulsions de tension sont susceptibles de pertur- ber le fonctionnement de composants disposés au voisinage du via. Par exemple, si l'un de ces composants est un transistor à effet de champ de type MOS, sa tension de seuil ou son courant de saturation pourra être modifié ; et si un tel transistor fait partie d'un point mémoire, l'état mémorisé peut être modifié.  These voltage pulses are likely to disturb the operation of components arranged in the vicinity of the via. For example, if one of these components is a MOS-type field effect transistor, its threshold voltage or saturation current may be modified; and if such a transistor is part of a memory point, the stored state can be changed.
Les vias traversants peuvent avoir des diamètres rela¬ tivement importants compris entre 5 et 100 ym et peuvent être partiellement ou complètement remplis de métal. La masse de métal constituant le via, par exemple du cuivre, est soumise, quand la puce s'échauffe ou quand des courants importants circulent dans le via, à une dilatation thermique qui n'est pas la même que celle du silicium environnant et cela peut entraîner 1 ' apparition de contraintes mécaniques dans les composants situés à côté du via. Il est bien connu que de telles contraintes mécaniques, en modifiant la mobilité des porteurs dans la zone de canal, perturbent le fonctionnement des transis¬ tors, et notamment en modifiant leur tension de seuil et leur vitesse de commutation. The through vias may have rela ¬ tively large diameters between 5 and 100 ym and may be partially or completely filled with metal. The metal mass constituting the via, for example copper, is subjected, when the chip heats up or when large currents circulate in the via, to a thermal expansion which is not the same as that of the surrounding silicon and this may result in the appearance of mechanical stresses in the components located next to the via. It is well known that such mechanical stresses, by changing the carrier mobility in the channel region, interfere with the operation of chilled ¬ twisted, and in particular by altering their threshold voltages and switching speed.
Diverses structures de protection ont été envisagées pour réduire 1 ' influence des vias traversants sur les composants voisins, comme cela est illustré dans les figures 3 à 6. Dans ces figures, le transistor 2 a été représenté de façon fortement schématique et est encadré d'une région isolante 20.  Various protective structures have been envisaged to reduce the influence of the through vias on the neighboring components, as illustrated in FIGS. 3 to 6. In these figures, the transistor 2 has been shown in a strongly schematic manner and is framed by an insulating region 20.
En figure 3, le via traversant est éloigné du transis¬ tor d'une distance de garde d. Ceci réduit l'influence des perturbations électrostatiques générées par le via, symbolisées par les flèches 22. Ceci remédie aussi au problème des perturba- tions mécaniques, mais au prix d'une augmentation sensible de la taille du circuit. En effet, en pratique, pour des circuits intégrés d'architecture CMOS réalisés par exemple en technologie 65 nm, et pour des vias traversants de 3 à 10 p de diamètre, la distance de garde d peut atteindre 5 à 15 ym. In FIG. 3, the via via is separated from the transis ¬ tor by a guard distance d. This reduces the influence of the electrostatic disturbances generated by the via, symbolized by the arrows 22. This also remedies the problem of disturbances. tions, but at the cost of a significant increase in the size of the circuit. Indeed, in practice, for CMOS architecture integrated circuits made for example in 65 nm technology, and for through vias of 3 to 10 p diameter, the guard distance d can reach 5 to 15 ym.
En figure 4, le via traversant est entouré d'une région isolante peu profonde 24 formée en même temps que les régions isolantes 20 (STI) encadrant les divers transistors du circuit. Interposer une telle région diélectrique entre le tran- sistor et la partie supérieure du via traversant ne réduit que partiellement le couplage capacitif entre le via et la région de canal du transistor, car le champ électrostatique continue de se propager jusqu'à la région de canal en passant par le substrat semiconducteur, sous les régions isolantes 20 (STI) .  In FIG. 4, the via via is surrounded by a shallow insulating region 24 formed at the same time as the insulating regions 20 (STI) framing the various transistors of the circuit. Interposing such a dielectric region between the transistor and the upper part of the via via only partially reduces the capacitive coupling between the via and the channel region of the transistor, since the electrostatic field continues to propagate to the channel region. passing through the semiconductor substrate, under insulating regions (STI).
En figure 5, on a illustré l'insertion de caissons 26 fortement dopés encadrant le via traversant. Ces caissons 26 sont du même type de conductivité que la région semiconductrice dans laquelle est formé le transistor et sont par exemple connectés à la masse pour modifier les lignes du champ électro- statique induit par le via et diminuer ainsi les perturbations induites sur le canal du transistor. Cette solution donne de meilleurs résultats que les précédentes mais n'est pas encore totalement efficace et notamment, si elle réduit l'influence des problèmes électrostatiques, elle ne résout pas le problème des contraintes mécaniques.  In Figure 5, there is illustrated the insertion of heavily doped boxes 26 flanking the via via. These boxes 26 are of the same type of conductivity as the semiconductor region in which the transistor is formed and are for example connected to ground to modify the lines of the electrostatic field induced by the via and thus reduce the disturbances induced on the channel of the transistor. transistor. This solution gives better results than the previous ones but is not yet completely effective and in particular, if it reduces the influence of electrostatic problems, it does not solve the problem of mechanical stresses.
En figure 6, l'épaisseur de l'isolant 14 entourant le via traversant 12 a été fortement augmentée, pour interposer une zone diélectrique épaisse entre les composants électroniques adjacents et le via, sur toute la hauteur de ce dernier. Cette solution est plus efficace que les précédentes du point de vue de la réduction des perturbations électrostatiques, mais ne résout pas le problème des contraintes mécaniques. De plus, cette solution est difficile à mettre en oeuvre en pratique car elle nécessite de recourir, au cours de la fabrication des circuits intégrés, à une étape de dépôt d'une couche diélectrique épaisse sur toute une face de la plaquette de circuits intégrés. De telles couches sont en général fortement mécaniquement stressées et induisent une courbure importante des plaquettes après dépôt, qui les fragilise et les rend difficiles à manipuler. In FIG. 6, the thickness of the insulator 14 surrounding the via via 12 has been greatly increased, to interpose a thick dielectric zone between the adjacent electronic components and the via, over the entire height of the latter. This solution is more efficient than the previous ones from the point of view of the reduction of electrostatic disturbances, but does not solve the problem of mechanical stresses. In addition, this solution is difficult to implement in practice because it requires the use, during the manufacture of integrated circuits, a step of depositing a thick dielectric layer on an entire face of the wafer. integrated circuits. Such layers are in general highly mechanically stressed and induce a significant curvature of the platelets after deposition, which makes them fragile and makes them difficult to handle.
Toutes ces structures de protection permettent de réduire les problèmes posés par la présence de vias traversants mais ne les suppriment pas. Si la distance entre le via et les composants immédiatement voisins est grande, on réduit l'in¬ fluence des perturbations mécaniques ainsi que des perturbations électriques, mais au prix d'une augmentation inacceptable de la taille du circuit intégré, surtout si celui-ci comporte un grand nombre de vias traversants. Quant aux solutions illustrées en figures 4 à 6, si elles conservent un encombrement acceptable, elles ne remédient que partiellement au problème des perturbations électriques, et que très mal au problème des perturbations mécaniques liées aux dilatations thermiques. All these protective structures reduce the problems posed by the presence of through vias but do not remove them. If the distance between the via and immediately adjacent components is large, reducing the in ¬ fluence mechanical disturbances and electrical disturbances, but at the cost of an unacceptable increase in the size of the integrated circuit, especially if it has a large number of through vias. As for the solutions illustrated in Figures 4 to 6, if they retain an acceptable size, they only partially remedy the problem of electrical disturbances, and very poorly to the problem of mechanical disturbances related to thermal expansion.
En outre, certaines de ces solutions, notamment celles décrites en relation avec la figure 6 entraînent la nécessité de prévoir des étapes de fabrication particulières qui compliquent la fabrication du circuit intégré.  In addition, some of these solutions, particularly those described in connection with FIG. 6, cause the need to provide particular manufacturing steps that complicate the manufacturing of the integrated circuit.
Ainsi, il existe un besoin de prévoir des structures de protection efficaces, peu encombrantes et facilement réalisa¬ bles pour réduire les influences perturbatrices de vias traver¬ sants dans des circuits intégrés. Thus, there is a need to provide effective protection structures, space-saving and easily realized ¬ ble to reduce disturbing influences vias traver ¬ sants in integrated circuits.
Résumé summary
Un objet de modes de réalisation de la présente inven¬ tion est de prévoir une structure de protection assurant l'isolement électrique et mécanique d'un via traversant. An object of embodiments of the present inven ¬ is to provide a protective structure providing electrical isolation and mechanics of a through via.
Un autre objet de modes de réalisation de la présente invention est de prévoir un procédé de fabrication d'une telle structure de protection qui n'implique que des étapes de fabrication déjà prévues dans la fabrication d'un circuit intégré classique.  Another object of embodiments of the present invention is to provide a method of manufacturing such a protective structure which involves only manufacturing steps already provided in the manufacture of a conventional integrated circuit.
Un autre objet de modes de réalisation de la présente invention est de prévoir une structure de protection dont la fabrication soit compatible avec les divers modes de fabrication de vias traversants. Another object of embodiments of the present invention is to provide a protection structure whose manufacturing is compatible with the various modes of manufacturing through vias.
Un mode de réalisation de la présente invention prévoit un circuit intégré comprenant du côté de sa face supé- rieure des composants électroniques actifs et au moins un via traversant le substrat, dans lequel le via est séparé des compo¬ sants électroniques actifs adjacents par une tranchée vide s' étendant dans le substrat sur au moins 50 % de sa hauteur à partir de ladite face supérieure, et dans lequel le via est séparé de la tranchée vide par une portion du substrat. An embodiment of the present invention provides an integrated circuit comprising the side of its face EXCEED active electronic components and at least one via through the substrate, wherein the via is separated from the electronic compo ¬ adjacent active sants by a trench vacuum extending in the substrate at least 50% of its height from said upper face, and wherein the via is separated from the empty trench by a portion of the substrate.
Selon un mode de réalisation de la présente invention, la tranchée vide traverse le substrat sur toute sa hauteur.  According to an embodiment of the present invention, the empty trench passes through the substrate over its entire height.
Selon un mode de réalisation de la présente invention, l'extrémité du via située du côté de la face supérieure se trouve dans le plan du substrat et le via est formé en un matériau comprenant du silicium polycristallin.  According to one embodiment of the present invention, the end of the via located on the side of the upper face is in the plane of the substrate and the via is formed of a material comprising polycrystalline silicon.
Selon un mode de réalisation de la présente invention, l'extrémité du via située du côté de la face supérieure est en contact avec le niveau de métallisation inférieur et le via est en un matériau choisi dans le groupe comprenant le cuivre et According to an embodiment of the present invention, the end of the via located on the side of the upper face is in contact with the lower level of metallization and the via is in a material selected from the group comprising copper and
1' aluminium. 1 aluminum.
Selon un mode de réalisation de la présente invention, la section de la tranchée, selon un plan parallèle au substrat, est formée d'un unique élément centré autour dudit via, de forme choisie parmi le cercle, le carré, le rectangle, l'hexagone et 1' octogone .  According to an embodiment of the present invention, the section of the trench, in a plane parallel to the substrate, is formed of a single element centered around said via, of a shape chosen from the circle, the square, the rectangle, the hexagon and octagon.
Selon un mode de réalisation de la présente invention, la section de la tranchée, selon un plan parallèle au substrat, est formée d'une pluralité d'éléments centrés autour dudit via, de forme choisie parmi le disque et la bande rectiligne.  According to one embodiment of the present invention, the section of the trench, in a plane parallel to the substrate, is formed of a plurality of elements centered around said via, of a shape chosen from the disk and the straight strip.
Un mode de réalisation de la présente invention pré¬ voit un procédé de réalisation d'un circuit intégré comprenant, sur la face supérieure du substrat, des composants électroniques actifs et au dessus desdits composants, un empilement de niveaux de métallisation comprenant au moins une première couche isolante en contact avec lesdits composants et au moins un premier niveau de métallisation, et un via traversant le substrat, isolé des composants électroniques actifs par une tranchée vide, comprenant les étapes suivantes : An embodiment of the present invention pre ¬ shows a method of making an integrated circuit comprising, on the upper face of the substrate, active electronic components and above said components, a metallization levels stack comprising at least one first insulating layer in contact with said components and at least one first level of metallization, and a via traversing the substrate, isolated from the active electronic components by an empty trench, comprising the following steps:
graver dans le substrat, à l'emplacement du via, un trou d'une première largeur et, autour de ce trou, une tranchée d'une deuxième largeur, inférieure à la première largeur ; et déposer une couche de matériau électriquement isolant de sorte que les parois du trou sont revêtues d'une couche isolante et que la tranchée est refermée et contient une cavité vide ; et  etching in the substrate, at the location of the via, a hole of a first width and, around this hole, a trench of a second width, smaller than the first width; and depositing a layer of electrically insulating material so that the walls of the hole are coated with an insulating layer and the trench is closed and contains an empty cavity; and
remplir le trou d'un matériau électriquement conduc¬ teur. filling the hole with an electrically conduc tor ¬ material.
Selon un mode de réalisation de la présente invention, le via et la tranchée vide sont formés dans la face supérieure du substrat avant la formation des composants électroniques actifs et le procédé comprend une étape d'amincissement du substrat par sa face inférieure de manière à découvrir l'extrémité inférieure du via sans découvrir l'extrémité inférieure de la tranchée.  According to one embodiment of the present invention, the via and the empty trench are formed in the upper face of the substrate before forming the active electronic components and the method comprises a step of thinning the substrate by its underside so as to discover the lower end of the via without discovering the lower end of the trench.
Selon un mode de réalisation de la présente invention, le via et la tranchée vide sont formés dans la face supérieure du substrat après la formation des composants électroniques actifs et de la première couche isolante, et le procédé comprend une étape d'amincissement du substrat par sa face inférieure de manière à découvrir l'extrémité inférieure du via sans découvrir l'extrémité inférieure de la tranchée.  According to one embodiment of the present invention, the via and the empty trench are formed in the upper face of the substrate after the formation of the active electronic components and the first insulating layer, and the method comprises a step of thinning the substrate by its lower face so as to discover the lower end of the via without discovering the lower end of the trench.
Selon un mode de réalisation de la présente invention, le via et la tranchée vide sont formés dans la face inférieure du substrat après les étapes suivantes :  According to one embodiment of the present invention, the via and the empty trench are formed in the underside of the substrate after the following steps:
former les composants électroniques actifs ; former l'empilement de niveaux de métallisation ; et amincir le substrat par sa face inférieure ; le trou et la tranchée traversant le substrat et le trou traversant ladite première couche isolante et débouchant sur une portion dudit au moins un premier niveau de métallisation. Brève description des dessins form active electronic components; forming the stack of metallization levels; and thin the substrate by its underside; the hole and the trench passing through the substrate and the hole passing through said first insulating layer and opening onto a portion of said at least one first level of metallization. Brief description of the drawings
Ces objets, caractéristiques et avantages, ainsi que d'autres seront exposés en détail dans la description suivante de modes de réalisation particuliers faite à titre non-limitatif en relation avec les figures jointes parmi lesquelles :  These and other objects, features, and advantages will be set forth in detail in the following description of particular embodiments in a non-limitative manner with reference to the accompanying figures in which:
la figure 1, décrite précédemment, est une vue en coupe d'une partie d'un circuit intégré comprenant un via traversant et un transistor ;  Figure 1, previously described, is a sectional view of a portion of an integrated circuit comprising a via via and a transistor;
les figures 2A et 2B, décrites précédemment, sont des chronogrammes illustrant les perturbations électriques apportées par la présence d'un via traversant ;  FIGS. 2A and 2B, previously described, are timing diagrams illustrating the electrical disturbances brought about by the presence of a via via;
les figures 3 à 6, décrites précédemment, illustrent divers modes simples de protection de composants d'un circuit intégré par rapport aux perturbations apportées par un via traversant ;  FIGS. 3 to 6, previously described, illustrate various simple modes of protecting components of an integrated circuit with respect to the disturbances introduced by a via via;
la figure 7 est une vue en coupe représentant schéma- tiquement un exemple d'une structure de protection ;  Fig. 7 is a sectional view schematically showing an example of a protective structure;
les figures 8A, 8B et 8C sont des vues de dessus illustrant un premier type de structures de protection ;  Figures 8A, 8B and 8C are top views illustrating a first type of protective structures;
la figure 9 est une vue de dessus illustrant un autre mode de protection de vias traversants ;  Figure 9 is a top view illustrating another method of protection vias through;
les figures 10A à 10F illustrent un premier mode de fabrication de structure de protection ;  FIGS. 10A to 10F illustrate a first method of manufacturing a protective structure;
les figures 11A à 11F illustrent un deuxième mode de fabrication de structure de protection ; et  Figs. 11A to 11F illustrate a second method of manufacturing a protection structure; and
les figures 12A à 12E illustrent un troisième mode de fabrication de structure de protection.  FIGS. 12A to 12E illustrate a third method of manufacturing a protective structure.
Par souci de clarté, de mêmes éléments ont été désignés par de mêmes références aux différentes figures et, de plus, comme cela est habituel dans la représentation des circuits intégrés, les diverses figures ne sont pas tracées à 1 ' échelle .  For the sake of clarity, the same elements have been designated with the same references in the various figures and, moreover, as is customary in the representation of the integrated circuits, the various figures are not drawn to scale.
Description détaillée  detailed description
La figure 7 est une vue en coupe illustrant schémati- quement l'allure générale d'une structure de protection, cette structure de protection étant destinée à assurer la protection de composants disposés au voisinage d'un via par rapport aux divers types de perturbations électriques et mécaniques suscep¬ tibles d'être produites par ce via lors du fonctionnement du circuit intégré. Un via 30 entouré d'une région isolante 32 traverse le substrat semiconducteur 34 d'une puce de circuit intégré. Ce via est entouré d'une tranchée 36 qui reste vide (remplie d'un gaz et non pas d'un matériau solide), la partie supérieure de cette tranchée étant occluse par un bouchon 38. La tranchée 36 étant réalisée légèrement à distance du via 30, elle se trouve séparée de ce dernier par une portion 35 du substrat semiconducteur 34. FIG. 7 is a sectional view schematically illustrating the general appearance of a protective structure, this protective structure being intended to provide the protection components disposed in the vicinity of a via relative to various types of electrical and mechanical disturbances Suspected ¬ patible to be produced by the via during operation of the integrated circuit. A via 30 surrounded by an insulating region 32 passes through the semiconductor substrate 34 of an integrated circuit chip. This via is surrounded by a trench 36 which remains empty (filled with a gas and not a solid material), the upper part of this trench being occluded by a plug 38. The trench 36 being made slightly away from the via 30, it is separated from the latter by a portion 35 of the semiconductor substrate 34.
Une telle structure résout complètement les deux problèmes que 1 ' on cherche à résoudre . En ce qui concerne d'éventuelles perturbations électriques, elles sont très forte- ment atténuées par la présence de la tranchée 36 dont la profon¬ deur est, selon les modes de réalisation envisagés, égale à l'épaisseur du substrat de la puce, ou légèrement inférieure à celle-ci. En effet, une telle cavité vide (ou remplie d'un gaz résiduel sous basse pression) représente le matériau diélec- trique idéal et procure une excellente isolation électrostatique avec un encombrement réduit. Les problèmes mécaniques sont également résolus puisque toute contrainte résultant d'une dilatation thermique du via est absorbée au niveau de la cavité constituée par la tranchée vide. Such a structure completely solves the two problems that one seeks to solve. As regards possible electrical interference, they are very strongly attenuated by the presence of the trench 36, the Profon ¬ deur is, according to the proposed embodiments, equal to the thickness of the substrate of the chip, or slightly lower than this. Indeed, such an empty cavity (or filled with a residual gas under low pressure) represents the ideal dielectric material and provides excellent electrostatic insulation with a small footprint. Mechanical problems are also solved since any stress resulting from a thermal expansion of the via is absorbed at the cavity constituted by the empty trench.
Les figures 8A, 8B et 8C sont des vues de dessus représentant un premier type de forme de tranchée dans lequel la tranchée entoure le via. On a représenté très schématiquement dans ces figures, un transistor voisin du via par la référence 40.  Figs. 8A, 8B and 8C are top views showing a first type of trench shape in which the trench surrounds the via. Very schematically shown in these figures, a transistor neighbor of the via by the reference 40.
Dans le cas des figures 8A et 8B, la section de la tranchée 36 dans un plan orthogonal à la direction du via entoure complètement le via. Cette section est de forme circulaire en figure 8A et de forme carrée en figure 8B. L'une ou l'autre de ces formes sera choisie en fonction des impératifs de conception. En figure 8C, on a représenté la tranchée 36 de la figure 8A non pas continue mais constituée d'une succession de trous 42 très voisins les uns des autres. Si ces trous sont suffisamment voisins, les problèmes mécaniques seront très atténués, ainsi que les problèmes électriques. In the case of FIGS. 8A and 8B, the section of the trench 36 in a plane orthogonal to the direction of the via completely surrounds the via. This section is circular in Figure 8A and square in Figure 8B. Either of these forms will be chosen based on design requirements. In FIG. 8C, the trench 36 of FIG. 8A is shown not to be continuous but constituted by a succession of holes 42 very close to one another. If these holes are sufficiently close, the mechanical problems will be very attenuated, as well as the electrical problems.
La figure 9 est une vue de dessus illustrant un deuxième type de forme de tranchée 36 adapté au cas où des vias traversants 44 et 45 sont sensiblement alignés et ne comprennent pas entre eux de composants actifs. Dans ce cas, on pourra prévoir seulement deux tranchées parallèles à l'alignement des vias, de part et d'autre de cet alignement, pour protéger des composants 40 voisins de l'influence de ces vias.  Figure 9 is a top view illustrating a second type of trench form 36 adapted to the case where through vias 44 and 45 are substantially aligned and do not include them active components. In this case, it will be possible to provide only two trenches parallel to the alignment of the vias, on either side of this alignment, to protect components 40 adjacent to the influence of these vias.
Il est connu de fabriquer des vias traversants par l'un ou l'autre de trois types de procédés. Selon un premier type de procédé, les vias sont fabriqués avant la réalisation de composants sur un substrat semiconducteur. Selon un deuxième type de procédé, les vias sont réalisés à partir de la face supérieure d'une tranche de circuit intégré dans laquelle on a déjà formé des composants et un premier niveau de connexion destiné à assurer les contacts avec des portions de ces composants. Selon un troisième type de procédé, les vias sont réalisés alors qu'on a déjà complètement formé les composants électroniques et les niveaux de métallisation les revêtant.  It is known to manufacture through vias by one or the other of three types of processes. According to a first type of method, the vias are manufactured before the production of components on a semiconductor substrate. According to a second type of method, the vias are made from the upper face of an integrated circuit wafer in which components have already been formed and a first connection level intended to ensure contacts with portions of these components. According to a third type of method, the vias are made while the electronic components and metallization levels coating them have already been completely formed.
Les figures 10A à 10F illustrent des étapes succes- sives d'un premier mode de réalisation dans lequel les vias sont formés avant toute réalisation de composants dans un substrat semiconducteur .  FIGS. 10A-10F illustrate successive steps of a first embodiment in which the vias are formed prior to any embodiment of components in a semiconductor substrate.
Comme l'illustre la figure 10A, on part d'une tranche semiconductrice 101 sur laquelle on forme un masque 103 muni de premières ouvertures 105 aux emplacements où on veut former des vias et de deuxièmes ouvertures 106 aux emplacements où on veut former une tranchée entourante ou plusieurs tranchées, comme cela a été décrit en relation avec les figures 8A-8C et 9.  As illustrated in FIG. 10A, one starts from a semiconductor wafer 101 on which a mask 103 is formed with first openings 105 at the locations where it is desired to form vias and second openings 106 at the locations where it is desired to form a surrounding trench. or more trenches, as described with reference to FIGS. 8A-8C and 9.
A l'étape illustrée en figure 10B, on a utilisé le masque 103 pour former des ouvertures 110 et 111 dans le substrat. L'ouverture 110 a la profondeur et le diamètre que l'on souhaite avoir pour le via. On notera que par les procédés classiques de gravure anisotrope, une gravure réalisée à travers une ouverture de plus petite dimension latérale aura une profon¬ deur plus faible que la même gravure réalisée simultanément à travers une ouverture ayant une plus grande dimension latérale. En pratique, on note que, si les tranchées latérales ont une dimension latérale qui est au moins trois fois inférieure à celle du via, leur profondeur sera de 5 à 10 % inférieure. In the step illustrated in FIG. 10B, the mask 103 was used to form openings 110 and 111 in the substrate. The opening 110 has the depth and diameter that we want to have for the via. Note that by conventional methods of anisotropic etching, etching performed through an opening of smaller lateral dimension will have a lower depth ¬ than the same etching performed simultaneously through an opening having a larger lateral dimension. In practice, it is noted that, if the side trenches have a lateral dimension which is at least three times smaller than that of the via, their depth will be 5 to 10% lower.
A l'étape illustrée en figure 10C, on a déposé une couche isolante 113 sur la face supérieure de l'ensemble de la structure, après enlèvement de la couche de résine 103.  In the step illustrated in FIG. 10C, an insulating layer 113 is deposited on the upper face of the assembly of the structure, after removal of the resin layer 103.
On forme ainsi le revêtement isolant 32 du via et des revêtements isolants 115 sur les parois des tranchées. Un tel dépôt peut par exemple être réalisé selon un procédé de dépôt chimique en phase vapeur, de préférence selon une variante en mode sub-atmosphérique, plus adaptée aux vias traversants de profondeur importante. Ces deux procédés étant bien connus sous les vocables anglais respectifs de Chemical Vapour Déposition (CVD) et Sub-Atmospheric Chemical Vapour Déposition (SACVD) .  The insulating coating 32 of the via and the insulating coatings 115 are thus formed on the walls of the trenches. Such a deposition may for example be carried out according to a chemical vapor deposition process, preferably in a sub-atmospheric variant, more suitable for through vias of considerable depth. Both of these processes are well known under the respective English names of Chemical Vapor Deposition (CVD) and Sub-Atmospheric Chemical Vapor Deposition (SACVD).
Etant donné que les tranchées sont beaucoup plus étroites que l'ouverture du via, le dépôt de la couche isolante 113 conduit à une obstruction de la partie supérieure des tranchées, en formant des bouchons 38 tels que le sommet de la cavité 36 soit situé sous le plan de la face avant 102 du substrat 101.  Since the trenches are much narrower than the opening of the via, the deposition of the insulating layer 113 leads to an obstruction of the upper part of the trenches, forming plugs 38 such that the top of the cavity 36 is located under the plane of the front face 102 of the substrate 101.
Bien entendu, l'homme de métier choisira un mode de dépôt de l'isolant qui favorise la formation de tels bouchons et le maintien d'un espace vide dans les tranchées. Pour cela, il pourra choisir, pour la première partie du dépôt, des conditions opératoires conduisant à un dépôt peu conforme, donc favorisant l'obstruction de la partie supérieure des tranchées, puis, dès que les tranchées seront refermées, des conditions opératoires conduisant à un dépôt le plus conforme possible, afin de finir de tapisser les parois du via d'une épaisseur d'isolant suffi- santé, sur toute la hauteur du via. Le dépôt de l'isolant 113 étant de façon générale réalisé à basse pression, le vide 36 sera rempli à basse pression du mélange de gaz utilisé lors du dépôt de l'isolant, couramment, pour un dépôt d'oxyde de silicium (S1O2) , un mélange d'argon, d'oxygène et d'un précurseur de silicium tel que le silane (S1H4) ou le Tétra-Ethyl-Ortho-Silicate (TEOS) . Of course, those skilled in the art will choose a method of depositing the insulation which promotes the formation of such plugs and the maintenance of a void space in the trenches. For this, it may choose, for the first part of the deposit, operating conditions leading to a poorly compliant deposit, thus promoting the obstruction of the upper part of the trenches, then, as soon as the trenches are closed, operating conditions leading to a deposit as compliant as possible, in order to finish upholstering the walls of the via with a sufficient thickness of insulation, over the entire height of the via. As the deposition of the insulator 113 is generally carried out at low pressure, the vacuum 36 will be filled at low pressure with the gas mixture used during the deposition of the insulator, commonly for a silicon oxide (SiO 2) deposit. ), a mixture of argon, oxygen and a silicon precursor such as silane (S1H4) or tetra-Ethyl-Ortho-Silicate (TEOS).
En figure 10D, on a déposé sur la structure une couche 119 d'un matériau électriquement conducteur et compatible avec la réalisation ultérieure de composants de circuits intégrés sur le substrat 101, par exemple du silicium polycristallin dopé.  In FIG. 10D, a layer 119 of an electrically conductive material which is compatible with the subsequent production of integrated circuit components on the substrate 101, for example doped polycrystalline silicon, has been deposited on the structure.
A l'étape illustrée en figure 10E, on a procédé à un polissage mécano-chimique pour éliminer de la surface supérieure de la structure les couches 119 et 113. On obtient ainsi un via 30, dont la face supérieure est dans le plan de la face supé- rieure du substrat 101, et des tranchées vides 36 dont la partie supérieure est obstruée par un bouchon 38 dont la face supérieure est également dans le plan de la face supérieure du substrat 101.  In the step illustrated in FIG. 10E, a chemical-mechanical polishing was carried out in order to eliminate the layers 119 and 113 from the upper surface of the structure. A via 30 is thus obtained, the upper face of which is in the plane of the upper side of the substrate 101, and empty trenches 36 whose upper part is obstructed by a plug 38 whose upper face is also in the plane of the upper face of the substrate 101.
A l'étape illustrée en figure 10F, on a formé succes- sivement des composants 2 dans la surface supérieure du substrat 101, des contacts 120 dans une couche isolante 121, et des niveaux successifs de métallisation 122, 123, 124, 125 reliés quand il y a lieu par des vias 127 traversants une couche isolante intermédiaire. En même temps que l'on réalise les contacts 120 avec des portions de composants semiconducteurs, on réalise des contacts 130 avec la face supérieure du via 30 pour relier ce via à un niveau de métallisation 132. Le détail des connexions entre niveaux de métallisation n'est pas illustré en figure 10F.  In the step illustrated in FIG. 10F, components 2 in the upper surface of the substrate 101 are formed successively, contacts 120 in an insulating layer 121, and successive levels of metallization 122, 123, 124, 125 connected when it is necessary by vias 127 through an intermediate insulating layer. At the same time that the contacts 120 are made with portions of semiconductor components, contacts 130 are made with the upper face of the via 30 to connect it via a metallization level 132. The details of the connections between metallization levels n is not illustrated in Figure 10F.
Une fois les composants et les niveaux de métallisa¬ tion formés, on arase la face arrière de la tranche semiconduc- trice pour rendre apparente la face inférieure 140 du via 30 et en faire un via traversant. Lors de cette étape, du fait que les tranchées 36 formées à côté du via sont moins profondes que ce via, le vide formé dans ces tranchées n'est pas affecté. Divers moyens sont connus de l'homme de l'art pour réaliser cet arasement de la face arrière d'une tranche semiconductrice . On pourra utiliser un polissage mécano-chimique . De façon courante, avant l'opération de polissage, la face avant de la tranche semiconductrice est montée sur une plaque intermédiaire ou poignée, non représentée ici. Once the components and levels of métallisa ¬ formed is leveled the rear face of the wafer semiconduc- trice to make apparent the lower face 140 of the via 30 and make a through via. In this step, because the trenches 36 formed next to the via are shallower than this via, the vacuum formed in these trenches is not affected. Various means are known to those skilled in the art for carrying out this recessing of the rear face of a semiconductor wafer. We can use a chemical mechanical polishing. Usually, before the polishing operation, the front face of the semiconductor wafer is mounted on an intermediate plate or handle, not shown here.
Les figures 11A à 11F illustrent des étapes successi¬ ves d'un deuxième mode de réalisation dans lequel les vias sont formés après que des composants électroniques ont été formés du côté de la face avant de la tranche semiconductrice et que des contacts ont été formés vers des éléments à connecter du circuit intégré à travers une première couche isolante. 11A-11F illustrate steps successi ve ¬ a second embodiment in which the vias are formed after the electronic components were formed on the side of the front face of the semiconductor wafer and that contacts were trained to elements to be connected to the integrated circuit through a first insulating layer.
La figure 11A illustre une tranche semiconductrice 101 sur laquelle des composants électroniques 2 ont été réalisés, dont des portions choisies sont reliées à des contacts 120 traversant une couche isolante 121. De préférence, on a formé dans la face supérieure du substrat 101 une région isolante 200 aux emplacements où l'on souhaite former un via et des tranchées de protection. La région isolante 200 est formée en même temps que les régions isolantes (STI) entourant de façon générale chaque composant électronique.  FIG. 11A illustrates a semiconductor wafer 101 on which electronic components 2 have been made, selected portions of which are connected to contacts 120 passing through an insulating layer 121. Preferably, an insulating region has been formed in the upper face of the substrate 101. 200 at locations where you want to form a via and trenches protection. The insulating region 200 is formed at the same time as the insulating regions (STI) generally surrounding each electronic component.
On a déposé sur la structure un masque 202 dans lequel on a formé une ouverture principale 205 à l'emplacement où l'on souhaite former un via et des ouvertures 206 aux emplacements où l'on souhaite former la ou les tranchées.  A mask 202 has been deposited on the structure in which a main opening 205 has been formed at the location where it is desired to form a via and openings 206 at the locations where it is desired to form the trench or trenches.
A l'étape illustrée en figure 11B, on a utilisé le masque 202 pour graver successivement la couche isolante 121, la région isolante 200 et le substrat 101, et former des ouvertures 210 et 211. Cet ensemble d'ouvertures du via et des tranchées aura les mêmes caractéristiques de pénétration dans le substrat que l'ensemble d'ouvertures 110 et 111 décrit en relation avec la figure 10B.  In the step illustrated in FIG. 11B, the mask 202 was used to successively etch the insulating layer 121, the insulating region 200 and the substrate 101, and to form openings 210 and 211. This set of via openings and trenches will have the same characteristics of penetration into the substrate as the set of openings 110 and 111 described in connection with Figure 10B.
A l'étape illustrée en figure 11C, on a procédé à des étapes similaires à celles décrites en relation avec la figure 10C pour former des régions et couches analogues, portant les mêmes références ou de mêmes références incrémentées d'une centaine . A l'étape illustrée en figure 11D, on a déposé une couche de barrière de diffusion 217 sur la face supérieure de l'ensemble de la structure. Les parois du via sont ainsi revê¬ tues d'une couche de barrière de diffusion 37 déposée sur la couche d'isolant 32. On a ensuite procédé au dépôt sur la face supérieure de l'ensemble de la structure d'une couche épaisse 219 en un matériau électriquement conducteur. Ce matériau remplit complètement l'ouverture 210 du via. La couche barrière de diffusion 217 peut par exemple être un empilement de nitrure de tantale (TaN) et de tantale, déposé selon un procédé de dépôt par pulvérisation, connu sous le vocable anglais de Physical Vapour Déposition (PVD) . La couche épaisse conductrice 219 peut par exemple être en cuivre (Cu) déposé selon un procédé électro¬ chimique. Si ce type de procédé est employé, on procédera au préalable au dépôt sur la couche de barrière 217 d'une couche conductrice d'accroché, non représentée sur la figure, par exemple une couche de cuivre déposée par pulvérisation (PVD) . In the step illustrated in FIG. 11C, steps similar to those described with reference to FIG. 10C were carried out to form regions and similar layers bearing the same references or the same incremented references of one hundred. At the step illustrated in FIG. 11D, a diffusion barrier layer 217 has been deposited on the upper face of the entire structure. The walls of the via are thus killed ¬ dream of a diffusion barrier layer 37 deposited on the insulating layer 32. It is then proceeded to deposit on the upper face of the whole of a thick layer 219 structure in an electrically conductive material. This material completely fills the aperture 210 of the via. The diffusion barrier layer 217 may for example be a stack of tantalum nitride (TaN) and tantalum deposited by a spray deposition process known as Physical Vapor Deposition (PVD). The conductive thick film 219 may for example be copper (Cu) deposited as an electro ¬ chemical process. If this type of method is used, the prior art will deposit on the barrier layer 217 a conductive layer of hooked, not shown in the figure, for example a layer of copper deposited by sputtering (PVD).
En figure 11E, on a représenté la structure après réalisation des mêmes étapes que celles décrites précédemment en relation avec la figure 10E, portant les mêmes références ou de mêmes références incrémentées d'une centaine. On arrive ainsi à une structure dont la surface supérieure correspond à la surface supérieure de la couche isolante 121. Au niveau de cette surface supérieure, on trouve les bouchons 38 bouchant les évidements 36 de la ou des tranchées et la surface supérieure du via conducteur 30.  In FIG. 11E, the structure is shown after carrying out the same steps as those previously described in relation with FIG. 10E, bearing the same references or the same references incremented by a hundred. This leads to a structure whose upper surface corresponds to the upper surface of the insulating layer 121. At this upper surface, there are the plugs 38 blocking the recesses 36 of the trench or trenches and the upper surface of the conductive via 30 .
En figure 11F, on a représenté la structure après réalisation des mêmes étapes que celles décrites précédemment en relation avec la figure 10F, pour réaliser les niveaux succes- sifs de métallisation puis l'arasement de la face arrière de la tranche semiconductrice pour rendre apparente la face inférieure 240 du via 30 et en faire un via traversant.  FIG. 11F shows the structure after carrying out the same steps as those previously described in connection with FIG. 10F, in order to achieve the successive levels of metallization then the leveling of the rear face of the semiconductor wafer to make apparent the underside 240 of the via 30 and make it a through via.
Les figures 12A à 12E illustrent des étapes successi¬ ves d'un troisième mode de réalisation d'un procédé de formation de via et de tranchées. Cette fois-ci, les vias sont formés après que les composants et tous les niveaux de métallisation ont été formés sur la surface supérieure de la tranche. 12A to 12E illustrate steps successi ve ¬ a third embodiment of a via and trench formation process. This time, the vias are formed after the components and all metallization levels have been formed on the upper surface of the wafer.
En figure 12A, on retrouve du côté de la face supé¬ rieure les éléments déjà représentés en relation avec la figure 11F désignés par les mêmes références. En outre, la face arrière de la tranche a été meulée et polie pour réduire l'épaisseur de la tranche à l'épaisseur finale que l'on souhaite obtenir. Comme on l'a indiqué précédemment, pendant cette étape et des étapes ultérieures, la partie supérieure de la tranche a été fixée à une tranche support ou poignée, non représentée ici. In 12A, found on the side of the Supe face ¬ higher the elements already shown in relation to FIG 11F designated by the same references. In addition, the back side of the wafer has been ground and polished to reduce the thickness of the wafer to the final thickness that is desired. As previously indicated, during this step and subsequent steps, the upper portion of the wafer was attached to a wafer or handle, not shown here.
Ensuite, comme l'illustre la figure 12B, on revêt la face arrière de la tranche amincie d'une couche de masquage 303 dans laquelle sont formées des ouvertures 305 pour le via et 306 pour les tranchées. On procède au travers de ces ouvertures à une gravure anisotrope, d'abord du silicium 101 du substrat puis de l'oxyde de silicium constituant les couches 200 et 121. On a représenté que l'ouverture du via atteint la couche métallique 132 alors que celles des tranchées s'arrêtent un peu avant. En fait, ceci est sans importance dans ce mode de réalisation et l'on pourrait poursuivre la gravure jusqu'à ce que les tranchées atteignent également la couche métallique 132.  Then, as shown in Fig. 12B, the back side of the thinned wafer is coated with a masking layer 303 in which openings 305 for the via and 306 for the trenches are formed. Through these openings, anisotropic etching is carried out first of the silicon 101 of the substrate and then of the silicon oxide constituting the layers 200 and 121. It has been shown that the opening of the via reaches the metal layer 132 while those of the trenches stop a little before. In fact, this is irrelevant in this embodiment and etching could be continued until the trenches also reach the metal layer 132.
A l'étape illustrée en figure 12C, on a procédé à un dépôt d'isolant de façon similaire à ce qui a été décrit en figure 11C, mais cette fois-ci à partir de la face arrière de la tranche.  At the step illustrated in FIG. 12C, an insulation deposit was made in a manner similar to that described in FIG. 11C, but this time starting from the rear face of the wafer.
De même, la figure 12D reprend des étapes similaires à celles décrites en relation avec la figure 11D, mais cette fois- ci également, à partir de la face arrière de la tranche.  Similarly, Figure 12D resumes similar steps to those described in relation to Figure 11D, but this time also from the back side of the wafer.
La figure 12E représente la structure après élimina- tion des couches déposées sur la face arrière.  Figure 12E shows the structure after removal of the layers deposited on the back face.
On a décrit ci-dessus trois modes de réalisation d'une structure selon la présente invention. Dans cette description de modes de réalisation particuliers, on a indiqué des natures spécifiques de matériaux et on a donné des exemples particuliers notamment en ce qui concerne l'épaisseur que l'on souhaite laisser en place pour le substrat, et le diamètre des vias . Bien entendu, ces diverses caractéristiques pourront être adaptées par l'homme de l'art pour la réalisation de structures spécifiques. On notera que chacun des trois procédés décrits ci- dessus conduit à l'obtention de la structure illustrée très schématiquement en relation avec la figure 7. De plus, l'homme de l'art pourra combiner divers éléments de ces divers modes de réalisation et variantes sans faire preuve d'activité inventive. Three embodiments of a structure according to the present invention have been described above. In this description of particular embodiments, specific natures of materials have been indicated and particular examples have been given in particular as regards the thickness that it is desired to leave in place for the substrate, and the diameter of the vias. Good Of course, these various features may be adapted by those skilled in the art for the realization of specific structures. It will be noted that each of the three methods described above leads to obtaining the structure illustrated very schematically in relation to FIG. 7. Moreover, one skilled in the art can combine various elements of these various embodiments and variants without demonstrating inventive activity.

Claims

REVENDICATIONS
1. Circuit intégré comprenant : An integrated circuit comprising:
des composants électroniques actifs et des niveaux de métallisation sur une face supérieure,  active electronic components and metallization levels on an upper face,
au moins un via isolé (30) traversant le substrat (34), et  at least one insulated via (30) passing through the substrate (34), and
une tranchée vide (36) s' étendant dans le substrat sur au moins 50 % de sa hauteur à partir de ladite face supérieure, cette tranchée entourant le via isolé, et en étant séparée par une portion du substrat, les composants électroniques étant disposés à l'extérieur de la tranchée par rapport au via.  an empty trench (36) extending in the substrate over at least 50% of its height from said upper face, this trench surrounding the insulated via, and being separated by a portion of the substrate, the electronic components being arranged at outside the trench in relation to via.
2. Circuit intégré selon la revendication 1, dans lequel la tranchée vide traverse le substrat sur toute sa hauteur.  2. Integrated circuit according to claim 1, wherein the empty trench passes through the substrate over its entire height.
3. Circuit intégré selon la revendication 1, dans lequel l'extrémité du via située du côté de la face supérieure se trouve dans le plan du substrat et dans lequel le via est formé en un matériau comprenant du silicium polycristallin .  An integrated circuit according to claim 1, wherein the end of the via located on the side of the upper face is in the plane of the substrate and wherein the via is formed of a material comprising polycrystalline silicon.
4. Circuit intégré selon la revendication 1, dans lequel l'extrémité du via située du côté de la face supérieure est en contact avec un niveau de métallisation inférieur et dans lequel le via est en un matériau choisi dans le groupe comprenant le cuivre et l'aluminium.  An integrated circuit according to claim 1, wherein the end of the via located on the side of the upper face is in contact with a lower level of metallization and wherein the via is of a material selected from the group consisting of copper and copper. 'aluminum.
5. Circuit intégré selon l'une quelconque des revendications 1 à 4, dans lequel la section de la tranchée, selon un plan parallèle au substrat, est formée d'un unique élément centré autour du via, de forme choisie parmi le cercle, le carré, le rectangle, l'hexagone et l'octogone.  5. Integrated circuit according to any one of claims 1 to 4, wherein the section of the trench, in a plane parallel to the substrate, is formed of a single element centered around the via, of a shape selected from the circle, the square, rectangle, hexagon and octagon.
6. Circuit intégré selon l'une quelconque des revendications 1 à 4, dans lequel la section de ladite tranchée, selon un plan parallèle au substrat, est formée d'une pluralité d'éléments centrés autour dudit via, de forme choisie parmi le disque et la bande rectiligne.  6. Integrated circuit according to any one of claims 1 to 4, wherein the section of said trench, in a plane parallel to the substrate, is formed of a plurality of elements centered around said via, selected from the disk and the straight strip.
7. Procédé de réalisation d'un circuit intégré comprenant, sur la face supérieure du substrat, des composants électroniques actifs et au dessus desdits composants, un empilement de niveaux de métallisation comprenant au moins une première couche isolante en contact avec lesdits composants et au moins un premier niveau de métallisation, et un via traversant le substrat, isolé des composants électroniques actifs par une tranchée vide, comprenant les étapes suivantes : 7. A method of producing an integrated circuit comprising, on the upper face of the substrate, components active electronics and above said components, a stack of metallization levels comprising at least a first insulating layer in contact with said components and at least a first metallization level, and a via passing through the substrate, isolated from the active electronic components by a trench empty, comprising the following steps:
graver dans le substrat, à l'emplacement du via, un trou (110) d'une première largeur et, autour de ce trou, une tranchée (111) d'une deuxième largeur, inférieure à la première largeur ; et  etching in the substrate, at the location of the via, a hole (110) of a first width and, around this hole, a trench (111) of a second width, smaller than the first width; and
déposer une couche d'un matériau électriquement isolant (113) de sorte que les parois du trou sont revêtues d'une couche isolante et que la tranchée est refermée ; et  depositing a layer of an electrically insulating material (113) so that the walls of the hole are coated with an insulating layer and the trench is closed; and
remplir le trou d'un matériau électriquement conduc- teur (30) .  filling the hole with an electrically conductive material (30).
8. Procédé selon la revendication 7, dans lequel le via et la tranchée vide sont formés dans la face supérieure du substrat avant la formation des composants électroniques actifs, et comprenant une étape d'amincissement du substrat par sa face inférieure de manière à découvrir l'extrémité inférieure du via sans découvrir l'extrémité inférieure de la tranchée.  8. The method of claim 7, wherein the via and the empty trench are formed in the upper face of the substrate before forming the active electronic components, and comprising a step of thinning the substrate by its underside so as to discover the lower end of the via without discovering the lower end of the trench.
9. Procédé selon la revendication 7, dans lequel le via et la tranchée vide sont formés dans la face supérieure du substrat après la formation des composants électroniques actifs et de ladite première couche isolante, et comprenant une étape d'amincissement du substrat par sa face inférieure de manière à découvrir l'extrémité inférieure du via sans découvrir l'extrémité inférieure de la tranchée.  9. The method of claim 7, wherein the via and the empty trench are formed in the upper face of the substrate after the formation of the active electronic components and said first insulating layer, and comprising a step of thinning the substrate by its face. lower so as to discover the lower end of the via without discovering the lower end of the trench.
10. Procédé selon la revendication 7, dans lequel le via et la tranchée vide sont formés dans la face inférieure du substrat après les étapes suivantes :  The method of claim 7, wherein the via and the empty trench are formed in the underside of the substrate after the following steps:
former les composants électroniques actifs ; former l'empilement de niveaux de métallisation ; et amincir le substrat par sa face inférieure ; le trou et la tranchée traversant le substrat et le trou traversant ladite première couche isolante et débouchant sur une portion dudit au moins un premier niveau de métallisation. form active electronic components; forming the stack of metallization levels; and thin the substrate by its underside; the hole and the trench passing through the substrate and the hole passing through said first insulating layer and opening on a portion of said at least one first level of metallization.
PCT/FR2011/053194 2010-12-31 2011-12-26 Insulated via hole WO2012089980A1 (en)

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US20120037412A1 (en) * 2010-08-13 2012-02-16 Jochen Reinmuth Method for producing an electrical feedthrough in a substrate, and substrate having an electrical feedthrough

Cited By (6)

* Cited by examiner, † Cited by third party
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CN104078414A (en) * 2013-03-28 2014-10-01 中芯国际集成电路制造(上海)有限公司 Silicon through hole and formation method
WO2015010195A1 (en) * 2013-07-22 2015-01-29 Conversant Intellectual Property Management Inc. Through semiconductor via structure with reduced stress proximity effect
CN110707068A (en) * 2019-09-09 2020-01-17 长江存储科技有限责任公司 Semiconductor interconnection structure and preparation method thereof
CN110707068B (en) * 2019-09-09 2021-10-19 长江存储科技有限责任公司 Semiconductor interconnection structure and preparation method thereof
CN115148790A (en) * 2022-09-02 2022-10-04 南京融芯微电子有限公司 Ultra-low parasitic capacitance bonding pad structure and manufacturing method
CN115148790B (en) * 2022-09-02 2022-12-13 南京融芯微电子有限公司 Ultra-low parasitic capacitance bonding pad structure and manufacturing method

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