TW201401507A - Semiconductor device and fabricating method thereof - Google Patents

Abstract

A semiconductor device includes a substrate with a front side and a back side, a dielectric layer, disposed on the substrate, a cap layer disposed on the backside of the substrate, a TSV penetrating the cap layer, the substrate and partial of the dielectric layer, wherein in the TSV, a sidewall of the cap layer bulge the sidewall of the substrate with a predetermined distance, and a liner disposed on the sidewall of the substrate, wherein the liner partially overlap with the cap layer.

Description

Semiconductor component and manufacturing method thereof

The present invention provides a semiconductor device, particularly a semiconductor device having a via hole.

In the modern information society, the microprocessor system consisting of integrated circuits has been widely used in all aspects of life, such as automatic control of household appliances, mobile communication devices, personal computers, etc., all of which have traces of integrated circuits. . With the increasing advancement of technology and the imagination of human society for electronic products, the integrated circuit has also developed in the direction of more yuan, more precision and smaller.

Generally, an integrated circuit is formed by a die produced in a conventional semiconductor process. The process of fabricating a die begins with the production of a wafer: first, a plurality of regions are distinguished on a wafer, and in each region, through various semiconductor processes such as deposition, lithography, etching, or flattening. The steps to form various required circuit paths, and then, the respective regions on the wafer are cut into individual chips, packaged into chips, and finally the wafer is electrically connected to a circuit board. Such as a printed circuit board (PCB), after the chip is electrically connected to the pins of the printed circuit board, a variety of stylized processing can be performed.

In order to improve the function and performance of the wafer and increase the degree of integration to accommodate more semiconductor components in a limited space, the related manufacturers have developed a number of semiconductor wafer stacking technologies, including flip chip technology (Flip-Chip) technology, multi-chip package ( Multi-chip Package (MCP) technology, package on package (PoP) technology, package in package (PiP) technology, etc., can be stacked by die or package. Increase the degree of integration of semiconductor components per unit volume. Under the above various package architectures, a technology called Through Silicon Via (TSV) has been developed in recent years to promote internal interconnection of the crystal grains in the package to improve stacking efficiency. Further advancement.

The principle of boring is to form a through-wafer via in the wafer by etching or laser, and then fill a via hole with a conductive material such as copper, polysilicon, tungsten, etc., and finally wafer or die. Thinned and stacked, Bonded, and become a 3D solid crystal grain stack structure. Since the connection path of the internal lines of each chip is the shortest, the transmission speed between the wafers is faster, the noise is smaller, and the performance is better, which is one of the currently promising technologies.

The present invention provides a semiconductor device comprising a substrate having a front surface and a back surface, an interlayer dielectric layer overlying the front surface of the substrate, a mask layer covering the back surface of the substrate, and a via electrode extending through the mask Cover layer, the substrate, and the interlayer dielectric a layer, wherein the sidewall electrode has a mask sidewall and a substrate sidewall, and the mask layer sidewall protrudes from the substrate sidewall by a predetermined length, and a liner layer is located on the substrate sidewall in the bore The liner layer partially overlaps the mask layer.

According to another preferred embodiment of the present invention, the present invention provides a method of fabricating a semiconductor device, comprising the steps of: first, providing a substrate having a front surface and a back surface; forming an interlayer dielectric layer on the substrate On the front side, a mask layer is formed on the back surface of the substrate, and the back surface of the substrate is etched to form an opening through the mask layer and the substrate, wherein a mask layer sidewall and a substrate sidewall are disposed in the opening. The sidewall of the mask layer protrudes from the sidewall of the substrate by a predetermined length, and then selectively deposits a liner layer on the sidewall of the substrate in the opening, and the liner layer at least partially overlaps the mask layer, and then etches the opening to form A via is inserted through the interlayer dielectric layer and a conductive layer is formed in the via.

The present invention will be further understood by those of ordinary skill in the art to which the present invention pertains. .

For the convenience of description, the drawings of the present invention are only for the purpose of understanding the present invention, and the detailed proportions thereof can be adjusted according to the design requirements. As described in the text for the relative relationship between the relative elements in the figure, anyone in the field should be able to understand the reference The relative positions of the components, therefore, can be reversed to present the same components, which are all within the scope of the present disclosure, which will be described first.

Please refer to FIGS. 1-7. FIG. 1 to FIG. 7 are schematic diagrams showing the manufacturing process of the semiconductor device according to the first preferred embodiment of the present invention. As shown in FIG. 1, the semiconductor device first provides a substrate 10, such as a silicon substrate, an epitaxial silicon substrate, a silicon germanium substrate, or a silicon carbide substrate. A substrate or a silicon-on-insulator (SOI) or the like, a preferred embodiment of the present invention is a bulk silicon substrate, but not limited thereto. 10 has a front side 12 and a back side 14, and then forms the desired various N-well or P-wells (not shown) and a plurality of shallow trench isolations 16 in the substrate 10.

Next, as shown in FIG. 2, at least one gate structure 18 is formed on the substrate 10, and the source/drain regions 20 are formed in the substrate 10 on both sides of the gate structure 18 by ion implantation or the like. The gate structure 18 can be a polysilicon gate, a metal gate or a dummy gate, etc., to form the gate structure 18 and the source/drain region 20, or even A method of forming a self-aligned metal salicide (not shown) on the surface of the source/drain region 20 is common in the art and will not be described herein. Then, an interlayer dielectric layer 22 is overlaid on the gate structure 18 and the front surface 12, and then a metal interconnect process is further performed to prepare a plurality of metal interlayer dielectric layers (IMD) on the interlayer dielectric layer 22 (Fig. Not shown) and the metal required to be placed in the dielectric layer between the metal layers Line (not shown).

For convenience of description, FIG. 2 only shows that a metal line 24 corresponding to a subsequently formed turns (TSV) is formed on the surface of the interlayer dielectric layer 22, and other metal lines and dielectric layers between the metal layers are omitted. The bottom surface of the metal line 24 can directly contact the subsequently formed via via (TSV) and be electrically connected to other components by metal lines (not shown) in the upper inter-metal dielectric layer (IMD). In addition, a contact etch stop layer (CESL) (not shown) may be selectively formed between the interlayer dielectric layer 22 and the substrate 10 to cover the gate structure 18 and the source/drain regions 20, and a plurality of contact plugs 28 They are respectively disposed on the gate structure 18 and the source/drain region 20 for electrically connecting metal lines (not shown) in the inter-metal dielectric layer (IMD) above the interlayer dielectric layer 22, in this embodiment, the metal The material of the line 24 and the contact plug 28 may be selected from the group consisting of a conductive metal such as copper, aluminum, tungsten, titanium, titanium nitride, tantalum, and tantalum nitride, but is not limited thereto.

After the metal interconnection process on the front side 12 of the substrate 10 and the bonding pad process on the dielectric layer between the metal layers are completed. Next, the substrate 10 is thinned by the back surface 14 of the substrate 10, and a mask layer 26 is formed on the back surface 14 of the substrate 10. The material of the mask layer 26 is, for example, cerium oxide (SiO ₂ ) or tantalum nitride (SiN). An insulator such as tantalum carbide (SiC) or bismuth oxynitride (SiON) is not limited thereto, and in the present invention, tantalum nitride is exemplified.

As shown in FIG. 3, at least one opening 30 is formed on the back surface 14 of the substrate 10 by lithography and etching to define the position of the ruthenium perforation (TSV). The opening 30 extends through the mask layer 26 and the substrate 10, and the bottom of the opening 30 rests on the bottom surface of the interlayer dielectric layer 22. At this time, the side wall inside the opening 30 can be roughly divided into a base side wall 32 and a mask layer side wall 34.

It should be noted that after the opening 30 is etched on the back surface 14 of the substrate 10, as shown in FIG. 4, the present invention further performs a pull back process for uniformly expanding the substrate sidewall 32, that is, Inside the opening 30, an opening diameter a formed by the side wall 32 of the substrate is larger than an opening diameter b formed by the side wall 34 of the mask layer, so that the side wall 34 of the mask layer protrudes from the front in the figure. The sidewall 32 has a predetermined length d (a predetermined distance), wherein d = (ab)/2, and the shrink etching may include a general wet etching such as hydrofluoric acid (HF) mixed ethylene glycol (ethylene glycol, EG), or an isotropic plasma etch, to selectively etch the mask layer 26 and the substrate 10, but is not limited thereto.

In addition, in this embodiment, the opening 30 is formed first, and then the substrate sidewall 32 is expanded by the retracting process. However, the present invention is not limited thereto, and the etching selectivity ratio may be adjusted to form the opening 30 only by one etching, and at the same time form an extension. Substrate sidewall 32.

Next, as shown in FIG. 5, a liner layer 36 is selectively deposited on the substrate sidewall 32 in the opening 30. The liner layer 36 is made of a single material such as tantalum nitride (SiN) or yttrium oxide (SiO ₂ ). A material layer or a composite structure layer, but is not limited thereto. It should be noted that the liner layer 36 can be selectively formed on the sidewalls 32 of the substrate by electrochemical or oxidation, etc., without being formed on the sidewalls 34 of the mask layer. For example, the liner layer 36 can be formed only on the sidewalls 32 of the substrate having electrical properties, such as the liner layer 36, that is, the liner layer 36 is not formed on the sidewalls 34 of the mask layer that are not of a conductive nature. Due to the above-described retracting process etching, the substrate sidewall 32 and the mask layer sidewall 34 are horizontally different by a predetermined length d, and a predetermined space formed by the predetermined length d is located on the substrate sidewall 32, and the liner layer 36 is deposited on the substrate. In the predetermined space, the spacer layer 36 and the mask layer 26 are overlapped at least by a width, and a bump is not easily generated at the boundary between the two to cause a leakage current. In this embodiment, the overlap width of the pad layer 36 and the mask layer 26 is preferably greater than 10 nm (10 nm), so that the interface between the pad layer 36 and the mask layer 26 has good adhesion. It is more effective in preventing leakage current from occurring. In addition, after the spacer layer 36 is formed in the predetermined space, the sidewall of the liner layer 36 may be aligned with or not aligned with the sidewalls 34 of the mask layer, that is, the sidewalls of the liner layer 36 may protrude. The mask layer sidewalls 34, or vice versa, the mask layer sidewalls 34 protrude from the sidewalls of the liner layer 36. However, regardless of whether the sidewall of the liner layer 36 is aligned with the sidewalls 34 of the mask layer, it is preferred to satisfy the condition that the portion of the overlap of the liner layer 36 and the mask layer 26 is greater than 10 nanometers.

Further, as shown in FIGS. 6-7, an opening step is performed on the opening 30 again to form a turn-by-hole 38, and the bottom of the turn-by-hole 38 rests on the bottom surface of the metal line 24. Thereafter, a barrier layer 40 is selectively formed inside the via hole 38, and a conductive layer 42 is covered in the via hole 38 and the back surface 14 to form a via electrode 44. The barrier layer 40 may be selected from titanium and nitrogen. A group consisting of titanium, tantalum and tantalum nitride, the material of the conductive layer 42 may be selected from a metal having good conductivity, and the method for forming the same may be copper. After depositing the barrier layer 40, a copper seed layer (not shown) is formed, and then a yellow back process of a crystal back bump is performed to form a patterned photoresist layer (not shown), and then After electroplating the copper, the patterned photoresist layer is removed, that is, the semiconductor element 1 having the tantalum perforated electrode of the present invention is completed. Therefore, the semiconductor device 1 of the present invention comprises a substrate 10 having a front surface 12 and a back surface 14, an interlayer dielectric layer 22 covering the front surface 12 of the substrate 10, and a mask layer 26 covering the substrate 10. The back surface 14, a perforated electrode 44, extends through the mask layer 26, the substrate 10, and the interlayer dielectric layer 22, wherein the germanium via electrode 44 has a mask layer sidewall 34 and a substrate sidewall 32, and the sidewall of the mask layer The base side wall 32 is protruded in a horizontal direction; and a backing layer 36 is disposed on the base side wall 32 of the base perforated electrode 44, and the backing layer 36 partially overlaps the mask layer 26. In addition, at least one gate structure 18 is disposed in the interlayer dielectric layer 22. The gate structure 18 includes a metal gate, a polysilicon gate or a dummy gate.

A conventional defect in the perforated electrode process has the disadvantage of selectively depositing a liner layer electrochemically, etc., when the diameter of the interior of the crucible electrode is equal to the diameter formed by the sidewall of the mask layer. On the sidewall of the substrate, the liner layer protrudes from the sidewall of the mask layer by a horizontal distance, and a corner is formed at the interface between the sidewall of the mask layer and the liner layer, which may further increase leakage current. produce. In general, the perforated electrode is connected to various semiconductor elements such as a transistor, a memory, an inductor, a resistor, etc., and various kinds of stylized processes can be performed. Since the perforated electrode acts as a power pin, when an external power source passes, strong electromagnetic interference (EMI) is generated, and interference is generated to a semiconductor element such as a gate structure located near the perforated electrode.

The invention is characterized in that an opening 30 is formed before the formation of the perforation 38, and during the formation of the opening, the substrate sidewall 32 is excessively uniformly etched such that the diameter a formed by the substrate sidewall 32 is larger than that of the mask layer. The diameter b formed by the side walls 34 is such that when the backing layer 36 is formed on the side wall 32 of the substrate, the backing layer 36 is substantially flush with the surface of the side wall 34 of the mask layer, so that the side walls 34 and the backing layer of the mask layer are not present. The junction of 36 produces a lobed corner that reduces the likelihood of leakage current generation. The method provided by the invention can effectively improve the process yield.

It can be understood that the present invention is applicable to various ruthenium perforated electrode processes, of course, not limited to the via last process, but also to the via middle process, or various lobes may be generated. The semiconductor component is in accordance with the present invention as long as it has a predetermined length between the sidewall of the substrate and the sidewall of the mask layer in a uniform over-etching manner, and then deposits a liner layer on the sidewall of the substrate by selective deposition. Within the scope covered.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

1‧‧‧Semiconductor components

10‧‧‧Base

12‧‧‧ positive

14‧‧‧ Back

16‧‧‧Shallow trench isolation

18‧‧‧ gate structure

20‧‧‧Source/bungee area

22‧‧‧Interlayer dielectric layer

24‧‧‧Metal lines

26‧‧‧ mask layer

28‧‧‧Contact plug

30‧‧‧ openings

32‧‧‧Base side wall

34‧‧‧Mask side wall

36‧‧‧ liner

38‧‧‧矽 piercing

40‧‧‧Barrier layer

42‧‧‧Main conductive layer

44‧‧‧矽perforated electrode

1 to 7 are views showing a process of manufacturing a semiconductor device according to a first preferred embodiment of the present invention.

1‧‧‧Semiconductor components

10‧‧‧Base

12‧‧‧ positive

14‧‧‧ Back

16‧‧‧Shallow trench isolation

18‧‧‧ gate structure

20‧‧‧Source/bungee area

22‧‧‧Interlayer dielectric layer

24‧‧‧Metal lines

26‧‧‧ mask layer

28‧‧‧Contact plug

32‧‧‧Base side wall

34‧‧‧Mask side wall

36‧‧‧ liner

40‧‧‧Barrier layer

42‧‧‧Main conductive layer

44‧‧‧矽perforated electrode

Claims (20)

A semiconductor device comprising: a substrate having a front surface and a back surface; an interlayer dielectric layer overlying the front surface of the substrate; a mask layer covering the back surface of the substrate; and a via electrode passing through the mask a layer, the substrate and the interlayer dielectric layer, wherein the ruthenium perforated electrode has a mask layer sidewall and a substrate sidewall, and the mask layer sidewall protrudes the substrate sidewall by a predetermined length; and a liner layer is located at the The substrate sidewall of the via electrode is interdigitated and the liner layer partially overlaps the mask layer. A semiconductor component as claimed in claim 1 further comprising a metal line on the interlayer dielectric layer. The semiconductor component of claim 1, further comprising a conductive layer in the via electrode. The semiconductor component of claim 1, wherein a sidewall of the spacer layer is aligned with a sidewall of the mask layer. The semiconductor component of claim 1, wherein a sidewall of the spacer layer protrudes from the sidewall of the mask layer. The semiconductor component of claim 1, wherein the sidewall of the mask layer protrudes from a sidewall of the liner layer. The semiconductor component of claim 1, wherein the liner layer is only located in the substrate. The semiconductor component of claim 1, wherein the spacer layer overlaps the mask layer by a width greater than 10 nm. The semiconductor component of claim 1, further comprising a barrier layer in the via electrode. The semiconductor device of claim 1, further comprising at least one gate structure disposed in the interlayer dielectric layer, wherein the gate structure comprises a metal gate, a polysilicon gate or a dummy gate (dummy gate) ). A semiconductor device manufacturing method comprising the steps of: providing a substrate having a front surface and a back surface; forming an interlayer dielectric layer on a front surface of the substrate; forming a mask layer on the back surface of the substrate; etching the The back surface of the substrate is formed with an opening extending through the mask layer and the substrate, wherein a sidewall of the mask layer and a sidewall of the substrate are formed in the opening, and the sidewall of the mask layer protrudes a predetermined length of the sidewall of the substrate; Selectively depositing a liner layer on the sidewall of the substrate, and the liner layer at least partially overlaps the mask layer; etching the interlayer dielectric layer through the opening to form a perforation of the crucible to form a perforation through the interlayer a dielectric layer; and forming a conductive layer within the crucible. The method of fabricating a semiconductor device according to claim 11, wherein a width of the portion of the spacer layer overlapping the mask layer is greater than 10 nm. The method of fabricating a semiconductor device according to claim 11, further comprising forming a metal line on the interlayer dielectric layer. The method of fabricating a semiconductor device according to claim 13, wherein the crucible is exposed to the metal line. The semiconductor device manufacturing method of claim 13, further comprising forming a barrier layer in the crucible. The method of fabricating a semiconductor device according to claim 11, further comprising forming at least one gate structure in the interlayer dielectric layer. The method of fabricating a semiconductor device according to claim 16, wherein the gate structure comprises a metal gate, a polysilicon gate or a dummy gate. The method of fabricating a semiconductor device according to claim 11, wherein the opening exposes the interlayer dielectric layer. The method of fabricating a semiconductor device according to claim 11, wherein the liner layer is formed on the sidewall of the substrate in the opening by electrochemical or atomic layer deposition. The method of fabricating a semiconductor device according to claim 11, further comprising forming at least one shallow trench to be isolated in the substrate.