TW201401507A - Semiconductor device and fabricating method thereof - Google Patents
Semiconductor device and fabricating method thereof Download PDFInfo
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Abstract
Description
本發明提供一種半導體元件,特別是一種具有矽穿孔的半導體元件。 The present invention provides a semiconductor device, particularly a semiconductor device having a via hole.
在現代的資訊社會中,由積體電路所構成的微處理機系統早已被普遍運用於生活的各個層面,例如自動控制之家電用品、行動通訊設備、個人電腦等,都有積體電路之蹤跡。而隨著科技的日益精進,以及人類社會對於電子產品的各種想像,使得積體電路也往更多元、更精密、更小型的方向發展。 In the modern information society, the microprocessor system consisting of integrated circuits has been widely used in all aspects of life, such as automatic control of household appliances, mobile communication devices, personal computers, etc., all of which have traces of integrated circuits. . With the increasing advancement of technology and the imagination of human society for electronic products, the integrated circuit has also developed in the direction of more yuan, more precision and smaller.
一般所謂積體電路,是透過習知半導體製程中所生產的晶粒(die)而形成。製造晶粒的過程,係由生產一晶圓(wafer)開始:首先,在一片晶圓上區分出多個區域,並在每個區域上,透過各種半導體製程如沈積、微影、蝕刻或平坦化步驟,以形成各種所需之電路路線,接著,再對晶圓上的各個區域進行切割而成各個晶粒,並加以封裝成晶片(chip),最後再將晶片電連至一電路板,如一印刷電路板(printed circuit board,PCB),使晶片與印刷電路板的接腳(pin)電性連結後,便可執行各種程式化之處理。 Generally, an integrated circuit is formed by a die produced in a conventional semiconductor process. The process of fabricating a die begins with the production of a wafer: first, a plurality of regions are distinguished on a wafer, and in each region, through various semiconductor processes such as deposition, lithography, etching, or flattening. The steps to form various required circuit paths, and then, the respective regions on the wafer are cut into individual chips, packaged into chips, and finally the wafer is electrically connected to a circuit board. Such as a printed circuit board (PCB), after the chip is electrically connected to the pins of the printed circuit board, a variety of stylized processing can be performed.
為了提高晶片功能與效能,增加積集度以便在有限空間下能容納更多半導體元件,相關廠商開發出許多半導體晶片的堆疊技術,包括了覆晶封裝(Flip-Chip)技術、多晶片封裝(Multi-chip Package,MCP)技術、封裝堆疊(Package on Package,PoP)技術、封裝內藏封裝體(Package in Package,PiP)技術等,都可以藉由晶粒或封裝體之間彼此的堆疊來增加單位體積內半導體元件的積集度。而在上述各種封裝架構下,近年來又發展一種稱為矽穿孔(Through silicon via,TSV)之技術,可促進在封裝體中各晶粒彼此之間的內部連結(interconnect),以將堆疊效率進一步往上提升。 In order to improve the function and performance of the wafer and increase the degree of integration to accommodate more semiconductor components in a limited space, the related manufacturers have developed a number of semiconductor wafer stacking technologies, including flip chip technology (Flip-Chip) technology, multi-chip package ( Multi-chip Package (MCP) technology, package on package (PoP) technology, package in package (PiP) technology, etc., can be stacked by die or package. Increase the degree of integration of semiconductor components per unit volume. Under the above various package architectures, a technology called Through Silicon Via (TSV) has been developed in recent years to promote internal interconnection of the crystal grains in the package to improve stacking efficiency. Further advancement.
矽穿孔原理是在晶圓中以蝕刻或雷射的方式形成貫穿晶圓的通孔(Via),再將導電材料如銅、多晶矽、鎢等填入通孔,最後則將晶圓或晶粒薄化並加以堆疊、結合(Bonding),而成為3D立體之晶粒堆疊結構。由於應用矽穿孔技術之各晶片內部線路之連結路徑最短,相較於其他堆疊技術,可使晶片間的傳輸速度更快、雜訊更小、效能更佳,是目前遠景看好的技術之一。 The principle of boring is to form a through-wafer via in the wafer by etching or laser, and then fill a via hole with a conductive material such as copper, polysilicon, tungsten, etc., and finally wafer or die. Thinned and stacked, Bonded, and become a 3D solid crystal grain stack structure. Since the connection path of the internal lines of each chip is the shortest, the transmission speed between the wafers is faster, the noise is smaller, and the performance is better, which is one of the currently promising technologies.
本發明提供一種半導體元件,包含有一基底具有一正面以及一背面,一層間介電層,覆蓋於該基底的正面上,一遮罩層,覆蓋於該基底背面,一矽穿孔電極,貫穿該遮罩層、該基底以及該層間介電 層,其中該矽穿孔電極內具有一遮罩層側壁與一基底側壁,且該遮罩層側壁突出該基底側壁一預定長度,以及一襯墊層,位於該矽穿孔內的該基底側壁,且該襯墊層與該遮罩層有部分重疊。 The present invention provides a semiconductor device comprising a substrate having a front surface and a back surface, an interlayer dielectric layer overlying the front surface of the substrate, a mask layer covering the back surface of the substrate, and a via electrode extending through the mask Cover layer, the substrate, and the interlayer dielectric a layer, wherein the sidewall electrode has a mask sidewall and a substrate sidewall, and the mask layer sidewall protrudes from the substrate sidewall by a predetermined length, and a liner layer is located on the substrate sidewall in the bore The liner layer partially overlaps the mask layer.
根據本發明的另一較佳實施例,本發明提供一種製作半導體元件的方法,包含以下步驟:首先,提供一基底,該基底具有一正面以及一背面;形成一層間介電層於該基底的正面上,接著形成一遮罩層於該基底的背面上,再蝕刻該基底背面,形成一開口貫穿該遮罩層以及該基底,其中於該開口內具有一遮罩層側壁與一基底側壁,該遮罩層側壁突出該基底側壁一預定長度,然後選擇性沉積一襯墊層於該開口內基底的側壁,且該襯墊層與該遮罩層至少有部分重疊,之後蝕刻該開口,形成一矽穿孔貫穿該層間介電層,以及形成一導電層於該矽穿孔內。 According to another preferred embodiment of the present invention, the present invention provides a method of fabricating a semiconductor device, comprising the steps of: first, providing a substrate having a front surface and a back surface; forming an interlayer dielectric layer on the substrate On the front side, a mask layer is formed on the back surface of the substrate, and the back surface of the substrate is etched to form an opening through the mask layer and the substrate, wherein a mask layer sidewall and a substrate sidewall are disposed in the opening. The sidewall of the mask layer protrudes from the sidewall of the substrate by a predetermined length, and then selectively deposits a liner layer on the sidewall of the substrate in the opening, and the liner layer at least partially overlaps the mask layer, and then etches the opening to form A via is inserted through the interlayer dielectric layer and a conductive layer is formed in the via.
為使熟習本發明所屬技術領域之一般技藝者能更進一步了解本發明,下文特列舉本發明之較佳實施例,並配合所附圖式,詳細說明本發明的構成內容及所欲達成之功效。 The present invention will be further understood by those of ordinary skill in the art to which the present invention pertains. .
為了方便說明,本發明之各圖式僅為示意以更容易了解本發明,其詳細的比例可依照設計的需求進行調整。在文中所描述對於圖形中相對元件之上下關係,在本領域之人皆應能理解其係指物 件之相對位置而言,因此皆可以翻轉而呈現相同之構件,此皆應同屬本說明書所揭露之範圍,在此容先敘明。 For the convenience of description, the drawings of the present invention are only for the purpose of understanding the present invention, and the detailed proportions thereof can be adjusted according to the design requirements. As described in the text for the relative relationship between the relative elements in the figure, anyone in the field should be able to understand the reference The relative positions of the components, therefore, can be reversed to present the same components, which are all within the scope of the present disclosure, which will be described first.
請先參考第1~7圖,第1~7圖繪示了本發明之第一較佳實施例之半導體元件的製程示意圖。如第1圖所示,半導體元件首先,提供一基底10,例如是矽基底(silicon substrate)、磊晶矽(epitaxial silicon substrate)、矽鍺半導體基底(silicon germanium substrate)、碳化矽基底(silicon carbide substrate)或絕緣層上覆矽基底(silicon-on-insulator,SOI)等,本發明之一較佳實施例係以塊狀矽基底(bulk silicon substrate)為例,但不以此為限,基底10具有一正面12與一背面14,接著,形成所需的各種離子井(N-well or P-well)(圖未示)以及複數個淺溝渠隔離(shallow trench isolation)16於基底10中。 Please refer to FIGS. 1-7. FIG. 1 to FIG. 7 are schematic diagrams showing the manufacturing process of the semiconductor device according to the first preferred embodiment of the present invention. As shown in FIG. 1, the semiconductor device first provides a substrate 10, such as a silicon substrate, an epitaxial silicon substrate, a silicon germanium substrate, or a silicon carbide substrate. A substrate or a silicon-on-insulator (SOI) or the like, a preferred embodiment of the present invention is a bulk silicon substrate, but not limited thereto. 10 has a front side 12 and a back side 14, and then forms the desired various N-well or P-wells (not shown) and a plurality of shallow trench isolations 16 in the substrate 10.
接著如第2圖所示,形成至少一閘極結構18於基底10上,並以離子佈植等方法形成源/汲極區域20於閘極結構18的兩側基底10中。閘極結構18可為多晶矽閘極(polysilicon gate)、金屬閘極(metal gate)或是虛置閘極(dummy gate)等,而形成上述閘極結構18與源/汲極區域20、甚或再於源/汲極區域20表面上形成自對準金屬矽化物(salicide)(圖未示)的方法,皆為本領域常見技術,在此不再贅述。然後覆蓋一層間介電層22於閘極結構18與正面12上,並接續再進行一金屬內連線製程,以於層間介電層22上製備複數層金屬層間介電層(IMD)(圖未示)以及設置於各金屬層間介電層中所需的金屬 線路(圖未示)。 Next, as shown in FIG. 2, at least one gate structure 18 is formed on the substrate 10, and the source/drain regions 20 are formed in the substrate 10 on both sides of the gate structure 18 by ion implantation or the like. The gate structure 18 can be a polysilicon gate, a metal gate or a dummy gate, etc., to form the gate structure 18 and the source/drain region 20, or even A method of forming a self-aligned metal salicide (not shown) on the surface of the source/drain region 20 is common in the art and will not be described herein. Then, an interlayer dielectric layer 22 is overlaid on the gate structure 18 and the front surface 12, and then a metal interconnect process is further performed to prepare a plurality of metal interlayer dielectric layers (IMD) on the interlayer dielectric layer 22 (Fig. Not shown) and the metal required to be placed in the dielectric layer between the metal layers Line (not shown).
為了方便說明起見,第2圖僅繪示形成一對應於後續製作之矽穿孔(TSV)的金屬線路24於層間介電層22表面,而省略其他的金屬線路與各金屬層間介電層,且該金屬線路24底面可直接接觸後續形成之矽穿孔(TSV)並藉由其上方金屬層間介電層(IMD)中的金屬線路(圖未示)與其他元件分別電性連接。此外,層間介電層22與基底10之間還可選擇性形成有一接觸蝕刻停止層(CESL)(圖未示)覆蓋閘極結構18與源/汲極區域20,以及複數個接觸插塞28分別位於閘極結構18與源/汲極區域20上,用來電性連接層間介電層22上方之金屬層間介電層(IMD)中的金屬線路(圖未示),本實施例中,金屬線路24與接觸插塞28之材料可選自導電性良好的金屬,如銅、鋁、鎢、鈦、氮化鈦、鉭以及氮化鉭所組成的群組,但不限於此。 For convenience of description, FIG. 2 only shows that a metal line 24 corresponding to a subsequently formed turns (TSV) is formed on the surface of the interlayer dielectric layer 22, and other metal lines and dielectric layers between the metal layers are omitted. The bottom surface of the metal line 24 can directly contact the subsequently formed via via (TSV) and be electrically connected to other components by metal lines (not shown) in the upper inter-metal dielectric layer (IMD). In addition, a contact etch stop layer (CESL) (not shown) may be selectively formed between the interlayer dielectric layer 22 and the substrate 10 to cover the gate structure 18 and the source/drain regions 20, and a plurality of contact plugs 28 They are respectively disposed on the gate structure 18 and the source/drain region 20 for electrically connecting metal lines (not shown) in the inter-metal dielectric layer (IMD) above the interlayer dielectric layer 22, in this embodiment, the metal The material of the line 24 and the contact plug 28 may be selected from the group consisting of a conductive metal such as copper, aluminum, tungsten, titanium, titanium nitride, tantalum, and tantalum nitride, but is not limited thereto.
在完成基底10正面12上之金屬內連線製程以及設置於金屬層間介電層上的銲墊(bonding pad)製程之後。接著由基底10背面14來薄化基底10,並全面性形成一遮罩層26於基底10的背面14上,遮罩層26材料例如為二氧化矽(SiO2)、氮化矽(SiN)、碳化矽(SiC)或氮氧化矽(SiON)等絕緣物,但不限於此,本發明中係以氮化矽為例。 After the metal interconnection process on the front side 12 of the substrate 10 and the bonding pad process on the dielectric layer between the metal layers are completed. Next, the substrate 10 is thinned by the back surface 14 of the substrate 10, and a mask layer 26 is formed on the back surface 14 of the substrate 10. The material of the mask layer 26 is, for example, cerium oxide (SiO 2 ) or tantalum nitride (SiN). An insulator such as tantalum carbide (SiC) or bismuth oxynitride (SiON) is not limited thereto, and in the present invention, tantalum nitride is exemplified.
如第3圖所示,利用微影暨蝕刻方式,於基底10背面14形成至少一開口30以定義出矽穿孔(TSV)的位置。開口30貫穿遮罩層26與基底10,且開口30的底部停留在層間介電層22的底面上。此時,開口30內部的側壁可概分為一基底側壁32與一遮罩層側壁34。 As shown in FIG. 3, at least one opening 30 is formed on the back surface 14 of the substrate 10 by lithography and etching to define the position of the ruthenium perforation (TSV). The opening 30 extends through the mask layer 26 and the substrate 10, and the bottom of the opening 30 rests on the bottom surface of the interlayer dielectric layer 22. At this time, the side wall inside the opening 30 can be roughly divided into a base side wall 32 and a mask layer side wall 34.
其中值得注意的是,在基底10背面14蝕刻出開口30後,如第4圖所示,本發明會再進行一退縮製程(pull back process),用以均勻地擴展基底側壁32,也就是說,在開口30內部,由基底側壁32所形成的一開口直徑a,比起遮罩層側壁34所形成的一開口直徑b更大,導致從圖上看來,遮罩層側壁34凸出基底側壁32一預定長度d(a predetermined distance),其中d=(a-b)/2,該退縮蝕刻可包含一般之濕式蝕刻,例如氫氟酸(hydrofluoric acid,HF)混合乙二醇(ethylene glycol,EG),或是等向性電漿蝕刻,俾以選擇性地蝕刻遮罩層26與基底10,但不限於此。 It should be noted that after the opening 30 is etched on the back surface 14 of the substrate 10, as shown in FIG. 4, the present invention further performs a pull back process for uniformly expanding the substrate sidewall 32, that is, Inside the opening 30, an opening diameter a formed by the side wall 32 of the substrate is larger than an opening diameter b formed by the side wall 34 of the mask layer, so that the side wall 34 of the mask layer protrudes from the front in the figure. The sidewall 32 has a predetermined length d (a predetermined distance), wherein d = (ab)/2, and the shrink etching may include a general wet etching such as hydrofluoric acid (HF) mixed ethylene glycol (ethylene glycol, EG), or an isotropic plasma etch, to selectively etch the mask layer 26 and the substrate 10, but is not limited thereto.
此外,本實施例係先形成開口30,然後再以退縮製程擴展基底側壁32,然而本發明卻不限於此,也可以調整蝕刻選擇比的方式,僅以一次蝕刻形成開口30,並同時形成擴展的基底側壁32。 In addition, in this embodiment, the opening 30 is formed first, and then the substrate sidewall 32 is expanded by the retracting process. However, the present invention is not limited thereto, and the etching selectivity ratio may be adjusted to form the opening 30 only by one etching, and at the same time form an extension. Substrate sidewall 32.
接著如第5圖所示,選擇性地沉積一襯墊層36於該開口30內的基底側壁32上,襯墊層36材料例如為氮化矽(SiN)或氧化矽 (SiO2)等單一材料層或複合結構層,但不限於此。值得注意的是,襯墊層36可藉由電化學或氧化等方式,選擇性形成在基底側壁32上,而不形成於遮罩層側壁34上。例如,襯墊層36可以電化學等方式,僅形成於具導體性質之基底側壁32上,也就是說,襯墊層36並不形成於不具導體性質之遮罩層側壁34上。由於上述以退縮製程蝕刻的方式,使得基底側壁32與遮罩層側壁34在水平方向相差一預定長度d,此預定長度d所形成的一預定空間位於基底側壁32上,襯墊層36沉積於該預定空間內,使襯墊層36與遮罩層26至少重疊一寬度,且兩者交界處不容易產生凸角而造成漏電流。本實施例中,襯墊層36與遮罩層26的重疊的部份寬度較佳大於10奈米(10nm),使襯墊層36與遮罩層26的交界處具有較好的密合性,而更能有效地防止漏電流發生。此外,形成襯墊層36於該預定空間後,襯墊層36的側壁可與遮罩層側壁34切齊,或是並不與之切齊,也就是說,襯墊層36的側壁可以突出遮罩層側壁34,或是反之,遮罩層側壁34突出襯墊層36的側壁。然而,無論襯墊層36的側壁與遮罩層側壁34切齊與否,較佳應滿足襯墊層36與遮罩層26的重疊的部分寬度大於10奈米的條件。 Next, as shown in FIG. 5, a liner layer 36 is selectively deposited on the substrate sidewall 32 in the opening 30. The liner layer 36 is made of a single material such as tantalum nitride (SiN) or yttrium oxide (SiO 2 ). A material layer or a composite structure layer, but is not limited thereto. It should be noted that the liner layer 36 can be selectively formed on the sidewalls 32 of the substrate by electrochemical or oxidation, etc., without being formed on the sidewalls 34 of the mask layer. For example, the liner layer 36 can be formed only on the sidewalls 32 of the substrate having electrical properties, such as the liner layer 36, that is, the liner layer 36 is not formed on the sidewalls 34 of the mask layer that are not of a conductive nature. Due to the above-described retracting process etching, the substrate sidewall 32 and the mask layer sidewall 34 are horizontally different by a predetermined length d, and a predetermined space formed by the predetermined length d is located on the substrate sidewall 32, and the liner layer 36 is deposited on the substrate. In the predetermined space, the spacer layer 36 and the mask layer 26 are overlapped at least by a width, and a bump is not easily generated at the boundary between the two to cause a leakage current. In this embodiment, the overlap width of the pad layer 36 and the mask layer 26 is preferably greater than 10 nm (10 nm), so that the interface between the pad layer 36 and the mask layer 26 has good adhesion. It is more effective in preventing leakage current from occurring. In addition, after the spacer layer 36 is formed in the predetermined space, the sidewall of the liner layer 36 may be aligned with or not aligned with the sidewalls 34 of the mask layer, that is, the sidewalls of the liner layer 36 may protrude. The mask layer sidewalls 34, or vice versa, the mask layer sidewalls 34 protrude from the sidewalls of the liner layer 36. However, regardless of whether the sidewall of the liner layer 36 is aligned with the sidewalls 34 of the mask layer, it is preferred to satisfy the condition that the portion of the overlap of the liner layer 36 and the mask layer 26 is greater than 10 nanometers.
再如第6~7圖所示,對開口30再次進行一蝕刻步驟,以形成一矽穿孔38,且矽穿孔38的底部停留在金屬線路24的底面上。之後,可選擇性地在矽穿孔38內部先形成一阻障層40,再覆蓋一導電層42於矽穿孔38內以及背面14以形成矽穿孔電極44,阻障層40可選自鈦、氮化鈦、鉭以及氮化鉭所組成的群組,導電層42材料可選自導電性良好的金屬,而其形成方法,以銅為例,可 在沉積阻障層40之後,即先形成一銅之晶種層(圖未示),然後進行一晶背凸塊的黃光製程以形成一圖案化的光阻層(圖未示),接著在電鍍銅之後,去除圖案化的光阻層,即完成本發明之具有矽穿孔電極的半導體元件1。因此,本發明的半導體元件1包含有一基底10,基底有一正面12以及一背面14,一層間介電層22,覆蓋於該基底10的正面12上;一遮罩層26,覆蓋於該基底10的背面14,一矽穿孔電極44,貫穿遮罩層26、基底10以及該層間介電層22,其中矽穿孔電極44內具有一遮罩層側壁34與一基底側壁32,且遮罩層側壁34於水平方向突出基底側壁32;以及一襯墊層36,位於該矽穿孔電極44內的基底側壁32上,且襯墊層36與遮罩層26有部分重疊。此外,另有至少一閘極結構18設置於層間介電層22中,其閘極結構18包括金屬閘極、多晶矽閘極或是虛置閘極(dummy gate)等。 Further, as shown in FIGS. 6-7, an opening step is performed on the opening 30 again to form a turn-by-hole 38, and the bottom of the turn-by-hole 38 rests on the bottom surface of the metal line 24. Thereafter, a barrier layer 40 is selectively formed inside the via hole 38, and a conductive layer 42 is covered in the via hole 38 and the back surface 14 to form a via electrode 44. The barrier layer 40 may be selected from titanium and nitrogen. A group consisting of titanium, tantalum and tantalum nitride, the material of the conductive layer 42 may be selected from a metal having good conductivity, and the method for forming the same may be copper. After depositing the barrier layer 40, a copper seed layer (not shown) is formed, and then a yellow back process of a crystal back bump is performed to form a patterned photoresist layer (not shown), and then After electroplating the copper, the patterned photoresist layer is removed, that is, the semiconductor element 1 having the tantalum perforated electrode of the present invention is completed. Therefore, the semiconductor device 1 of the present invention comprises a substrate 10 having a front surface 12 and a back surface 14, an interlayer dielectric layer 22 covering the front surface 12 of the substrate 10, and a mask layer 26 covering the substrate 10. The back surface 14, a perforated electrode 44, extends through the mask layer 26, the substrate 10, and the interlayer dielectric layer 22, wherein the germanium via electrode 44 has a mask layer sidewall 34 and a substrate sidewall 32, and the sidewall of the mask layer The base side wall 32 is protruded in a horizontal direction; and a backing layer 36 is disposed on the base side wall 32 of the base perforated electrode 44, and the backing layer 36 partially overlaps the mask layer 26. In addition, at least one gate structure 18 is disposed in the interlayer dielectric layer 22. The gate structure 18 includes a metal gate, a polysilicon gate or a dummy gate.
習知的矽穿孔電極製程有一缺點,那就是當矽穿孔電極內部由基底側壁所形成的直徑與由遮罩層側壁所形成的直徑相等時,以電化學等方式,選擇性沉積一襯墊層於基底側壁上,會造成襯墊層突出遮罩層側壁一水平距離,而導致遮罩層側壁與襯墊層的交界處產生一凸角(corner),該凸角可能會進一步增加漏電流的產生。一般而言,矽穿孔電極連接各種半導體元件如電晶體、記憶體、電感、電阻等,而可執行各種程式化之處理。由於矽穿孔電極作為電力接腳,當外部電源通過時,會產生強大的電磁干擾(electromagnetic interference,EMI),而對位於矽穿孔電極附近的半導體元件如閘極結構產生干擾雜訊。 A conventional defect in the perforated electrode process has the disadvantage of selectively depositing a liner layer electrochemically, etc., when the diameter of the interior of the crucible electrode is equal to the diameter formed by the sidewall of the mask layer. On the sidewall of the substrate, the liner layer protrudes from the sidewall of the mask layer by a horizontal distance, and a corner is formed at the interface between the sidewall of the mask layer and the liner layer, which may further increase leakage current. produce. In general, the perforated electrode is connected to various semiconductor elements such as a transistor, a memory, an inductor, a resistor, etc., and various kinds of stylized processes can be performed. Since the perforated electrode acts as a power pin, when an external power source passes, strong electromagnetic interference (EMI) is generated, and interference is generated to a semiconductor element such as a gate structure located near the perforated electrode.
本發明的特徵在於,形成矽穿孔38前,先形成一開口30,且形成開口的過程中,對基底側壁32進行過度的均勻蝕刻,使得由基底側壁32所形成的直徑a大於由遮罩層側壁34所形成的直徑b,使襯墊層36形成於基底側壁32上時,襯墊層36與遮罩層側壁34表面大致上切齊,所以不會在遮罩層側壁34與襯墊層36的交界處產生凸角,而降低漏電流產生的可能性。本發明所提供的方式,可以有效提高製程良率。 The invention is characterized in that an opening 30 is formed before the formation of the perforation 38, and during the formation of the opening, the substrate sidewall 32 is excessively uniformly etched such that the diameter a formed by the substrate sidewall 32 is larger than that of the mask layer. The diameter b formed by the side walls 34 is such that when the backing layer 36 is formed on the side wall 32 of the substrate, the backing layer 36 is substantially flush with the surface of the side wall 34 of the mask layer, so that the side walls 34 and the backing layer of the mask layer are not present. The junction of 36 produces a lobed corner that reduces the likelihood of leakage current generation. The method provided by the invention can effectively improve the process yield.
可理解的是,本發明適用於各種矽穿孔電極製程,當然,並不限於後矽穿孔製程(via last process),也可適用於中矽穿孔製程(via middle process),或各種可能產生凸角的半導體元件,只要符合:以均勻過度蝕刻的方式,讓基底側壁與遮罩層側壁之間留有一預定長度,再以選擇性沉積方式,沉積一襯墊層於基底側壁上,皆屬於本發明所涵蓋的範圍內。 It can be understood that the present invention is applicable to various ruthenium perforated electrode processes, of course, not limited to the via last process, but also to the via middle process, or various lobes may be generated. The semiconductor component is in accordance with the present invention as long as it has a predetermined length between the sidewall of the substrate and the sidewall of the mask layer in a uniform over-etching manner, and then deposits a liner layer on the sidewall of the substrate by selective deposition. Within the scope covered.
以上所述僅為本發明之較佳實施例,凡依本發明申請專利範圍所做之均等變化與修飾,皆應屬本發明之涵蓋範圍。 The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.
1‧‧‧半導體元件 1‧‧‧Semiconductor components
10‧‧‧基底 10‧‧‧Base
12‧‧‧正面 12‧‧‧ positive
14‧‧‧背面 14‧‧‧ Back
16‧‧‧淺溝渠隔離 16‧‧‧Shallow trench isolation
18‧‧‧閘極結構 18‧‧‧ gate structure
20‧‧‧源/汲極區域 20‧‧‧Source/bungee area
22‧‧‧層間介電層 22‧‧‧Interlayer dielectric layer
24‧‧‧金屬線路 24‧‧‧Metal lines
26‧‧‧遮罩層 26‧‧‧ mask layer
28‧‧‧接觸插塞 28‧‧‧Contact plug
30‧‧‧開口 30‧‧‧ openings
32‧‧‧基底側壁 32‧‧‧Base side wall
34‧‧‧遮罩層側壁 34‧‧‧Mask side wall
36‧‧‧襯墊層 36‧‧‧ liner
38‧‧‧矽穿孔 38‧‧‧矽 piercing
40‧‧‧阻障層 40‧‧‧Barrier layer
42‧‧‧主導電層 42‧‧‧Main conductive layer
44‧‧‧矽穿孔電極 44‧‧‧矽perforated electrode
第1~7圖繪製本發明第一較佳實施例的半導體元件的製程示意圖。 1 to 7 are views showing a process of manufacturing a semiconductor device according to a first preferred embodiment of the present invention.
1‧‧‧半導體元件 1‧‧‧Semiconductor components
10‧‧‧基底 10‧‧‧Base
12‧‧‧正面 12‧‧‧ positive
14‧‧‧背面 14‧‧‧ Back
16‧‧‧淺溝渠隔離 16‧‧‧Shallow trench isolation
18‧‧‧閘極結構 18‧‧‧ gate structure
20‧‧‧源/汲極區域 20‧‧‧Source/bungee area
22‧‧‧層間介電層 22‧‧‧Interlayer dielectric layer
24‧‧‧金屬線路 24‧‧‧Metal lines
26‧‧‧遮罩層 26‧‧‧ mask layer
28‧‧‧接觸插塞 28‧‧‧Contact plug
32‧‧‧基底側壁 32‧‧‧Base side wall
34‧‧‧遮罩層側壁 34‧‧‧Mask side wall
36‧‧‧襯墊層 36‧‧‧ liner
40‧‧‧阻障層 40‧‧‧Barrier layer
42‧‧‧主導電層 42‧‧‧Main conductive layer
44‧‧‧矽穿孔電極 44‧‧‧矽perforated electrode
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TWI555152B (en) * | 2014-04-25 | 2016-10-21 | 台灣積體電路製造股份有限公司 | Semiconductor structure and fabricating method thereof |
TWI723762B (en) * | 2019-05-31 | 2021-04-01 | 台灣積體電路製造股份有限公司 | Integrated circuit and method for forming the same |
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Cited By (5)
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TWI555152B (en) * | 2014-04-25 | 2016-10-21 | 台灣積體電路製造股份有限公司 | Semiconductor structure and fabricating method thereof |
US9601411B2 (en) | 2014-04-25 | 2017-03-21 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor structure |
TWI723762B (en) * | 2019-05-31 | 2021-04-01 | 台灣積體電路製造股份有限公司 | Integrated circuit and method for forming the same |
US11062977B2 (en) | 2019-05-31 | 2021-07-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Shield structure for backside through substrate vias (TSVs) |
US11764129B2 (en) | 2019-05-31 | 2023-09-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of forming shield structure for backside through substrate vias (TSVS) |
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