JP2014170793A - Semiconductor device, semiconductor device manufacturing method and electronic apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To inhibit scattering and outflow of a solder at the time of joining of a semiconductor chip to be stacked.SOLUTION: A semiconductor chip 1 comprises: a semiconductor substrate 10 on which an element region 20 including a semiconductor element is provided on a surface 10a; terminals 61 each of which is buried in a rear face 10b of the semiconductor substrate 10 and includes a recess 64; and a TSV 60 connected to the terminal 61, respectively. Terminals 140 of a semiconductor chip 100 to be stacked are inserted into the recesses 64 of the semiconductor chip 1 and bonded to the terminals 61 by joint materials 150. By providing the recess 64 on the terminal 61 of the semiconductor chip 1, scattering and outflow of the joint material 150 which melts at the time of joining are inhibited.

Description

  The present invention relates to a semiconductor device, a method for manufacturing the semiconductor device, and an electronic device including the semiconductor device.

A three-dimensional integration technique is known in which a plurality of electronic components such as a plurality of semiconductor chips are stacked and electrically connected.
With regard to a three-dimensional integration technique of a semiconductor chip, a technique is known in which a through electrode (also referred to as TSV (Through Silicon Via)) is provided on a semiconductor substrate such as a silicon substrate used in the semiconductor chip. As the through electrode, there are a via hole provided in a semiconductor substrate filled with a conductive material, and a through electrode provided with a conductive material conformally inside the via hole.

  With respect to a semiconductor chip provided with a through electrode, a technique for providing a terminal electrically connected to the through electrode is known. Here, the term “terminal” refers to a conductor provided for electrically connecting a semiconductor chip and another semiconductor chip. Regarding the terminal, a technology for forming a terminal protruding on the side of the semiconductor chip stacked on the semiconductor chip, or a groove on the surface of the semiconductor chip on the side of the semiconductor chip stacked on the semiconductor chip, the conductive in the groove A technique for filling a material to form a terminal is known.

JP 2011-249563 A JP 2010-157656 A JP 2009-302453 A JP 2007-142026 A JP 2010-129749 A JP 2010-263208 A

  In the three-dimensional integration of semiconductor chips, for example, terminals provided on the upper semiconductor chip are joined to terminals provided on the lower semiconductor chip using solder. However, the terminal of the upper semiconductor chip is soldered to the protruding terminal formed on the lower semiconductor chip as described above or the terminal formed by filling the groove provided in the lower semiconductor chip with a conductive material. When doing so, there is a risk of short-circuiting between the terminal joints due to the scattering or outflow of the solder.

  According to an aspect of the present invention, a semiconductor substrate provided with a semiconductor element on a first surface, and a first terminal embedded in a second surface opposite to the first surface of the semiconductor substrate and provided with a recess. A semiconductor device including a via provided in the semiconductor substrate and electrically connected to the first terminal is provided.

  According to another aspect of the present invention, a method for manufacturing a semiconductor device as described above and an electronic device including the semiconductor device are provided.

  According to the disclosed technology, it is possible to suppress the scattering and outflow of solder when stacking semiconductor chips, and to suppress a short circuit between terminal junctions. As a result, a highly reliable semiconductor device and an electronic device using such a semiconductor device can be realized.

It is a figure which shows an example of a semiconductor package. FIG. 3 is a first diagram illustrating a configuration example of a semiconductor chip. FIG. 3 is a second diagram illustrating a configuration example of a semiconductor chip. It is a figure which shows an example of the element area | region provided in a semiconductor chip. It is explanatory drawing of TSV and a terminal. It is explanatory drawing of the connection process of a semiconductor chip. It is a figure which shows the structural example of a semiconductor package. It is a figure which shows the structural example of an electronic apparatus. It is explanatory drawing (the 1) of an example of a semiconductor chip formation method. It is explanatory drawing (the 2) of an example of a semiconductor chip formation method. It is explanatory drawing (the 3) of an example of a semiconductor chip formation method. It is explanatory drawing (the 4) of an example of a semiconductor chip formation method. It is explanatory drawing (the 5) of an example of a semiconductor chip formation method. It is explanatory drawing (the 6) of an example of a semiconductor chip formation method. It is explanatory drawing (the 7) of an example of a semiconductor chip formation method. It is explanatory drawing (the 8) of an example of a semiconductor chip formation method. It is explanatory drawing (the 9) of an example of a semiconductor chip formation method. It is explanatory drawing (the 10) of an example of a semiconductor chip formation method. It is explanatory drawing (the 11) of an example of a semiconductor chip formation method. It is explanatory drawing (the 12) of an example of a semiconductor chip formation method. It is explanatory drawing (the 13) of an example of a semiconductor chip formation method. It is explanatory drawing (the 14) of an example of a semiconductor chip formation method. It is explanatory drawing (the 15) of an example of a semiconductor chip formation method. It is explanatory drawing (the 1) of an example of a semiconductor chip mounting method. It is explanatory drawing (the 2) of an example of the semiconductor chip mounting method. It is explanatory drawing (the 1) of another example of the semiconductor chip mounting method. It is explanatory drawing (the 2) of another example of the semiconductor chip mounting method. It is explanatory drawing (the 3) of another example of the semiconductor chip mounting method. It is explanatory drawing (the 4) of another example of the semiconductor chip mounting method.

First, an example of a semiconductor device (semiconductor package) using a three-dimensional integration technique will be described.
FIG. 1 is a diagram illustrating an example of a semiconductor package. FIG. 1 is a schematic cross-sectional view of an essential part of an example of a semiconductor package.

  A semiconductor package 600 shown in FIG. 1 includes a semiconductor chip 610 and a semiconductor chip 620 that is stacked on and electrically connected to the semiconductor chip 610. On the semiconductor chip 620, a heat radiator 640 such as metal is provided via a thermal interface material (TIM) 630 such as a heat conductive sheet or paste. A stacked body of the semiconductor chip 620 and the semiconductor chip 610 provided with such a heat radiating body 640 is mounted on a circuit substrate (package substrate) 650.

  The lower semiconductor chip 610 includes a semiconductor substrate 611 such as a silicon (Si) substrate. An element region 612 including an element such as a transistor is provided on one surface (front surface) 611 a of the semiconductor substrate 611. On the surface 611a of the semiconductor substrate 611, a wiring layer 613 including a conductive portion including a wiring and a via electrically connected to the element in the element region 612 and an insulating portion covering the conductive portion is provided.

  The semiconductor substrate 611 is provided with a via hole 611c extending from the wiring layer 613 on the front surface 611a to the surface (back surface) 611b opposite to the front surface 611a. A conductive material is provided in the via hole 611c through the insulating film 614 and the barrier metal film 615, and a TSV 616 is formed. As the insulating film 614, a silicon oxide (SiO) film, a silicon nitride (SiN) film, or the like is used. As the barrier metal film 615, a tantalum (Ta) film, a titanium nitride (TiN) film, or the like is used. A conductive material such as copper (Cu) is used for TSV616.

  On the back surface 611b of the semiconductor substrate 611, a rewiring 617 is provided via an insulating film 614 continuous from the inner surface of the via hole 611c. A conductive material such as Cu is used for the rewiring 617. The TSV 616 electrically connects the conductive portion in the wiring layer 613 provided on the front surface 611a of the semiconductor substrate 611 and the rewiring 617 provided on the back surface 611b via the insulating film 614.

  An insulating protective film 618 is provided on the back surface 611b side of the semiconductor substrate 611 so that a part of the rewiring 617 is exposed. As the protective film 618, an organic insulating film such as a polyimide film or an inorganic insulating film such as a SiO film or a SiN film is used. The portion of the rewiring 617 exposed from the protective film 618 serves as a connection terminal 617a with the semiconductor chip 620 stacked on the back surface 611b side of the semiconductor chip 610.

  The wiring layer 613 on the surface 611a of the semiconductor substrate 611 is provided with an electrode 613a that is electrically connected to the conductive portion. The electrode 613a is connected to the electrode 650a of the package substrate 650 using bumps 660 such as solder, and the semiconductor chip 610 and the package substrate 650 are electrically connected.

  The upper semiconductor chip 620 includes a semiconductor substrate 621, an element region 622 including elements on the one surface (front surface) 621 a, a conductive portion electrically connected to the elements in the element region 622, and insulation covering the elements. A wiring layer 623 including a portion is included. Here, as an example of the upper semiconductor chip 620, a semiconductor chip having no TSV is illustrated.

  The wiring layer 623 on the surface 621a of the semiconductor substrate 621 is provided with bumps 661 such as solder electrically connected to the conductive portion. The bump 661 is connected to the connection terminal 617a of the lower semiconductor chip 610, and the upper semiconductor chip 620 and the lower semiconductor chip 610 are electrically connected.

  An underfill material 670 is provided between the lower semiconductor chip 610 joined by the bumps 660 and the package substrate 650. Similarly, an underfill material 671 is provided between the upper semiconductor chip 620 and the lower semiconductor chip 610 joined by the bumps 661. As the underfill material 670 and the underfill material 671, an insulating resin such as an epoxy resin or a material containing an insulating filler in such an insulating resin is used.

  In the manufacture of the semiconductor package 600 having the above configuration, when solder is used for the bumps 661, the solder is melted when the upper semiconductor chip 620 and the lower semiconductor chip 610 are joined. If the molten solder scatters around or flows out, a short circuit may occur between other joints. When the rewiring 617 is not covered with the protective film 618, the melted bump 661 is more likely to flow out. The scattering and outflow of the solder are not limited to the above-described bonding by the bump 661, but a pillar electrode such as copper is provided as a terminal on the upper semiconductor chip 620, and the pillar electrode is connected to the connection terminal 617a of the lower semiconductor chip 610. The same can occur when joining with solder.

  Further, the semiconductor chip 610 and the semiconductor chip 620 may generate heat during the operation of the semiconductor package 600 having the above configuration. In this case, the heat generated in the upper semiconductor chip 620 is transferred to, for example, the thermal interface material 630 and the heat radiating body 640 and is radiated to the outside of the semiconductor package 600. The heat generated in the lower semiconductor chip 610 is transferred to, for example, the upper semiconductor chip 620, transferred from there to the thermal interface material 630 and the heat radiating body 640, and radiated to the outside of the semiconductor package 600. .

  Note that the heat transfer path and heat dissipation path of the semiconductor package 600 are not limited to this example, and heat transfer from the lower semiconductor chip 610 to the package substrate 650, or from the upper semiconductor chip 620 to the lower semiconductor. Heat transfer to the chip 610 may also occur. Further, heat radiation from the semiconductor chip 610, the semiconductor chip 620, and the package substrate 650 to the outside may occur.

Here, attention is focused on heat conduction between the lower semiconductor chip 610 and the upper semiconductor chip 620.
First, the lower semiconductor chip 610 has a structure in which the rewiring 617 is provided on the back surface 611b of the semiconductor substrate 611 as described above. Thus, the rewiring 617 arranged so as to protrude on the back surface 611b of the semiconductor substrate 611 is covered with the protective film 618 while exposing the connection terminal 617a.

  In the semiconductor chip 610 on the lower side, the protective film 618 covering the rewiring 617 is also thickened by the protrusion of the rewiring 617 on the back surface 611b. Furthermore, since the upper semiconductor chip 620 is disposed on the part of the rewiring 617 protruding on the back surface 611b, that is, on the connection terminal 617a via the bump 661, the underfill is performed according to the thickness of the bump 661. The material 671 becomes thicker.

  Most of the space between the semiconductor substrate 611 of the lower semiconductor chip 610 and the wiring layer 623 of the upper semiconductor chip 620 (X portion in FIG. 1) has a lower thermal conductivity than a material such as Cu. The protective film 618 and the underfill material 671 are occupied. Therefore, when such a protective film 618 or the underfill material 671 interposed between the lower semiconductor chip 610 and the upper semiconductor chip 620 becomes thick, the lower semiconductor chip 610 and the upper semiconductor chip 620 Heat conduction between them is not performed efficiently. As a result, for example, the lower semiconductor chip 610 may be overheated, and its malfunction or damage may occur.

Therefore, in view of the above points, the following configuration is adopted for the semiconductor device (semiconductor chip) here.
2 and 3 are diagrams showing a configuration example of a semiconductor chip. 2 is a schematic plan view of a main part of the semiconductor chip, and FIG. 3 is a schematic cross-sectional view taken along line LL in FIG.

  2 and 3 includes a semiconductor substrate 10 such as a Si substrate. An element region 20 including an element such as a transistor is provided on one surface (front surface) 10 a of the semiconductor substrate 10. On the surface 10 a of the semiconductor substrate 10, there is provided a wiring layer 30 including a conductive portion including wirings and vias electrically connected to elements in the element region 20 and an insulating portion covering the conductive portion.

An example of the element region 20 provided in the semiconductor chip 1 is shown in FIG.
The element region 20 shown in FIG. 4 includes an n-channel MOS (Metal Oxide Semiconductor) transistor (nMOS) 21 and a p-channel MOS transistor (pMOS) 22. Each of the nMOS 21 and the pMOS 22 is provided in a region defined by the element isolation region 23 of the semiconductor substrate 10.

  The nMOS 21 is provided in a p-type well region 21 a formed in the semiconductor substrate 10. The nMOS 21 has a gate electrode 21c formed on the semiconductor substrate 10 via a gate insulating film 21b, and n-type diffusion layers 21d formed in the semiconductor substrate 10 on both sides of the gate electrode 21c. The gate electrode 21c is made of, for example, n-type polysilicon. The n-type diffusion layer 21d functions as the source and drain of the nMOS 21. Sidewall spacers 21e are provided on the side walls of the gate electrode 21c. Silicide layers 21f are provided on the surface layer portions of the gate electrode 21c and the n-type diffusion layer 21d, respectively.

  The pMOS 22 is provided in an n-type well region 22a formed in the semiconductor substrate 10, and a gate electrode 22c formed on the semiconductor substrate 10 via a gate insulating film 22b, and in the semiconductor substrate 10 on both sides of the gate electrode 22c. The p-type diffusion layer 22d is formed. The gate electrode 22c is made of, for example, p-type polysilicon. The p-type diffusion layer 22d functions as the source and drain of the pMOS 22. Sidewall spacers 22e are provided on the side walls of the gate electrode 22c. Silicide layers 22f are provided on the surface layer portions of the gate electrode 22c and the p-type diffusion layer 22d, respectively.

  The nMOS 21 and the pMOS 22 are covered with the insulating film 31a and the insulating film 31b, and are electrically connected to the wiring 32 formed on the insulating film 31b through the contact plug 33. Here, as an example, the contact plug 33 connected to the n-type diffusion layer 21d and the p-type diffusion layer 22d is shown, but the gate electrode 21c and the gate electrode 22c are also connected to the wiring via the contact plugs.

  A via 34 and a wiring 35 provided in the interlayer insulating film 31c are electrically connected to the wiring 32. The nMOS 21 and the pMOS 22 in the element region 20 are electrically connected to a part of the plurality of electrodes 36 provided on the surface of the wiring layer 30 through the contact plug 33, the wiring 32, the via 34 and the wiring 35.

Returning to FIG. 2 and FIG.
A recess 11 is provided on the surface (back surface) 10b of the semiconductor substrate 10 opposite to the front surface 10a on which the wiring layer 30 is provided. Here, as an example, a recess 11a, a recess 11b, a recess 11c, and a recess 11d, and a recess 11e that communicates with the recess 11b and the recess 11c are illustrated. In addition, although the planar circular shaped hollow 11a, the hollow 11b, the hollow 11c, and the hollow 11d are shown here, these planar shapes may be elliptical, square shape, etc. other than circular shape.

  The semiconductor substrate 10 is provided with a via hole 12 that communicates with the recess 11 and reaches the conductive portion 30 a of the wiring layer 30. Here, as an example, a via hole 12a communicating with the depression 11a and a via hole 12b communicating with the depression 11b are illustrated. The via hole 12 (in this example, the via hole 12a and the via hole 12b) has a planar size (diameter) smaller than the planar size (diameter) of the recess 11 (in this example, the recess 11a and the recess 11b). Details of this point will be described later.

  An insulating film 40 is provided on the inner surface of the recess 11 and the via hole 12 and the back surface 10 b of the semiconductor substrate 10. For the insulating film 40, a SiO film, a SiN film, or the like is used. A barrier metal film 50 is provided in the depression 11 and the via hole 12 via an insulating film 40. For the barrier metal film 50, a Ta film, a TiN film, or the like is used.

  The recess 11 and the via hole 12 are provided with a conductive material such as Cu via the insulating film 40 and the barrier metal film 50. In this way, the via hole 12 is provided with the conductive material, and the TSV 60 (60a, 60b) of the semiconductor chip 1 is formed. In addition, a conductive material is provided in the recess 11 to form the terminals 61 (61a, 61b, 61c), the rewiring 62, and the connecting portion 63 between the rewiring 62 and the TSV 60 (60b) of the semiconductor chip 1.

  An insulating protective film 80 is provided on the rewiring 62 and the connection portion 63. As the protective film 80, an organic insulating film such as a polyimide film or an inorganic insulating film such as a SiO film or a SiN film is used.

  The terminal 61 is provided with a recess 64. Here, the concave portion refers to a concave portion formed by removing a part of the conductor constituting the wiring and the terminal. The recess 64 serves as a portion (receiving portion) to which a terminal of another semiconductor chip stacked on the semiconductor chip 1 is inserted and joined. Details of this point will be described later.

  The wiring layer 30 on the surface 10a of the semiconductor substrate 10 is provided with a plurality of electrodes 36 that are electrically connected to the element region 20 and the TSV 60 through vias 34, wirings 35, and the like. Each electrode 36 is provided with bumps (terminals) 90 such as solder, which serve as external connection terminals of the semiconductor chip 1.

The TSV 60 and the terminal 61 of the semiconductor chip 1 having the above configuration will be further described.
FIG. 5 is an explanatory diagram of TSVs and terminals.

  In the semiconductor chip 1, the via hole 12 has a diameter smaller than that of the recess 11 as described above. As shown in FIG. 5A, the TSV 60 provided in the via hole 12 has a smaller diameter than the terminal 61 provided in the recess 11.

  Here, the diameter of TSV60 shall be about 5 micrometers-about 20 micrometers, for example. The diameter of the terminal 61 is, for example, about 0.5 to 0.6 times the pitch between adjacent TSVs 60 (between via holes 12). That is, when the pitch of the TSV 60 is 50 μm, the diameter of the terminal 61 is 25 μm to 30 μm, and when the pitch of the TSV 60 is 30 μm, the diameter of the terminal 61 is 15 μm to 18 μm. However, the diameter of the terminal 61 is larger than the diameter of the TSV 60. Further, the depth of the recess 64 provided in the terminal 61 is, for example, about one third of the diameter of the terminal 61. That is, if the diameter of the terminal 61 is 30 μm, the depth of the concave portion 64 of the terminal 61 is 10 μm, and if the diameter of the terminal 61 is 15 μm, the depth of the concave portion 64 of the terminal 61 is 5 μm.

  As shown in FIG. 5A, when the diameter of the TSV 60 is made smaller than the diameter of the terminal 61, the narrowing of the terminals 61 to be arranged is suppressed while suppressing a decrease in mechanical strength of the semiconductor substrate 10 and the semiconductor chip 1 using the same. It becomes possible to increase the pitch and the number.

  For comparison, FIG. 5B shows a semiconductor chip 1 a having a so-called conformal TSV 800. The conformal TSV 800 has a structure in which a conductive material 850 such as Cu is conformally provided in the via hole 820 of the semiconductor substrate 810 with an insulating film 830 and a barrier metal film 840 interposed therebetween. The central portion 800a of the conformal TSV 800 is hollow as shown in FIG. 5B, for example. The hollow central portion 800a may be filled with resin.

  When a plurality of conformal TSVs 800 having a hollow central portion 800a as shown in FIG. 5B are provided at a narrow pitch, the mechanical strength of the semiconductor substrate 810 and the semiconductor chip 1a using the same may be reduced. . In addition, when the resin is filled in the central portion 800a, a certain improvement in mechanical strength can be achieved, but due to the difference in thermal expansion coefficient between the resin and the semiconductor substrate 810 in a process involving heating, The semiconductor substrate 810 and the semiconductor chip 1a may be deformed or damaged such as warpage.

  When the conformal TSV 800 is used as a terminal and a plurality of terminals of other semiconductor chips are to be connected to the plurality of conformal TSV 800, respectively, providing the plurality of conformal TSVs 800 at a narrow pitch as described above It can lead to a decrease in strength. In addition, there is a method of pressing or press-fitting a terminal of another semiconductor chip in the conformal TSV 800. In this method, stress is generated in the semiconductor substrate 810 due to the press-fitting of the terminal into the conformal TSV 800, and the semiconductor. The chip 1a may be deformed or damaged.

  In the conformal TSV 800 as shown in FIG. 5B, there is a possibility that a certain mechanical strength cannot be obtained for the semiconductor substrate 810 and the semiconductor chip 1a, and the pitch of the terminals to be arranged and the number of terminals to be arranged are increased. May not be possible.

  On the other hand, the TSV 60 shown in FIG. 5A can be filled with a conductive material such as Cu, and such a TSV 60 is provided directly below the terminal 61 with a smaller diameter than the terminal 61. Since the TSV 60 having a small diameter filled with the conductive material is provided immediately below the terminal 61 as described above, the mechanical strength of the semiconductor substrate 10 and the semiconductor chip 1 is reduced even when the plurality of terminals 61 are arranged at a narrow pitch. Can be suppressed. According to the terminal 61 and the TSV 60 as shown in FIG. 5A, it is possible to reduce the pitch and increase the number of the terminals 61 to be arranged while suppressing the decrease in the mechanical strength of the semiconductor substrate 10 and the semiconductor chip 1. It becomes possible.

Further, as shown in FIG. 5A, the terminal 61 of the semiconductor chip 1 is provided with a recess 64 into which a terminal of another semiconductor chip to be stacked is inserted as will be described later.
For example, as in the semiconductor chip 1b shown in FIG. 5C, a TSV 900 having a relatively large diameter is formed by filling the via hole 922 with a conductive material such as Cu through the insulating film 930 and the barrier metal film 940. Similarly, the case where the terminal 960 is also formed by filling with a conductive material is considered. In this case, the filling amount of the conductive material into the depression 921 provided in the semiconductor substrate 910 increases, and due to the difference in thermal expansion coefficient between the conductive material and the semiconductor substrate 910 in the process involving heating, There is a possibility that stress is generated, and the semiconductor chip 1b is deformed or damaged, such as warpage.

  On the other hand, as shown in FIG. 5A, when the recesses 64 are provided in the terminals 61, the amount (volume) of the conductive material provided in the recess 11 of the semiconductor substrate 10 can be reduced. It is possible to reduce the generated stress and suppress the deformation and breakage of the semiconductor chip 1.

Next, connection between the semiconductor chip 1 having the above-described configuration and another semiconductor chip will be described.
FIG. 6 is an explanatory diagram of a semiconductor chip connection process. 6A and 6B are schematic cross-sectional views of the main part of the semiconductor chip connection process, where FIG. 6A shows an example of the state before the semiconductor chip bonding, and FIG. 6B shows an example of the state after the semiconductor chip bonding. FIG. 4C is a diagram illustrating an example of a state after filling with the underfill material.

6A to 6C illustrate a process (mounting process) in which the semiconductor chip 100 is stacked on the semiconductor chip 1 as shown in FIGS. 2 and 3 and connected. ing.
As shown in FIG. 6A, the stacked semiconductor chips 100 include a semiconductor substrate 110 such as a Si substrate, and an element region 120 including elements such as transistors is provided on one surface (front surface) 110a. Yes. On the surface 110a, a wiring layer 130 including a conductive portion including a wiring and a via electrically connected to the element in the element region 120 and an insulating portion covering the conductive portion is provided. The wiring layer 130 is provided with bumps (terminals) 140 that are electrically connected to the conductive portions.

  Here, a pillar electrode is illustrated as an example of the terminal 140 of the semiconductor chip 100. Cu, nickel (Ni) or the like is used for the pillar electrode. The terminal 140 is provided corresponding to the terminal 61 of the lower semiconductor chip 1.

  As shown in FIG. 6B, the semiconductor chip 100 is stacked on the semiconductor chip 1 such that the terminal 140 is inserted into the recess 64 provided in the terminal 61 of the lower semiconductor chip 1.

  Here, the terminal 61 of the lower semiconductor chip 1 is formed in advance so as to have a recess 64 of a size into which the terminal 140 of the upper semiconductor chip 100 can be inserted. For example, the terminal 61 provided with the recess 64 having a diameter larger than the diameter of the terminal 140 to be inserted is formed. Providing the concave portion 64 of such a size suppresses the semiconductor substrate 10 from being stressed by the inner wall of the terminal 61 being pushed by the terminal 140 at the time of insertion or after insertion, and the semiconductor substrate 10 being damaged. It becomes possible.

  The terminal 140 of the semiconductor chip 100 is inserted into the concave portion 64 of the terminal 61 of the semiconductor chip 1 and bonded using a bonding material 150 as shown in FIG. For example, solder is used for the bonding material 150. As the solder, tin (Sn), Sn—Ag, In, or the like can be used. Note that the bonding material 150 can be provided in advance at the tip of the terminal 140 before insertion. Further, the bonding material 150 can be provided in advance in the recess 64 of the terminal 61 before the terminal 140 is inserted.

  At the time of bonding using the bonding material 150, the terminal 140 is inserted into the corresponding recess 64 of the terminal 61, and the semiconductor chip 100 is pressed toward the semiconductor chip 1 while being heated at a temperature at which the bonding material 150 melts.

  At this time, the bonding material 150 melted by heating is pushed by the terminal 140 and spreads wet on the side surface of the terminal 140 and the inner surface (bottom surface, side surface) of the recess 64. By adjusting the amount of the bonding material 150, the depth of the recess 64, and the like, even if the terminal 140 is inserted into the recess 64 of the terminal 61 and the semiconductor chip 100 is pressed toward the semiconductor chip 1, the bonding material 150 Scattering and outflow from the recess 64 can be suppressed. By suppressing scattering and outflow from the concave portion 64 of the bonding material 150, it is possible to suppress a short circuit between the bonding portions due to the bonding material 150 being scattered and flowed out.

  Further, the molten bonding material 150 wets and spreads on the side surface of the terminal 140 and the inner surface of the recess 64, whereby the contact area between the bonding material 150 and the terminal 140 and the terminal 61 can be increased. Thereby, the connection strength between the terminal 140 and the terminal 61 through the bonding material 150 can be increased, and the thermal conductivity and electrical characteristics can be improved.

  Further, when the semiconductor chip 100 and the semiconductor chip 1 are joined, the terminal 140 is inserted into the concave portion 64 of the terminal 61 corresponding thereto, so that even if the semiconductor chip 100 is pressed to the semiconductor chip 1 side, the terminal 140 and the terminal to be joined are joined. The position shift 61 can be suppressed.

  As described above, the semiconductor chip 1 is provided with the recess 11 on the back surface 10b (the surface on which the semiconductor chip 100 is laminated) of the semiconductor substrate 10, and the terminal 61, the rewiring 62, and the connection portion 63 are provided in the recess 11. ing. Thereby, in the semiconductor chip 1, it is avoided that the terminal and wiring which protrude in the semiconductor chip 100 side laminated | stacked exist.

  Further, in the semiconductor chip 1, the recess 64 is provided in the terminal 61 corresponding to the terminal 140 of the semiconductor chip 100 to be stacked. As a result, compared to the case where the concave portion 64 is not provided, damage to the semiconductor substrate 10 can be suppressed, and the semiconductor chip 100 can be brought close to and bonded to the semiconductor chip 1 while suppressing displacement. .

  As described above, according to the semiconductor chip 1 in which the terminal 61, the rewiring 62, and the connection portion 63 are embedded in the semiconductor substrate 10 and the recess 61 is provided in the terminal 61, the gap between the stacked semiconductor chips 100 is suppressed. be able to.

  As shown in FIG. 6C, an underfill material 160 is filled between the stacked semiconductor chips 1 and 100. Since the gap between the semiconductor chip 1 and the semiconductor chip 100 can be kept small, the filled underfill material 160 can also be made thin.

  Further, in the semiconductor chip 1, the terminal 61, the rewiring 62, and the connection portion 63 are embedded in the back surface 10 b of the semiconductor substrate 10, so that at least the protruding terminal and wiring thickness are compared with the case where the terminal and the wiring protrude. Thus, the protective film 80 provided on the back surface 10b can be thinned.

  In this way, the underfill material 160 can be made thin, and the protective film 80 provided on the semiconductor chip 1 can be made thin, so that the relatively high thermal conductivity existing between the semiconductor chip 1 and the semiconductor chip 100 can be obtained. Low material can be reduced. Thereby, it is possible to improve the heat conduction efficiency between the semiconductor chip 1 and the semiconductor chip 100.

  When the terminal 140 of the upper semiconductor chip 100 is a pillar electrode as described above, the gap between the semiconductor chip 1 and the semiconductor chip 100 is adjusted by adjusting the height of the pillar electrode. be able to. The gap between the semiconductor chip 1 and the semiconductor chip 100 can be narrowed as the pillar electrode serving as the terminal 140 is lowered. The pillar electrode (terminal 140) of the semiconductor chip 100 can be formed on the wiring layer 130 by using a photolithography technique and a plating technique, for example. In this method, a resist having an opening is formed in a region where a pillar electrode is to be formed on the wiring layer 130, and copper or the like is plated using the resist as a mask to form a pillar electrode on the wiring layer 130. When solder is provided at the tip of the pillar electrode, after plating with copper or the like, further solder plating may be performed. When the pillar electrode is formed by such a method, the height of the pillar electrode can be adjusted by adjusting the plating conditions such as copper, for example, the plating time. By adjusting the height of the pillar electrode and adjusting the gap between the semiconductor chip 1 and the semiconductor chip 100, the underfill material 160 to be filled is made thin, and the heat conduction between the semiconductor chip 1 and the semiconductor chip 100 is achieved. Efficiency can be improved.

  Here, the pillar electrode terminals 140 are provided on the semiconductor chip 100, but various types of protruding terminals such as ball-shaped bumps can be used for the semiconductor chip 100. By inserting the tip of such a protruding terminal into the recess 64 of the terminal 61, the gap between the semiconductor chip 1 and the semiconductor chip 100 is suppressed, the underfill material 160 is thinned, and the semiconductor chip 1 and the semiconductor chip It is possible to improve the heat conduction efficiency between 100.

Next, an example of a semiconductor package including the stacked semiconductor chip 1 and semiconductor chip 100 will be described.
FIG. 7 is a diagram illustrating a configuration example of a semiconductor package. 7A is a schematic cross-sectional view of the main part of the semiconductor package, and FIG. 7B is an enlarged view of the Z part in FIG. 7A.

  A semiconductor package 200 illustrated in FIG. 7A includes the semiconductor chip 1 and the semiconductor chip 100 that are stacked and connected as illustrated in FIG. That is, as shown in FIG. 7B, the terminal 140 of the upper semiconductor chip 100 is inserted into the recess 64 of the terminal 61 embedded in the semiconductor substrate 10 of the lower semiconductor chip 1, and the bonding material 150 is inserted. Are joined through. An underfill material 160 is filled between the semiconductor chip 1 and the semiconductor chip 100.

  In the lower semiconductor chip 1, bumps 90 provided on the electrodes 36 of the wiring layer 30 are bonded to the electrodes 211 of the circuit board (package board) 210. An underfill material 230 is filled between the semiconductor chip 1 and the package substrate 210. The package substrate 210 is provided with an electrode 212 electrically connected to the electrode 211 on the arrangement surface on the surface opposite to the arrangement surface side of the electrode 211 to which the bump 90 is bonded. A bump 260 is provided on the electrode 212.

  On the upper semiconductor chip 100, a heat radiating body 250 such as a Cu lid is joined via a thermal interface material 240 such as a thermal conductive paste. A side portion of the radiator 250 is also bonded to the package substrate 210 via a thermal interface material 240.

  During the operation of the semiconductor package 200 having the above configuration, the semiconductor chip 1 and the semiconductor chip 100 can generate heat. The heat generated in the upper semiconductor chip 100 is transferred to, for example, the thermal interface material 240 and further to the heat radiating body 250 and is radiated to the outside of the semiconductor package 200. The heat generated in the lower semiconductor chip 1 is transferred to, for example, the upper semiconductor chip 100, transferred from there to the thermal interface material 240 and the heat radiating body 250, and released to the outside of the semiconductor package 200.

  Between the semiconductor chip 1 and the semiconductor chip 100, as described above, by reducing the gap and reducing the material having a relatively low thermal conductivity existing in the gap, the heat conduction efficiency can be improved. It is illustrated. As a result, the heat generated in the semiconductor chip 1 can be efficiently transferred to the semiconductor chip 100 and dissipated, and the semiconductor chip 1 can be prevented from being overheated, causing malfunction and damage. As a result, it is possible to realize a highly reliable semiconductor package 200 having excellent thermal conductivity.

  Although heat transfer between the semiconductor chip 1 and the semiconductor chip 100 has been described here, the heat transfer path and heat dissipation path of the semiconductor package 200 are not limited to this example. Heat transfer from the lower semiconductor chip 1 to the package substrate 210, heat transfer from the upper semiconductor chip 100 to the lower semiconductor chip 1, and the like may occur. In addition, heat radiation from the semiconductor chip 1, the semiconductor chip 100, and the package substrate 210 to the outside may occur.

Note that the semiconductor package 200 as shown in FIG. 7 can be mounted on still another circuit board (secondary mounting board).
FIG. 8 is a diagram illustrating a configuration example of an electronic device. FIG. 8 is a schematic cross-sectional view of the main part of the electronic device.

  The electronic device 300 shown in FIG. 8 has a structure in which the semiconductor package 200 as shown in FIG. 7 is mounted on the secondary mounting substrate 310. The package substrate 210 of the semiconductor package 200 is provided with an electrode 212 electrically connected to the electrode 211 on the mounting surface on the surface opposite to the mounting surface side of the semiconductor chip 1 or the like. A bump 260 is provided on the electrode 212. The secondary mounting substrate 310 includes electrodes 311 corresponding to the bumps 260 of the semiconductor package 200. The bumps 260 of the semiconductor package 200 are bonded to the electrodes 311 of the secondary mounting substrate 310, and the semiconductor package 200 and the secondary mounting substrate 310 are electrically connected.

A highly reliable electronic device 300 can be realized using the highly reliable semiconductor package 200 having excellent thermal conductivity.
Hereinafter, a method for forming a semiconductor chip and a method for mounting a semiconductor chip will be described.

First, a method for forming a semiconductor chip will be described with reference to FIGS.
9 to 23 are explanatory diagrams of an example of a semiconductor chip forming method. 9 to 23 are schematic cross-sectional views of the relevant part in the process of forming the semiconductor chip.

  In the formation of the semiconductor chip 1, first, an element region 20 is formed by forming an element such as a transistor as shown in FIG. 9B on a semiconductor substrate 10 (for example, a Si substrate) as shown in FIG. To do. In the element region 20, other elements such as resistors can be formed in addition to the elements shown in FIG. After the formation of the element region 20, as shown in FIG. 9C, wirings and vias electrically connected to the elements in the element region 20 are formed on the formation surface side (surface 10 a side) of the element region 20 of the semiconductor substrate 10. A wiring layer 30 including a conductive portion including the insulating portion and an insulating portion covering the conductive portion is formed. The wiring layer 30 includes a conductive portion 30a connected to the TSV 60 formed as described below. An electrode 36 is formed on the surface of the wiring layer 30.

  Next, as shown in FIG. 10A, bumps 90 are formed on the electrodes 36 of the wiring layer 30. After that, as shown in FIG. 10B, a support substrate 410 such as a Si substrate or a glass substrate is attached to the bump 90 forming surface side using an adhesive 400. Then, as shown in FIG. 10C, the semiconductor substrate 10 attached to the support substrate 410 is back-ground from the surface opposite to the attachment surface of the support substrate 410 to reduce the thickness.

  Next, as shown in FIG. 11A, a resist 420 is applied to the surface (back surface 10b) of the semiconductor substrate 10 after back grinding. Then, as shown in FIG. 11B, a resist 420 is used using a mask 430 having an opening 430a corresponding to the recess 11 (the recess 11 for forming the terminal 61 and the connection portion 63) formed in the semiconductor substrate 10. Exposure. Thereafter, development is performed to form an opening 420 a in the resist 420 as shown in FIG.

Next, as shown in FIG. 12A, the semiconductor substrate 10 is etched using the resist 420 in which the opening 420a is formed as a mask, and the recess 11 for forming the terminal 61 and the connecting portion 63 on the back surface 10b. (11a, 11b, 11c) are formed. Note that carbon tetrafluoride (CF ₄ ), CF ₄ and oxygen (O ₂ ), sulfur hexafluoride (SF ₆ ), or the like can be used for etching the semiconductor substrate 10. Then, as shown in FIG. 12B, after removing the resist 420, the resist is applied, exposed, developed, and etched in the same manner. As shown in FIG. 12C, the back surface 10b of the semiconductor substrate 10 is formed. Then, the recess 11 (11e) for forming the rewiring 62 is formed.

  Next, as shown in FIG. 13A, an insulating film 40a is formed on the semiconductor substrate 10 in which the depressions 11 are formed, and a resist 421 is applied thereon. Then, as shown in FIG. 13B, the resist 421 is exposed using a mask 431 having an opening 431a corresponding to the via hole 12 formed in the semiconductor substrate 10, and thereafter, as shown in FIG. 13C. Then, development is performed to form an opening 421 a in the resist 421.

  Next, as shown in FIG. 14A, using the resist 421 in which the opening 421a is formed as a mask, the insulating film 40a, the semiconductor substrate 10, and a part of the wiring layer 30 (up to the conductive portion 30a connecting the TSV 60). Etching is performed. By this etching, the via hole 12 (12a, 12b) is formed to a predetermined depth at the position of the recess 11 (11a, 11b) for forming the terminal 61 and the connecting portion 63.

The via hole 12 can be formed by using a Si deep etching technique, for example, a Bosch process as shown in FIG.
In the Bosch process, first, as shown in FIG. 15A, isotropic etching using SF ₆ radicals is performed using the resist 421 having the opening 421a as a mask to form the opening 12A in the semiconductor substrate 10. To do. Next, as shown in FIG. 15B, a polymer film 12 </ b> Aa is formed on the inner wall (bottom surface and side surface) of the opening 12 </ b> A of the semiconductor substrate 10 using butene octafluoride (C ₄ F ₈ ). Thereafter, as shown in FIG. 15C, anisotropic etching using SF ₆ ions is performed to remove the polymer film 12Aa formed on the bottom surface of the opening 12A.

In this way, isotropic etching using SF ₆ radicals as shown in FIG. 15A is performed again with the side surface of the opening 12A protected by the polymer film 12Aa. Thereafter, formation of the polymer film 12Aa as shown in FIG. 15B and anisotropic etching using SF ₆ ions as shown in FIG. 15C are performed. By repeating the steps shown in FIGS. 15A to 15C, a via hole 12 having a predetermined depth as shown in FIG. 15D is formed.

  After the via hole 12 is formed, the resist 421 is removed as shown in FIG. 14B, and the insulating film 40 is formed on the inner wall (bottom surface and side surface) of the via hole 12 as shown in FIG. 14C. . Note that the insulating film 40 formed in the step of FIG. 14C is also formed on the insulating film 40a previously formed on the back surface 10b of the semiconductor substrate 10, but here, for convenience, from the inner wall of the via hole 12 to the semiconductor. This is illustrated as a single-layer insulating film 40 that is continuous with the back surface 10 b of the substrate 10.

After the formation of the insulating film 40, as shown in FIG. 16A, the portion of the insulating film 40 formed on the bottom surface of the via hole 12 (the conductive portion 30a of the wiring layer 30) is removed by anisotropic etching. In the etching of the insulating film 40, for example, when a SiO film is formed as the insulating film 40, a fluorine-based material such as CF ₄ , trifluoromethane (CHF ₃ ), hexafluoroethane (C ₂ F ₆ ) or the like. Gas can be used. After removing the insulating film 40 on the bottom surface of the via hole 12, a barrier metal film 50 is formed by sputtering or the like as shown in FIG. Then, as shown in FIG. 16C, the portion of the barrier metal film 50 formed on the bottom surface of the via hole 12 is removed by anisotropic etching. For example, if a TiN film is formed as the barrier metal film 50, a chlorine-based gas such as chlorine (Cl ₂ ) or boron trichloride (BCl ₃ ) can be used for the etching of the barrier metal film 50.

  Next, as shown in FIG. 17A, the recess 11 and the via hole 12 formed in the semiconductor substrate 10 are embedded with a conductive material. For example, a seed layer (not shown) is first formed by sputtering or the like, and then a plating layer 440 of Cu or the like is formed by electrolytic plating using the seed layer. Thereafter, as shown in FIG. 17B, planarization by CMP (Chemical Mechanical Polishing) is performed, and unnecessary plating layer 440 and barrier metal film 50 are removed. As a result, the TSV 60 is formed in the via hole 12, and the terminal 61, the rewiring 62, and the connection portion 63 are formed in the recess 11.

  Next, as shown in FIG. 18A, a resist 422 is applied to the surface after the TSV 60 and the terminals 61 are formed. Then, as shown in FIG. 18B, the resist 422 is exposed using a mask 432 having an opening 432a corresponding to the recess 64 formed in the terminal 61, and thereafter, as shown in FIG. 18C. Development is performed to form an opening 422a in the resist 422.

Next, as shown in FIG. 19A, the terminal 61 is etched using the resist 422 in which the opening 422a is formed as a mask to form the recess 64. The recess 64 can be formed by, for example, wet etching. For wet etching, for example, when the terminal 61 is made of Cu, copper chloride (CuCl ₂ ), iron chloride (FeCl ₃ ), tetraammine copper dichloride (Cu (NH ₃ ) ₄ Cl ₂ ), etc. Can be used. The recess 64 can also be formed by dry etching using a gas corresponding to the type of conductive material used for the terminal 61. After the recess 64 is formed, the resist 422 is removed as shown in FIG. 19B, and an insulating film 80a is formed as shown in FIG. 19C.

  Next, as shown in FIG. 20A, a resist 423 is applied. Then, as shown in FIG. 20B, the resist 423 is exposed using a mask 433 having an opening 433a corresponding to a portion other than the rewiring 62, and thereafter, as shown in FIG. Development is performed to form an opening 423 a in the resist 423.

  Next, as illustrated in FIG. 21A, the insulating film 80 a is etched using the resist 423 in which the opening 423 a is formed as a mask, so that the protective film 80 is formed over the rewiring 62. After the formation of the protective film 80, the resist 423 is removed as shown in FIG.

  When a photosensitive organic insulating film is formed as the insulating film 80a formed in the step of FIG. 19C, the formation of the resist 423 as shown in FIG. The protective film 80 may be formed by exposing and developing the conductive insulating film 80a.

  After the protective film 80 is formed on the rewiring 62, the adhesive 400 and the support substrate 410 are peeled off as shown in FIG. Then, dicing is performed to obtain individual semiconductor chips 1. Note that in the case where such dicing is not performed, the step of FIG. 21C may be omitted.

  Note that after the formation of the insulating film 40 shown in FIG. 14C, a method shown in FIG. 22 may be used. That is, after the formation of the insulating film 40, a barrier metal film 50 is formed on the insulating film 40 as shown in FIG. After forming the barrier metal film 50 on the insulating film 40 in this way, as shown in FIG. 22B, the bottom surface of the via hole 12 (the conductive portion 30a of the wiring layer 30) of the insulating film 40 and the barrier metal film 50. The portion formed in (1) is removed by anisotropic etching. Thereafter, the steps after FIG. 17A may be performed to obtain the semiconductor chip 1.

  Further, after the formation of the barrier metal film 50 shown in FIG. 16B, a method as shown in FIG. 23 can be used. That is, after the formation of the barrier metal film 50, as shown in FIG. 23A, first, a seed layer (not shown) is formed by a sputtering method or the like, and Cu or the like is formed by an electrolytic plating method using the seed layer. A plating layer 440 is formed. Then, as shown in FIG. 23B, unnecessary plating layer 440 and barrier metal film 50 are removed by CMP to form TSV 60, terminal 61, rewiring 62, and connection portion 63. Thereafter, the steps after FIG. 18A may be performed to obtain the semiconductor chip 1. In this method, the barrier metal film 50 remains between the bottom surface of the via hole 12 (the conductive portion 30a of the wiring layer 30) and the plating layer 440 (TSV60). The method shown in FIG. 23 may be employed.

Next, a semiconductor chip mounting method will be described with reference to FIGS.
24 and 25 are explanatory diagrams of an example of a semiconductor chip mounting method. 24 and 25 are schematic cross-sectional views of the relevant part in the semiconductor chip mounting process.

  In this example, first, the semiconductor chip 1 is mounted on the package substrate 210 as shown in FIG. The semiconductor chip 1 is mounted on the package substrate 210 by bonding bumps 90 provided on the electrodes 36 of the wiring layer 30 to the electrodes 211 of the package substrate 210. After the mounting, as shown in FIG. 24B, an underfill material 230 is filled between the semiconductor chip 1 and the package substrate 210.

  The semiconductor chip 100 is mounted on the semiconductor chip 1 mounted on the package substrate 210 as shown in FIG. The semiconductor chip 100 is mounted on the semiconductor chip 1 by inserting the terminal 140 into the recess 64 provided in the terminal 61 of the semiconductor chip 1 and bonding the terminal 140 and the terminal 61 using the bonding material 150. After the semiconductor chip 100 is mounted on the semiconductor chip 1, an underfill material 160 is filled between the semiconductor chip 1 and the semiconductor chip 100 as shown in FIG.

  For example, the stacked body of the package substrate 210, the semiconductor chip 1, and the semiconductor chip 100, that is, the semiconductor package 200 can be obtained by using such a method. Such a semiconductor package 200 can be mounted on a secondary mounting substrate to form an electronic device.

26 to 29 are explanatory diagrams of another example of the semiconductor chip mounting method. 26 to 29 are schematic cross-sectional views of the relevant part in the semiconductor chip mounting process.
In this example, first, as shown in FIG. 26A, the semiconductor chip 1 is mounted on a relay substrate (interposer) 500.

  The interposer 500 includes a Si substrate 510, a TSV 520 penetrating the Si substrate 510, a wiring layer 530 and an insulating film 540 provided on the Si substrate 510. The wiring layer 530 includes a conductive portion electrically connected to the TSV 520 and an insulating portion that covers the conductive portion, and an electrode 531 is provided on the surface corresponding to the electrode 36 of the stacked semiconductor chip 1. . The insulating film 540 is provided with electrodes 541 corresponding to the electrodes 211 of the package substrate 210 to which the interposer 500 is connected as will be described later.

  The semiconductor chip 1 is mounted on such an interposer 500, and the bumps 90 provided on the electrodes 36 are bonded to the electrodes 531 of the interposer 500 and mounted. After mounting, an underfill material 161 is filled between the semiconductor chip 1 and the interposer 500 as shown in FIG.

  Next, as shown in FIG. 27A, the semiconductor chip 100 is mounted on the semiconductor chip 1 mounted on the interposer 500. The semiconductor chip 100 is mounted on the semiconductor chip 1 by inserting the terminal 140 into the recess 64 provided in the terminal 61 of the semiconductor chip 1 and bonding the terminal 140 and the terminal 61 using the bonding material 150. After the semiconductor chip 100 is mounted on the semiconductor chip 1, an underfill material 160 is filled between the semiconductor chip 1 and the semiconductor chip 100 as shown in FIG.

  The stacked body 2 of the interposer 500, the semiconductor chip 1, and the semiconductor chip 100 thus obtained is mounted on the package substrate 210 as shown in FIG. The stacked body 2 is mounted on the package substrate 210 by bonding the electrode 541 of the interposer 500 and the electrode 211 of the package substrate 210 using a bonding material 220 such as solder. After mounting, an underfill material 230 is filled between the interposer 500 and the package substrate 210 as shown in FIG.

  For example, using such a method, a stacked body of the package substrate 210, the interposer 500, the semiconductor chip 1, and the semiconductor chip 100, that is, the semiconductor package 200a can be obtained. Such a semiconductor package 200a can be mounted on a secondary mounting substrate to form an electronic device.

Regarding the embodiment described above, the following additional notes are further disclosed.
(Supplementary note 1) a semiconductor substrate provided with a semiconductor element on the first surface;
A first terminal embedded in a second surface opposite to the first surface of the semiconductor substrate and provided with a recess;
A semiconductor device comprising: a via provided in the semiconductor substrate and electrically connected to the first terminal.

(Additional remark 2) The semiconductor device of Additional remark 1 characterized by including the wiring embed | buried under the said 2nd surface.
(Supplementary Note 3) The first surface has a wiring layer including a conductive portion,
The semiconductor device according to appendix 1 or 2, wherein the via penetrates the semiconductor substrate and is connected to the conductive portion.

(Additional remark 4) The diameter of the said via | veer is smaller than the diameter of the said 1st terminal, The semiconductor device in any one of Additional remark 1 thru | or 3 characterized by the above-mentioned.
(Additional remark 5) Any of Additional remark 1 thru | or 4 characterized by including the semiconductor chip provided in the said 2nd surface side and provided with the 2nd terminal inserted in the said recessed part and electrically connected to the said 1st terminal. A semiconductor device according to claim 1.

(Appendix 6) The second terminal includes a first portion having a first conductor, and a second conductor that is located farther from the semiconductor chip than the first portion and is different from the first conductor. A second part,
The semiconductor device according to appendix 5, wherein the second portion and the first terminal are connected in the recess.

(Additional remark 7) The semiconductor device of Additional remark 5 or 6 characterized by including the resin layer provided between the said 2nd surface and the said semiconductor chip.
(Additional remark 8) The semiconductor device in any one of additional remark 1 thru | or 7 characterized by including the circuit board provided in the said 1st surface side and electrically connected to the said semiconductor element.

(Supplementary note 9) The semiconductor device according to any one of supplementary notes 2 to 8, wherein the wiring and the first terminal are continuously provided.
(Supplementary note 10) The semiconductor device according to any one of supplementary notes 2 to 8, wherein the wiring and the first terminal are provided apart from each other.

(Additional remark 11) The semiconductor device in any one of Additional remark 2 thru | or 10 with which the insulating film is provided on the said wiring.
(Additional remark 12) The process of preparing the semiconductor substrate by which the semiconductor element was provided in the 1st surface,
Forming a first terminal embedded in a second surface opposite to the first surface and a via electrically connected to the first terminal in the semiconductor substrate;
Forming a recess in the first terminal. A method for manufacturing a semiconductor device, comprising:

  (Supplementary note 13) The method for manufacturing a semiconductor device according to supplementary note 12, wherein in the step of forming the first terminal and the via, the via is formed with a diameter smaller than a diameter of the first terminal.

(Additional remark 14) The process of providing the semiconductor chip provided with a 2nd terminal on the said 2nd surface side,
14. The method of manufacturing a semiconductor device according to appendix 12 or 13, wherein the step of providing the semiconductor chip includes a step of inserting the second terminal into the recess and electrically connecting the second terminal to the first terminal.

(Supplementary Note 15) The second terminal includes a first portion having a first conductor, and a second conductor that is located farther from the semiconductor chip than the first portion and is different from the first conductor. A second part,
The method of manufacturing a semiconductor device according to any one of appendices 12 to 14, wherein the step of providing the semiconductor chip includes a step of joining the second portion and the first terminal in the recess.

(Supplementary Note 16) including a step of providing a circuit board on the first surface side,
The method of manufacturing a semiconductor device according to any one of appendices 12 to 15, wherein the step of providing the circuit board includes a step of electrically connecting the semiconductor element to the circuit board.

(Supplementary Note 17) a semiconductor device;
A first circuit board on which the semiconductor device is mounted,
The semiconductor device includes:
A semiconductor substrate provided with a semiconductor element on a first surface;
A first terminal embedded in a second surface opposite to the first surface of the semiconductor substrate and provided with a recess;
A via provided in the semiconductor substrate and electrically connected to the first terminal;
An electronic device comprising: a second circuit board provided on the first surface side and electrically connected to the semiconductor element and the first circuit board.

  (Supplementary note 18) The electron according to supplementary note 17, further comprising: a semiconductor chip provided on the second surface side, the semiconductor chip including a second terminal inserted into the recess and electrically connected to the first terminal. apparatus.

(Supplementary Note 19) The second terminal includes a first portion having a first conductor, and a second conductor that is located farther from the semiconductor chip than the first portion and is different from the first conductor. A second part,
The electronic device according to appendix 18, wherein the second portion and the first terminal are connected in the recess.

1, 1a, 1b, 100, 610, 620, 710, 720 Semiconductor chip 2 Laminate 10, 110, 611, 621, 810, 910 Semiconductor substrate 10a, 110a, 611a, 621a Front surface 10b, 611b, 710b Back surface 11, 11a , 11b, 11c, 11d, 11e, 921 Dimple 12, 12a, 12b, 611c, 820, 922 Via hole 12A, 420a, 421a, 422a, 423a, 430a, 431a, 432a, 433a Opening portion 12Aa Polymer film 20, 120, 612 , 622 Element region 21 nMOS
21a p-type well region 21b, 22b gate insulating film 21c, 22c gate electrode 21d n-type diffusion layer 21e, 22e sidewall spacer 21f, 22f silicide layer 22 pMOS
22a n-type well region 22d p-type diffusion layer 23 element isolation region 30, 130, 530, 613, 623 wiring layer 30a conductive portion 31a, 31b, 40, 40a, 80a, 540, 614, 830, 930 insulating film 31c interlayer insulation Film 32, 35 Wiring 33 Contact plug 34 Via 36, 211, 212, 311, 531, 541, 613a, 650a Electrode 50, 615, 840, 940 Barrier metal film 60, 520, 616, 900 TSV
61, 140, 960 Terminal 62, 617 Rewiring 63 Connection portion 64 Recess 80, 618 Protective film 90, 260, 660, 661, 760, 762 Bump 150, 220 Bonding material 160, 161, 230, 670, 671, 770, 771 Underfill material 200, 200a, 600, 700 Semiconductor package 210, 650, 750 Package substrate 240, 630, 730 Thermal interface material 250, 640, 740 Heat dissipator 300 Electronic device 310, 751 Secondary mounting substrate 400 Adhesive 410 Support Substrate 420, 421, 422, 423 Resist 430, 431, 432, 433 Mask 440 Plating layer 450 Dicing tape 500 Interposer 510 Si substrate 617a Connection terminal 761 Cu pillar electrode 800 Conformal TSV
800a Central part 850 conductive material

Claims (8)

A semiconductor substrate provided with a semiconductor element on a first surface;
A first terminal embedded in a second surface opposite to the first surface of the semiconductor substrate and provided with a recess;
A semiconductor device comprising: a via provided in the semiconductor substrate and electrically connected to the first terminal. A wiring layer including a conductive portion on the first surface;
The semiconductor device according to claim 1, wherein the via penetrates the semiconductor substrate and is connected to the conductive portion.   The semiconductor device according to claim 1, wherein a diameter of the via is smaller than a diameter of the first terminal.   4. The semiconductor chip according to claim 1, further comprising: a semiconductor chip provided on the second surface side, the semiconductor chip including a second terminal inserted into the recess and electrically connected to the first terminal. 5. Semiconductor device. The second terminal includes a first portion having a first conductor, a second portion having a second conductor that is located farther from the semiconductor chip than the first portion and is different from the first conductor, Have
The semiconductor device according to claim 4, wherein the second portion and the first terminal are connected in the recess.   6. The semiconductor device according to claim 1, further comprising a circuit board provided on the first surface side and electrically connected to the semiconductor element. Preparing a semiconductor substrate provided with a semiconductor element on the first surface;
Forming a first terminal embedded in a second surface opposite to the first surface and a via electrically connected to the first terminal in the semiconductor substrate;
Forming a recess in the first terminal. A method for manufacturing a semiconductor device, comprising: A semiconductor device;
A first circuit board on which the semiconductor device is mounted,
The semiconductor device includes:
A semiconductor substrate provided with a semiconductor element on a first surface;
A first terminal embedded in a second surface opposite to the first surface of the semiconductor substrate and provided with a recess;
A via provided in the semiconductor substrate and electrically connected to the first terminal;
An electronic device comprising: a second circuit board provided on the first surface side and electrically connected to the semiconductor element and the first circuit board.

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