WO2017141547A1 - Semiconductor device and method for manufacturing same - Google Patents

Semiconductor device and method for manufacturing same Download PDF

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Publication number
WO2017141547A1
WO2017141547A1 PCT/JP2016/088735 JP2016088735W WO2017141547A1 WO 2017141547 A1 WO2017141547 A1 WO 2017141547A1 JP 2016088735 W JP2016088735 W JP 2016088735W WO 2017141547 A1 WO2017141547 A1 WO 2017141547A1
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Prior art keywords
semiconductor device
vias
substrate body
main surface
land
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PCT/JP2016/088735
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French (fr)
Japanese (ja)
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訓彦 猿田
秀年 椛澤
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ソニー株式会社
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Publication of WO2017141547A1 publication Critical patent/WO2017141547A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15172—Fan-out arrangement of the internal vias
    • H01L2924/15173—Fan-out arrangement of the internal vias in a single layer of the multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Definitions

  • the present technology relates to, for example, a semiconductor device having a through silicon via (TSV: Through Silicon Silicon Via) and a manufacturing method thereof.
  • TSV through Silicon Silicon Via
  • TSV is often formed on a silicon substrate on which an integrated circuit is built, or solder or resin is formed on one side or both sides of the silicon substrate.
  • solder or resin is formed on one side or both sides of the silicon substrate.
  • a strong stress gradient is generated depending on the operating temperature of the device. Therefore, in order to suppress fluctuations in device characteristics, it is necessary to avoid forming an element such as a transistor in the vicinity of TSV.
  • the element formation region is limited.
  • Patent Document 1 discloses a semiconductor element region and a through electrode plug in order to prevent fluctuations in characteristics of a semiconductor device due to stress propagation from a buried electrode plug and unstable operation due to electrical noise propagation from the buried electrode plug.
  • Patent Document 2 discloses a structure that eliminates stress distribution bias by arranging TSVs symmetrically with respect to a semiconductor element.
  • a semiconductor device includes a substrate body and a plurality of vias.
  • the substrate body is provided on at least one of the first main surface, the second main surface opposite to the first main surface, the first main surface, and the second main surface. And an element formation region.
  • the plurality of vias are arranged in the substrate body.
  • Each of the plurality of vias has a hollow conductor portion and an annular land portion.
  • the hollow conductor has a first end exposed on the first main surface and a second end exposed on the second main surface, and penetrates the substrate body.
  • the annular land portion extends from the peripheral edge portion of the first end portion onto the first main surface.
  • the minimum arrangement pitch of the conductor portions is 160 ⁇ m or less, and the land width of the land portions is 20 ⁇ m or less.
  • the land portions of each of the plurality of vias are limited to a land width of 20 ⁇ m or less, a strong stress distribution that can be generated in the periphery of the via depending on the use temperature can be relaxed. Furthermore, since the minimum pitch between adjacent vias is suppressed to 160 ⁇ m or less, an effective element disposition area is expanded. Thereby, it is possible to secure the area of the element formation region while reducing the size of the device.
  • the land width refers to the amount of extension from the peripheral edge of the conductor portion.
  • the land width corresponds to the difference between the outer diameter of the land portion and the outer diameter of the conductor portion.
  • the plurality of vias may be arranged along the peripheral edge of the substrate body. Thereby, the element formation region can be expanded.
  • the minimum arrangement pitch of the conductor portions may be 140 ⁇ m or less, and the land width may be 0 to 15 ⁇ m.
  • the outer diameter of the conductor part and the size of the land width are not particularly limited. Typically, the outer diameter of the conductor part is 60 ⁇ m or less and the thickness of the land part is 6 ⁇ m or less.
  • the planar shape of the substrate body is typically rectangular.
  • the plurality of vias may include a group of vias arranged so as to be biased to at least one corner region of the substrate body.
  • the plurality of vias may include a group of vias arranged so as to be biased toward a peripheral edge portion excluding a corner region of the substrate body.
  • the substrate body may further include a trench part.
  • the trench portion is provided on the first main surface and is disposed between each of the plurality of vias. Thereby, the stress distribution between vias can be further relaxed.
  • the semiconductor device may further include a circuit board.
  • the circuit board is disposed on the first main surface and is electrically connected to the plurality of vias.
  • the circuit board is composed of, for example, a semiconductor element or a sensor element.
  • a method for manufacturing a semiconductor device includes forming a plurality of through holes in a substrate body so that a minimum arrangement pitch thereof is 160 ⁇ m or less.
  • a hollow conductor portion that covers the inner wall surface of each of the plurality of through holes and a conductor layer that covers the surface of the substrate body are formed on the substrate body.
  • a mask pattern is formed on the conductor layer. By performing wet etching on the conductor layer using the mask pattern as a mask, an annular land portion extending from the peripheral edge portion of the end portion of the conductor portion onto the surface of the substrate body has a land width of 20 ⁇ m or less. It is formed.
  • the land portion is formed by side etching the region of the conductor layer covered with the mask pattern.
  • an area where a semiconductor element can be formed can be ensured while downsizing the device.
  • the effects described here are not necessarily limited, and may be any of the effects described in the present disclosure.
  • FIG. 1 is a side view schematically showing a semiconductor device according to a first embodiment of the present technology. It is a schematic plan view of the principal part in the said semiconductor device. It is a figure explaining the internal structure of the via
  • A is a schematic sectional side view of the principal part
  • B is the top view.
  • A is a schematic sectional side view explaining the other example of arrangement
  • B is the top view.
  • A is a schematic plan view explaining the other example of arrangement
  • B is a principal part schematic sectional side view explaining the other structural example of the said via
  • FIG. 1 is a side view schematically showing a semiconductor device according to the first embodiment of the present technology
  • FIG. 2 is a plan view thereof.
  • the X-axis and the Y-axis indicate plane directions orthogonal to each other
  • the Z-axis indicates a height (thickness) direction orthogonal to these (the same applies to the subsequent figures).
  • the semiconductor device 1 of the present embodiment has a stacked structure (CoC structure) of a first circuit board 10 and a second circuit board 20.
  • the semiconductor device 1 is configured as a single package component formed in a substantially rectangular parallelepiped shape as a whole.
  • the second circuit board 20 is mounted on the first circuit board 10 by, for example, a flip chip method.
  • the semiconductor device 1 is mounted on the mounting substrate 30.
  • the semiconductor device 1 is flip-chip mounted on the mounting substrate 30 via the external connection terminals 120, but is not limited thereto, and may be mounted by a wire bond method.
  • the semiconductor device 1 is mounted on various electronic devices such as a video camera, a game machine, and a portable information terminal.
  • the mounting board 30 may be a single-sided board or a double-sided board.
  • Many electric / electronic devices other than the semiconductor device 1 are mounted on the mounting substrate 30 and constitute at least a part of a control circuit of the electronic apparatus.
  • the first circuit board 10 has a board body 11.
  • the substrate body 11 has a first main surface 111 and a second main surface 112.
  • the planar shape of the substrate body 11 is typically a rectangular shape.
  • the thickness of the substrate body 11 is not particularly limited, and is, for example, 100 ⁇ m to 150 ⁇ m.
  • the substrate body 11 is typically composed of a semiconductor substrate such as a silicon substrate or a gallium-arsenide substrate.
  • the semiconductor substrate includes an integrated circuit including a transistor, a memory, and the like, and vias penetrating the front and back of the semiconductor substrate.
  • the first circuit board 10 may incorporate a control circuit that controls driving of the second circuit board 20.
  • the first main surface 111 constitutes one main surface (upper surface in FIG. 1) of the substrate body 11, and the second main surface 112 is a main surface opposite to the first main surface 111 (FIG. 1). The lower surface).
  • Conductive pattern 12 including a plurality of pad portions 121 is formed on first main surface 111, and conductive pattern 13 including a plurality of external terminals 131 is formed on second main surface 112.
  • Each of the conductor patterns 12 and 13 is typically formed on an insulating film such as a silicon oxide film or a silicon nitride film constituting the first and second main surfaces 111 and 112.
  • Each of the conductor patterns 12 and 13 is covered with a protective film such as a solder resist except for a connection region with the second circuit board 20 and a region where the external connection terminal 120 is formed.
  • Each of the conductor patterns 12 and 13 is composed of a conductor layer having a predetermined shape provided on both main surfaces 111 and 112 of the substrate body 11.
  • the conductor material constituting each of the conductor patterns 12 and 13 is not particularly limited, and may be composed of a metal single layer film such as Cu or Al, or may be composed of a laminated film of different metals such as Au / Ti / Ni. Also good.
  • each pad portion 121 is arranged corresponding to the plurality of connection terminals 22 arranged on the terminal surface 211 of the second circuit board 20.
  • the number of pad portions 121 may be the same as or different from the number of external terminals 131.
  • the pad portion 121 and the external terminal 131 are electrically connected to each other through the inside (via 14) of the substrate body 11.
  • the external terminal 131 typically has a function of rearranging the layout of the pad portion 121 on the second main surface 112.
  • the external connection terminal 120 is configured by, for example, a metal bump provided on the external terminal 131.
  • the second circuit board 20 includes a board body 21 and a plurality of connection terminals 22.
  • the board body 21 has a terminal surface 211 that faces the first circuit board 10 (first main surface 111), and a plurality of connection terminals 22 are arranged on the terminal surface 211.
  • the planar shape of the second circuit board 20 is formed in a rectangular shape like the first circuit board 10.
  • the planar shape of the second circuit board 10 may be formed in other geometric shapes.
  • the second circuit board 20 is formed in a size smaller than that of the first circuit board 10, but is not limited thereto, and is formed in the same size as the first circuit board 10. Alternatively, it may be formed in a size larger than that of the first circuit board 10.
  • the second circuit board 20 is typically composed of a wiring board, an IC chip, a sensor device, and the like.
  • the second circuit board 20 is configured by a bare chip having an integrated circuit formed on its surface, or an imaging device incorporating a CCD (Charge-Coupled Device) / CMOS (Complementary Metal-Oxide Semiconductor) imager, It has a sensor section such as an angular velocity sensor manufactured using MEMS (Micro Electro Mechanical System) technology.
  • the substrate body 21 may be composed of a single layer silicon substrate or a composite substrate such as an SOI (Silicon On On Insulator) substrate.
  • Each terminal portion 22 of the second circuit board 20 is electrically and mechanically connected to the pad portion 121 of the first circuit board 10 via a conductive bonding material such as solder. An underfill resin layer for reinforcing these joints may be formed between the first circuit board 10 and the second circuit board 20.
  • Each terminal portion 22 of the second circuit board 20 is electrically connected to the external terminal 131 through the conductor pattern 12 including the pad portion 121 and the plurality of vias 14.
  • the plurality of vias 14 are arranged along the peripheral edge of the substrate body 11.
  • the plurality of vias 14 are arranged in an arrangement area of an integrated circuit including an element such as a transistor formed in the first main surface 111 or an area outside the arrangement area of the pad portion 121.
  • the Each via 14 is individually connected to a predetermined pad portion 121 via a wiring 122.
  • the number of vias 14 may or may not correspond to the number of pad portions 121.
  • each of the plurality of vias 14 corresponds to a TSV and constitutes a group of vias arranged in a biased manner in each corner region of the substrate body 11.
  • the plurality of vias 14 is not limited to the example in which the vias 14 are biased and arranged in all corner areas of the substrate body 11, and may be arranged in a biased manner in at least one corner area.
  • the plurality of vias 14 may constitute a group of vias arranged so as to be biased to the peripheral edge portion excluding the corner region of the substrate body 11 as described later.
  • each of the plurality of vias 14 by devising the structure of each of the plurality of vias 14, a strong stress gradient in the vicinity of the TSV is suppressed, and the element formation region is ensured while ensuring miniaturization of the device.
  • details of the via 14 will be described.
  • 3A and 3B are a schematic cross-sectional view and a plan view of a main part for explaining the internal structure of the via 14.
  • the plurality of vias 14 function as interlayer connection portions that electrically connect the first main surface 111 and the second main surface 112 of the substrate body 11.
  • the plurality of vias 14 are configured as conformal vias, and each have a hollow conductor portion 141 and a land portion 142.
  • the conductor portion 141 is provided in each of the plurality of through holes 113 provided in the peripheral edge portion of the substrate body 11.
  • the conductor 141 is typically made of a metal material such as copper, and is formed by a sputtering method, an electrolytic plating method, or a combination thereof.
  • the through hole 113 is typically formed as a round hole, and its inner wall surface is covered with an insulating film 16 such as a silicon oxide film together with the two main surfaces 111 and 112 of the substrate body 11.
  • the conductor portion 141 is formed in a substantially cylindrical shape on the inner wall surface of the through hole 113 through the insulating film 16.
  • the conductor portion 141 has a first end portion 141 a exposed on the first surface 111 of the substrate body 11 and a second end portion 141 b exposed on the second main surface 112 of the substrate body 11.
  • the first end portion 141a is electrically connected to the conductor pattern 12 (pad portion 121, wiring portion 122) on the first main surface 111, and the second end portion 141b is on the second main surface 112.
  • the conductor pattern 13 (external terminal 131) is electrically connected.
  • the land portion 142 is formed in an annular shape so as to extend on the first main surface 111 from the peripheral edge portion of the first end portion 141a.
  • the land portion 142 is for electrically connecting the first end portion 141 b and the conductor pattern 12, but the first end portion 141 a and the conductor pattern 12 are directly connected without the land portion 142. May be connected.
  • the land portion 142 is typically formed at the same time as the process of forming the conductor pattern 12 with the same material as that of the conductor pattern 12.
  • the second end portion 141b constitutes the bottom portion of the conductor portion 141 and is electrically connected to the wiring portion 132 that closes the opening portion of the through hole 13 on the second main surface 112 side.
  • the wiring part 132 constitutes a part of the conductor pattern 13 formed on the second main surface 112 and electrically connects the second end part 141 b and the external terminal 131.
  • FIG. 4A is a schematic plan view of a semiconductor device showing a typical arrangement example of vias (TSV).
  • the vias 14A in the typical example are often arranged at equal intervals around the periphery of the semiconductor substrate 11A as shown in FIG. 4A.
  • the reason is that if the distance between the vias 14A is extremely narrowed, the substrate stress increases and cracks are likely to occur, resulting in a problem in reliability.
  • the stress gradient near the via 14A may cause variations in device characteristics in the integrated circuit in the peripheral element formation region.
  • an element arrangement prohibition region (KOZ: Keep Out Zone) 14z is provided in a region where the stress gradient is relatively large.
  • KOZ Keep Out Zone
  • KOZ varies depending on the element size, it is generally set to 50 ⁇ m or more from the edge of the via. Therefore, in the arrangement example of the via 14A shown in FIG. 4A, it is difficult to increase the area of the element formation region (effective element arrangement possible region) 110.
  • the vias 14 are collectively arranged at the four corners of the substrate body 11.
  • the element formation region 110 is enlarged as compared with the arrangement example of FIG. 4A.
  • the via diameter is 60 ⁇ m
  • KOZ is 50 ⁇ m from the edge of the via
  • the via center is 120 ⁇ m away from the edge of the substrate
  • the vias are arranged according to the rule that the four corners of the substrate are separated by one via. Think about the case.
  • the area of the element formation region is the same when arranged evenly (FIG. 4A) and when concentrated via the distance between vias reduced to 120 ⁇ m (FIG.
  • FIG. 5 is a simulation result showing a stress distribution when the distance between vias is narrowed for a via having a diameter of 60 ⁇ m.
  • the stress at the via midpoint increases rapidly from 60 MPa to 130 MPa.
  • the present inventors paid attention to the fact that the stress between vias has a deep correlation with the size of the land width of the via land.
  • the land width W [ ⁇ m] corresponds to a half of the difference between the outer diameter D2 [ ⁇ m] of the land portion 142 and the outer diameter D1 [ ⁇ m] of the conductor portion 141. .
  • the stress between vias decreased as the land width W value decreased.
  • Fig. 6 shows the relationship between the distance between vias (TSV) and the stress when the land width value is changed.
  • TSV distance between vias
  • the plurality of vias 14 have a minimum arrangement pitch (distance between the centers of the conductor portions 141) P between adjacent vias 14 of 160 ⁇ m or less, and the land width of the land portion 142.
  • W is configured to be 20 ⁇ m or less.
  • the “minimum arrangement pitch” is a distance between two vias 14 adjacent to each other in the X-axis direction or the Y-axis direction in a group of vias concentrated in one corner region of the substrate body 11 as shown in FIG. Say. Therefore, the distance between the via located at the right end of the via group arranged in the upper left corner area of the figure and the via located at the left end of the via group arranged in the upper right corner area of the figure Are distinguished.
  • the land portion 142 of each of the plurality of vias 14 is limited to a land width W of 20 ⁇ m or less, the strong stress distribution that can be generated in the periphery of the via depending on the use temperature is relaxed, and the substrate Damage or the like can be prevented. Furthermore, since the minimum pitch between adjacent vias 14 is suppressed to 160 ⁇ m or less, the element formation region is enlarged. Thereby, it is possible to secure the area of the element formation region while reducing the size of the device.
  • each via 14 is configured so that the arrangement pitch P is 140 ⁇ m or less and the land width W is 0 ⁇ m or more and 15 ⁇ m or less.
  • the arrangement pitch P is 120 ⁇ m or less, and the land width W is 10 ⁇ m or less.
  • the lower limit of the arrangement pitch P is set to an appropriate value so that the vias 14 do not contact each other (do not short-circuit).
  • the stress between vias has a large correlation with the thickness T of the land part 142 and the via diameter (outer diameter of the conductor part 141) D1 (see FIG. 3A).
  • the via diameter is 60 ⁇ m or less, and the land portion 142 has a thickness of 6 ⁇ m or less.
  • FIG. 7 shows the relationship between the land width and stress when the land thickness T and via diameter D1 are changed.
  • the distance P between vias is constant at 120 ⁇ m.
  • the land width W is relatively large as 20 ⁇ m, the larger the via diameter D1 and the land portion thickness T, the larger the stress tends to be.
  • the value of the land width W is reduced, it is understood that the stress is reduced as a whole.
  • the via diameter D1 is large, the reduction width of the stress is also large.
  • the land width W is reduced to 5 ⁇ m, the stress can be reduced to 100 MPa or less even under the maximum stress conditions when the via diameter D1 is 60 ⁇ m and the land thickness T is 5 ⁇ m. It was done.
  • 8A and 8B show the relationship between the via diameter D1, the land portion thickness T, and the land width W when the upper limit of the substrate stress is fixed at 100 MPa and the distance P between the vias is 140 ⁇ m.
  • the upper limit value of the land width (W) changes in inverse proportion to the 0.5th power of the via diameter (D1) from FIG. 8A, and linearly changes with respect to the land thickness (T) from FIG. 8B. Confirmed to do. From these results, the size of the land width W satisfies the relationship represented by the following expression (1) between the via diameter D1 [ ⁇ m] and the land thickness T [ ⁇ m]. W ⁇ (10 [ ⁇ m] ⁇ T) ⁇ (D1) 0.5 ⁇ 23.265 [ ⁇ m] (1)
  • each of the plurality of vias 14 is formed of a conformal type via having a hollow conductor portion 141, and therefore, a structure in which the inside of the through hole 113 is embedded with a conductor (hereinafter referred to as an embedded type).
  • the stress between the vias can be further relaxed compared to the via.
  • Fig. 9 shows the relationship between inter-via distance and stress for conformal vias and buried vias. As shown in the figure, in the conformal via, the stress is about half that in the buried type. Therefore, an increase in stress associated with a narrow pitch between vias can be effectively suppressed.
  • the stress gradient in the plane of the substrate body 10 is reduced and the gap between vias is reduced.
  • the distance can be reduced, and the area of the element formation region can be increased without increasing the device size.
  • the reliability of the electronic component 1 can be improved.
  • FIG. 10 is a schematic process cross-sectional view of the main part for explaining the manufacturing method of the first circuit board 10.
  • an insulating film 16 such as a silicon oxide film is formed on both main surfaces 111 and 112 of the substrate body 11 provided with a plurality of through holes 113 and on the inner wall surface of each through hole 113.
  • the insulating film 16 is typically a thermal oxide film, but is not limited thereto, and may be a vapor deposition film or the like.
  • a conductor pattern (wiring portion 132) that closes one end of each through hole 113 is formed on the second main surface 112 of the substrate body 11.
  • the plurality of through holes 113 are formed at a predetermined minimum arrangement pitch of 160 ⁇ m or less at the peripheral edge of the substrate body 11 (in the vicinity of each corner region in this example).
  • the formation method of the through-hole 113 is not specifically limited, For example, it forms by dry processes, such as RIE (Reactive * Ion
  • a seed layer (feeding layer) 140 for forming vias is formed on the first main surface 111 of the substrate body 11.
  • the seed layer 140 is typically formed on the insulating layer 16 covering the first main surface 111 and the inner wall surface of the through hole 113 by sputtering.
  • the seed layer 140 is also formed on the inner surface of the wiring part 132 that closes one end of the through hole 113.
  • a mask pattern 17 for etching the seed layer 140 is formed on the first main surface 111 of the substrate body 11.
  • the mask pattern 17 is patterned into a shape that covers a region where the conductor pattern 12 is formed, such as the inside of the through hole 113 and its peripheral edge, and a wiring region.
  • the mask pattern 17 is made of a material that can ensure an etching selectivity ratio higher than a predetermined level with the seed layer 140 with respect to the etching solution to be used. Is done.
  • the seed layer 140 is pattern-etched by a wet etching method using the mask pattern 17 as an etching mask. Thereby, the conductor pattern 12 (pad portion 121, wiring portion 122) and the underlayer of the via 14 are formed.
  • a condition is adopted in which, in the seed layer 140 covered with the mask pattern 17, a region 142a corresponding to the ground layer of the land portion 142 of the via 14 is side-etched by a predetermined amount or more. Is done.
  • the side etching amount of the region 142a is not particularly limited as long as the land width is finally 20 ⁇ m or less, and is typically controlled by the etching time.
  • the region of the mask pattern 17 covering the region where the wiring part 122 is formed has a width that can prevent disconnection. It is formed.
  • a plating layer of a predetermined thickness such as copper plating is formed on the patterned seed layer 140.
  • the via 14 including the hollow conductor portion 141 and the land portion 142 and the conductor pattern 12 (FIG. 2) including the pad portion 121 and the wiring portion 122 are formed.
  • the plating method is not particularly limited, and typically, an electrolytic plating method is employed. Thereby, a conductor layer having a predetermined thickness can be easily formed in the through hole 113 and on the first main surface 111.
  • the thickness of the plating layer is not particularly limited. In the present embodiment, the plating layer is formed with a thickness such that the land portion 142 has a thickness of 6 ⁇ m or less.
  • the first circuit board 10 in the present embodiment is manufactured.
  • the land width of the land portion 142 of each via 14 is controlled by the side etching amount of the land portion 142 (region 142a), it is necessary to control the shape of the mask pattern 17 with high accuracy.
  • the via 14 having a desired land width can be formed. That is, it is possible to control the land portion 142 with high accuracy with accuracy equal to or lower than the alignment accuracy of the mask pattern 17.
  • 11A and 11B are a schematic cross-sectional view and a plan view of the main part showing the configuration of the semiconductor device according to the second embodiment of the present technology.
  • the configuration different from the first embodiment will be mainly described, and the same configuration as the first embodiment will be denoted by the same reference numeral, and the description thereof will be omitted or simplified.
  • the circuit board 100 shown in the figure corresponds to the first circuit board 10 in the first embodiment.
  • the first circuit board 100 is provided with a trench portion 101 between adjacent vias 14. Different from the embodiment.
  • the trench portion 101 is a first main surface 111 of the substrate body 11 and is formed of a half trench formed so as to divide a region between two adjacent vias 14.
  • the trench portion 101 is typically formed linearly from the periphery of the substrate body 11 inward.
  • the width (X-axis direction), depth (Z-axis direction), and length (Y-axis direction) of the trench portion 101 are not particularly limited, and stress distribution between vias can be relaxed while ensuring the strength of the substrate body 11.
  • An appropriate value is set.
  • the width of the trench portion 101 can be 10 ⁇ m
  • the depth can be 50 ⁇ m
  • the length can be 120 ⁇ m.
  • a plurality of trench portions 101 may be provided between the vias 14. Or the trench part 101 is not restricted to a linear thing, A curved shape may be sufficient, and the shape etc. which the some linear part was combined may be sufficient.
  • the example in which the plurality of vias 14 are concentrated on each corner area of the substrate body 11 has been described.
  • the plurality of vias 14 are arranged in the corner area of the substrate body 11.
  • the connection reliability of the vias 14 can be ensured by forming the vias avoiding the four corners of the substrate having the largest amount of warpage.
  • the element formation region 110 is expanded to the four corners of the substrate body, for example, as shown in FIG. can do. Thereby, it becomes possible to further promote downsizing of the device.
  • each via 14 is provided with the land portion 142 only on the first end portion 141a side of the conductor portion 141 has been described.
  • the present invention is not limited to this, and the semiconductor device 300 shown in FIG.
  • the land portion 142 may also be provided on the second end portion 141b side.
  • the land portion 142 on the second end portion 141b side is configured under the same conditions as the land portion 142 on the first end portion 141a side, thereby obtaining the same operational effects as those of the above-described embodiments. be able to.
  • the via 14 is arranged in the in-plane central portion of the substrate main body 11. May be.
  • the electronic device having the CoC structure or the semiconductor device for CoC has been described as an example of the semiconductor device.
  • the present invention is not limited to this, and can be similarly applied to a single-layer semiconductor device.
  • this technique can also take the following structures.
  • (1) Element formation provided on at least one of the first main surface, the second main surface opposite to the first main surface, and the first main surface and the second main surface A substrate body having a region; A plurality of vias arranged in the substrate body, The plurality of vias are A hollow conductor having a first end exposed on the first main surface and a second end exposed on the second main surface and penetrating the substrate body; and the first end Each having an annular land portion extending from the peripheral portion of the portion onto the first main surface, The minimum arrangement pitch of the said conductor part is 160 micrometers or less, and the land width of the said land part is 20 micrometers or less.
  • Semiconductor device is 160 micrometers or less, and the land width of the said land part is 20 micrometers or less.
  • the semiconductor device according to (1) above The plurality of vias are arranged along a peripheral edge of the substrate body.
  • the semiconductor device according to (1) or (2) above, The minimum arrangement pitch of the said conductor part is 140 micrometers or less, and the said land width is 0-15 micrometer.
  • the semiconductor device according to (3) above, The semiconductor device has an outer diameter of 60 ⁇ m or less and a thickness of the land portion of 6 ⁇ m or less.
  • the semiconductor device according to any one of (1) to (5) above The planar shape of the substrate body is rectangular, The plurality of vias include a group of vias arranged in a biased manner on a peripheral edge except for a corner region of the substrate body.
  • the substrate body further includes a trench portion provided on the first main surface and disposed between each of the plurality of vias.
  • a semiconductor device further comprising a circuit board disposed on the first main surface and electrically connected to the plurality of vias.
  • the circuit board is a semiconductor element or a sensor element.
  • a plurality of through holes are formed in the substrate body so that the minimum arrangement pitch is 160 ⁇ m or less, A hollow conductor portion covering the inner wall surface of each of the plurality of through holes and a conductor layer covering the surface of the substrate body are formed on the substrate body, Forming a mask pattern on the conductor layer; By performing wet etching on the conductor layer using the mask pattern as a mask, an annular land portion extending from the peripheral edge portion of the end portion of the conductor portion onto the surface of the substrate body has a land width of 20 ⁇ m or less.
  • a method of manufacturing a semiconductor device includes forming an annular mask portion having a pattern width of 20 ⁇ m or more covering a peripheral portion of each of the plurality of through holes.
  • the land portion is formed by side etching a region of the conductor layer covered with the mask portion.
  • SYMBOLS 1 Electronic component 10, 100, 300 ... 1st circuit board (semiconductor device) 11 ... Board body 14 ... Via (TSV) DESCRIPTION OF SYMBOLS 17 ... Mask pattern 20 ... 2nd circuit board 101 ... Trench part 111 ... 1st main surface 112 ... 2nd main surface 113 ... Through-hole 141 ... Conductor part 141a ... 1st edge part 141b ... 2nd edge Part 142 ... Land part

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Abstract

According to one embodiment of the present art, a semiconductor device is provided with a substrate body, and a plurality of vias. The substrate body has a first main surface, a second main surface, and an element formation region provided as a part of the first main surface and/or the second main surface. The vias are arrayed in the substrate body. Each of the vias has a hollow conductor section and an annular land section. The hollow conductor section has a first end portion exposed from the first main surface, and a second end portion exposed from the second main surface, and traverses the substrate body. The annular land section extends from a peripheral edge of the first end portion onto the first main surface. The minimum array pitch of the conductor sections is 160 μm or less, and the land width of the land section is 20 μm or less.

Description

半導体デバイス及びその製造方法Semiconductor device and manufacturing method thereof
　本技術は、例えば、シリコン貫通電極（ＴＳＶ：Through Silicon Via）を有する半導体デバイス及びその製造方法に関する。 The present technology relates to, for example, a semiconductor device having a through silicon via (TSV: Through Silicon Silicon Via) and a manufacturing method thereof.
　近年、例えばＣｏＣ（Chip on Chip）のような積層型実装技術によって、半導体デバイスの小型化が進みつつある。その一方で、例えば集積回路に組み込まれたトランジスタのモビリティが変化することで生じるデバイス特性の劣化は、小型積層実装を実現するための大きな課題の一つである。 In recent years, for example, semiconductor devices are being reduced in size by a stacked mounting technology such as CoC (Chip-on-Chip). On the other hand, degradation of device characteristics caused by, for example, a change in the mobility of a transistor incorporated in an integrated circuit is one of the major issues for realizing small stack mounting.
　また、積層型実装においては、集積回路が作り込まれたシリコン基板上にＴＳＶが形成され、あるいはシリコン基板の片面もしくは両面にハンダや樹脂などが形成されている場合が多い。特にＴＳＶの近傍では、デバイスの使用温度によって強い応力勾配が発生するため、デバイス特性の変動を抑えるためには、ＴＳＶの近傍にトランジスタ等の素子を形成することを避けねばならず、その結果、素子形成領域が制限されてしまう。 Also, in the stacked mounting, TSV is often formed on a silicon substrate on which an integrated circuit is built, or solder or resin is formed on one side or both sides of the silicon substrate. Particularly in the vicinity of TSV, a strong stress gradient is generated depending on the operating temperature of the device. Therefore, in order to suppress fluctuations in device characteristics, it is necessary to avoid forming an element such as a transistor in the vicinity of TSV. The element formation region is limited.
　このような問題を解決するためのデバイス構造の工夫がいくつか提案がなされている。例えば特許文献１には、埋め込み電極プラグからの応力伝播による半導体装置の特性変動、および、埋め込み電極プラグからの電気的雑音伝播による、動作不安定化を防止するため、半導体素子領域と貫通電極プラグとの間にハーフトレンチに溝型電極を埋め込む技術が開示されている。また、特許文献２には、ＴＳＶを半導体素子に対して対称に配置することで、応力分布の偏りをなくす構造が開示されている。 Several proposals have been made for device structures to solve such problems. For example, Patent Document 1 discloses a semiconductor element region and a through electrode plug in order to prevent fluctuations in characteristics of a semiconductor device due to stress propagation from a buried electrode plug and unstable operation due to electrical noise propagation from the buried electrode plug. A technique for embedding a groove-type electrode in a half trench is disclosed. Patent Document 2 discloses a structure that eliminates stress distribution bias by arranging TSVs symmetrically with respect to a semiconductor element.
特開２０１２－１６４７０２号公報JP 2012-164702 A 特表２０１４－５２３６４５号公報Special table 2014-523645 gazette
　しかしながら、これらの従来技術においては、以下のような問題点がある。すなわち、特許文献１に開示の構成では、溝型電極を形成する分フットプリントが減少し、半導体素子を形成可能な面積が減少する。また、特許文献２に開示の構成では、ＴＳＶと半導体素子の設計制約が大きく、素子配置の自由度が著しく制限される。 However, these conventional techniques have the following problems. That is, in the configuration disclosed in Patent Document 1, the footprint is reduced by forming the groove-type electrode, and the area where the semiconductor element can be formed is reduced. Further, in the configuration disclosed in Patent Document 2, design restrictions on TSVs and semiconductor elements are large, and the degree of freedom of element arrangement is significantly limited.
　以上のような事情に鑑み、本技術の目的は、デバイスの小型化を図りつつ、半導体素子の形成可能な面積を確保することができる半導体デバイス及びその製造方法を提供することにある。 In view of the circumstances as described above, it is an object of the present technology to provide a semiconductor device and a method for manufacturing the semiconductor device that can secure the area where a semiconductor element can be formed while downsizing the device.
　本技術の一形態に係る半導体デバイスは、基板本体と、複数のビアとを具備する。
　上記基板本体は、第１の主面と、上記第１の主面とは反対側の第２の主面と、上記第１の主面及び上記第２の主面の少なくとも一方に設けられた素子形成領域とを有する。
　上記複数のビアは、上記基板本体に配列される。
　上記複数のビアは、中空の導体部と、環状のランド部とをそれぞれ有する。上記中空の導体部は、上記第１の主面に露出する第１の端部と、上記第２の主面に露出する第２の端部とを有し、上記基板本体を貫通する。上記環状のランド部は、上記第１の端部の周縁部から上記第１の主面上に延出する。上記導体部の最小配列ピッチは１６０μｍ以下であり、上記ランド部のランド幅は２０μｍ以下である。 A semiconductor device according to an embodiment of the present technology includes a substrate body and a plurality of vias.
The substrate body is provided on at least one of the first main surface, the second main surface opposite to the first main surface, the first main surface, and the second main surface. And an element formation region.
The plurality of vias are arranged in the substrate body.
Each of the plurality of vias has a hollow conductor portion and an annular land portion. The hollow conductor has a first end exposed on the first main surface and a second end exposed on the second main surface, and penetrates the substrate body. The annular land portion extends from the peripheral edge portion of the first end portion onto the first main surface. The minimum arrangement pitch of the conductor portions is 160 μm or less, and the land width of the land portions is 20 μm or less.
　上記半導体デバイスにおいて、複数のビア各々のランド部が２０μｍ以下のランド幅に制限されているため、使用温度によってビア周辺部に発生し得る強い応力分布を緩和することができる。さらに、隣接するビア間の最小ピッチが１６０μｍ以下に抑えられているため、実効的な素子の配置可能領域が拡大される。これにより、デバイスの小型化を図りつつ、素子形成領域の面積を確保することが可能となる。 In the semiconductor device described above, since the land portions of each of the plurality of vias are limited to a land width of 20 μm or less, a strong stress distribution that can be generated in the periphery of the via depending on the use temperature can be relaxed. Furthermore, since the minimum pitch between adjacent vias is suppressed to 160 μm or less, an effective element disposition area is expanded. Thereby, it is possible to secure the area of the element formation region while reducing the size of the device.
　なお、ランド幅とは、導体部の周縁部からの延出量をいい、導体部が円筒形状の場合、ランド幅は、ランド部の外径と導体部の外径との差に相当する。 The land width refers to the amount of extension from the peripheral edge of the conductor portion. When the conductor portion is cylindrical, the land width corresponds to the difference between the outer diameter of the land portion and the outer diameter of the conductor portion.
　上記複数のビアは、上記基板本体の周縁部に沿って配列されてもよい。これにより、素子形成領域の拡張を図ることができる。 The plurality of vias may be arranged along the peripheral edge of the substrate body. Thereby, the element formation region can be expanded.
　上記導体部の最小配列ピッチは１４０μｍ以下であり、上記ランド幅は０以上１５μｍ以下であってもよい。 The minimum arrangement pitch of the conductor portions may be 140 μm or less, and the land width may be 0 to 15 μm.
　上記導体部の外径及び上記ランド幅の大きさは特に限定されず、典型的には、導体部の外径は６０μｍ以下であり、ランド部の厚みは６μｍ以下である。 The outer diameter of the conductor part and the size of the land width are not particularly limited. Typically, the outer diameter of the conductor part is 60 μm or less and the thickness of the land part is 6 μm or less.
　上記導体部の外径をＤ１［μｍ］、上記ランド部の厚みをＴ［μｍ］、上記ランド幅をＷ［μｍ］としたとき、Ｄ１、Ｔ及びＷは、
　　Ｗ≦（１０［μｍ］－Ｔ）÷（Ｄ１）0.5 ×23.265［μｍ］
の関係を満たすように構成されてもよい。 When the outer diameter of the conductor portion is D1 [μm], the thickness of the land portion is T [μm], and the land width is W [μm], D1, T and W are:
W ≦ (10 [μm] −T) ÷ (D1) 0.5 × 23.265 [μm]
It may be configured to satisfy the relationship.
　上記基板本体の平面形状は、典型的には、矩形状である。
　この場合、上記複数のビアは、上記基板本体の少なくとも１つのコーナ領域に偏って配置されたビア群を含んでもよい。
　あるいは、上記複数のビアは、上記基板本体のコーナ領域を除く周縁部に偏って配置されたビア群を含んでもよい。 The planar shape of the substrate body is typically rectangular.
In this case, the plurality of vias may include a group of vias arranged so as to be biased to at least one corner region of the substrate body.
Alternatively, the plurality of vias may include a group of vias arranged so as to be biased toward a peripheral edge portion excluding a corner region of the substrate body.
　上記基板本体は、トレンチ部をさらに有してもよい。上記トレンチ部は、上記第１の主面に設けられ、上記複数のビア各々の間に配置される。
　これにより、ビア間の応力分布をさらに緩和することができる。 The substrate body may further include a trench part. The trench portion is provided on the first main surface and is disposed between each of the plurality of vias.
Thereby, the stress distribution between vias can be further relaxed.
　上記半導体デバイスは、回路基板をさらに具備してもよい。上記回路基板は、上記第１の主面に配置され、上記複数のビアと電気的に接続される。
　上記回路基板は、例えば、半導体素子又はセンサ素子で構成される。 The semiconductor device may further include a circuit board. The circuit board is disposed on the first main surface and is electrically connected to the plurality of vias.
The circuit board is composed of, for example, a semiconductor element or a sensor element.
　本技術の一形態に係る半導体デバイスの製造方法は、基板本体に複数の貫通孔を、その最小配列ピッチが１６０μｍ以下となるように形成することを含む。
　上記基板本体に、上記複数の貫通孔各々の内壁面を被覆する中空の導体部と上記基板本体の表面を被覆する導体層とがそれぞれ形成される。
　上記導体層の上にマスクパターンが形成される。
　上記マスクパターンをマスクとして上記導体層をウェットエッチングすることで、上記導体部の端部の周縁部から上記基板本体の表面上に延出する環状のランド部が２０μｍ以下のランド幅となるように形成される。 A method for manufacturing a semiconductor device according to an embodiment of the present technology includes forming a plurality of through holes in a substrate body so that a minimum arrangement pitch thereof is 160 μm or less.
A hollow conductor portion that covers the inner wall surface of each of the plurality of through holes and a conductor layer that covers the surface of the substrate body are formed on the substrate body.
A mask pattern is formed on the conductor layer.
By performing wet etching on the conductor layer using the mask pattern as a mask, an annular land portion extending from the peripheral edge portion of the end portion of the conductor portion onto the surface of the substrate body has a land width of 20 μm or less. It is formed.
　上記ランド部は、上記マスクパターンで被覆される上記導体層の領域をサイドエッチングすることで形成される。 The land portion is formed by side etching the region of the conductor layer covered with the mask pattern.
　以上のように、本技術によれば、デバイスの小型化を図りつつ、半導体素子の形成可能な面積を確保することができる。
　なお、ここに記載された効果は必ずしも限定されるものではなく、本開示中に記載されたいずれかの効果であってもよい。 As described above, according to the present technology, an area where a semiconductor element can be formed can be ensured while downsizing the device.
Note that the effects described here are not necessarily limited, and may be any of the effects described in the present disclosure.
本技術の第１の実施形態に係る半導体デバイスを概略的に示す側面図である。1 is a side view schematically showing a semiconductor device according to a first embodiment of the present technology. 上記半導体デバイスにおける要部の概略平面図である。It is a schematic plan view of the principal part in the said semiconductor device. 上記半導体デバイスにおけるビアの内部構造を説明する図であり、Ａは要部概略側断面図、Ｂはその平面図である。It is a figure explaining the internal structure of the via | veer in the said semiconductor device, A is a principal part schematic sectional side view, B is the top view. 上記ビアの配置例を示す要部の概略平面図である。It is a schematic plan view of the principal part which shows the example of arrangement | positioning of the said via | veer. 上記ビア間の応力分布を示す図である。It is a figure which shows the stress distribution between the said via | veer. 上記ビアのランド幅の値を変えたときのビア間距離と応力との関係を説明する図である。It is a figure explaining the relationship between the distance between vias, and stress when the value of the land width of the said via is changed. 上記ランド部の厚み及びビア径を変えたときのランド幅と応力との関係を説明する図である。It is a figure explaining the relationship between the land width and stress when the thickness of the said land part and via diameter are changed. ビア径及びランド部厚みとランド幅の上限値との関係を説明する図である。It is a figure explaining the relationship between via diameter and land part thickness, and the upper limit of land width. コンフォーマル型ビア及び埋込型ビアについてのビア間距離と応力との関係を説明する図である。It is a figure explaining the relationship between the distance between via | veer about a conformal type via | veer and an embedded type via, and stress. 上記半導体デバイスの製造方法を説明する概略工程断面図である。It is a schematic process sectional drawing explaining the manufacturing method of the said semiconductor device. 本技術の第１の実施形態に係る半導体デバイスを説明する図であり、Ａは要部の概略側断面図、Ｂはその平面図である。It is a figure explaining the semiconductor device which concerns on 1st Embodiment of this technique, A is a schematic sectional side view of the principal part, B is the top view. 上記ビアの他の配置例を説明する要部概略平面図である。It is a principal part schematic plan view explaining the other example of arrangement | positioning of the said via | veer. 上記ビアの他の構成例を説明する要部概略側断面図である。It is a principal part schematic sectional side view explaining the other structural example of the said via | veer.
　以下、本技術に係る実施形態を、図面を参照しながら説明する。 Hereinafter, embodiments of the present technology will be described with reference to the drawings.
＜第１の実施形態＞
　図１は、本技術の第１の実施形態に係る半導体デバイスを概略的に示す側面図であり、図２はその平面図である。
　各図において、Ｘ軸およびＹ軸は相互に直交する平面方向を示し、Ｚ軸はこれらに直交する高さ（厚み）方向を示している（以後の各図においても同様とする）。 <First Embodiment>
FIG. 1 is a side view schematically showing a semiconductor device according to the first embodiment of the present technology, and FIG. 2 is a plan view thereof.
In each figure, the X-axis and the Y-axis indicate plane directions orthogonal to each other, and the Z-axis indicates a height (thickness) direction orthogonal to these (the same applies to the subsequent figures).
［半導体デバイスの基本構成］
　図１に示すように、本実施形態の半導体デバイス１は、第１の回路基板１０と、第２の回路基板２０との積層構造（ＣｏＣ構造）を有する。半導体デバイス１は、全体的に略直方体形状に形成された単一のパッケージ部品として構成される。第２の回路基板２０は、第１の回路基板１０上に、例えばフリップチップ方式により実装される。 [Basic configuration of semiconductor devices]
As shown in FIG. 1, the semiconductor device 1 of the present embodiment has a stacked structure (CoC structure) of a first circuit board 10 and a second circuit board 20. The semiconductor device 1 is configured as a single package component formed in a substantially rectangular parallelepiped shape as a whole. The second circuit board 20 is mounted on the first circuit board 10 by, for example, a flip chip method.
　半導体デバイス１は、実装基板３０上に実装される。図示の例では半導体デバイス１は、外部接続端子１２０を介して実装基板３０上にフリップチップ実装されるが、これに限られず、ワイヤボンド方式で実装されてもよい。 The semiconductor device 1 is mounted on the mounting substrate 30. In the illustrated example, the semiconductor device 1 is flip-chip mounted on the mounting substrate 30 via the external connection terminals 120, but is not limited thereto, and may be mounted by a wire bond method.
　半導体デバイス１は、例えば、ビデオカメラ、ゲーム機、携帯情報端末等の各種電子機器に搭載される。実装基板３０は、片面基板であってもよいし、両面基板であってもよい。実装基板３０には、半導体デバイス１以外の他の多くの電気・電子デバイスが搭載され、電子機器の制御回路の少なくとも一部を構成する。 The semiconductor device 1 is mounted on various electronic devices such as a video camera, a game machine, and a portable information terminal. The mounting board 30 may be a single-sided board or a double-sided board. Many electric / electronic devices other than the semiconductor device 1 are mounted on the mounting substrate 30 and constitute at least a part of a control circuit of the electronic apparatus.
　続いて、半導体デバイス１を構成する第１及び第２の回路基板１０，２０の詳細について説明する。 Subsequently, details of the first and second circuit boards 10 and 20 constituting the semiconductor device 1 will be described.
　第１の回路基板１０は、基板本体１１を有する。基板本体１１は、第１の主面１１１と、第２の主面１１２とを有する。 The first circuit board 10 has a board body 11. The substrate body 11 has a first main surface 111 and a second main surface 112.
　基板本体１１の平面形状は、典型的には、矩形状である。基板本体１１の厚みは特に限定されず、例えば、１００μｍ～１５０μｍである。基板本体１１は、典型的には、シリコン基板やガリウム－ヒ素基板等の半導体基板で構成される。半導体基板には、トランジスタやメモリ等を含む集積回路、半導体基板の表裏を貫通するビア等が構成される。第１の回路基板１０は、第２の回路基板２０の駆動を制御する制御回路を内蔵してもよい。 The planar shape of the substrate body 11 is typically a rectangular shape. The thickness of the substrate body 11 is not particularly limited, and is, for example, 100 μm to 150 μm. The substrate body 11 is typically composed of a semiconductor substrate such as a silicon substrate or a gallium-arsenide substrate. The semiconductor substrate includes an integrated circuit including a transistor, a memory, and the like, and vias penetrating the front and back of the semiconductor substrate. The first circuit board 10 may incorporate a control circuit that controls driving of the second circuit board 20.
　第１の主面１１１は、基板本体１１の一方の主面（図１において上面）を構成し、第２の主面１１２は、第１の主面１１１とは反対側の主面（図１において下面）を構成する。第１の主面１１１には、複数のパッド部１２１を含む導体パターン１２が形成され、第２の主面１１２には、複数の外部端子１３１を含む導体パターン１３が形成される。 The first main surface 111 constitutes one main surface (upper surface in FIG. 1) of the substrate body 11, and the second main surface 112 is a main surface opposite to the first main surface 111 (FIG. 1). The lower surface). Conductive pattern 12 including a plurality of pad portions 121 is formed on first main surface 111, and conductive pattern 13 including a plurality of external terminals 131 is formed on second main surface 112.
　各導体パターン１２，１３は、典型的には、第１及び第２の主面１１１，１１２を構成するシリコン酸化膜、シリコン窒化膜等の絶縁膜の上に形成される。各導体パターン１２，１３は、第２の回路基板２０との接続領域や外部接続端子１２０の形成領域を除いて、ソルダレジスト等の保護膜で被覆される。 Each of the conductor patterns 12 and 13 is typically formed on an insulating film such as a silicon oxide film or a silicon nitride film constituting the first and second main surfaces 111 and 112. Each of the conductor patterns 12 and 13 is covered with a protective film such as a solder resist except for a connection region with the second circuit board 20 and a region where the external connection terminal 120 is formed.
　各導体パターン１２，１３は、基板本体１１の両主面１１１，１１２に設けられた所定形状の導体層で構成される。各導体パターン１２，１３を構成する導体材料は特に限定されず、Ｃｕ、Ａｌ等の金属単層膜で構成されてもよいし、Ａｕ／Ｔｉ／Ｎｉなどの異種金属の積層膜で構成されてもよい。 Each of the conductor patterns 12 and 13 is composed of a conductor layer having a predetermined shape provided on both main surfaces 111 and 112 of the substrate body 11. The conductor material constituting each of the conductor patterns 12 and 13 is not particularly limited, and may be composed of a metal single layer film such as Cu or Al, or may be composed of a laminated film of different metals such as Au / Ti / Ni. Also good.
　図２に示すように、各パッド部１２１は、第２の回路基板２０の端子面２１１に配置された複数の接続端子２２に対応して配置される。パッド部１２１の数は、外部端子１３１の数と同じでもよいし、異なっていてもよい。これらパッド部１２１及び外部端子１３１は、基板本体１１の内部（ビア１４）を介して相互に電気的に接続される。外部端子１３１は、典型的には、パッド部１２１のレイアウトを第２の主面１１２に再配列する機能を有する。外部接続端子１２０は、例えば、外部端子１３１上に設けられた金属バンプで構成される。 As shown in FIG. 2, each pad portion 121 is arranged corresponding to the plurality of connection terminals 22 arranged on the terminal surface 211 of the second circuit board 20. The number of pad portions 121 may be the same as or different from the number of external terminals 131. The pad portion 121 and the external terminal 131 are electrically connected to each other through the inside (via 14) of the substrate body 11. The external terminal 131 typically has a function of rearranging the layout of the pad portion 121 on the second main surface 112. The external connection terminal 120 is configured by, for example, a metal bump provided on the external terminal 131.
　一方、第２の回路基板２０は、基板本体２１と、複数の接続端子２２とを有する。基板本体２１は、第１の回路基板１０（第１の主面１１１）に対向する端子面２１１を有し、その端子面２１１には、複数の接続端子２２が配置される。 On the other hand, the second circuit board 20 includes a board body 21 and a plurality of connection terminals 22. The board body 21 has a terminal surface 211 that faces the first circuit board 10 (first main surface 111), and a plurality of connection terminals 22 are arranged on the terminal surface 211.
　本実施形態において第２の回路基板２０の平面形状は、第１の回路基板１０と同様に、矩形状に形成される。これに限られず、第２の回路基板１０の平面形状は、他の幾何学的形状に形成されてもよい。また本実施形態において、第２の回路基板２０は、第１の回路基板１０よりも小さいサイズで形成されるが、これに限られず、第１の回路基板１０と同一の大きさに形成されてもよいし、第１の回路基板１０よりも大きいサイズで形成されてもよい。 In the present embodiment, the planar shape of the second circuit board 20 is formed in a rectangular shape like the first circuit board 10. However, the planar shape of the second circuit board 10 may be formed in other geometric shapes. In the present embodiment, the second circuit board 20 is formed in a size smaller than that of the first circuit board 10, but is not limited thereto, and is formed in the same size as the first circuit board 10. Alternatively, it may be formed in a size larger than that of the first circuit board 10.
　第２の回路基板２０は、典型的には、配線基板、ＩＣチップ、センサデバイス等で構成される。具体的には、第２の回路基板２０は、集積回路が表面に形成されたベアチップで構成され、あるいは、ＣＣＤ（Charge Coupled Device）／ＣＭＯＳ（Complementary Metal Oxide Semiconductor）イメージャ等を内蔵した撮像デバイス、ＭＥＭＳ（Micro Electro Mechanical System）技術を用いて作製された角速度センサ等のセンサ部を有する。基板本体２１は、単層のシリコン基板で構成されてもよいし、ＳＯＩ（Silicon On Insulator）基板等の複合基板で構成されてもよい。 The second circuit board 20 is typically composed of a wiring board, an IC chip, a sensor device, and the like. Specifically, the second circuit board 20 is configured by a bare chip having an integrated circuit formed on its surface, or an imaging device incorporating a CCD (Charge-Coupled Device) / CMOS (Complementary Metal-Oxide Semiconductor) imager, It has a sensor section such as an angular velocity sensor manufactured using MEMS (Micro Electro Mechanical System) technology. The substrate body 21 may be composed of a single layer silicon substrate or a composite substrate such as an SOI (Silicon On On Insulator) substrate.
　第２の回路基板２０の各端子部２２は、ハンダ等の導電性接合材を介して第１の回路基板１０のパッド部１２１に電気的、機械的に接続される。第１の回路基板１０と第２の回路基板２０との間には、これらの接合部を補強するためのアンダーフィル樹脂層が形成されてもよい。第２の回路基板２０の各端子部２２は、パッド部１２１を含む導体パターン１２及び複数のビア１４を介して、外部端子１３１に電気的に接続される。 Each terminal portion 22 of the second circuit board 20 is electrically and mechanically connected to the pad portion 121 of the first circuit board 10 via a conductive bonding material such as solder. An underfill resin layer for reinforcing these joints may be formed between the first circuit board 10 and the second circuit board 20. Each terminal portion 22 of the second circuit board 20 is electrically connected to the external terminal 131 through the conductor pattern 12 including the pad portion 121 and the plurality of vias 14.
　次に、第１の回路基板１０に設けられた複数のビア１４について説明する。 Next, the plurality of vias 14 provided in the first circuit board 10 will be described.
　図２に示すように複数のビア１４は、基板本体１１の周縁部に沿って配列されている。典型的には、複数のビア１４は、第１の主面１１１に作り込まれたトランジスタ等の素子を含む集積回路の配置領域、あるいは、パッド部１２１の配置領域よりも外側の領域に配置される。各ビア１４は、所定のパッド部１２１に配線１２２を介して個々に接続される。ビア１４の個数はパッド部１２１の数に対応していてもよいし、対応していなくてもよい。 As shown in FIG. 2, the plurality of vias 14 are arranged along the peripheral edge of the substrate body 11. Typically, the plurality of vias 14 are arranged in an arrangement area of an integrated circuit including an element such as a transistor formed in the first main surface 111 or an area outside the arrangement area of the pad portion 121. The Each via 14 is individually connected to a predetermined pad portion 121 via a wiring 122. The number of vias 14 may or may not correspond to the number of pad portions 121.
　本実施形態において、複数のビア１４各々は、ＴＳＶに相当し、基板本体１１の各コーナ領域に偏って配置されたビア群を構成する。なお、複数のビア１４は、基板本体１１の全てのコーナ領域に偏って配置される例に限られず、少なくとも１つのコーナ領域に偏って配置されてもよい。あるいは、複数のビア１４は、後述するように、基板本体１１のコーナ領域を除く周縁部に偏って配置されたビア群を構成してもよい。 In the present embodiment, each of the plurality of vias 14 corresponds to a TSV and constitutes a group of vias arranged in a biased manner in each corner region of the substrate body 11. Note that the plurality of vias 14 is not limited to the example in which the vias 14 are biased and arranged in all corner areas of the substrate body 11, and may be arranged in a biased manner in at least one corner area. Alternatively, the plurality of vias 14 may constitute a group of vias arranged so as to be biased to the peripheral edge portion excluding the corner region of the substrate body 11 as described later.
　一般にＴＳＶの近傍では、デバイスの使用温度、基板上下のハンダの影響等によって回路形成面に応力勾配が発生する。したがって、ＴＳＶ近傍にトランジスタ等を含む集積回路が存在すると、モビリティが変化する等、デバイス特性の変動あるいは劣化が生じる。一方、デバイス特性の変動を抑えるためには、ＴＳＶの近傍にトランジスタ等の素子を形成を禁止する領域（素子配置禁止領域）を設定しなければならず、この場合には素子形成領域が制限されるという問題を招く。また、十分な素子形成領域を確保しようとすると、デバイスの面積が大型化するという問題を招く。 Generally, in the vicinity of TSV, a stress gradient is generated on the circuit formation surface due to the operating temperature of the device, the influence of solder on the top and bottom of the substrate, and the like. Therefore, when an integrated circuit including a transistor or the like is present in the vicinity of TSV, device characteristics change or deteriorate, such as mobility. On the other hand, in order to suppress fluctuations in device characteristics, it is necessary to set a region for prohibiting the formation of elements such as transistors (element placement prohibited region) in the vicinity of TSV. In this case, the element formation region is limited. Cause the problem of In addition, if a sufficient element formation region is to be secured, there is a problem that the area of the device increases.
　そこで本実施形態では、複数のビア１４各々の構造を工夫することで、ＴＳＶ近傍での強い応力勾配を抑制し、デバイスの小型化を確保しつつ、素子形成領域を確保するようにしている。以下、ビア１４の詳細について説明する。 Therefore, in the present embodiment, by devising the structure of each of the plurality of vias 14, a strong stress gradient in the vicinity of the TSV is suppressed, and the element formation region is ensured while ensuring miniaturization of the device. Hereinafter, details of the via 14 will be described.
　図３Ａ，Ｂは、ビア１４の内部構造を説明する要部の概略断面図及び平面図である。 3A and 3B are a schematic cross-sectional view and a plan view of a main part for explaining the internal structure of the via 14.
　複数のビア１４は、基板本体１１の第１の主面１１１と第２の主面１１２との間を電気的に接続する層間接続部として機能する。複数のビア１４は、コンフォーマル型のビアで構成され、中空の導体部１４１と、ランド部１４２とをそれぞれ有する。 The plurality of vias 14 function as interlayer connection portions that electrically connect the first main surface 111 and the second main surface 112 of the substrate body 11. The plurality of vias 14 are configured as conformal vias, and each have a hollow conductor portion 141 and a land portion 142.
　導体部１４１は、基板本体１１の周縁部に設けられた複数の貫通孔１１３の内部にそれぞれ設けられる。導体部１４１は、典型的には、銅などの金属材料で構成され、スパッタ法あるいは電解メッキ法、あるいはこれらを組み合わせて形成される。貫通孔１１３は、典型的には丸孔で形成され、その内壁面は、基板本体１１の両主面１１１，１１２とともにシリコン酸化膜等の絶縁膜１６で被覆される。導体部１４１は、その絶縁膜１６を介して貫通孔１１３の内壁面上に概略円筒形状に形成される。 The conductor portion 141 is provided in each of the plurality of through holes 113 provided in the peripheral edge portion of the substrate body 11. The conductor 141 is typically made of a metal material such as copper, and is formed by a sputtering method, an electrolytic plating method, or a combination thereof. The through hole 113 is typically formed as a round hole, and its inner wall surface is covered with an insulating film 16 such as a silicon oxide film together with the two main surfaces 111 and 112 of the substrate body 11. The conductor portion 141 is formed in a substantially cylindrical shape on the inner wall surface of the through hole 113 through the insulating film 16.
　導体部１４１は、基板本体１１の第１の表面１１１に露出する第１の端部１４１ａと、基板本体１１の第２の主面１１２に露出する第２の端部１４１ｂとを有する。第１の端部１４１ａは、第１の主面１１１上の導体パターン１２（パッド部１２１、配線部１２２）と電気的に接続され、第２の端部１４１ｂは、第２の主面１１２上の導体パターン１３（外部端子１３１）と電気的に接続される。 The conductor portion 141 has a first end portion 141 a exposed on the first surface 111 of the substrate body 11 and a second end portion 141 b exposed on the second main surface 112 of the substrate body 11. The first end portion 141a is electrically connected to the conductor pattern 12 (pad portion 121, wiring portion 122) on the first main surface 111, and the second end portion 141b is on the second main surface 112. The conductor pattern 13 (external terminal 131) is electrically connected.
　ランド部１４２は、第１の端部１４１ａの周縁部から第１の主面１１１上に延出するように環状に形成される。ランド部１４２は、第１の端部１４１ｂと導体パターン１２とを電気的に接続するためのものであるが、ランド部１４２を介さずに第１の端部１４１ａと導体パターン１２とが直接的に接続されてもよい。ランド部１４２は、典型的には、導体パターン１２と同一の材料で導体パターン１２の形成工程と同時に形成される。 The land portion 142 is formed in an annular shape so as to extend on the first main surface 111 from the peripheral edge portion of the first end portion 141a. The land portion 142 is for electrically connecting the first end portion 141 b and the conductor pattern 12, but the first end portion 141 a and the conductor pattern 12 are directly connected without the land portion 142. May be connected. The land portion 142 is typically formed at the same time as the process of forming the conductor pattern 12 with the same material as that of the conductor pattern 12.
　第２の端部１４１ｂは、導体部１４１の底部を構成し、貫通孔１３の第２の主面１１２側の開口部を閉塞する配線部１３２と電気的に接続される。配線部１３２は、第２の主面１１２上に形成された導体パターン１３の一部を構成するもので、第２の端部１４１ｂと外部端子１３１との間を電気的に接続する。 The second end portion 141b constitutes the bottom portion of the conductor portion 141 and is electrically connected to the wiring portion 132 that closes the opening portion of the through hole 13 on the second main surface 112 side. The wiring part 132 constitutes a part of the conductor pattern 13 formed on the second main surface 112 and electrically connects the second end part 141 b and the external terminal 131.
　ここで、本実施形態におけるビア１４の配置例を、典型的なビアの配置例と比較して説明する。図４Ａは、ビア（ＴＳＶ）の典型的な配置例を示す半導体デバイスの概略平面図である。 Here, an arrangement example of the vias 14 in the present embodiment will be described in comparison with a typical via arrangement example. FIG. 4A is a schematic plan view of a semiconductor device showing a typical arrangement example of vias (TSV).
　典型例におけるビア１４Ａは、図４Ａに示すように半導体基板１１Ａの周縁部に均等な間隔で配置されることが多い。その理由としては、ビア１４Ａ間の距離を極端に狭めると基板応力が大きくなり、クラックが発生しやすくなるなど信頼性に問題が生じるためである。また、ビア１４Ａの近傍の応力勾配で周辺の素子形成領域内の集積回路にデバイス特性の変動をもたらすことがある。このため、応力勾配が比較的大きい領域については、素子配置禁止領域（ＫＯＺ：Keep Out Zone）１４ｚが設けられる。ＫＯＺは、素子サイズによって異なるが、一般的にビアの縁から５０μｍ以上とされる。そのため、図４Ａに示すビア１４Ａの配置例では、素子形成領域（実効的な素子配置可能領域）１１０の面積を大きくすることが困難であった。 The vias 14A in the typical example are often arranged at equal intervals around the periphery of the semiconductor substrate 11A as shown in FIG. 4A. The reason is that if the distance between the vias 14A is extremely narrowed, the substrate stress increases and cracks are likely to occur, resulting in a problem in reliability. In addition, the stress gradient near the via 14A may cause variations in device characteristics in the integrated circuit in the peripheral element formation region. For this reason, an element arrangement prohibition region (KOZ: Keep Out Zone) 14z is provided in a region where the stress gradient is relatively large. Although KOZ varies depending on the element size, it is generally set to 50 μm or more from the edge of the via. Therefore, in the arrangement example of the via 14A shown in FIG. 4A, it is difficult to increase the area of the element formation region (effective element arrangement possible region) 110.
　これに対して本実施形態では、図４Ｂに示すように、基板本体１１の四隅部にビア１４が集約配置される。これにより、素子形成領域１１０が図４Ａの配置例よりも拡大する。例えば、２ｍｍ角の基板に対し、ビア直径を６０μｍ、ＫＯＺをビア縁から５０μｍとし、ビアの中心は基板の端から１２０μｍ離し、基板の四隅はビアを１個分空けるというルールでビアを配置する場合を考える。ビアを各辺の６個ずつ置いたとき、均等に配置した場合（図４Ａ）と、ビア間距離を１２０μｍまで狭めて集中配置した場合（図４Ｂ）とでは、素子形成領域の面積が前者では２．５６ｍｍ2、後者では３．１６ｍｍ2となり、およそ０．６ｍｍ2も異なる。これは、図４Ｂに示すとおり、基板の外側にビア間距離を狭めたことで空きが増えるためである。このとき、隣接する２つのビアについては、ＫＯＺが４０μｍ重なっている。 On the other hand, in the present embodiment, as shown in FIG. 4B, the vias 14 are collectively arranged at the four corners of the substrate body 11. Thereby, the element formation region 110 is enlarged as compared with the arrangement example of FIG. 4A. For example, for a 2 mm square substrate, the via diameter is 60 μm, KOZ is 50 μm from the edge of the via, the via center is 120 μm away from the edge of the substrate, and the vias are arranged according to the rule that the four corners of the substrate are separated by one via. Think about the case. When the six vias are placed on each side, the area of the element formation region is the same when arranged evenly (FIG. 4A) and when concentrated via the distance between vias reduced to 120 μm (FIG. 4B). 2.56 mm 2, the latter in next 3.16 mm 2 is about 0.6 mm 2 are different. This is because, as shown in FIG. 4B, the vacant space is increased by reducing the distance between vias outside the substrate. At this time, KOZ overlaps by 40 μm for two adjacent vias.
　その一方で、ビア間の距離を狭めた場合、上述のとおり、ビア間の基板応力が増加し、基板へのクラックの発生が懸念される。図５は、直径６０μｍのビアに対し、ビア間距離を狭めた場合の応力分布を示すシミュレーション結果である。ビア間距離が１６μｍから１２０μｍまで狭まると、ビアの中点（図中×印の部分）の応力は６０ＭＰａから１３０ＭＰａへと急激に増大する。 On the other hand, when the distance between the vias is narrowed, the substrate stress between the vias increases as described above, and there is a concern that cracks may occur in the substrate. FIG. 5 is a simulation result showing a stress distribution when the distance between vias is narrowed for a via having a diameter of 60 μm. When the distance between vias is narrowed from 16 μm to 120 μm, the stress at the via midpoint (the portion marked with x in the figure) increases rapidly from 60 MPa to 130 MPa.
　本発明者らは、ビア間の応力がビアのランド部のランド幅の大きさに深い相関があることに着目した。図３Ａに示すように、ランド幅Ｗ［μｍ］は、ランド部１４２の外径Ｄ２［μｍ］と導体部１４１の外径Ｄ１［μｍ］との差の２分の１の大きさに相当する。ビア間距離を狭めた場合、ランド幅Ｗの値が小さいほど、ビア間の応力が低下することが確認された。 The present inventors paid attention to the fact that the stress between vias has a deep correlation with the size of the land width of the via land. As shown in FIG. 3A, the land width W [μm] corresponds to a half of the difference between the outer diameter D2 [μm] of the land portion 142 and the outer diameter D1 [μm] of the conductor portion 141. . When the distance between vias was narrowed, it was confirmed that the stress between vias decreased as the land width W value decreased.
　図６に、ランド幅の値を変えたときのビア（ＴＳＶ）間距離と応力との関係を示す。同図に示すように、ビアのランド幅を小さくしていくと、ビア間距離の狭めた場合の応力が大幅に緩和される。これにより、図２及び図４Ｂに示すように、ビア１４を近接させて集中配置した場合においても、応力による基板の破壊等のリスクを大幅に減らすことができるとともに、ＫＯＺを必要以上に大きくする必要がなくなる。 Fig. 6 shows the relationship between the distance between vias (TSV) and the stress when the land width value is changed. As shown in the figure, as the via land width is reduced, the stress when the distance between the vias is reduced is greatly relieved. As a result, as shown in FIG. 2 and FIG. 4B, even when the vias 14 are arranged close to each other, the risk of substrate breakage due to stress can be greatly reduced, and the KOZ is increased more than necessary. There is no need.
　本実施形態において複数のビア１４は、図３Ａに示すように、相互に隣接するビア１４間の最小配列ピッチ（導体部１４１の中心間距離）Ｐが１６０μｍ以下であり、ランド部１４２のランド幅Ｗが２０μｍ以下となるように構成される。配列ピッチＰが１６０μｍを超えると、デバイスの小型化を図ることが困難となり、ランド幅Ｗが２０μｍを超えると、ビア間の応力の緩和を図ることが困難となる。 In the present embodiment, as shown in FIG. 3A, the plurality of vias 14 have a minimum arrangement pitch (distance between the centers of the conductor portions 141) P between adjacent vias 14 of 160 μm or less, and the land width of the land portion 142. W is configured to be 20 μm or less. When the arrangement pitch P exceeds 160 μm, it is difficult to reduce the size of the device, and when the land width W exceeds 20 μm, it is difficult to relieve stress between vias.
　なお、「最小配列ピッチ」とは、例えば図２に示すように、基板本体１１の１コーナ領域に集約されたビア群において、Ｘ軸方向あるいはＹ軸方向に隣接する２つのビア１４間の距離をいう。したがって、同図の左上のコーナ領域に配置されたビア群のうち右端に位置するビアと、同図の右上のコーナ領域に配置されたビア群のうち左端に位置するビアとの間の距離とは区別される。 The “minimum arrangement pitch” is a distance between two vias 14 adjacent to each other in the X-axis direction or the Y-axis direction in a group of vias concentrated in one corner region of the substrate body 11 as shown in FIG. Say. Therefore, the distance between the via located at the right end of the via group arranged in the upper left corner area of the figure and the via located at the left end of the via group arranged in the upper right corner area of the figure Are distinguished.
　本実施形態によれば、複数のビア１４各々のランド部１４２が２０μｍ以下のランド幅Ｗに制限されているため、使用温度によってビア周辺部に発生し得る強い応力分布を緩和して、基板の破損等を防止することができる。さらに、隣接するビア１４間の最小ピッチが１６０μｍ以下に抑えられているため、素子形成領域が拡大される。これにより、デバイスの小型化を図りつつ、素子形成領域の面積を確保することが可能となる。 According to the present embodiment, since the land portion 142 of each of the plurality of vias 14 is limited to a land width W of 20 μm or less, the strong stress distribution that can be generated in the periphery of the via depending on the use temperature is relaxed, and the substrate Damage or the like can be prevented. Furthermore, since the minimum pitch between adjacent vias 14 is suppressed to 160 μm or less, the element formation region is enlarged. Thereby, it is possible to secure the area of the element formation region while reducing the size of the device.
　典型的には、配列ピッチＰは１４０μｍ以下であり、かつ、ランド幅Ｗは０μｍ以上１５μｍ以下となるように各ビア１４が構成される。好適には、配列ピッチＰは１２０μｍ以下、ランド幅Ｗは１０μｍ以下である。これにより、図６に示したように、基板応力の低減と素子形成領域の面積拡大を効果的に実現することができる。
　なお、配列ピッチＰの下限は、ビア１４相互が接触しない（短絡しない）適宜の値とされる。 Typically, each via 14 is configured so that the arrangement pitch P is 140 μm or less and the land width W is 0 μm or more and 15 μm or less. Preferably, the arrangement pitch P is 120 μm or less, and the land width W is 10 μm or less. Thereby, as shown in FIG. 6, it is possible to effectively reduce the substrate stress and increase the area of the element formation region.
The lower limit of the arrangement pitch P is set to an appropriate value so that the vias 14 do not contact each other (do not short-circuit).
　一方、ビア間の応力は、ランド部１４２の厚みＴ及びビア径（導体部１４１の外径）Ｄ１（図３Ａ参照）とも大きな相関を有する。典型的には、ランド部厚みＴ及びビア径Ｄ１の値が大きいほど、ビア間の応力も大きくなる傾向にある。好適には、ビア径は６０μｍ以下であり、ランド部１４２の厚みは６μｍ以下である。 On the other hand, the stress between vias has a large correlation with the thickness T of the land part 142 and the via diameter (outer diameter of the conductor part 141) D1 (see FIG. 3A). Typically, the larger the values of the land portion thickness T and the via diameter D1, the greater the stress between vias. Preferably, the via diameter is 60 μm or less, and the land portion 142 has a thickness of 6 μm or less.
　ランド部厚みＴ及びビア径Ｄ１を変えたときのランド幅と応力との関係を図７に示す。なおこの例では、ビア間距離Ｐを１２０μｍと一定とした。 FIG. 7 shows the relationship between the land width and stress when the land thickness T and via diameter D1 are changed. In this example, the distance P between vias is constant at 120 μm.
　図７に示すように、ランド幅Ｗが２０μｍと比較的大きい場合、ビア径Ｄ１及びランド部厚みＴが大きいものほど応力が大きくなる傾向にある。一方、ランド幅Ｗの値を小さくしていくと、全体的に応力が低減されていくことがわかる。特に、ビア径Ｄ１が大きい場合は応力の減少幅も大きい。結果的に、ランド幅Ｗが５μｍまで小さくなると、ビア径Ｄ１が６０μｍでランド部厚みＴが５μｍである場合の最も応力が大きい条件下であっても、１００ＭＰａ以下にまで応力を低減できることが確認された。 As shown in FIG. 7, when the land width W is relatively large as 20 μm, the larger the via diameter D1 and the land portion thickness T, the larger the stress tends to be. On the other hand, as the value of the land width W is reduced, it is understood that the stress is reduced as a whole. In particular, when the via diameter D1 is large, the reduction width of the stress is also large. As a result, it is confirmed that when the land width W is reduced to 5 μm, the stress can be reduced to 100 MPa or less even under the maximum stress conditions when the via diameter D1 is 60 μm and the land thickness T is 5 μm. It was done.
　基板応力の上限を１００ＭＰａ、ビア間距離Ｐを１４０μｍで固定したときの、ビア径Ｄ１及びランド部厚みＴとランド幅Ｗの上限値との関係を図８Ａ，Ｂにそれぞれ示す。 8A and 8B show the relationship between the via diameter D1, the land portion thickness T, and the land width W when the upper limit of the substrate stress is fixed at 100 MPa and the distance P between the vias is 140 μm.
　ランド幅（Ｗ）の上限値は、図８Ａより、おおよそビア径（Ｄ１）の０．５乗に反比例して変化するとともに、図８Ｂより、ランド部厚み（Ｔ）に対して線形的に変化することが確認された。これらの結果から、ランド幅Ｗの大きさは、ビア径Ｄ１［μｍ］、ランド厚みＴ［μｍ］との間に次式（１）で表される関係を満たす。
　　Ｗ≦（１０［μｍ］－Ｔ）÷（Ｄ１）0.5 ×23.265［μｍ］　…（１） The upper limit value of the land width (W) changes in inverse proportion to the 0.5th power of the via diameter (D1) from FIG. 8A, and linearly changes with respect to the land thickness (T) from FIG. 8B. Confirmed to do. From these results, the size of the land width W satisfies the relationship represented by the following expression (1) between the via diameter D1 [μm] and the land thickness T [μm].
W ≦ (10 [μm] −T) ÷ (D1) 0.5 × 23.265 [μm] (1)
　例えば、複数のビア１４各々のビア径Ｄ１が６０μｍ、ランド部厚みＴが４μｍの場合、ランド幅Ｗの上限値Ｗmaxは、（１）式より、
　　Ｗmax≒（１０－４）÷（６０）0.5×23.265［μｍ］＝18.02［μｍ］
となる。そこで当該条件では、ビアのランド幅Ｗを例えば１５μｍとすることができる。 For example, when the via diameter D1 of each of the plurality of vias 14 is 60 μm and the land portion thickness T is 4 μm, the upper limit value Wmax of the land width W is calculated from the equation (1):
Wmax≈ (10-4) ÷ (60) 0.5 × 23.265 [μm] = 18.02 [μm]
It becomes. Under these conditions, the via land width W can be set to 15 μm, for example.
　また、複数のビア１４各々のビア径Ｄ１が５０μｍ、ランド部厚みＴが６μｍの場合、ランド幅Ｗの上限値Ｗmaxは、（１）式より、
　　（１０－６）÷（５０）0.5×23.265［μｍ］＝13.16［μｍ］
となる。そこで当該条件では、ビアのランド幅Ｗを例えば１０μｍとすることができる。 Further, when the via diameter D1 of each of the plurality of vias 14 is 50 μm and the land portion thickness T is 6 μm, the upper limit value Wmax of the land width W is calculated from the equation (1):
(10-6) ÷ (50) 0.5 x 23.265 [μm] = 13.16 [μm]
It becomes. Under these conditions, the via land width W can be set to 10 μm, for example.
　さらに本実施形態では、複数のビア１４各々が中空の導体部１４１を有するコンフォーマル型のビアで構成されているため、貫通孔１１３の内部が導体で埋め込まれた構造（以下、埋込型ともいう）のビアと比較して、ビア間の応力をより緩和することができる。 Further, in the present embodiment, each of the plurality of vias 14 is formed of a conformal type via having a hollow conductor portion 141, and therefore, a structure in which the inside of the through hole 113 is embedded with a conductor (hereinafter referred to as an embedded type). The stress between the vias can be further relaxed compared to the via.
　コンフォーマル型ビア及び埋込型ビアについてのビア間距離と応力との関係を図９に示す。同図に示すように、コンフォーマル型のビアでは、埋込型に比べて応力がおよそ半分程度となる。よって、ビア間の狭ピッチ化に伴う応力の増大を効果的に抑制することができる。 Fig. 9 shows the relationship between inter-via distance and stress for conformal vias and buried vias. As shown in the figure, in the conformal via, the stress is about half that in the buried type. Therefore, an increase in stress associated with a narrow pitch between vias can be effectively suppressed.
　以上のように本実施形態によれば、第１の回路基板１０に設けられる複数のビア１４が上述のように構成されているため、基板本体１０の面内の応力勾配を緩和しつつビア間距離を狭めることができ、デバイスサイズを大型化することなく素子形成領域の面積の拡大を図ることができる。また、素子形成領域内に作り込まれた集積回路の動作特性の変動を阻止できるため、電子部品１の信頼性を高めることができる。 As described above, according to this embodiment, since the plurality of vias 14 provided in the first circuit board 10 are configured as described above, the stress gradient in the plane of the substrate body 10 is reduced and the gap between vias is reduced. The distance can be reduced, and the area of the element formation region can be increased without increasing the device size. In addition, since the fluctuation of the operating characteristics of the integrated circuit built in the element formation region can be prevented, the reliability of the electronic component 1 can be improved.
［製造方法］
　続いて、第１の回路基板１０の製造方法について説明する。図１０は、第１の回路基板１０の製造方法を説明する要部の概略工程断面図である。 [Production method]
Then, the manufacturing method of the 1st circuit board 10 is demonstrated. FIG. 10 is a schematic process cross-sectional view of the main part for explaining the manufacturing method of the first circuit board 10.
　まず図１０Ａに示すように、複数の貫通孔１１３が設けられた基板本体１１の両主面１１１，１１２及び各貫通孔１１３の内壁面に、シリコン酸化膜等の絶縁膜１６が形成される。絶縁膜１６は、典型的には熱酸化膜であるが、これに限られず、蒸着膜等であってもよい。その後、基板本体１１の第２の主面１１２に、各貫通孔１１３の一端を閉塞する導体パターン（配線部１３２）が形成される。 First, as shown in FIG. 10A, an insulating film 16 such as a silicon oxide film is formed on both main surfaces 111 and 112 of the substrate body 11 provided with a plurality of through holes 113 and on the inner wall surface of each through hole 113. The insulating film 16 is typically a thermal oxide film, but is not limited thereto, and may be a vapor deposition film or the like. Thereafter, a conductor pattern (wiring portion 132) that closes one end of each through hole 113 is formed on the second main surface 112 of the substrate body 11.
　複数の貫通孔１１３は、基板本体１１の周縁部（本例では各コーナ領域の近傍）に１６０μｍ以下の所定の最小配列ピッチで形成される。貫通孔１１３の形成方法は特に限定されず、例えばＲＩＥ（Reactive Ion Etching）等のドライプロセスで形成される。 The plurality of through holes 113 are formed at a predetermined minimum arrangement pitch of 160 μm or less at the peripheral edge of the substrate body 11 (in the vicinity of each corner region in this example). The formation method of the through-hole 113 is not specifically limited, For example, it forms by dry processes, such as RIE (Reactive * Ion | Etching).
　続いて図１０Ｂに示すように、基板本体１１の第１の主面１１１に、ビア形成用のシード層（給電層）１４０が形成される。シード層１４０は、典型的にはスパッタ法により、第１の主面１１１及び貫通孔１１３の内壁面を被覆する絶縁層１６の上にそれぞれ形成される。また、シード層１４０は、貫通孔１１３の一端を閉塞する配線部１３２の内面にも形成される。 Subsequently, as shown in FIG. 10B, a seed layer (feeding layer) 140 for forming vias is formed on the first main surface 111 of the substrate body 11. The seed layer 140 is typically formed on the insulating layer 16 covering the first main surface 111 and the inner wall surface of the through hole 113 by sputtering. The seed layer 140 is also formed on the inner surface of the wiring part 132 that closes one end of the through hole 113.
　続いて図１０Ｃに示すように、基板本体１１の第１の主面１１１に、シード層１４０をエッチングするためのマスクパターン１７が形成される。マスクパターン１７は、貫通孔１１３の内部及びその周縁部、配線領域など、導体パターン１２が形成される領域を被覆する形状にパターニングされる。マスクパターン１７は、使用するエッチング液に対して、シード層１４０と所定以上のエッチング選択比を確保することができる材料で構成され、例えば金属、金属化合物等の無機材料、あるいは有機材料等で構成される。 Subsequently, as shown in FIG. 10C, a mask pattern 17 for etching the seed layer 140 is formed on the first main surface 111 of the substrate body 11. The mask pattern 17 is patterned into a shape that covers a region where the conductor pattern 12 is formed, such as the inside of the through hole 113 and its peripheral edge, and a wiring region. The mask pattern 17 is made of a material that can ensure an etching selectivity ratio higher than a predetermined level with the seed layer 140 with respect to the etching solution to be used. Is done.
　続いて図１０Ｄに示すように、マスクパターン１７をエッチングマスクとするウェットエッチング法により、シード層１４０がパターンエッチングされる。これにより、導体パターン１２（パッド部１２１、配線部１２２）やビア１４の下地層が形成される。 Subsequently, as shown in FIG. 10D, the seed layer 140 is pattern-etched by a wet etching method using the mask pattern 17 as an etching mask. Thereby, the conductor pattern 12 (pad portion 121, wiring portion 122) and the underlayer of the via 14 are formed.
　このときのエッチング条件として、本実施形態では、マスクパターン１７で被覆されるシード層１４０のうち、ビア１４のランド部１４２の下地層に相当する領域１４２ａが、所定以上サイドエッチングされる条件が採用される。領域１４２ａのサイドエッチング量は、最終的にランド幅が２０μｍ以下となるような値であれば、特に限定されず、典型的には、エッチング時間で制御される。 As an etching condition at this time, in the present embodiment, a condition is adopted in which, in the seed layer 140 covered with the mask pattern 17, a region 142a corresponding to the ground layer of the land portion 142 of the via 14 is side-etched by a predetermined amount or more. Is done. The side etching amount of the region 142a is not particularly limited as long as the land width is finally 20 μm or less, and is typically controlled by the etching time.
　なお、当該エッチング条件は領域１４２ａ以外の他の領域にも同様に適用されるため、例えば配線部１２２の形成領域を被覆するマスクパターン１７の領域は、断線を阻止することができる程度の幅で形成される。 Since the etching conditions are similarly applied to other regions other than the region 142a, for example, the region of the mask pattern 17 covering the region where the wiring part 122 is formed has a width that can prevent disconnection. It is formed.
　続いて図１０Ｅに示すように、マスクパターン１７が除去された後、パターニングされたシード層１４０の上に銅メッキ等の所定厚みのメッキ層が形成される。これにより、中空の導体部１４１及びランド部１４２を含むビア１４や、パッド部１２１及び配線部１２２を含む導体パターン１２（図２）が形成される。 Subsequently, as shown in FIG. 10E, after the mask pattern 17 is removed, a plating layer of a predetermined thickness such as copper plating is formed on the patterned seed layer 140. Thereby, the via 14 including the hollow conductor portion 141 and the land portion 142 and the conductor pattern 12 (FIG. 2) including the pad portion 121 and the wiring portion 122 are formed.
　メッキ法は特に限定されず、典型的には、電解メッキ法が採用される。これにより、貫通孔１１３の内部及び第１の主面１１１上に所定厚みの導体層を容易に形成することができる。上記メッキ層の厚みは特に限定されず、本実施形態では、ランド部１４２の厚みが６μｍ以下となる厚みで上記メッキ層が形成される。 The plating method is not particularly limited, and typically, an electrolytic plating method is employed. Thereby, a conductor layer having a predetermined thickness can be easily formed in the through hole 113 and on the first main surface 111. The thickness of the plating layer is not particularly limited. In the present embodiment, the plating layer is formed with a thickness such that the land portion 142 has a thickness of 6 μm or less.
　以上のようにして、本実施形態における第１の回路基板１０が作製される。本実施形態において、各ビア１４のランド部１４２のランド幅は、当該ランド部１４２（領域１４２ａ）のサイドエッチング量で制御しているため、マスクパターン１７の高精度な形状制御を必要とすることなく所望の大きさのランド幅を有するビア１４を形成することができる。すなわち、マスクパターン１７のアライメント精度以下の精度で、ランド部１４２を高精度に制御することが可能となる。 As described above, the first circuit board 10 in the present embodiment is manufactured. In the present embodiment, since the land width of the land portion 142 of each via 14 is controlled by the side etching amount of the land portion 142 (region 142a), it is necessary to control the shape of the mask pattern 17 with high accuracy. The via 14 having a desired land width can be formed. That is, it is possible to control the land portion 142 with high accuracy with accuracy equal to or lower than the alignment accuracy of the mask pattern 17.
＜第２の実施形態＞
　図１１Ａ，Ｂは、本技術の第２の実施形態に係る半導体デバイスの構成を示す要部の概略断面図及び平面図である。
　以下、第１の実施形態と異なる構成について主に説明し、第１の実施形態と同様の構成については同様の符号を付しその説明を省略または簡略化する。 <Second Embodiment>
11A and 11B are a schematic cross-sectional view and a plan view of the main part showing the configuration of the semiconductor device according to the second embodiment of the present technology.
Hereinafter, the configuration different from the first embodiment will be mainly described, and the same configuration as the first embodiment will be denoted by the same reference numeral, and the description thereof will be omitted or simplified.
　同図に示す回路基板１００は、第１の実施形態における第１の回路基板１０に相当し、本実施形態では、隣接するビア１４の間にトレンチ部１０１が設けられている点で第１の実施形態と異なる。 The circuit board 100 shown in the figure corresponds to the first circuit board 10 in the first embodiment. In this embodiment, the first circuit board 100 is provided with a trench portion 101 between adjacent vias 14. Different from the embodiment.
　トレンチ部１０１は、基板本体１１の第１の主面１１１であって、隣接する２つのビア１４間の領域を分断するように形成されたハーフトレンチで構成される。トレンチ部１０１は、典型的には、基板本体１１の周縁部から内方に向かって直線的に形成される。ビア１４の間にトレンチ部１０１を設けることによって、ビア１４間の応力分布をさらに緩和することができるので、ビア間距離（Ｐ）のさらなる縮小を図ることができる。 The trench portion 101 is a first main surface 111 of the substrate body 11 and is formed of a half trench formed so as to divide a region between two adjacent vias 14. The trench portion 101 is typically formed linearly from the periphery of the substrate body 11 inward. By providing the trench portion 101 between the vias 14, the stress distribution between the vias 14 can be further relaxed, so that the distance (P) between the vias can be further reduced.
　トレンチ部１０１の幅（Ｘ軸方向）、深さ（Ｚ軸方向）、長さ（Ｙ軸方向）は特に限定されず、基板本体１１の強度を確保しつつ、ビア間の応力分布を緩和できる適宜の値に設定される。例えば、基板本体１１の厚みが１００μｍ、ビア間の最小配列ピッチＰが１６０μｍ以下である場合、トレンチ部１０１の幅は１０μｍ、深さは５０μｍ、長さは１２０μｍとすることができる。 The width (X-axis direction), depth (Z-axis direction), and length (Y-axis direction) of the trench portion 101 are not particularly limited, and stress distribution between vias can be relaxed while ensuring the strength of the substrate body 11. An appropriate value is set. For example, when the thickness of the substrate body 11 is 100 μm and the minimum arrangement pitch P between vias is 160 μm or less, the width of the trench portion 101 can be 10 μm, the depth can be 50 μm, and the length can be 120 μm.
　トレンチ部１０１は、ビア１４の間に複数設けられてもよい。あるいは、トレンチ部１０１は直線的なものに限られず、曲線的な形状であってもよいし、複数の直線部が組み合わされた形状等であってもよい。 A plurality of trench portions 101 may be provided between the vias 14. Or the trench part 101 is not restricted to a linear thing, A curved shape may be sufficient, and the shape etc. which the some linear part was combined may be sufficient.
＜変形例＞
以上、本技術の実施形態について説明したが、本技術は上述の実施形態にのみ限定されるものではなく、種々変更を加え得ることは勿論である。 <Modification>
As mentioned above, although embodiment of this technique was described, this technique is not limited only to the above-mentioned embodiment, Of course, a various change can be added.
　例えば以上の実施形態では、複数のビア１４が基板本体１１の各コーナ領域に集中して配置される例について説明したが、これに代えて、複数のビア１４は、基板本体１１のコーナ領域を除く周縁部に偏って配置されたビア群で構成されてもよい。この場合、例えば基板本体１１の厚みが比較的小さい場合においては、反り量が最も大きい基板の四隅を避けてビアを形成することで、ビア１４の接続信頼性を確保することができる。 For example, in the above-described embodiment, the example in which the plurality of vias 14 are concentrated on each corner area of the substrate body 11 has been described. Instead, the plurality of vias 14 are arranged in the corner area of the substrate body 11. You may be comprised by the via group arrange | positioned biased to the peripheral part except. In this case, for example, when the thickness of the substrate body 11 is relatively small, the connection reliability of the vias 14 can be ensured by forming the vias avoiding the four corners of the substrate having the largest amount of warpage.
　一方、例えば基板本体１１の厚みが比較的大きく、四隅の反り量が問題にならない程度に抑えられる場合においては、例えば図１２に示すように、素子形成領域１１０を基板本体の四隅部にまで拡大することができる。これにより、デバイスの小型化をより促進することが可能となる。 On the other hand, for example, when the thickness of the substrate body 11 is relatively large and the amount of warping at the four corners can be suppressed to a problem, the element formation region 110 is expanded to the four corners of the substrate body, for example, as shown in FIG. can do. Thereby, it becomes possible to further promote downsizing of the device.
　また以上の実施形態では、各ビア１４は、導体部１４１の第１の端部１４１ａ側にのみランド部１４２が設けられた例について説明したが、これに限られず、図１３に示す半導体デバイス３００のように、第２の端部１４１ｂ側にもランド部１４２が設けられてもよい。この場合も、第２の端部１４１ｂ側のランド部１４２が第１の端部１４１ａ側のランド部１４２と同一の条件で構成されることにより、上述の各実施形態と同様の作用効果を得ることができる。 In the above embodiment, the example in which each via 14 is provided with the land portion 142 only on the first end portion 141a side of the conductor portion 141 has been described. However, the present invention is not limited to this, and the semiconductor device 300 shown in FIG. As described above, the land portion 142 may also be provided on the second end portion 141b side. Also in this case, the land portion 142 on the second end portion 141b side is configured under the same conditions as the land portion 142 on the first end portion 141a side, thereby obtaining the same operational effects as those of the above-described embodiments. be able to.
　また以上の実施形態では、複数のビア１４が基板本体１１の周縁部に沿って配置された例を説明したが、これに代えて又はこれに加えて、基板本体１１の面内中央部に配置されてもよい。 In the above embodiment, the example in which the plurality of vias 14 are arranged along the peripheral edge of the substrate main body 11 has been described. However, instead of or in addition to this, the via 14 is arranged in the in-plane central portion of the substrate main body 11. May be.
　さらに以上の実施形態では、半導体デバイスとしてＣｏＣ構造の電子部品、あるいはＣｏＣ用の半導体デバイスを例に挙げて説明したが、これに限られず、単層の半導体デバイスにも同様に適用可能である。 In the above embodiment, the electronic device having the CoC structure or the semiconductor device for CoC has been described as an example of the semiconductor device. However, the present invention is not limited to this, and can be similarly applied to a single-layer semiconductor device.
　なお、本技術は以下のような構成もとることができる。
（１）　第１の主面と、前記第１の主面とは反対側の第２の主面と、前記第１の主面及び前記第２の主面の少なくとも一方に設けられた素子形成領域を有する基板本体と、
　前記基板本体に配列された複数のビアと
　を具備し、
　前記複数のビアは、
　前記第１の主面に露出する第１の端部と前記第２の主面に露出する第２の端部とを有し前記基板本体を貫通する中空の導体部と、前記第１の端部の周縁部から前記第１の主面上に延出する環状のランド部とをそれぞれ有し、
　前記導体部の最小配列ピッチは１６０μｍ以下であり、前記ランド部のランド幅は２０μｍ以下である
　半導体デバイス。
（２）上記（１）に記載の半導体デバイスであって、
　前記複数のビアは、前記基板本体の周縁部に沿って配列される
　半導体デバイス。
（３）上記（１）又は（２）に記載の半導体デバイスであって、
　前記導体部の最小配列ピッチは１４０μｍ以下であり、前記ランド幅は０以上１５μｍ以下である
　半導体デバイス。
（４）上記（３）に記載の半導体デバイスであって、
　前記導体部の外径は６０μｍ以下であり、前記ランド部の厚みは６μｍ以下である
　半導体デバイス。
（５）上記（１）～（４）のいずれか１つに記載の半導体デバイスであって、
　前記導体部の外径をＤ１［μｍ］、前記ランド部の厚みをＴ［μｍ］、前記ランド幅をＷ［μｍ］としたとき、Ｄ１、Ｔ及びＷは、
　　Ｗ≦（１０［μｍ］－Ｔ）÷（Ｄ１）0.5 ×23.265［μｍ］
の関係を満たす
　半導体デバイス。
（６）上記（１）～（５）のいずれか１つに記載の半導体デバイスであって、
　前記基板本体の平面形状は矩形状であり、
　前記複数のビアは、前記基板本体の少なくとも１つのコーナ領域に偏って配置されたビア群を含む
　半導体デバイス。
（７）上記（１）～（５）のいずれか１つに記載の半導体デバイスであって、
　前記基板本体の平面形状は矩形状であり、
　前記複数のビアは、前記基板本体のコーナ領域を除く周縁部に偏って配置されたビア群を含む
　半導体デバイス。
（８）上記（１）～（７）のいずれか１つに記載の半導体デバイスであって、
　前記基板本体は、前記第１の主面に設けられ前記複数のビア各々の間に配置されたトレンチ部をさらに有する
　半導体デバイス。
（９）上記（１）～（８）のいずれか１つに記載の半導体デバイスであって、
　前記第１の主面に配置され、前記複数のビアと電気的に接続される回路基板をさらに具備する
　半導体デバイス。
（１０）上記（９）に記載の半導体デバイスであって、
　前記回路基板は、半導体素子又はセンサ素子である
　半導体デバイス。
（１１）　基板本体に複数の貫通孔を、その最小配列ピッチが１６０μｍ以下となるように形成し、
　前記基板本体に、前記複数の貫通孔各々の内壁面を被覆する中空の導体部と前記基板本体の表面を被覆する導体層とをそれぞれ形成し、
　前記導体層の上にマスクパターンを形成し、
　前記マスクパターンをマスクとして前記導体層をウェットエッチングすることで、前記導体部の端部の周縁部から前記基板本体の表面上に延出する環状のランド部を２０μｍ以下のランド幅となるように形成する
　半導体デバイスの製造方法。
（１２）上記（１１）に記載の半導体デバイスの製造方法であって、
　前記マスクパターンを形成する工程は、前記複数の貫通孔各々の周縁部を被覆するパターン幅が２０μｍ以上の円環状のマスク部を形成することを含み、
　前記ランド部は、前記マスク部で被覆される前記導体層の領域をサイドエッチングすることで形成される
　半導体デバイスの製造方法。 In addition, this technique can also take the following structures.
(1) Element formation provided on at least one of the first main surface, the second main surface opposite to the first main surface, and the first main surface and the second main surface A substrate body having a region;
A plurality of vias arranged in the substrate body,
The plurality of vias are
A hollow conductor having a first end exposed on the first main surface and a second end exposed on the second main surface and penetrating the substrate body; and the first end Each having an annular land portion extending from the peripheral portion of the portion onto the first main surface,
The minimum arrangement pitch of the said conductor part is 160 micrometers or less, and the land width of the said land part is 20 micrometers or less. Semiconductor device.
(2) The semiconductor device according to (1) above,
The plurality of vias are arranged along a peripheral edge of the substrate body.
(3) The semiconductor device according to (1) or (2) above,
The minimum arrangement pitch of the said conductor part is 140 micrometers or less, and the said land width is 0-15 micrometer. Semiconductor device.
(4) The semiconductor device according to (3) above,
The semiconductor device has an outer diameter of 60 μm or less and a thickness of the land portion of 6 μm or less.
(5) The semiconductor device according to any one of (1) to (4) above,
When the outer diameter of the conductor portion is D1 [μm], the thickness of the land portion is T [μm], and the land width is W [μm], D1, T and W are:
W ≦ (10 [μm] −T) ÷ (D1) 0.5 × 23.265 [μm]
A semiconductor device that satisfies the above relationship.
(6) The semiconductor device according to any one of (1) to (5) above,
The planar shape of the substrate body is rectangular,
The plurality of vias include a group of vias arranged in a biased manner in at least one corner region of the substrate body.
(7) The semiconductor device according to any one of (1) to (5) above,
The planar shape of the substrate body is rectangular,
The plurality of vias include a group of vias arranged in a biased manner on a peripheral edge except for a corner region of the substrate body.
(8) The semiconductor device according to any one of (1) to (7) above,
The substrate body further includes a trench portion provided on the first main surface and disposed between each of the plurality of vias.
(9) The semiconductor device according to any one of (1) to (8) above,
A semiconductor device further comprising a circuit board disposed on the first main surface and electrically connected to the plurality of vias.
(10) The semiconductor device according to (9) above,
The circuit board is a semiconductor element or a sensor element.
(11) A plurality of through holes are formed in the substrate body so that the minimum arrangement pitch is 160 μm or less,
A hollow conductor portion covering the inner wall surface of each of the plurality of through holes and a conductor layer covering the surface of the substrate body are formed on the substrate body,
Forming a mask pattern on the conductor layer;
By performing wet etching on the conductor layer using the mask pattern as a mask, an annular land portion extending from the peripheral edge portion of the end portion of the conductor portion onto the surface of the substrate body has a land width of 20 μm or less. A method of manufacturing a semiconductor device to be formed.
(12) A method of manufacturing a semiconductor device according to (11) above,
The step of forming the mask pattern includes forming an annular mask portion having a pattern width of 20 μm or more covering a peripheral portion of each of the plurality of through holes.
The land portion is formed by side etching a region of the conductor layer covered with the mask portion.
　１…電子部品
　１０，１００，３００…第１の回路基板（半導体デバイス）
　１１…基板本体
　１４…ビア（ＴＳＶ）
　１７…マスクパターン
　２０…第２の回路基板
　１０１…トレンチ部
　１１１…第１の主面
　１１２…第２の主面
　１１３…貫通孔
　１４１…導体部
　１４１ａ…第１の端部
　１４１ｂ…第２の端部
　１４２…ランド部 DESCRIPTION OF SYMBOLS 1 ... Electronic component 10, 100, 300 ... 1st circuit board (semiconductor device)
11 ... Board body 14 ... Via (TSV)
DESCRIPTION OF SYMBOLS 17 ... Mask pattern 20 ... 2nd circuit board 101 ... Trench part 111 ... 1st main surface 112 ... 2nd main surface 113 ... Through-hole 141 ... Conductor part 141a ... 1st edge part 141b ... 2nd edge Part 142 ... Land part

Claims (12)

  1. 　第１の主面と、前記第１の主面とは反対側の第２の主面と、前記第１の主面及び前記第２の主面の少なくとも一方に設けられた素子形成領域を有する基板本体と、
    　前記基板本体に配列された複数のビアと
    　を具備し、
    　前記複数のビアは、
    　前記第１の主面に露出する第１の端部と前記第２の主面に露出する第２の端部とを有し前記基板本体を貫通する中空の導体部と、前記第１の端部の周縁部から前記第１の主面上に延出する環状のランド部とをそれぞれ有し、
    　前記導体部の最小配列ピッチは１６０μｍ以下であり、前記ランド部のランド幅は２０μｍ以下である
    　半導体デバイス。     A first main surface; a second main surface opposite to the first main surface; and an element formation region provided on at least one of the first main surface and the second main surface. A substrate body;
    A plurality of vias arranged in the substrate body,
    The plurality of vias are
    A hollow conductor having a first end exposed on the first main surface and a second end exposed on the second main surface and penetrating the substrate body; and the first end Each having an annular land portion extending from the peripheral portion of the portion onto the first main surface,
    The minimum arrangement pitch of the said conductor part is 160 micrometers or less, and the land width of the said land part is 20 micrometers or less. Semiconductor device.
  2. 　請求項１に記載の半導体デバイスであって、
    　前記複数のビアは、前記基板本体の周縁部に沿って配列される
    　半導体デバイス。     The semiconductor device according to claim 1,
    The plurality of vias are arranged along a peripheral edge of the substrate body.
  3. 　請求項１に記載の半導体デバイスであって、
    　前記導体部の最小配列ピッチは１４０μｍ以下であり、前記ランド幅は０以上１５μｍ以下である
    　半導体デバイス。     The semiconductor device according to claim 1,
    The minimum arrangement pitch of the said conductor part is 140 micrometers or less, and the said land width is 0-15 micrometer. Semiconductor device.
  4. 　請求項３に記載の半導体デバイスであって、
    　前記導体部の外径は６０μｍ以下であり、前記ランド部の厚みは６μｍ以下である
    　半導体デバイス。     A semiconductor device according to claim 3, wherein
    The semiconductor device has an outer diameter of 60 μm or less and a thickness of the land portion of 6 μm or less.
  5. 　請求項１に記載の半導体デバイスであって、
    　前記導体部の外径をＤ１［μｍ］、前記ランド部の厚みをＴ［μｍ］、前記ランド幅をＷ［μｍ］としたとき、Ｄ１、Ｔ及びＷは、
    　　Ｗ≦（１０［μｍ］－Ｔ）÷（Ｄ１）0.5 ×23.265［μｍ］
    の関係を満たす
    　半導体デバイス。     The semiconductor device according to claim 1,
    When the outer diameter of the conductor portion is D1 [μm], the thickness of the land portion is T [μm], and the land width is W [μm], D1, T and W are:
    W ≦ (10 [μm] −T) ÷ (D1) 0.5 × 23.265 [μm]
    A semiconductor device that satisfies the above relationship.
  6. 　請求項１に記載の半導体デバイスであって、
    　前記基板本体の平面形状は矩形状であり、
    　前記複数のビアは、前記基板本体の少なくとも１つのコーナ領域に偏って配置されたビア群を含む
    　半導体デバイス。     The semiconductor device according to claim 1,
    The planar shape of the substrate body is rectangular,
    The plurality of vias include a group of vias arranged in a biased manner in at least one corner region of the substrate body.
  7. 　請求項１に記載の半導体デバイスであって、
    　前記基板本体の平面形状は矩形状であり、
    　前記複数のビアは、前記基板本体のコーナ領域を除く周縁部に偏って配置されたビア群を含む
    　半導体デバイス。     The semiconductor device according to claim 1,
    The planar shape of the substrate body is rectangular,
    The plurality of vias include a group of vias arranged in a biased manner on a peripheral edge except for a corner region of the substrate body.
  8. 　請求項１に記載の半導体デバイスであって、
    　前記基板本体は、前記第１の主面に設けられ前記複数のビア各々の間に配置されたトレンチ部をさらに有する
    　半導体デバイス。     The semiconductor device according to claim 1,
    The substrate body further includes a trench portion provided on the first main surface and disposed between each of the plurality of vias.
  9. 　請求項１に記載の半導体デバイスであって、
    　前記第１の主面に配置され、前記複数のビアと電気的に接続される回路基板をさらに具備する
    　半導体デバイス。     The semiconductor device according to claim 1,
    A semiconductor device further comprising a circuit board disposed on the first main surface and electrically connected to the plurality of vias.
  10. 　請求項９に記載の半導体デバイスであって、
    　前記回路基板は、半導体素子又はセンサ素子である
    　半導体デバイス。     A semiconductor device according to claim 9, wherein
    The circuit board is a semiconductor element or a sensor element.
  11. 　基板本体に複数の貫通孔を、その最小配列ピッチが１６０μｍ以下となるように形成し、
    　前記基板本体に、前記複数の貫通孔各々の内壁面を被覆する中空の導体部と前記基板本体の表面を被覆する導体層とをそれぞれ形成し、
    　前記導体層の上にマスクパターンを形成し、
    　前記マスクパターンをマスクとして前記導体層をウェットエッチングすることで、前記導体部の端部の周縁部から前記基板本体の表面上に延出する環状のランド部を２０μｍ以下のランド幅となるように形成する
    　半導体デバイスの製造方法。     A plurality of through holes are formed in the substrate body so that the minimum arrangement pitch is 160 μm or less,
    A hollow conductor portion covering the inner wall surface of each of the plurality of through holes and a conductor layer covering the surface of the substrate body are formed on the substrate body,
    Forming a mask pattern on the conductor layer;
    By performing wet etching on the conductor layer using the mask pattern as a mask, an annular land portion extending from the peripheral edge portion of the end portion of the conductor portion onto the surface of the substrate body has a land width of 20 μm or less. A method of manufacturing a semiconductor device to be formed.
  12. 　請求項１１に記載の半導体デバイスの製造方法であって、
    　前記ランド部は、前記マスクパターンで被覆される前記導体層の領域をサイドエッチングすることで形成される
    　半導体デバイスの製造方法。     A method of manufacturing a semiconductor device according to claim 11,
    The land part is formed by side-etching a region of the conductor layer covered with the mask pattern.
PCT/JP2016/088735 2016-02-16 2016-12-26 Semiconductor device and method for manufacturing same WO2017141547A1 (en)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2010023812A1 (en) * 2008-08-28 2010-03-04 パナソニック株式会社 Semiconductor device
JP2012124484A (en) * 2010-12-07 2012-06-28 Imec Method for forming isolation trench
JP2012253182A (en) * 2011-06-02 2012-12-20 Panasonic Corp Semiconductor device and method of manufacturing the same
JP2014170793A (en) * 2013-03-01 2014-09-18 Fujitsu Semiconductor Ltd Semiconductor device, semiconductor device manufacturing method and electronic apparatus

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2010023812A1 (en) * 2008-08-28 2010-03-04 パナソニック株式会社 Semiconductor device
JP2012124484A (en) * 2010-12-07 2012-06-28 Imec Method for forming isolation trench
JP2012253182A (en) * 2011-06-02 2012-12-20 Panasonic Corp Semiconductor device and method of manufacturing the same
JP2014170793A (en) * 2013-03-01 2014-09-18 Fujitsu Semiconductor Ltd Semiconductor device, semiconductor device manufacturing method and electronic apparatus

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