WO2011148444A1 - Semiconductor device and method for manufacturing same - Google Patents

Semiconductor device and method for manufacturing same Download PDF

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Publication number
WO2011148444A1
WO2011148444A1 PCT/JP2010/007013 JP2010007013W WO2011148444A1 WO 2011148444 A1 WO2011148444 A1 WO 2011148444A1 JP 2010007013 W JP2010007013 W JP 2010007013W WO 2011148444 A1 WO2011148444 A1 WO 2011148444A1
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Prior art keywords
electrode
semiconductor device
semiconductor substrate
recess
film
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PCT/JP2010/007013
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French (fr)
Japanese (ja)
Inventor
青井信雄
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パナソニック株式会社
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Publication of WO2011148444A1 publication Critical patent/WO2011148444A1/en

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Definitions

  • the present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a chip-chip stacking, a chip-wafer stacking or a wafer-wafer stacking semiconductor device and a manufacturing method thereof.
  • the thermal conductivity of a TEOS (tetraethylorthosilicate) film is as low as about 1.2 W / (m ⁇ K), which is a factor that hinders heat dissipation of the semiconductor substrate.
  • an object of the present invention is to provide a semiconductor device having a heat dissipation structure with high heat dissipation efficiency and a method for manufacturing the same, which can obtain a sufficient heat dissipation effect even when a three-dimensional integration technique is applied.
  • the inventor of the present application leads to the outside of the three-dimensional semiconductor chip in the three-dimensional semiconductor chip configuration disclosed in Patent Document 1, that is, the surface of each LSI chip to which other chips are bonded.
  • Patent Document 1 the surface of each LSI chip to which other chips are bonded.
  • the inventor of the present application prevents the electrical short circuit between the through electrode and the semiconductor substrate, and provides a heat dissipation recess connected to the through electrode on the back surface of the substrate, or the back surface of the substrate.
  • an insulating high heat dissipation material film specifically, a diamond-like carbon film
  • the inventors have come up with an invention that realizes a semiconductor device having a heat dissipation structure with high heat dissipation efficiency.
  • a first semiconductor device includes a semiconductor substrate and a through electrode penetrating the semiconductor substrate, and at least an end surface of the through electrode is exposed on a surface opposite to an element formation surface of the semiconductor substrate.
  • a first recess and a second recess that does not expose the through electrode, and an inner surface of the first recess excluding the end surface of the through electrode and the second substrate are formed on the opposite surface of the semiconductor substrate.
  • a first insulating film is formed so as to cover the inner surface of the second recess, and the first insulating film is connected to the end surface of the through electrode and extends to the outside of the first recess on the first insulating film.
  • a conductive film is formed.
  • the heat-dissipating recess (the first recess) exposing the end face of the through electrode (that is, connecting to the through electrode) on the opposite surface (substrate back surface) of the element formation surface of the semiconductor substrate. ) Is provided. For this reason, heat generated on the element formation surface of the semiconductor substrate and transmitted to the back surface of the substrate via the through electrode can be radiated from the first recess, so that the through electrode is not exposed (that is, connected to the through electrode). No) The heat radiation efficiency can be sufficiently improved even when the three-dimensional integration technique is applied, compared with the conventional structure in which only the heat radiation recess is provided on the back surface of the substrate.
  • the first insulating film is formed on the back surface of the substrate so as to cover the inner surface of the first recess except for the end surface of the through electrode, formation of a conductive film (that is, an extraction wiring) connected to the end surface of the through electrode is formed. It is possible to reliably prevent an electrical short circuit between the through electrode and the semiconductor substrate due to the above.
  • the second recess may be a groove reaching the outside of the semiconductor substrate.
  • the conductive film may have a heat radiating portion for further improving the heat radiation efficiency, separately from the portion serving as the lead wiring of the through electrode.
  • an electrode is formed on the conductive film in a portion located outside the first recess, and the electrode is formed on the first insulating film and the conductive film.
  • the second insulating film may be formed so that at least the upper surface of the electrode is exposed.
  • the thermal conductivity of the first insulating film may be higher than the thermal conductivity of the silicon oxide film. If it does in this way, heat dissipation efficiency can be improved further.
  • the thermal conductivity of the first insulating film may be 1.5 W / (m ⁇ K) or more. If it does in this way, heat dissipation efficiency can be improved further.
  • the first insulating film may be composed of a diamond-like carbon film.
  • the thermal conductivity of the diamond-like carbon film is as high as about 30 W / (m ⁇ K), so that the heat dissipation efficiency can be further improved.
  • the first method for manufacturing a semiconductor device includes a step (a) of preparing a semiconductor substrate embedded so that the through electrode is not exposed on the opposite surface of the element formation surface, and the opposite surface of the semiconductor substrate. Forming a first recess that exposes at least an end surface of the through electrode and a second recess that does not expose the through electrode; and the first recess on the opposite surface of the semiconductor substrate.
  • the first semiconductor device according to the present invention can be obtained according to the first semiconductor device manufacturing method according to the present invention, the same effects as those of the first semiconductor device according to the present invention can be obtained. be able to.
  • the heat radiation recess (first recess) exposing the end face of the through electrode (that is, connecting to the through electrode) does not expose the through electrode (that is, Since it can be formed at the same time as the heat radiation recess (second recess) (not connected to the through electrode), the same effects as those of the first semiconductor device according to the present invention described above can be obtained without complicating the process. Can do.
  • the second recess may be a groove reaching the outside of the semiconductor substrate.
  • the conductive film may have a heat radiating portion for further improving the heat radiation efficiency, separately from the portion serving as the lead wiring of the through electrode.
  • the semiconductor substrate is polished from the opposite surface side between the step (a) and the step (b), and is applied to the opposite surface after the polishing.
  • the method may further include a step of thinning the semiconductor substrate so that the through electrode is not exposed.
  • the first method of manufacturing a semiconductor device after the step (d), after forming an electrode on the conductive film in a portion located outside the first recess, the first A step of forming a second insulating film on the insulating film and the conductive film so that at least an upper surface of the electrode is exposed may be further provided.
  • the thermal conductivity of the first insulating film may be higher than the thermal conductivity of the silicon oxide film. If it does in this way, heat dissipation efficiency can be improved further.
  • the thermal conductivity of the first insulating film may be 1.5 W / (mK) or more. If it does in this way, heat dissipation efficiency can be improved further.
  • the first insulating film may be composed of a diamond-like carbon film.
  • the thermal conductivity of the diamond-like carbon film is as high as about 30 W / (m ⁇ K), so that the heat dissipation efficiency can be further improved.
  • the first surface is provided on the opposite surface of the semiconductor substrate. Two recesses may not be formed.
  • a second semiconductor device includes a semiconductor substrate and a through electrode penetrating the semiconductor substrate, and at least an end surface of the through electrode is exposed on a surface opposite to an element formation surface of the semiconductor substrate. Thus, a diamond-like carbon film is formed.
  • a diamond-like material having a maximum thermal conductivity of about 30 W / (m ⁇ K) on the surface opposite to the element formation surface (substrate back surface) of the semiconductor substrate from which the through electrode is exposed.
  • a carbon film is formed.
  • the heat generated on the element formation surface of the semiconductor substrate and transmitted to the back surface of the substrate via the through electrode can be dissipated very efficiently. Therefore, even when the three-dimensional integration technology is applied, the heat dissipates. Efficiency can be improved sufficiently.
  • the diamond-like carbon film has an insulating property, it is possible to reliably prevent an electrical short circuit between the through electrode and the semiconductor substrate due to the diamond-like carbon film.
  • the through electrode may protrude from the opposite surface of the semiconductor substrate.
  • the diamond-like carbon film is in contact with the side wall of the protruding portion of the through electrode, the heat dissipation efficiency can be further improved.
  • an electrode may be formed on the end face of the through electrode.
  • a recess that exposes at least the end face of the through electrode may be formed on the opposite surface of the semiconductor substrate.
  • the heat dissipation efficiency can be further improved.
  • the diamond-like carbon film covers the inner surface of the recess except the end surface of the through electrode, the heat dissipation efficiency can be further improved.
  • the diamond-like carbon film may be formed apart from the through electrode.
  • the second method for manufacturing a semiconductor device includes a step (a) of preparing a semiconductor substrate formed so that the through electrode is exposed on the opposite surface of the element formation surface, and an element formation surface of the semiconductor substrate. (B) forming a diamond-like carbon film on the opposite surface of the through electrode so that at least the end face of the through electrode is exposed.
  • the second semiconductor device according to the present invention can be obtained according to the second semiconductor device manufacturing method according to the present invention, the same effects as those of the second semiconductor device according to the present invention can be obtained. be able to.
  • the step (a) is performed by polishing and etching the opposite surface of the semiconductor substrate so that the through electrode is disposed on the opposite surface of the semiconductor substrate.
  • the process of protruding from may be included.
  • the diamond-like carbon film is formed so as to be in contact with the side wall of the protruding portion of the through electrode, the heat dissipation efficiency can be further improved.
  • the second method of manufacturing a semiconductor device according to the present invention may further include a step of forming an electrode on the end face of the through electrode after the step (b).
  • the step of the semiconductor substrate is performed.
  • the opposite surface may include a step of forming a recess exposing at least the end surface of the through electrode.
  • the heat dissipation efficiency can be further improved.
  • the step (b) includes the step of forming the diamond-like carbon film so as to cover the inner surface of the concave portion excluding the end face, the heat dissipation efficiency can be further improved.
  • the step (b) may include a step of forming the diamond-like carbon film apart from the through electrode.
  • the present invention while preventing an electrical short circuit between the through electrode and the semiconductor substrate, by providing a heat radiation recess connected to the through electrode on the back surface of the substrate, or on the back surface of the substrate or in the vicinity thereof.
  • a semiconductor device having a heat dissipation structure with high heat dissipation efficiency can be obtained.
  • FIGS. 1A to 1C are cross-sectional views showing respective steps of the semiconductor device manufacturing method according to the first embodiment.
  • 2A to 2C are cross-sectional views showing respective steps of the semiconductor device manufacturing method according to the first embodiment.
  • FIG. 3A is a view of the state where the semiconductor device according to the first embodiment is formed in each chip region of the semiconductor substrate (wafer) from the back side of the substrate, and FIG. It is the figure which looked at a mode that the 1st crevice and the 2nd crevice were formed in one chip field from the substrate back side, and Drawing 3 (c) is a penetration electrode arranged in a chip field, the 1st FIG. 3D is a perspective view of a recess and a second recess, and FIGS.
  • 3D and 3E respectively show a first recess (including a through electrode) and a second before an electrode and a second insulating film are formed. It is an expanded sectional view of a crevice.
  • 4A to 4C are cross-sectional views showing respective steps of a method for manufacturing a semiconductor device according to a modification of the first embodiment.
  • FIGS. 5A to 5C are cross-sectional views showing respective steps of the method for manufacturing the semiconductor device according to the modification of the first embodiment.
  • FIG. 6 is a plan view of the heat dissipation portion of the semiconductor device according to the modification of the first embodiment as viewed from the back side of the substrate.
  • FIG. 7A is a view of a state in which the semiconductor device according to the modification of the first embodiment is formed in each chip region of the semiconductor substrate (wafer) as viewed from the back side of the substrate.
  • FIG. 7C shows the through electrode and the first recess disposed in the chip region.
  • FIG. 7D is an enlarged cross-sectional view of the first recess (including the through electrode) before forming the electrode and the second insulating film.
  • 8A to 8C are cross-sectional views showing respective steps of the method for manufacturing the semiconductor device according to the second embodiment.
  • FIGS. 9A and 9B are cross-sectional views illustrating respective steps of the method for manufacturing the semiconductor device according to the second embodiment.
  • FIGS. 10A and 10B are cross-sectional views of a semiconductor device according to a modification of the second embodiment.
  • FIGS. 1A to 1C and FIGS. 2A to 2C are cross-sectional views showing respective steps of the semiconductor device manufacturing method according to the first embodiment.
  • a semiconductor substrate 1 is prepared in which a through electrode 2 is buried so as not to be exposed on the surface opposite to the element formation surface (back surface 1b).
  • Various functional elements such as the transistor 11 are formed on the element formation surface (front surface 1 a) side of the semiconductor substrate 1.
  • a wiring layer 12 having a multilayer wiring that is electrically connected to the through electrode 2 and the transistor 11 is formed.
  • the through electrode 2 has, for example, a 5 ⁇ m square shape in plan view from the back surface 1 b side of the semiconductor substrate 1.
  • the through electrode 2 is formed so as to reach the inside of the wiring layer 12, and the side wall of the through electrode 2 is covered with an insulating film 13 with a barrier film (not shown) interposed therebetween.
  • the semiconductor substrate 1 is polished from the back surface 1b side using, for example, CMP (chemical mechanical polishing), and the through electrode 2 is not exposed to the back surface 1b after the polishing.
  • CMP chemical mechanical polishing
  • a rectangular shape of, for example, 20 ⁇ m ⁇ is formed in a region including the portion directly above the through electrode 2 and other regions other than the region.
  • a resist pattern (not shown) having the openings
  • dry etching is performed on the semiconductor substrate 1 using the resist pattern as a mask, and then the resist pattern is removed.
  • the first recess 3 that exposes at least the end face (bottom surface) of the through electrode 2 is formed on the back surface 1b of the semiconductor substrate 1, and the second recess 8 that does not expose the through electrode is formed.
  • the first recess 3 has a bottom portion larger than the bottom surface of the through electrode 2.
  • the depth of each of the first recess 3 and the second recess 8 is, for example, about 10 ⁇ m.
  • a CVD (chemical vapor deposition) method is performed on the back surface 1b of the semiconductor substrate 1 so as to cover the inner surfaces of the first concave portion 3 and the second concave portion 8, respectively.
  • the first insulating film 4 made of a silicon oxide film having a thickness of about 500 nm is formed. Thereafter, only the portion of the first insulating film 4 formed on the bottom surface of the through electrode 2 is removed using, for example, a dry etching method.
  • a TiN film (not shown) having a thickness of, for example, about 100 nm is formed as a barrier film on the first insulating film 4 by, for example, sputtering, and then, for example, 20 nm in thickness is formed on the TiN film by, for example, sputtering.
  • a Cu seed film (not shown) is formed.
  • a conductive film 5 made of a Cu film having a thickness of about 1 ⁇ m is formed.
  • the conductive film 5 is connected to the bottom surface of the through electrode 2 and extends to the outside of the first recess 3. Then, after removing the resist pattern, the TiN film and the Cu seed film in a region where the conductive film 5 is not formed are removed by dry etching, for example, using the conductive film 5 as a mask.
  • an electrode 6 made of, for example, a solder bump is formed on a portion of the conductive film 5 located outside the first recess 3.
  • a CVD method is used to form a first silicon oxide film having a thickness of, for example, about 500 nm over the entire surface of the back surface 1b of the semiconductor substrate 1 including the inner surfaces of the first recess 3 and the second recess 8.
  • the second insulating film 7 is patterned so as to completely cover the conductive film 5 and expose at least the upper surface of the electrode 6.
  • the semiconductor device of this embodiment is completed.
  • FIG. 3A is a view (bird's eye view) of a state in which the semiconductor device of the present embodiment is formed in each chip region 50 of the semiconductor substrate (wafer) 1 from the back surface 1b side
  • FIG. 3C is a view (bird's eye view) of a state in which the first concave portion 3 and the second concave portion 8 are formed in one chip region 50 from the back surface 1b side
  • FIG. It is a perspective view (semi-transparent figure) of the penetration electrode 2, the 1st crevice 3, and the 2nd crevice 8 arranged.
  • FIGS. 3D and 3E are enlarged sectional views of the first recess 3 (including the through electrode 2) and the second recess 8 before forming the electrode 6 and the second insulating film 7, respectively. It is.
  • FIG. 3D shows a barrier film (TiN film) 14 not shown in FIGS. 2B and 2C.
  • the back surface 1b of the semiconductor substrate 1 is provided with a heat radiation recess (first recess 3) that exposes the end surface of the through electrode 2 (that is, is connected to the through electrode 2).
  • first recess 3 a heat radiation recess
  • the heat generated on the element formation surface (front surface 1a) of the semiconductor substrate 1 and transmitted to the back surface 1b via the through electrode 2 can be radiated from the first recess 3, so that the through electrode is exposed.
  • the heat radiation efficiency can be sufficiently improved even when the three-dimensional integration technique is applied.
  • the first insulating film 4 is formed on the back surface 1 b of the semiconductor substrate 1 so as to cover the inner surface of the first recess 3 except for the end surface of the through electrode 2, the conductive material connected to the end surface of the through electrode 2. It is possible to reliably prevent an electrical short circuit between the through electrode 2 and the semiconductor substrate 1 due to the formation of the film 5 (that is, the lead wiring).
  • the conductive film 5 has a heat dissipating part for further improving the heat dissipating efficiency on the back surface 1b of the semiconductor substrate 1 outside the first recessed part 3 separately from the part serving as the lead wiring of the through electrode 2. You may do it.
  • the second recess 8 is formed also in the back surface 1b of the semiconductor substrate 1 in the region where the through electrode 2 is not formed, the substantial back surface 1b of the semiconductor substrate 1 is formed. Since the surface area can be greatly increased, the heat radiation efficiency can be further enhanced.
  • the heat radiation recess (first recess 3) that exposes the end face of the through electrode 2 (that is, is connected to the through electrode 2) does not expose the through electrode 2 (that is, the through electrode 2). Since the heat dissipation recess (second recess 8) can be formed at the same time, the above-described effects can be obtained without complicating the process.
  • a silicon oxide film formed by a CVD method is used as the first insulating film 4 formed on the back surface 1b of the semiconductor substrate 1.
  • an insulating material having a higher thermal conductivity than the silicon oxide film specifically, a thermal conductivity of 1.5 W / (m ⁇ K) or more
  • a low stress amorphous silicon nitride film thermal conductivity is about 4 W / (m ⁇ K) at maximum
  • a diamond-like carbon (DLC) film thermal conductivity is about 30 W / (m ⁇ K) at maximum
  • the DLC film is an amorphous carbon film in which both the sp 3 bond of diamond and the sp 2 bond of graphite have a skeleton structure of carbon atoms.
  • a method for forming the DLC film there are a plasma CVD method, a thermal CVD method, a photo CVD method, a sputtering method, and the like, which can be formed at a low temperature of about 200 ° C. (that is, a temperature range suitable for a semiconductor process).
  • the size and shape of the first recess 3 that is connected to the through electrode 2 and the second recess 8 that is not connected to the through electrode 2 are not particularly limited.
  • both the size and shape of the first recess 3 and the second recess 8 may be the same, or at least one of the size and shape of the first recess 3 and the second recess 8 is different. It may be.
  • the second recess 8 may be a groove reaching the outside of the semiconductor substrate 1.
  • the semiconductor device and the manufacturing method thereof include chip-chip stacking (stacking of chip-state semiconductor devices obtained by wafer dicing), chip-wafer stacking (chip-state semiconductor device and pre-dicing semiconductor device).
  • the semiconductor device can be applied to any of the semiconductor devices in which the wafer state semiconductor device is stacked) or the wafer-wafer stack (lamination of the semiconductor devices in the wafer state) and the manufacturing method thereof.
  • FIGS. 5 (a) to 5 (c) are cross-sectional views showing respective steps of a method for manufacturing a semiconductor device according to this modification.
  • a semiconductor substrate 1 is prepared in which a through electrode 2 is buried so as not to be exposed on the surface opposite to the element formation surface (back surface 1b).
  • Various functional elements such as the transistor 11 are formed on the element formation surface (front surface 1 a) side of the semiconductor substrate 1.
  • a wiring layer 12 having a multilayer wiring that is electrically connected to the through electrode 2 and the transistor 11 is formed.
  • the through electrode 2 has, for example, a 5 ⁇ m square shape in plan view from the back surface 1 b side of the semiconductor substrate 1.
  • the through electrode 2 is formed so as to reach the inside of the wiring layer 12, and the side wall of the through electrode 2 is covered with an insulating film 13 with a barrier film (not shown) interposed therebetween.
  • the semiconductor substrate 1 is polished from the back surface 1b side using, for example, CMP, and the thickness of the semiconductor substrate 1 is set so that the through electrode 2 is not exposed to the back surface 1b after the polishing. Thin out.
  • the first recess 3 is formed on the back surface 1 b of the semiconductor substrate 1 to expose at least the end surface (bottom surface) of the through electrode 2.
  • the first recess 3 has a bottom portion larger than the bottom surface of the through electrode 2.
  • the depth of the first recess 3 is, for example, about 10 ⁇ m.
  • a silicon oxide film having a thickness of, for example, about 500 nm is formed on the back surface 1b of the semiconductor substrate 1 by using, for example, a CVD method so as to cover the inner surface of the first recess 3.
  • a first insulating film 4 made of is formed. Thereafter, only the portion of the first insulating film 4 formed on the bottom surface of the through electrode 2 is removed using, for example, a dry etching method.
  • a TiN film (not shown) having a thickness of, for example, about 100 nm is formed as a barrier film on the first insulating film 4 by, for example, sputtering, and then, for example, 20 nm in thickness is formed on the TiN film by, for example, sputtering.
  • a Cu seed film (not shown) is formed.
  • a conductive film 5 made of a Cu film having a thickness of about 1 ⁇ m is formed.
  • the conductive film 5 is connected to the bottom surface of the through electrode 2 and extends to the outside of the first recess 3.
  • the conductive film 5 is provided on the semiconductor substrate 1 outside the first recess 3 separately from the lead-out wiring portion for electrically connecting the electrode 6 (see FIG. 5C) described later and the through electrode 2.
  • On the back surface 1b there is a heat dissipating part 5a for improving the heat dissipating efficiency.
  • FIG. 6 is a plan view of the heat radiating portion 5 a as viewed from the back surface 1 b side of the semiconductor substrate 1. As shown in FIG. 6, the heat radiating portion 5 a has a wider shape than the other portions of the conductive film 5.
  • the TiN film and the Cu seed film in a region where the conductive film 5 is not formed are removed by dry etching, for example, using the conductive film 5 as a mask.
  • an electrode 6 made of, for example, a solder bump is formed on a portion of the conductive film 5 located outside the first recess 3.
  • the second insulating film 7 made of, for example, a silicon oxide film having a thickness of about 500 nm is formed over the entire surface of the back surface 1b of the semiconductor substrate 1 including the inner surface of the first recess 3 by using, for example, the CVD method.
  • the second insulating film 7 is patterned so as to completely cover the conductive film 5 and expose at least the upper surface of the electrode 6.
  • FIG. 7A is a view (bird's eye view) of a state in which the semiconductor device of the present modification is formed in each chip region 50 of the semiconductor substrate (wafer) 1 as viewed from the back surface 1b side.
  • FIG. 7C is a view (bird's eye view) of a state in which the first concave portion 3 is formed in one chip region 50 from the back surface 1b side, and
  • FIG. 7C is a through electrode 2 arranged in the chip region 50.
  • FIG. 3 is a perspective view (semi-transparent view) of the first recess 3.
  • FIG. 7D is an enlarged cross-sectional view of the first recess 3 (including the through electrode 2) before the electrode 6 and the second insulating film 7 are formed.
  • FIG. 7D shows a barrier film (TiN film) 14 that is not shown in FIGS. 5B and 5C.
  • a heat radiation recess (first recess 3) is provided on the back surface 1b of the semiconductor substrate 1 to expose the end face of the through electrode 2 (that is, to be connected to the through electrode 2).
  • first recess 3 the heat generated on the element formation surface (front surface 1a) of the semiconductor substrate 1 and transmitted to the back surface 1b via the through electrode 2 can be radiated from the first recess 3, so that the through electrode is exposed.
  • the heat radiation efficiency can be sufficiently improved even when the three-dimensional integration technique is applied.
  • the first insulating film 4 is formed on the back surface 1 b of the semiconductor substrate 1 so as to cover the inner surface of the first recess 3 except for the end surface of the through electrode 2, the conductive material connected to the end surface of the through electrode 2. It is possible to reliably prevent an electrical short circuit between the through electrode 2 and the semiconductor substrate 1 due to the formation of the film 5 (that is, the lead wiring).
  • the conductive film (Cu film in this embodiment) 5 connected to the through electrode 2 in which heat from the heat source (element formation surface (surface 1a) of the semiconductor substrate 1) is accumulated is the first. Since the surface area of the conductive film 5 having a high thermal conductivity is increased, the heat radiation efficiency can be further increased.
  • the heat radiating portion 5 a apart from the portion where the conductive film 5 becomes the lead wiring of the through electrode 2, the heat radiating portion 5 a (see FIG. 6) is formed on the back surface 1 b of the semiconductor substrate 1 outside the first recess 3. Therefore, the heat dissipation efficiency can be further improved.
  • a silicon oxide film formed by a CVD method is used as the first insulating film 4 formed on the back surface 1b of the semiconductor substrate 1.
  • an insulating material having a higher thermal conductivity than the silicon oxide film specifically, a thermal conductivity of 1.5 W / (m ⁇ K) or more
  • a low stress amorphous silicon nitride film thermal conductivity is about 4 W / (m ⁇ K) at maximum
  • a diamond-like carbon (DLC) film thermal conductivity is about 30 W / (m ⁇ K) at maximum
  • the DLC film is an amorphous carbon film in which both the sp 3 bond of diamond and the sp 2 bond of graphite have a skeleton structure of carbon atoms.
  • a method for forming the DLC film there are a plasma CVD method, a thermal CVD method, a photo CVD method, a sputtering method, and the like, which can be formed at a low temperature of about 200 ° C. (that is, a temperature range suitable for a semiconductor process).
  • the semiconductor device and the manufacturing method thereof according to this modification include chip-chip stacking (stacking of chip-state semiconductor devices obtained by wafer dicing), chip-wafer stacking (chip-state semiconductor device and pre-dicing semiconductor device).
  • the semiconductor device can be applied to any of the semiconductor devices in which the wafer state semiconductor device is stacked) or the wafer-wafer stack (lamination of the semiconductor devices in the wafer state) and the manufacturing method thereof.
  • FIGS. 8A to 8C and FIGS. 9A and 9B are cross-sectional views showing respective steps of the semiconductor device manufacturing method according to the second embodiment.
  • a semiconductor substrate 1 is prepared in which the through electrode 2 is buried so as not to be exposed on the opposite surface (back surface 1b) of the element formation surface.
  • Various functional elements such as the transistor 11 are formed on the element formation surface (front surface 1 a) side of the semiconductor substrate 1.
  • a wiring layer 12 having a multilayer wiring that is electrically connected to the through electrode 2 and the transistor 11 is formed on the surface 1 a of the semiconductor substrate 1.
  • the through electrode 2 has, for example, a 5 ⁇ m square shape in plan view from the back surface 1 b side of the semiconductor substrate 1.
  • the through electrode 2 is formed so as to reach the inside of the wiring layer 12, and the side wall of the through electrode 2 is covered with an insulating film 13 with a barrier film (not shown) interposed therebetween.
  • the thickness of the semiconductor substrate 1 is such that the semiconductor substrate 1 is polished from the back surface 1b side using, for example, CMP, and the through electrode 2 is exposed on the back surface 1b after the polishing. Thin out. Thereafter, by etching the back surface 1b of the semiconductor substrate 1, the end portion (bottom portion) of the through electrode 2 is raised from the back surface 1b after the etching, for example, by about 400 nm. At this time, the insulating film 13 covering the side wall of the protruding portion of the through electrode 2 may be removed.
  • a diamond-like carbon film having a thickness of, for example, about 200 nm is formed as an insulating film having high thermal conductivity on the back surface 1b of the semiconductor substrate 1 where the bottom of the through electrode 2 is exposed. 9 is formed.
  • a resist 10 having a thickness of, for example, about 500 nm is formed on the diamond-like carbon film 9.
  • the diamond-like carbon film 9 on the bottom surface of the through electrode 2 is selectively removed as shown in FIG. 9B.
  • the bottom surface of the through electrode 2 is exposed, and the diamond-like carbon is formed on the side wall of the through electrode 2 protruding from the back surface 1 b of the semiconductor substrate 1 and on the back surface 1 b of the semiconductor substrate 1 including the periphery of the through electrode 2.
  • the film 9 can remain.
  • an electrode 6 made of, for example, a solder bump is formed on the exposed bottom surface of the through electrode 2.
  • the semiconductor device of this embodiment is completed.
  • the diamond-like carbon film 9 having a maximum thermal conductivity of about 30 W / (m ⁇ K) is formed on the back surface 1b of the semiconductor substrate 1 where the through electrode 2 is exposed. For this reason, the heat generated on the element formation surface (front surface 1a) of the semiconductor substrate 1 and transmitted to the back surface 1b via the through electrode 2 can be dissipated very efficiently. Even when applied, the heat dissipation efficiency can be sufficiently improved. Further, since the diamond-like carbon film 9 has an insulating property, it is possible to reliably prevent an electrical short circuit between the through electrode 2 and the semiconductor substrate 1 due to the diamond-like carbon film 9.
  • the bottom of the through electrode 2 protrudes from the back surface 1b of the semiconductor substrate 1, and the diamond-like carbon film 9 is in contact with the side wall of the protruding portion. Can be improved.
  • the electrode 6 may not be formed if the height of the protruding portion of the through electrode 2 from the back surface 1b of the semiconductor substrate 1 is sufficient. Further, the bottom portion of the through electrode 2 may not protrude from the back surface 1 b of the semiconductor substrate 1.
  • the diamond-like carbon film 9 and the through electrode 2 may be separated from each other.
  • a first recess 3 that exposes at least an end surface (bottom surface) of the through electrode 2 may be provided on the back surface 1 b of the semiconductor substrate 1. In this way, since the substantial surface area of the back surface 1b of the semiconductor substrate 1 can be increased, the heat dissipation efficiency can be further improved.
  • the semiconductor device and the manufacturing method thereof include chip-chip stacking (stacking of chip-state semiconductor devices obtained by wafer dicing), chip-wafer stacking (chip-state semiconductor device and pre-dicing semiconductor device).
  • the semiconductor device can be applied to any of the semiconductor devices in which the wafer state semiconductor device is stacked) or the wafer-wafer stack (lamination of the semiconductor devices in the wafer state) and the manufacturing method thereof.
  • the semiconductor device and the manufacturing method thereof according to the present invention are provided by providing a heat radiation recess connected to the through electrode on the back surface of the substrate while preventing an electrical short circuit between the through electrode and the semiconductor substrate.
  • a heat radiation recess connected to the through electrode on the back surface of the substrate while preventing an electrical short circuit between the through electrode and the semiconductor substrate.
  • an insulating high heat dissipation material film that reaches the through electrode or the vicinity thereof on the back surface of the substrate, a heat dissipation structure with high heat dissipation efficiency is realized.
  • chip-chip stacking, chip-wafer stacking or This is useful in a wafer-wafer stacked semiconductor device, a manufacturing method thereof, and the like.

Abstract

The opposite surface (1b) of a semiconductor substrate (1), which is on the reverse side of an element formation surface (1a) of the semiconductor substrate (1), is provided with a first recess (3), from which at least an end face of a through electrode (2) is exposed, and a second recess (8), from which the through electrode (2) is not exposed. The opposite surface (1b) of the semiconductor substrate (1) is provided with a first insulating film (4) such that the inner surface of the first recess (3) other than the end face of the through electrode (2) and the inner surface of the second recess (8) are covered by the first insulating film (4). A conductive film (5) is formed on the first insulating film (4) so as to extend to the outside of the first recess (3), while being connected to the end face of the through electrode (2).

Description

半導体装置及びその製造方法Semiconductor device and manufacturing method thereof
　本発明は、半導体装置及びその製造方法に関し、特に、チップ－チップ積層、チップ－ウェーハ積層又はウェーハ－ウェーハ積層された半導体装置及びその製造方法に関する。 The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a chip-chip stacking, a chip-wafer stacking or a wafer-wafer stacking semiconductor device and a manufacturing method thereof.
　近年、半導体集積回路装置の高集積化、高機能化及び高速化に伴って、貫通ビア（貫通電極）を用いた半導体基板のチップ－チップ積層、チップ－ウェーハ積層又はウェーハ－ウェーハ積層による３次元集積化技術が提案されている。 In recent years, as semiconductor integrated circuit devices become highly integrated, highly functional, and speeded up, three-dimensional semiconductor chip-chip stacking, chip-wafer stacking, or wafer-wafer stacking using through vias (through electrodes) Integration techniques have been proposed.
　このような３次元集積化技術が注目される中において、例えば、ロジックＬＳＩチップと他のチップとを積層した場合、半導体基板における他の基板が貼り合わされる面上に形成された絶縁膜の熱伝導性が低く放熱効率が悪いことに起因して、ロジックＬＳＩチップに集積されたトランジスタの動作によって発生した熱がロジックＬＳＩチップの発熱箇所近傍に蓄積されて温度上昇が引き起こされ、動作不良や信頼性不良等が発生するという問題があった。具体的には、通常、絶縁膜として多用されているＴＥＯＳ（tetraethylorthosilicate ）膜の熱伝導率は１．２Ｗ／（ｍ・Ｋ）程度と低いため、半導体基板の放熱を妨げる要因となっている。 While such a three-dimensional integration technique is attracting attention, for example, when a logic LSI chip and another chip are stacked, the heat of the insulating film formed on the surface of the semiconductor substrate to which the other substrate is bonded. Due to the low conductivity and poor heat dissipation efficiency, heat generated by the operation of the transistors integrated in the logic LSI chip is accumulated near the heat generation point of the logic LSI chip, causing a temperature rise, resulting in malfunction and reliability. There has been a problem that inferiority or the like occurs. Specifically, the thermal conductivity of a TEOS (tetraethylorthosilicate) film, which is normally used as an insulating film, is as low as about 1.2 W / (m · K), which is a factor that hinders heat dissipation of the semiconductor substrate.
　この問題を解決する対策として、薄膜状のＬＳＩチップを３次元的に貼り合わせて集積してなる３次元半導体チップにおいて、各ＬＳＩチップにおける他のチップが貼り合わされる面に３次元半導体チップの外側に通じるように溝を設け、当該溝に放熱用材料を埋め込む方法が提案されている（例えば特許文献１参照）。 As a countermeasure to solve this problem, in a three-dimensional semiconductor chip obtained by three-dimensionally bonding thin-film LSI chips and integrating them, the outer surface of the three-dimensional semiconductor chip is placed on the surface of each LSI chip to which other chips are bonded. There has been proposed a method in which a groove is provided so as to lead to and a material for heat dissipation is embedded in the groove (see, for example, Patent Document 1).
特開２００２－３３４９６８号公報JP 2002-334968 A
　しかしながら、前述の従来技術においては、十分な放熱効果が得られず、動作不良や信頼性不良等の発生を抑制できない場合がある。 However, in the above-described conventional technology, a sufficient heat dissipation effect cannot be obtained, and the occurrence of malfunctions or reliability failures may not be suppressed.
　前記に鑑み、本発明は、３次元集積化技術を適用した場合にも十分な放熱効果が得られる、放熱効率の高い放熱構造を持つ半導体装置及びその製造方法を提供することを目的とする。 In view of the above, an object of the present invention is to provide a semiconductor device having a heat dissipation structure with high heat dissipation efficiency and a method for manufacturing the same, which can obtain a sufficient heat dissipation effect even when a three-dimensional integration technique is applied.
　前記の目的を達成するために、本願発明者は、特許文献１に開示された３次元半導体チップ構成、つまり、各ＬＳＩチップにおける他のチップが貼り合わされる面に３次元半導体チップの外側に通じるように形成された放熱用溝に放熱用材料が埋め込まれている構成について、種々の検討を行った結果、次のような知見を得た。 In order to achieve the above-mentioned object, the inventor of the present application leads to the outside of the three-dimensional semiconductor chip in the three-dimensional semiconductor chip configuration disclosed in Patent Document 1, that is, the surface of each LSI chip to which other chips are bonded. As a result of various studies on the structure in which the heat dissipation material is embedded in the heat dissipation groove formed as described above, the following knowledge was obtained.
　すなわち、ＬＳＩチップの発熱部（基板の素子形成面上に形成された素子群等）で発生した熱のうちのかなりの部分は、基板を貫通する貫通電極の導体部分を伝わって基板裏面（素子形成面の反対面（他のチップが貼り合わされる面））に到達する一方、特許文献１に開示された３次元半導体チップにおいては基板裏面に放熱用溝が貫通電極から離間して形成されているため、放熱効果が低下していることが判明した。 That is, a considerable part of the heat generated in the heat generating part (element group formed on the element formation surface of the substrate) of the LSI chip is transmitted through the conductor portion of the through electrode penetrating the substrate and the back surface of the substrate (element On the other hand, in the three-dimensional semiconductor chip disclosed in Patent Document 1, a heat radiating groove is formed away from the through electrode on the back surface of the substrate. Therefore, it was found that the heat dissipation effect was reduced.
　そこで、本願発明者は、以上の知見に基づいて、貫通電極と半導体基板との電気的な短絡を防止しつつ、基板裏面に貫通電極と連結する放熱用凹部を設けることにより、又は、基板裏面上に貫通電極若しくはその近傍に達する絶縁性高放熱材料膜（具体的にはダイヤモンドライクカーボン膜）を設けることにより、放熱効率の高い放熱構造を持つ半導体装置を実現するという発明に想到した。 Therefore, based on the above knowledge, the inventor of the present application prevents the electrical short circuit between the through electrode and the semiconductor substrate, and provides a heat dissipation recess connected to the through electrode on the back surface of the substrate, or the back surface of the substrate. By providing an insulating high heat dissipation material film (specifically, a diamond-like carbon film) that reaches the through electrode or the vicinity thereof, the inventors have come up with an invention that realizes a semiconductor device having a heat dissipation structure with high heat dissipation efficiency.
　本発明に係る第１の半導体装置は、半導体基板と、前記半導体基板を貫通する貫通電極とを備え、前記半導体基板の素子形成面の反対面には、前記貫通電極の少なくとも端面を露出させる第１の凹部と、前記貫通電極を露出させない第２の凹部とが形成されており、前記半導体基板の前記反対面上には、前記第１の凹部における前記貫通電極の前記端面を除く内面及び前記第２の凹部の内面を覆うように第１の絶縁膜が形成されており、前記第１の絶縁膜上には、前記貫通電極の前記端面と接続し且つ前記第１の凹部の外側まで延びる導電膜が形成されている。 A first semiconductor device according to the present invention includes a semiconductor substrate and a through electrode penetrating the semiconductor substrate, and at least an end surface of the through electrode is exposed on a surface opposite to an element formation surface of the semiconductor substrate. A first recess and a second recess that does not expose the through electrode, and an inner surface of the first recess excluding the end surface of the through electrode and the second substrate are formed on the opposite surface of the semiconductor substrate. A first insulating film is formed so as to cover the inner surface of the second recess, and the first insulating film is connected to the end surface of the through electrode and extends to the outside of the first recess on the first insulating film. A conductive film is formed.
　本発明に係る第１の半導体装置によると、半導体基板の素子形成面の反対面（基板裏面）に、貫通電極の端面を露出させる（つまり貫通電極と連結する）放熱用凹部（第１の凹部）が設けられている。このため、半導体基板の素子形成面で発生し且つ貫通電極を経由して基板裏面まで伝わってきた熱を第１の凹部から放熱することができるので、貫通電極を露出させない（つまり貫通電極と連結しない）放熱用凹部しか基板裏面に設けられていない従来構造と比較して、３次元集積化技術を適用した場合にも放熱効率を十分に向上させることができる。また、第１の凹部における貫通電極の端面を除く内面を覆うように基板裏面上に第１の絶縁膜が形成されているため、貫通電極の端面と接続する導電膜（つまり引き出し配線）の形成に起因する貫通電極と半導体基板との電気的な短絡を確実に防止することができる。 According to the first semiconductor device of the present invention, the heat-dissipating recess (the first recess) exposing the end face of the through electrode (that is, connecting to the through electrode) on the opposite surface (substrate back surface) of the element formation surface of the semiconductor substrate. ) Is provided. For this reason, heat generated on the element formation surface of the semiconductor substrate and transmitted to the back surface of the substrate via the through electrode can be radiated from the first recess, so that the through electrode is not exposed (that is, connected to the through electrode). No) The heat radiation efficiency can be sufficiently improved even when the three-dimensional integration technique is applied, compared with the conventional structure in which only the heat radiation recess is provided on the back surface of the substrate. In addition, since the first insulating film is formed on the back surface of the substrate so as to cover the inner surface of the first recess except for the end surface of the through electrode, formation of a conductive film (that is, an extraction wiring) connected to the end surface of the through electrode is formed. It is possible to reliably prevent an electrical short circuit between the through electrode and the semiconductor substrate due to the above.
　尚、前記第２の凹部は、前記半導体基板の外側に達する溝であってもよい。また、前記導電膜は、前記貫通電極の引き出し配線となる部分とは別に、放熱効率をさらに向上させるための放熱部を有していてもよい。 The second recess may be a groove reaching the outside of the semiconductor substrate. In addition, the conductive film may have a heat radiating portion for further improving the heat radiation efficiency, separately from the portion serving as the lead wiring of the through electrode.
　本発明に係る第１の半導体装置において、前記第１の凹部の外側に位置する部分の前記導電膜上に電極が形成されており、前記第１の絶縁膜上及び前記導電膜上に、前記電極の少なくとも上面が露出するように第２の絶縁膜が形成されていてもよい。 In the first semiconductor device according to the present invention, an electrode is formed on the conductive film in a portion located outside the first recess, and the electrode is formed on the first insulating film and the conductive film. The second insulating film may be formed so that at least the upper surface of the electrode is exposed.
　本発明に係る第１の半導体装置において、前記第１の絶縁膜の熱伝導率は、シリコン酸化膜の熱導電率よりも高くてもよい。このようにすると、放熱効率をより一層向上させることができる。 In the first semiconductor device according to the present invention, the thermal conductivity of the first insulating film may be higher than the thermal conductivity of the silicon oxide film. If it does in this way, heat dissipation efficiency can be improved further.
　本発明に係る第１の半導体装置において、前記第１の絶縁膜の熱伝導率は、１．５Ｗ／（ｍ・Ｋ）以上であってもよい。このようにすると、放熱効率をより一層向上させることができる。 In the first semiconductor device according to the present invention, the thermal conductivity of the first insulating film may be 1.5 W / (m · K) or more. If it does in this way, heat dissipation efficiency can be improved further.
　本発明に係る第１の半導体装置において、前記第１の絶縁膜はダイヤモンドライクカーボン膜から構成されていてもよい。このようにすると、ダイヤモンドライクカーボン膜の熱伝導率は、最大３０Ｗ／（ｍ・Ｋ）程度にもなるので、放熱効率をより一層向上させることができる。 In the first semiconductor device according to the present invention, the first insulating film may be composed of a diamond-like carbon film. In this case, the thermal conductivity of the diamond-like carbon film is as high as about 30 W / (m · K), so that the heat dissipation efficiency can be further improved.
　尚、第１の凹部のみによって十分な放熱効率が得られる場合には、本発明に係る第１の半導体装置において、前記半導体基板の前記反対面に前記第２の凹部が形成されていなくてもよい。 When sufficient heat radiation efficiency can be obtained only by the first recess, in the first semiconductor device according to the present invention, even if the second recess is not formed on the opposite surface of the semiconductor substrate. Good.
　本発明に係る第１の半導体装置の製造方法は、貫通電極が素子形成面の反対面に露出しないように埋設されている半導体基板を準備する工程（ａ）と、前記半導体基板の前記反対面に、前記貫通電極の少なくとも端面を露出させる第１の凹部と、前記貫通電極を露出させない第２の凹部とを形成する工程（ｂ）と、前記半導体基板の前記反対面上に、前記第１の凹部における前記貫通電極の前記端面を除く内面及び前記第２の凹部の内面を覆うように第１の絶縁膜を形成する工程（ｃ）と、前記第１の絶縁膜上に、前記貫通電極の前記端面と接続し且つ前記第１の凹部の外側まで延びる導電膜を形成する工程（ｄ）とを備えている。 The first method for manufacturing a semiconductor device according to the present invention includes a step (a) of preparing a semiconductor substrate embedded so that the through electrode is not exposed on the opposite surface of the element formation surface, and the opposite surface of the semiconductor substrate. Forming a first recess that exposes at least an end surface of the through electrode and a second recess that does not expose the through electrode; and the first recess on the opposite surface of the semiconductor substrate. A step (c) of forming a first insulating film so as to cover an inner surface excluding the end face of the through electrode and an inner surface of the second concave portion in the recess, and the through electrode on the first insulating film A step (d) of forming a conductive film connected to the end face and extending to the outside of the first recess.
　本発明に係る第１の半導体装置の製造方法によると、前述の本発明に係る第１の半導体装置を得ることができるので、前述の本発明に係る第１の半導体装置と同様の効果を得ることができる。 Since the first semiconductor device according to the present invention can be obtained according to the first semiconductor device manufacturing method according to the present invention, the same effects as those of the first semiconductor device according to the present invention can be obtained. be able to.
　また、本発明に係る第１の半導体装置の製造方法によると、貫通電極の端面を露出させる（つまり貫通電極と連結する）放熱用凹部（第１の凹部）を、貫通電極を露出させない（つまり貫通電極と連結しない）放熱用凹部（第２の凹部）と同時に形成することができるので、工程を複雑化することなく、前述の本発明に係る第１の半導体装置と同様の効果を得ることができる。 Further, according to the first method for manufacturing a semiconductor device of the present invention, the heat radiation recess (first recess) exposing the end face of the through electrode (that is, connecting to the through electrode) does not expose the through electrode (that is, Since it can be formed at the same time as the heat radiation recess (second recess) (not connected to the through electrode), the same effects as those of the first semiconductor device according to the present invention described above can be obtained without complicating the process. Can do.
　尚、前記第２の凹部は、前記半導体基板の外側に達する溝であってもよい。また、前記導電膜は、前記貫通電極の引き出し配線となる部分とは別に、放熱効率をさらに向上させるための放熱部を有していてもよい。 The second recess may be a groove reaching the outside of the semiconductor substrate. In addition, the conductive film may have a heat radiating portion for further improving the heat radiation efficiency, separately from the portion serving as the lead wiring of the through electrode.
　本発明に係る第１の半導体装置の製造方法において、前記工程（ａ）と前記工程（ｂ）との間に、前記半導体基板を前記反対面側から研磨し、当該研磨後の前記反対面に前記貫通電極が露出しないように前記半導体基板を薄くする工程をさらに備えていてもよい。 In the first method for manufacturing a semiconductor device according to the present invention, the semiconductor substrate is polished from the opposite surface side between the step (a) and the step (b), and is applied to the opposite surface after the polishing. The method may further include a step of thinning the semiconductor substrate so that the through electrode is not exposed.
　本発明に係る第１の半導体装置の製造方法において、前記工程（ｄ）よりも後に、前記第１の凹部の外側に位置する部分の前記導電膜上に電極を形成した後、前記第１の絶縁膜上及び前記導電膜上に、前記電極の少なくとも上面が露出するように第２の絶縁膜を形成する工程をさらに備えていてもよい。 In the first method of manufacturing a semiconductor device according to the present invention, after the step (d), after forming an electrode on the conductive film in a portion located outside the first recess, the first A step of forming a second insulating film on the insulating film and the conductive film so that at least an upper surface of the electrode is exposed may be further provided.
　本発明に係る第１の半導体装置の製造方法において、前記第１の絶縁膜の熱伝導率は、シリコン酸化膜の熱導電率よりも高くてもよい。このようにすると、放熱効率をより一層向上させることができる。 In the first method for manufacturing a semiconductor device according to the present invention, the thermal conductivity of the first insulating film may be higher than the thermal conductivity of the silicon oxide film. If it does in this way, heat dissipation efficiency can be improved further.
　本発明に係る第１の半導体装置の製造方法において、前記第１の絶縁膜の熱伝導率は、１．５Ｗ／（ｍＫ）以上であってもよい。このようにすると、放熱効率をより一層向上させることができる。 In the first method for manufacturing a semiconductor device according to the present invention, the thermal conductivity of the first insulating film may be 1.5 W / (mK) or more. If it does in this way, heat dissipation efficiency can be improved further.
　本発明に係る第１の半導体装置の製造方法において、前記第１の絶縁膜はダイヤモンドライクカーボン膜から構成されていてもよい。このようにすると、ダイヤモンドライクカーボン膜の熱伝導率は、最大３０Ｗ／（ｍ・Ｋ）程度にもなるので、放熱効率をより一層向上させることができる。 In the first method for manufacturing a semiconductor device according to the present invention, the first insulating film may be composed of a diamond-like carbon film. In this case, the thermal conductivity of the diamond-like carbon film is as high as about 30 W / (m · K), so that the heat dissipation efficiency can be further improved.
　尚、第１の凹部のみによって十分な放熱効率が得られる場合には、本発明に係る第１の半導体装置の製造方法において、前記工程（ｂ）で、前記半導体基板の前記反対面に前記第２の凹部を形成しなくてもよい。 When sufficient heat radiation efficiency can be obtained only by the first recess, in the first method for manufacturing a semiconductor device according to the present invention, in the step (b), the first surface is provided on the opposite surface of the semiconductor substrate. Two recesses may not be formed.
　本発明に係る第２の半導体装置は、半導体基板と、前記半導体基板を貫通する貫通電極とを備え、前記半導体基板の素子形成面の反対面上には、前記貫通電極の少なくとも端面が露出するようにダイヤモンドライクカーボン膜が形成されている。 A second semiconductor device according to the present invention includes a semiconductor substrate and a through electrode penetrating the semiconductor substrate, and at least an end surface of the through electrode is exposed on a surface opposite to an element formation surface of the semiconductor substrate. Thus, a diamond-like carbon film is formed.
　本発明に係る第２の半導体装置によると、貫通電極が露出する半導体基板の素子形成面の反対面（基板裏面）上に、熱伝導率が最大３０Ｗ／（ｍ・Ｋ）程度になるダイヤモンドライクカーボン膜が形成されている。このため、半導体基板の素子形成面で発生し且つ貫通電極を経由して基板裏面まで伝わってきた熱を極めて効率的に放熱することができるので、３次元集積化技術を適用した場合にも放熱効率を十分に向上させることができる。また、ダイヤモンドライクカーボン膜は絶縁性を有しているので、ダイヤモンドライクカーボン膜に起因する貫通電極と半導体基板との電気的な短絡を確実に防止できる。 According to the second semiconductor device of the present invention, a diamond-like material having a maximum thermal conductivity of about 30 W / (m · K) on the surface opposite to the element formation surface (substrate back surface) of the semiconductor substrate from which the through electrode is exposed. A carbon film is formed. For this reason, the heat generated on the element formation surface of the semiconductor substrate and transmitted to the back surface of the substrate via the through electrode can be dissipated very efficiently. Therefore, even when the three-dimensional integration technology is applied, the heat dissipates. Efficiency can be improved sufficiently. In addition, since the diamond-like carbon film has an insulating property, it is possible to reliably prevent an electrical short circuit between the through electrode and the semiconductor substrate due to the diamond-like carbon film.
　本発明に係る第２の半導体装置において、前記貫通電極は、前記半導体基板の前記反対面から突き出ていてもよい。この場合、ダイヤモンドライクカーボン膜は、貫通電極の突き出し部分の側壁に接していると、放熱効率をより一層向上させることができる。 In the second semiconductor device according to the present invention, the through electrode may protrude from the opposite surface of the semiconductor substrate. In this case, if the diamond-like carbon film is in contact with the side wall of the protruding portion of the through electrode, the heat dissipation efficiency can be further improved.
　本発明に係る第２の半導体装置において、前記貫通電極の前記端面上に電極が形成されていてもよい。 In the second semiconductor device according to the present invention, an electrode may be formed on the end face of the through electrode.
　本発明に係る第２の半導体装置において、前記半導体基板の前記反対面には、前記貫通電極の少なくとも前記端面を露出させる凹部が形成されていてもよい。このようにすると、基板裏面の実質的な表面積を増大させることができるので、放熱効率をより一層向上させることができる。この場合、前記ダイヤモンドライクカーボン膜が、前記凹部における前記貫通電極の前記端面を除く内面を覆っていると、放熱効率をさらに向上させることができる。 In the second semiconductor device according to the present invention, a recess that exposes at least the end face of the through electrode may be formed on the opposite surface of the semiconductor substrate. In this way, since the substantial surface area of the back surface of the substrate can be increased, the heat dissipation efficiency can be further improved. In this case, if the diamond-like carbon film covers the inner surface of the recess except the end surface of the through electrode, the heat dissipation efficiency can be further improved.
　本発明に係る第２の半導体装置において、前記ダイヤモンドライクカーボン膜は、前記貫通電極から離間して形成されていてもよい。 In the second semiconductor device according to the present invention, the diamond-like carbon film may be formed apart from the through electrode.
　本発明に係る第２の半導体装置の製造方法は、貫通電極が素子形成面の反対面に露出するように形成されている半導体基板を準備する工程（ａ）と、前記半導体基板の素子形成面の反対面上に、前記貫通電極の少なくとも端面が露出するようにダイヤモンドライクカーボン膜を形成する工程（ｂ）とを備えている。 The second method for manufacturing a semiconductor device according to the present invention includes a step (a) of preparing a semiconductor substrate formed so that the through electrode is exposed on the opposite surface of the element formation surface, and an element formation surface of the semiconductor substrate. (B) forming a diamond-like carbon film on the opposite surface of the through electrode so that at least the end face of the through electrode is exposed.
　本発明に係る第２の半導体装置の製造方法によると、前述の本発明に係る第２の半導体装置を得ることができるので、前述の本発明に係る第２の半導体装置と同様の効果を得ることができる。 Since the second semiconductor device according to the present invention can be obtained according to the second semiconductor device manufacturing method according to the present invention, the same effects as those of the second semiconductor device according to the present invention can be obtained. be able to.
　本発明に係る第２の半導体装置の製造方法において、前記工程（ａ）は、前記半導体基板の前記反対面に対して研磨及びエッチングを行うことにより、前記貫通電極を前記半導体基板の前記反対面から突き出させる工程を含んでいてもよい。この場合、ダイヤモンドライクカーボン膜を、貫通電極の突き出し部分の側壁に接するように形成すると、放熱効率をより一層向上させることができる。 In the second method of manufacturing a semiconductor device according to the present invention, the step (a) is performed by polishing and etching the opposite surface of the semiconductor substrate so that the through electrode is disposed on the opposite surface of the semiconductor substrate. The process of protruding from may be included. In this case, if the diamond-like carbon film is formed so as to be in contact with the side wall of the protruding portion of the through electrode, the heat dissipation efficiency can be further improved.
　本発明に係る第２の半導体装置の製造方法において、前記工程（ｂ）よりも後に、前記貫通電極の前記端面上に電極を形成する工程をさらに備えていてもよい。 The second method of manufacturing a semiconductor device according to the present invention may further include a step of forming an electrode on the end face of the through electrode after the step (b).
　本発明に係る第２の半導体装置の製造方法において、前記工程（ａ）は、前記貫通電極が前記反対面に露出しないように埋設されている前記半導体基板を準備した後、前記半導体基板の前記反対面に、前記貫通電極の少なくとも前記端面を露出させる凹部を形成する工程を含んでいてもよい。このようにすると、基板裏面の実質的な表面積を増大させることができるので、放熱効率をより一層向上させることができる。この場合、前記工程（ｂ）が、前記ダイヤモンドライクカーボン膜を、前記凹部における前記貫通電極の前記端面を除く内面を覆うように形成する工程を含むと、放熱効率をさらに向上させることができる。 In the second method of manufacturing a semiconductor device according to the present invention, in the step (a), after preparing the semiconductor substrate embedded so that the through electrode is not exposed on the opposite surface, the step of the semiconductor substrate is performed. The opposite surface may include a step of forming a recess exposing at least the end surface of the through electrode. In this way, since the substantial surface area of the back surface of the substrate can be increased, the heat dissipation efficiency can be further improved. In this case, when the step (b) includes the step of forming the diamond-like carbon film so as to cover the inner surface of the concave portion excluding the end face, the heat dissipation efficiency can be further improved.
　本発明に係る第２の半導体装置の製造方法において、前記工程（ｂ）は、前記ダイヤモンドライクカーボン膜を、前記貫通電極から離間して形成する工程を含んでいてもよい。 In the second method for manufacturing a semiconductor device according to the present invention, the step (b) may include a step of forming the diamond-like carbon film apart from the through electrode.
　本発明によれば、貫通電極と半導体基板との電気的な短絡を防止しつつ、基板裏面に貫通電極と連結する放熱用凹部を設けることにより、又は、基板裏面上に貫通電極若しくはその近傍に達する絶縁性高放熱材料膜を設けることにより、放熱効率の高い放熱構造を持つ半導体装置を得ることができる。 According to the present invention, while preventing an electrical short circuit between the through electrode and the semiconductor substrate, by providing a heat radiation recess connected to the through electrode on the back surface of the substrate, or on the back surface of the substrate or in the vicinity thereof. By providing the insulating high heat dissipation material film that reaches, a semiconductor device having a heat dissipation structure with high heat dissipation efficiency can be obtained.
図１（ａ）～（ｃ）は、第１の実施形態に係る半導体装置の製造方法の各工程を示す断面図である。FIGS. 1A to 1C are cross-sectional views showing respective steps of the semiconductor device manufacturing method according to the first embodiment. 図２（ａ）～（ｃ）は、第１の実施形態に係る半導体装置の製造方法の各工程を示す断面図である。2A to 2C are cross-sectional views showing respective steps of the semiconductor device manufacturing method according to the first embodiment. 図３（ａ）は、半導体基板（ウェーハ）の各チップ領域に第１の実施形態に係る半導体装置が形成されている様子を基板裏面側から見た図であり、図３（ｂ）は、１つのチップ領域に第１の凹部及び第２の凹部が形成されている様子を基板裏面側から見た図であり、図３（ｃ）は、チップ領域に配置された貫通電極、第１の凹部及び第２の凹部の斜視図であり、図３（ｄ）及び（ｅ）はそれぞれ、電極及び第２の絶縁膜を形成する前の第１の凹部（貫通電極を含む）及び第２の凹部の拡大断面図である。FIG. 3A is a view of the state where the semiconductor device according to the first embodiment is formed in each chip region of the semiconductor substrate (wafer) from the back side of the substrate, and FIG. It is the figure which looked at a mode that the 1st crevice and the 2nd crevice were formed in one chip field from the substrate back side, and Drawing 3 (c) is a penetration electrode arranged in a chip field, the 1st FIG. 3D is a perspective view of a recess and a second recess, and FIGS. 3D and 3E respectively show a first recess (including a through electrode) and a second before an electrode and a second insulating film are formed. It is an expanded sectional view of a crevice. 図４（ａ）～（ｃ）は、第１の実施形態の変形例に係る半導体装置の製造方法の各工程を示す断面図である。4A to 4C are cross-sectional views showing respective steps of a method for manufacturing a semiconductor device according to a modification of the first embodiment. 図５（ａ）～（ｃ）は、第１の実施形態の変形例に係る半導体装置の製造方法の各工程を示す断面図である。FIGS. 5A to 5C are cross-sectional views showing respective steps of the method for manufacturing the semiconductor device according to the modification of the first embodiment. 図６は、第１の実施形態の変形例に係る半導体装置の放熱部を基板裏面側から見た平面図である。FIG. 6 is a plan view of the heat dissipation portion of the semiconductor device according to the modification of the first embodiment as viewed from the back side of the substrate. 図７（ａ）は、半導体基板（ウェーハ）の各チップ領域に第１の実施形態の変形例に係る半導体装置が形成されている様子を基板裏面側から見た図であり、図７（ｂ）は、１つのチップ領域に第１の凹部が形成されている様子を基板裏面側から見た図であり、図７（ｃ）は、チップ領域に配置された貫通電極及び第１の凹部の斜視図であり、図７（ｄ）は、電極及び第２の絶縁膜を形成する前の第１の凹部（貫通電極を含む）の拡大断面図である。FIG. 7A is a view of a state in which the semiconductor device according to the modification of the first embodiment is formed in each chip region of the semiconductor substrate (wafer) as viewed from the back side of the substrate. ) Is a view of a state in which the first recess is formed in one chip region from the back side of the substrate, and FIG. 7C shows the through electrode and the first recess disposed in the chip region. FIG. 7D is an enlarged cross-sectional view of the first recess (including the through electrode) before forming the electrode and the second insulating film. 図８（ａ）～（ｃ）は、第２の実施形態に係る半導体装置の製造方法の各工程を示す断面図である。8A to 8C are cross-sectional views showing respective steps of the method for manufacturing the semiconductor device according to the second embodiment. 図９（ａ）及び（ｂ）は、第２の実施形態に係る半導体装置の製造方法の各工程を示す断面図である。FIGS. 9A and 9B are cross-sectional views illustrating respective steps of the method for manufacturing the semiconductor device according to the second embodiment. 図１０（ａ）及び（ｂ）はそれぞれ、第２の実施形態の変形例に係る半導体装置の断面図である。FIGS. 10A and 10B are cross-sectional views of a semiconductor device according to a modification of the second embodiment.
　（第１の実施形態）
　以下、本発明の第１の実施形態に係る半導体装置及びその製造方法について、図面を参照しながら説明する。 (First embodiment)
Hereinafter, a semiconductor device and a manufacturing method thereof according to a first embodiment of the present invention will be described with reference to the drawings.
　図１（ａ）～（ｃ）及び図２（ａ）～（ｃ）は、第１の実施形態に係る半導体装置の製造方法の各工程を示す断面図である。 FIGS. 1A to 1C and FIGS. 2A to 2C are cross-sectional views showing respective steps of the semiconductor device manufacturing method according to the first embodiment.
　まず、図１（ａ）に示すように、貫通電極２が素子形成面の反対面（裏面１ｂ）に露出しないように埋設されている半導体基板１を準備する。半導体基板１の素子形成面（表面１ａ）側には、トランジスタ１１等の各種の機能素子が形成されている。また、半導体基板１の表面１ａ上には、貫通電極２及びトランジスタ１１等と電気的に接続する多層配線を有する配線層１２が形成されている。貫通電極２は、半導体基板１の裏面１ｂ側からの平面視において、例えば５μｍ□の方形状を有している。また、貫通電極２は、配線層１２の内部に達するように形成されていると共に、貫通電極２の側壁は、バリア膜（図示省略）を挟んで絶縁膜１３によって覆われている。 First, as shown in FIG. 1A, a semiconductor substrate 1 is prepared in which a through electrode 2 is buried so as not to be exposed on the surface opposite to the element formation surface (back surface 1b). Various functional elements such as the transistor 11 are formed on the element formation surface (front surface 1 a) side of the semiconductor substrate 1. Further, on the surface 1 a of the semiconductor substrate 1, a wiring layer 12 having a multilayer wiring that is electrically connected to the through electrode 2 and the transistor 11 is formed. The through electrode 2 has, for example, a 5 μm square shape in plan view from the back surface 1 b side of the semiconductor substrate 1. The through electrode 2 is formed so as to reach the inside of the wiring layer 12, and the side wall of the through electrode 2 is covered with an insulating film 13 with a barrier film (not shown) interposed therebetween.
　次に、図１（ｂ）に示すように、例えばＣＭＰ（chemical mechanical polishing ）を用いて半導体基板１を裏面１ｂ側から研磨し、当該研磨後の裏面１ｂに貫通電極２が露出しないように半導体基板１の厚さを薄くする。 Next, as shown in FIG. 1B, the semiconductor substrate 1 is polished from the back surface 1b side using, for example, CMP (chemical mechanical polishing), and the through electrode 2 is not exposed to the back surface 1b after the polishing. The thickness of the substrate 1 is reduced.
　次に、図１（ｃ）に示すように、半導体基板１の裏面１ｂ側からの平面視において貫通電極２の直上を包含する領域及び当該領域以外の他の領域にそれぞれ例えば２０μｍ□の矩形状の開口部を有するレジストパターン（図示省略）を形成した後、当該レジストパターンをマスクとして、半導体基板１に対してドライエッチングを行い、その後、当該レジストパターンを除去する。これにより、半導体基板１の裏面１ｂに、貫通電極２の少なくとも端面（底面）を露出させる第１の凹部３を形成すると共に、貫通電極を露出させない第２の凹部８を形成する。ここで、第１の凹部３は、貫通電極２の底面よりも大きい底部を有している。また、第１の凹部３及び第２の凹部８のそれぞれの深さは、例えば１０μｍ程度である。 Next, as shown in FIG. 1C, in a plan view from the back surface 1b side of the semiconductor substrate 1, a rectangular shape of, for example, 20 μm □ is formed in a region including the portion directly above the through electrode 2 and other regions other than the region. After forming a resist pattern (not shown) having the openings, dry etching is performed on the semiconductor substrate 1 using the resist pattern as a mask, and then the resist pattern is removed. Thus, the first recess 3 that exposes at least the end face (bottom surface) of the through electrode 2 is formed on the back surface 1b of the semiconductor substrate 1, and the second recess 8 that does not expose the through electrode is formed. Here, the first recess 3 has a bottom portion larger than the bottom surface of the through electrode 2. The depth of each of the first recess 3 and the second recess 8 is, for example, about 10 μm.
　次に、図２（ａ）に示すように、半導体基板１の裏面１ｂ上に、第１の凹部３及び第２の凹部８のそれぞれの内面を覆うように、例えばＣＶＤ（chemical vapor deposition ）法を用いて、例えば厚さ５００ｎｍ程度のシリコン酸化膜からなる第１の絶縁膜４を形成する。その後、第１の絶縁膜４における貫通電極２の底面上に形成されている部分のみを例えばドライエッチング法を用いて除去する。 Next, as shown in FIG. 2A, for example, a CVD (chemical vapor deposition) method is performed on the back surface 1b of the semiconductor substrate 1 so as to cover the inner surfaces of the first concave portion 3 and the second concave portion 8, respectively. For example, the first insulating film 4 made of a silicon oxide film having a thickness of about 500 nm is formed. Thereafter, only the portion of the first insulating film 4 formed on the bottom surface of the through electrode 2 is removed using, for example, a dry etching method.
　次に、例えばスパッタ法により、第１の絶縁膜４上にバリア膜として例えば厚さ１００ｎｍ程度のＴｉＮ膜（図示省略）を形成した後、例えばスパッタ法により、当該ＴｉＮ膜上に例えば厚さ２０ｎｍ程度のＣｕシード膜（図示省略）を形成する。その後、第１の凹部３上を含む所定の領域に開口を持つレジストパターン（図示省略）をマスクとして、図２（ｂ）に示すように、例えば電解メッキ法により、前記Ｃｕシード膜上に例えば厚さ１μｍ程度のＣｕ膜からなる導電膜５を形成する。ここで、導電膜５は、貫通電極２の底面と接続すると共に、第１の凹部３の外側まで延びている。その後、前記レジストパターンを除去した後、導電膜５をマスクとして、例えばドライエッチングにより、導電膜５が形成されていない領域の前記ＴｉＮ膜及び前記Ｃｕシード膜を除去する。 Next, a TiN film (not shown) having a thickness of, for example, about 100 nm is formed as a barrier film on the first insulating film 4 by, for example, sputtering, and then, for example, 20 nm in thickness is formed on the TiN film by, for example, sputtering. A Cu seed film (not shown) is formed. Then, using a resist pattern (not shown) having an opening in a predetermined region including the first recess 3 as a mask, as shown in FIG. 2B, for example, on the Cu seed film by, for example, electrolytic plating. A conductive film 5 made of a Cu film having a thickness of about 1 μm is formed. Here, the conductive film 5 is connected to the bottom surface of the through electrode 2 and extends to the outside of the first recess 3. Then, after removing the resist pattern, the TiN film and the Cu seed film in a region where the conductive film 5 is not formed are removed by dry etching, for example, using the conductive film 5 as a mask.
　次に、図２（ｃ）に示すように、第１の凹部３の外側に位置する部分の導電膜５上に、例えば半田バンプからなる電極６を形成する。その後、例えばＣＶＤ法を用いて、第１の凹部３及び第２の凹部８の内面上を含む半導体基板１の裏面１ｂ上の全面に亘って、例えば厚さ５００ｎｍ程度のシリコン酸化膜からなる第２の絶縁膜７を形成した後、導電膜５を完全に覆い且つ電極６の少なくとも上面を露出させるように第２の絶縁膜７をパターニングする。 Next, as shown in FIG. 2C, an electrode 6 made of, for example, a solder bump is formed on a portion of the conductive film 5 located outside the first recess 3. Thereafter, for example, a CVD method is used to form a first silicon oxide film having a thickness of, for example, about 500 nm over the entire surface of the back surface 1b of the semiconductor substrate 1 including the inner surfaces of the first recess 3 and the second recess 8. After the second insulating film 7 is formed, the second insulating film 7 is patterned so as to completely cover the conductive film 5 and expose at least the upper surface of the electrode 6.
　以上のようにして、本実施形態の半導体装置が完成する。 As described above, the semiconductor device of this embodiment is completed.
　図３（ａ）は、半導体基板（ウェーハ）１の各チップ領域５０に本実施形態の半導体装置が形成されている様子を裏面１ｂ側から見た図（鳥瞰図）であり、図３（ｂ）は、１つのチップ領域５０に第１の凹部３及び第２の凹部８が形成されている様子を裏面１ｂ側から見た図（鳥瞰図）であり、図３（ｃ）は、チップ領域５０に配置された貫通電極２、第１の凹部３及び第２の凹部８の斜視図（半透視図）である。また、図３（ｄ）及び（ｅ）はそれぞれ、電極６及び第２の絶縁膜７を形成する前の第１の凹部３（貫通電極２を含む）及び第２の凹部８の拡大断面図である。尚、図３（ｄ）においては、図２（ｂ）及び（ｃ）で図示を省略したバリア膜（ＴｉＮ膜）１４を示している。 FIG. 3A is a view (bird's eye view) of a state in which the semiconductor device of the present embodiment is formed in each chip region 50 of the semiconductor substrate (wafer) 1 from the back surface 1b side, and FIG. FIG. 3C is a view (bird's eye view) of a state in which the first concave portion 3 and the second concave portion 8 are formed in one chip region 50 from the back surface 1b side, and FIG. It is a perspective view (semi-transparent figure) of the penetration electrode 2, the 1st crevice 3, and the 2nd crevice 8 arranged. 3D and 3E are enlarged sectional views of the first recess 3 (including the through electrode 2) and the second recess 8 before forming the electrode 6 and the second insulating film 7, respectively. It is. FIG. 3D shows a barrier film (TiN film) 14 not shown in FIGS. 2B and 2C.
　第１の実施形態によると、半導体基板１の裏面１ｂに、貫通電極２の端面を露出させる（つまり貫通電極２と連結する）放熱用凹部（第１の凹部３）が設けられている。このため、半導体基板１の素子形成面（表面１ａ）で発生し且つ貫通電極２を経由して裏面１ｂまで伝わってきた熱を第１の凹部３から放熱することができるので、貫通電極を露出させない（つまり貫通電極と連結しない）放熱用凹部しか基板裏面に設けられていない従来構造と比較して、３次元集積化技術を適用した場合にも放熱効率を十分に向上させることができる。また、第１の凹部３における貫通電極２の端面を除く内面を覆うように半導体基板１の裏面１ｂ上に第１の絶縁膜４が形成されているため、貫通電極２の端面と接続する導電膜５（つまり引き出し配線）の形成に起因する貫通電極２と半導体基板１との電気的な短絡を確実に防止することができる。 According to the first embodiment, the back surface 1b of the semiconductor substrate 1 is provided with a heat radiation recess (first recess 3) that exposes the end surface of the through electrode 2 (that is, is connected to the through electrode 2). For this reason, the heat generated on the element formation surface (front surface 1a) of the semiconductor substrate 1 and transmitted to the back surface 1b via the through electrode 2 can be radiated from the first recess 3, so that the through electrode is exposed. Compared with a conventional structure in which only the heat radiation recess is not provided on the back surface of the substrate (that is, not connected to the through electrode), the heat radiation efficiency can be sufficiently improved even when the three-dimensional integration technique is applied. In addition, since the first insulating film 4 is formed on the back surface 1 b of the semiconductor substrate 1 so as to cover the inner surface of the first recess 3 except for the end surface of the through electrode 2, the conductive material connected to the end surface of the through electrode 2. It is possible to reliably prevent an electrical short circuit between the through electrode 2 and the semiconductor substrate 1 due to the formation of the film 5 (that is, the lead wiring).
　また、第１の実施形態によると、発熱源（半導体基板１の素子形成面（表面１ａ））からの熱が蓄積されている貫通電極２に接続する導電膜（本実施形態ではＣｕ膜）５が第１の凹部３内にも形成されているため、熱伝導率の高い導電膜５の表面積が増大するので、放熱効率をさらに高めることが可能となる。ここで、導電膜５は、貫通電極２の引き出し配線となる部分とは別に、第１の凹部３の外側の半導体基板１の裏面１ｂ上に、放熱効率をさらに向上させるための放熱部を有していてもよい。 Further, according to the first embodiment, the conductive film (Cu film in this embodiment) 5 connected to the through electrode 2 in which heat from the heat source (element formation surface (surface 1a) of the semiconductor substrate 1) is accumulated. Is also formed in the first recess 3, the surface area of the conductive film 5 having a high thermal conductivity is increased, and the heat dissipation efficiency can be further increased. Here, the conductive film 5 has a heat dissipating part for further improving the heat dissipating efficiency on the back surface 1b of the semiconductor substrate 1 outside the first recessed part 3 separately from the part serving as the lead wiring of the through electrode 2. You may do it.
　また、第１の実施形態によると、貫通電極２が形成されていない領域の半導体基板１の裏面１ｂにも第２の凹部８を形成しているため、半導体基板１の裏面１ｂの実質的な表面積を大幅に増大させることができるので、放熱効率をより一層高めることが可能となる。 Further, according to the first embodiment, since the second recess 8 is formed also in the back surface 1b of the semiconductor substrate 1 in the region where the through electrode 2 is not formed, the substantial back surface 1b of the semiconductor substrate 1 is formed. Since the surface area can be greatly increased, the heat radiation efficiency can be further enhanced.
　さらに、第１の実施形態によると、貫通電極２の端面を露出させる（つまり貫通電極２と連結する）放熱用凹部（第１の凹部３）を、貫通電極２を露出させない（つまり貫通電極２と連結しない）放熱用凹部（第２の凹部８）と同時に形成することができるので、工程を複雑化することなく、前述の効果を得ることができる。 Furthermore, according to the first embodiment, the heat radiation recess (first recess 3) that exposes the end face of the through electrode 2 (that is, is connected to the through electrode 2) does not expose the through electrode 2 (that is, the through electrode 2). Since the heat dissipation recess (second recess 8) can be formed at the same time, the above-described effects can be obtained without complicating the process.
　尚、第１の実施形態では、半導体基板１の裏面１ｂ上に形成する第１の絶縁膜４として、ＣＶＤ法により形成されたシリコン酸化膜を用いた。しかし、これに代えて、第１の絶縁膜４として、熱伝導率がシリコン酸化膜よりも高い（具体的には、熱伝導率が１．５Ｗ／（ｍ・Ｋ）以上の）絶縁材料を用いることにより、放熱性をさらに向上させることが可能となる。例えば、低ストレスアモルファスシリコン窒化膜（熱導電率は最大４Ｗ／（ｍ・Ｋ）程度）、及びダイヤモンドライクカーボン（ＤＬＣ）膜（熱導電率は最大３０Ｗ／（ｍ・Ｋ）程度）等は、極めて有用な絶縁材料である。ここで、ＤＬＣ膜は、ダイヤモンドのｓｐ3 結合とグラファイトのｓｐ2 結合の両者を炭素原子の骨格構造としたアモルファス炭素膜であり、絶縁性を有していながら、シリコン酸化膜の２０倍以上の熱伝導率を有する。ＤＬＣ膜の形成方法としては、プラズマＣＶＤ法、熱ＣＶＤ法、光ＣＶＤ法、スパッタ法などがあり、２００℃程度の低温（つまり半導体プロセスに適合した温度範囲）で成膜可能である。 In the first embodiment, a silicon oxide film formed by a CVD method is used as the first insulating film 4 formed on the back surface 1b of the semiconductor substrate 1. However, instead of this, an insulating material having a higher thermal conductivity than the silicon oxide film (specifically, a thermal conductivity of 1.5 W / (m · K) or more) is used as the first insulating film 4. By using it, it becomes possible to further improve heat dissipation. For example, a low stress amorphous silicon nitride film (thermal conductivity is about 4 W / (m · K) at maximum), a diamond-like carbon (DLC) film (thermal conductivity is about 30 W / (m · K) at maximum), etc. It is a very useful insulating material. Here, the DLC film is an amorphous carbon film in which both the sp 3 bond of diamond and the sp 2 bond of graphite have a skeleton structure of carbon atoms. Has thermal conductivity. As a method for forming the DLC film, there are a plasma CVD method, a thermal CVD method, a photo CVD method, a sputtering method, and the like, which can be formed at a low temperature of about 200 ° C. (that is, a temperature range suitable for a semiconductor process).
　また、本実施形態において、貫通電極２と連結する第１の凹部３、及び貫通電極２と連結しない第２の凹部８のそれぞれのサイズ及び形状は特に限定されない。例えば、第１の凹部３及び第２の凹部８のサイズ及び形状の両方が同一であってもよいし、或いは、第１の凹部３及び第２の凹部８のサイズ及び形状の少なくとも一方が異なっていてもよい。また、第２の凹部８は、半導体基板１の外側に達する溝であってもよい。 In the present embodiment, the size and shape of the first recess 3 that is connected to the through electrode 2 and the second recess 8 that is not connected to the through electrode 2 are not particularly limited. For example, both the size and shape of the first recess 3 and the second recess 8 may be the same, or at least one of the size and shape of the first recess 3 and the second recess 8 is different. It may be. The second recess 8 may be a groove reaching the outside of the semiconductor substrate 1.
　また、本実施形態に係る半導体装置及びその製造方法は、チップ－チップ積層（ウェハダイシングにより得られたチップ状態の半導体装置同士の積層）、チップ－ウェーハ積層（チップ状態の半導体装置と、ダイシング前のウェーハ状態の半導体装置との積層）、又はウェーハ－ウェーハ積層（ウェーハ状態の半導体装置同士の積層）された半導体装置及びその製造方法のいずれにも適用可能である。 In addition, the semiconductor device and the manufacturing method thereof according to the present embodiment include chip-chip stacking (stacking of chip-state semiconductor devices obtained by wafer dicing), chip-wafer stacking (chip-state semiconductor device and pre-dicing semiconductor device). The semiconductor device can be applied to any of the semiconductor devices in which the wafer state semiconductor device is stacked) or the wafer-wafer stack (lamination of the semiconductor devices in the wafer state) and the manufacturing method thereof.
　（第１の実施形態の変形例）
　以下、本発明の第１の実施形態の変形例に係る半導体装置及びその製造方法について、図面を参照しながら説明する。本変形例が前述の第１の実施形態と異なっている点は、半導体基板１の裏面１ｂに、貫通電極２を露出させない（つまり貫通電極２と連結していない）第２の凹部８が形成されていないことである。すなわち、貫通電極２を露出させる（つまり貫通電極２と連結している）第１の凹部３のみによって十分な放熱効率が得られる場合には、第２の凹部８を設けなくてもよい。 (Modification of the first embodiment)
Hereinafter, a semiconductor device and a manufacturing method thereof according to a modification of the first embodiment of the present invention will be described with reference to the drawings. This modification is different from the first embodiment described above in that a second recess 8 is formed on the back surface 1b of the semiconductor substrate 1 so that the through electrode 2 is not exposed (that is, not connected to the through electrode 2). It is not done. That is, when sufficient heat radiation efficiency can be obtained only by the first recess 3 exposing the through electrode 2 (that is, connected to the through electrode 2), the second recess 8 may not be provided.
　図４（ａ）～（ｃ）及び図５（ａ）～（ｃ）は、本変形例に係る半導体装置の製造方法の各工程を示す断面図である。 4 (a) to 4 (c) and FIGS. 5 (a) to 5 (c) are cross-sectional views showing respective steps of a method for manufacturing a semiconductor device according to this modification.
　まず、図４（ａ）に示すように、貫通電極２が素子形成面の反対面（裏面１ｂ）に露出しないように埋設されている半導体基板１を準備する。半導体基板１の素子形成面（表面１ａ）側には、トランジスタ１１等の各種の機能素子が形成されている。また、半導体基板１の表面１ａ上には、貫通電極２及びトランジスタ１１等と電気的に接続する多層配線を有する配線層１２が形成されている。貫通電極２は、半導体基板１の裏面１ｂ側からの平面視において、例えば５μｍ□の方形状を有している。また、貫通電極２は、配線層１２の内部に達するように形成されていると共に、貫通電極２の側壁は、バリア膜（図示省略）を挟んで絶縁膜１３によって覆われている。 First, as shown in FIG. 4A, a semiconductor substrate 1 is prepared in which a through electrode 2 is buried so as not to be exposed on the surface opposite to the element formation surface (back surface 1b). Various functional elements such as the transistor 11 are formed on the element formation surface (front surface 1 a) side of the semiconductor substrate 1. Further, on the surface 1 a of the semiconductor substrate 1, a wiring layer 12 having a multilayer wiring that is electrically connected to the through electrode 2 and the transistor 11 is formed. The through electrode 2 has, for example, a 5 μm square shape in plan view from the back surface 1 b side of the semiconductor substrate 1. The through electrode 2 is formed so as to reach the inside of the wiring layer 12, and the side wall of the through electrode 2 is covered with an insulating film 13 with a barrier film (not shown) interposed therebetween.
　次に、図４（ｂ）に示すように、例えばＣＭＰを用いて半導体基板１を裏面１ｂ側から研磨し、当該研磨後の裏面１ｂに貫通電極２が露出しないように半導体基板１の厚さを薄くする。 Next, as shown in FIG. 4B, the semiconductor substrate 1 is polished from the back surface 1b side using, for example, CMP, and the thickness of the semiconductor substrate 1 is set so that the through electrode 2 is not exposed to the back surface 1b after the polishing. Thin out.
　次に、図４（ｃ）に示すように、半導体基板１の裏面１ｂ側からの平面視において貫通電極２の直上を包含する領域に例えば２０μｍ□の矩形状の開口部を有するレジストパターン（図示省略）を形成した後、当該レジストパターンをマスクとして、半導体基板１に対してドライエッチングを行い、その後、当該レジストパターンを除去する。これにより、半導体基板１の裏面１ｂに、貫通電極２の少なくとも端面（底面）を露出させる第１の凹部３を形成する。ここで、第１の凹部３は、貫通電極２の底面よりも大きい底部を有している。また、第１の凹部３の深さは、例えば１０μｍ程度である。 Next, as shown in FIG. 4C, a resist pattern having a rectangular opening of, for example, 20 μm square in a region including the portion directly above the through electrode 2 in a plan view from the back surface 1b side of the semiconductor substrate 1 (illustrated). (Omitted) is formed, and then the semiconductor substrate 1 is dry-etched using the resist pattern as a mask, and then the resist pattern is removed. As a result, the first recess 3 is formed on the back surface 1 b of the semiconductor substrate 1 to expose at least the end surface (bottom surface) of the through electrode 2. Here, the first recess 3 has a bottom portion larger than the bottom surface of the through electrode 2. The depth of the first recess 3 is, for example, about 10 μm.
　次に、図５（ａ）に示すように、半導体基板１の裏面１ｂ上に、第１の凹部３の内面を覆うように、例えばＣＶＤ法を用いて、例えば厚さ５００ｎｍ程度のシリコン酸化膜からなる第１の絶縁膜４を形成する。その後、第１の絶縁膜４における貫通電極２の底面上に形成されている部分のみを例えばドライエッチング法を用いて除去する。 Next, as shown in FIG. 5A, a silicon oxide film having a thickness of, for example, about 500 nm is formed on the back surface 1b of the semiconductor substrate 1 by using, for example, a CVD method so as to cover the inner surface of the first recess 3. A first insulating film 4 made of is formed. Thereafter, only the portion of the first insulating film 4 formed on the bottom surface of the through electrode 2 is removed using, for example, a dry etching method.
　次に、例えばスパッタ法により、第１の絶縁膜４上にバリア膜として例えば厚さ１００ｎｍ程度のＴｉＮ膜（図示省略）を形成した後、例えばスパッタ法により、当該ＴｉＮ膜上に例えば厚さ２０ｎｍ程度のＣｕシード膜（図示省略）を形成する。その後、第１の凹部３上を含む所定の領域に開口を持つレジストパターン（図示省略）をマスクとして、図５（ｂ）に示すように、例えば電解メッキ法により、前記Ｃｕシード膜上に例えば厚さ１μｍ程度のＣｕ膜からなる導電膜５を形成する。ここで、導電膜５は、貫通電極２の底面と接続すると共に、第１の凹部３の外側まで延びている。また、導電膜５は、後述する電極６（図５（ｃ）参照）と貫通電極２とを電気的に接続するための引き出し配線部分とは別に、第１の凹部３の外側の半導体基板１の裏面１ｂ上に、放熱効率を向上させるための放熱部５ａを有している。図６は、放熱部５ａを半導体基板１の裏面１ｂ側から見た平面図である。図６に示すように、放熱部５ａは、導電膜５の他の部分と比較して幅広形状を持つ。 Next, a TiN film (not shown) having a thickness of, for example, about 100 nm is formed as a barrier film on the first insulating film 4 by, for example, sputtering, and then, for example, 20 nm in thickness is formed on the TiN film by, for example, sputtering. A Cu seed film (not shown) is formed. Then, using a resist pattern (not shown) having an opening in a predetermined region including the first concave portion 3 as a mask, as shown in FIG. 5B, for example, on the Cu seed film by, for example, electrolytic plating. A conductive film 5 made of a Cu film having a thickness of about 1 μm is formed. Here, the conductive film 5 is connected to the bottom surface of the through electrode 2 and extends to the outside of the first recess 3. In addition, the conductive film 5 is provided on the semiconductor substrate 1 outside the first recess 3 separately from the lead-out wiring portion for electrically connecting the electrode 6 (see FIG. 5C) described later and the through electrode 2. On the back surface 1b, there is a heat dissipating part 5a for improving the heat dissipating efficiency. FIG. 6 is a plan view of the heat radiating portion 5 a as viewed from the back surface 1 b side of the semiconductor substrate 1. As shown in FIG. 6, the heat radiating portion 5 a has a wider shape than the other portions of the conductive film 5.
　その後、前記レジストパターンを除去した後、導電膜５をマスクとして、例えばドライエッチングにより、導電膜５が形成されていない領域の前記ＴｉＮ膜及び前記Ｃｕシード膜を除去する。 Then, after removing the resist pattern, the TiN film and the Cu seed film in a region where the conductive film 5 is not formed are removed by dry etching, for example, using the conductive film 5 as a mask.
　次に、図５（ｃ）に示すように、第１の凹部３の外側に位置する部分の導電膜５上に、例えば半田バンプからなる電極６を形成する。その後、例えばＣＶＤ法を用いて、第１の凹部３の内面上を含む半導体基板１の裏面１ｂ上の全面に亘って、例えば厚さ５００ｎｍ程度のシリコン酸化膜からなる第２の絶縁膜７を形成した後、導電膜５を完全に覆い且つ電極６の少なくとも上面を露出させるように第２の絶縁膜７をパターニングする。 Next, as shown in FIG. 5C, an electrode 6 made of, for example, a solder bump is formed on a portion of the conductive film 5 located outside the first recess 3. Thereafter, the second insulating film 7 made of, for example, a silicon oxide film having a thickness of about 500 nm is formed over the entire surface of the back surface 1b of the semiconductor substrate 1 including the inner surface of the first recess 3 by using, for example, the CVD method. After the formation, the second insulating film 7 is patterned so as to completely cover the conductive film 5 and expose at least the upper surface of the electrode 6.
　以上のようにして、本変形例の半導体装置が完成する。 As described above, the semiconductor device of this modification is completed.
　図７（ａ）は、半導体基板（ウェーハ）１の各チップ領域５０に本変形例の半導体装置が形成されている様子を裏面１ｂ側から見た図（鳥瞰図）であり、図７（ｂ）は、１つのチップ領域５０に第１の凹部３が形成されている様子を裏面１ｂ側から見た図（鳥瞰図）であり、図７（ｃ）は、チップ領域５０に配置された貫通電極２及び第１の凹部３の斜視図（半透視図）である。また、図７（ｄ）は、電極６及び第２の絶縁膜７を形成する前の第１の凹部３（貫通電極２を含む）の拡大断面図である。尚、図７（ｄ）においては、図５（ｂ）及び（ｃ）で図示を省略したバリア膜（ＴｉＮ膜）１４を示している。 FIG. 7A is a view (bird's eye view) of a state in which the semiconductor device of the present modification is formed in each chip region 50 of the semiconductor substrate (wafer) 1 as viewed from the back surface 1b side. FIG. 7C is a view (bird's eye view) of a state in which the first concave portion 3 is formed in one chip region 50 from the back surface 1b side, and FIG. 7C is a through electrode 2 arranged in the chip region 50. FIG. 3 is a perspective view (semi-transparent view) of the first recess 3. FIG. 7D is an enlarged cross-sectional view of the first recess 3 (including the through electrode 2) before the electrode 6 and the second insulating film 7 are formed. FIG. 7D shows a barrier film (TiN film) 14 that is not shown in FIGS. 5B and 5C.
　本変形例によると、半導体基板１の裏面１ｂに、貫通電極２の端面を露出させる（つまり貫通電極２と連結する）放熱用凹部（第１の凹部３）が設けられている。このため、半導体基板１の素子形成面（表面１ａ）で発生し且つ貫通電極２を経由して裏面１ｂまで伝わってきた熱を第１の凹部３から放熱することができるので、貫通電極を露出させない（つまり貫通電極と連結しない）放熱用凹部しか基板裏面に設けられていない従来構造と比較して、３次元集積化技術を適用した場合にも放熱効率を十分に向上させることができる。また、第１の凹部３における貫通電極２の端面を除く内面を覆うように半導体基板１の裏面１ｂ上に第１の絶縁膜４が形成されているため、貫通電極２の端面と接続する導電膜５（つまり引き出し配線）の形成に起因する貫通電極２と半導体基板１との電気的な短絡を確実に防止することができる。 According to this modification, a heat radiation recess (first recess 3) is provided on the back surface 1b of the semiconductor substrate 1 to expose the end face of the through electrode 2 (that is, to be connected to the through electrode 2). For this reason, the heat generated on the element formation surface (front surface 1a) of the semiconductor substrate 1 and transmitted to the back surface 1b via the through electrode 2 can be radiated from the first recess 3, so that the through electrode is exposed. Compared with a conventional structure in which only the heat radiation recess is not provided on the back surface of the substrate (that is, not connected to the through electrode), the heat radiation efficiency can be sufficiently improved even when the three-dimensional integration technique is applied. In addition, since the first insulating film 4 is formed on the back surface 1 b of the semiconductor substrate 1 so as to cover the inner surface of the first recess 3 except for the end surface of the through electrode 2, the conductive material connected to the end surface of the through electrode 2. It is possible to reliably prevent an electrical short circuit between the through electrode 2 and the semiconductor substrate 1 due to the formation of the film 5 (that is, the lead wiring).
　また、本変形例によると、発熱源（半導体基板１の素子形成面（表面１ａ））からの熱が蓄積されている貫通電極２に接続する導電膜（本実施形態ではＣｕ膜）５が第１の凹部３内にも形成されているため、熱伝導率の高い導電膜５の表面積が増大するので、放熱効率をさらに高めることが可能となる。ここで、本変形例では、導電膜５が、貫通電極２の引き出し配線となる部分とは別に、第１の凹部３の外側の半導体基板１の裏面１ｂ上に放熱部５ａ（図６参照）を有しているため、放熱効率をより一層向上させることができる。 Further, according to the present modification, the conductive film (Cu film in this embodiment) 5 connected to the through electrode 2 in which heat from the heat source (element formation surface (surface 1a) of the semiconductor substrate 1) is accumulated is the first. Since the surface area of the conductive film 5 having a high thermal conductivity is increased, the heat radiation efficiency can be further increased. Here, in this modification, apart from the portion where the conductive film 5 becomes the lead wiring of the through electrode 2, the heat radiating portion 5 a (see FIG. 6) is formed on the back surface 1 b of the semiconductor substrate 1 outside the first recess 3. Therefore, the heat dissipation efficiency can be further improved.
　尚、本変形例では、半導体基板１の裏面１ｂ上に形成する第１の絶縁膜４として、ＣＶＤ法により形成されたシリコン酸化膜を用いた。しかし、これに代えて、第１の絶縁膜４として、熱伝導率がシリコン酸化膜よりも高い（具体的には、熱伝導率が１．５Ｗ／（ｍ・Ｋ）以上の）絶縁材料を用いることにより、放熱性をさらに向上させることが可能となる。例えば、低ストレスアモルファスシリコン窒化膜（熱導電率は最大４Ｗ／（ｍ・Ｋ）程度）、及びダイヤモンドライクカーボン（ＤＬＣ）膜（熱導電率は最大３０Ｗ／（ｍ・Ｋ）程度）等は、極めて有用な絶縁材料である。ここで、ＤＬＣ膜は、ダイヤモンドのｓｐ3 結合とグラファイトのｓｐ2 結合の両者を炭素原子の骨格構造としたアモルファス炭素膜であり、絶縁性を有していながら、シリコン酸化膜の２０倍以上の熱伝導率を有する。ＤＬＣ膜の形成方法としては、プラズマＣＶＤ法、熱ＣＶＤ法、光ＣＶＤ法、スパッタ法などがあり、２００℃程度の低温（つまり半導体プロセスに適合した温度範囲）で成膜可能である。 In this modification, a silicon oxide film formed by a CVD method is used as the first insulating film 4 formed on the back surface 1b of the semiconductor substrate 1. However, instead of this, an insulating material having a higher thermal conductivity than the silicon oxide film (specifically, a thermal conductivity of 1.5 W / (m · K) or more) is used as the first insulating film 4. By using it, it becomes possible to further improve heat dissipation. For example, a low stress amorphous silicon nitride film (thermal conductivity is about 4 W / (m · K) at maximum), a diamond-like carbon (DLC) film (thermal conductivity is about 30 W / (m · K) at maximum), etc. It is a very useful insulating material. Here, the DLC film is an amorphous carbon film in which both the sp 3 bond of diamond and the sp 2 bond of graphite have a skeleton structure of carbon atoms. Has thermal conductivity. As a method for forming the DLC film, there are a plasma CVD method, a thermal CVD method, a photo CVD method, a sputtering method, and the like, which can be formed at a low temperature of about 200 ° C. (that is, a temperature range suitable for a semiconductor process).
　また、本変形例に係る半導体装置及びその製造方法は、チップ－チップ積層（ウェハダイシングにより得られたチップ状態の半導体装置同士の積層）、チップ－ウェーハ積層（チップ状態の半導体装置と、ダイシング前のウェーハ状態の半導体装置との積層）、又はウェーハ－ウェーハ積層（ウェーハ状態の半導体装置同士の積層）された半導体装置及びその製造方法のいずれにも適用可能である。 In addition, the semiconductor device and the manufacturing method thereof according to this modification include chip-chip stacking (stacking of chip-state semiconductor devices obtained by wafer dicing), chip-wafer stacking (chip-state semiconductor device and pre-dicing semiconductor device). The semiconductor device can be applied to any of the semiconductor devices in which the wafer state semiconductor device is stacked) or the wafer-wafer stack (lamination of the semiconductor devices in the wafer state) and the manufacturing method thereof.
　（第２の実施形態）
　以下、本発明の第２の実施形態に係る半導体装置及びその製造方法について、図面を参照しながら説明する。 (Second Embodiment)
Hereinafter, a semiconductor device and a manufacturing method thereof according to a second embodiment of the present invention will be described with reference to the drawings.
　図８（ａ）～（ｃ）及び図９（ａ）、（ｂ）は、第２の実施形態に係る半導体装置の製造方法の各工程を示す断面図である。 FIGS. 8A to 8C and FIGS. 9A and 9B are cross-sectional views showing respective steps of the semiconductor device manufacturing method according to the second embodiment.
　まず、図８（ａ）に示すように、貫通電極２が素子形成面の反対面（裏面１ｂ）に露出しないように埋設されている半導体基板１を準備する。半導体基板１の素子形成面（表面１ａ）側には、トランジスタ１１等の各種の機能素子が形成されている。また、半導体基板１の表面１ａ上には、貫通電極２及びトランジスタ１１等と電気的に接続する多層配線を有する配線層１２が形成されている。貫通電極２は、半導体基板１の裏面１ｂ側からの平面視において、例えば５μｍ□の方形状を有している。また、貫通電極２は、配線層１２の内部に達するように形成されていると共に、貫通電極２の側壁は、バリア膜（図示省略）を挟んで絶縁膜１３によって覆われている。 First, as shown in FIG. 8A, a semiconductor substrate 1 is prepared in which the through electrode 2 is buried so as not to be exposed on the opposite surface (back surface 1b) of the element formation surface. Various functional elements such as the transistor 11 are formed on the element formation surface (front surface 1 a) side of the semiconductor substrate 1. Further, on the surface 1 a of the semiconductor substrate 1, a wiring layer 12 having a multilayer wiring that is electrically connected to the through electrode 2 and the transistor 11 is formed. The through electrode 2 has, for example, a 5 μm square shape in plan view from the back surface 1 b side of the semiconductor substrate 1. The through electrode 2 is formed so as to reach the inside of the wiring layer 12, and the side wall of the through electrode 2 is covered with an insulating film 13 with a barrier film (not shown) interposed therebetween.
　次に、図８（ｂ）に示すように、例えばＣＭＰを用いて半導体基板１を裏面１ｂ側から研磨し、当該研磨後の裏面１ｂに貫通電極２が露出するように半導体基板１の厚さを薄くする。その後、半導体基板１の裏面１ｂに対して、エッチングを行うことにより、貫通電極２の端部（底部）を、エッチング後の裏面１ｂから高さにして例えば４００ｎｍ程度突き出させる。このとき、貫通電極２の突き出し部分の側壁を覆う絶縁膜１３を除去してもよい。 Next, as shown in FIG. 8B, the thickness of the semiconductor substrate 1 is such that the semiconductor substrate 1 is polished from the back surface 1b side using, for example, CMP, and the through electrode 2 is exposed on the back surface 1b after the polishing. Thin out. Thereafter, by etching the back surface 1b of the semiconductor substrate 1, the end portion (bottom portion) of the through electrode 2 is raised from the back surface 1b after the etching, for example, by about 400 nm. At this time, the insulating film 13 covering the side wall of the protruding portion of the through electrode 2 may be removed.
　次に、図８（ｃ）に示すように、貫通電極２の底部が露出した半導体基板１の裏面１ｂ上に、高い熱伝導性を持つ絶縁膜として、例えば厚さ２００ｎｍ程度のダイヤモンドライクカーボン膜９を形成する。 Next, as shown in FIG. 8C, a diamond-like carbon film having a thickness of, for example, about 200 nm is formed as an insulating film having high thermal conductivity on the back surface 1b of the semiconductor substrate 1 where the bottom of the through electrode 2 is exposed. 9 is formed.
　次に、図９（ａ）に示すように、ダイヤモンドライクカーボン膜９上に例えば厚さ５００ｎｍ程度のレジスト１０を形成する。 Next, as shown in FIG. 9A, a resist 10 having a thickness of, for example, about 500 nm is formed on the diamond-like carbon film 9.
　次に、レジスト１０を用いてエッチバックを行うことにより、図９（ｂ）に示すように、貫通電極２の底面上のダイヤモンドライクカーボン膜９を選択的に除去する。これによって、貫通電極２の底面が露出すると共に、半導体基板１の裏面１ｂから突き出た部分の貫通電極２の側壁上、及び貫通電極２の周辺を含む半導体基板１の裏面１ｂ上にダイヤモンドライクカーボン膜９を残存させることができる。その後、露出した貫通電極２の底面上に、例えば半田バンプからなる電極６を形成する。 Next, by performing etch back using the resist 10, the diamond-like carbon film 9 on the bottom surface of the through electrode 2 is selectively removed as shown in FIG. 9B. As a result, the bottom surface of the through electrode 2 is exposed, and the diamond-like carbon is formed on the side wall of the through electrode 2 protruding from the back surface 1 b of the semiconductor substrate 1 and on the back surface 1 b of the semiconductor substrate 1 including the periphery of the through electrode 2. The film 9 can remain. Thereafter, an electrode 6 made of, for example, a solder bump is formed on the exposed bottom surface of the through electrode 2.
　以上のようにして、本実施形態の半導体装置が完成する。 As described above, the semiconductor device of this embodiment is completed.
　第２の実施形態によると、貫通電極２が露出する半導体基板１の裏面１ｂ上に、熱伝導率が最大３０Ｗ／（ｍ・Ｋ）程度になるダイヤモンドライクカーボン膜９が形成されている。このため、半導体基板１の素子形成面（表面１ａ）で発生し且つ貫通電極２を経由して裏面１ｂまで伝わってきた熱を極めて効率的に放熱することができるので、３次元集積化技術を適用した場合にも放熱効率を十分に向上させることができる。また、ダイヤモンドライクカーボン膜９は絶縁性を有しているので、ダイヤモンドライクカーボン膜９に起因する貫通電極２と半導体基板１との電気的な短絡を確実に防止することができる。 According to the second embodiment, the diamond-like carbon film 9 having a maximum thermal conductivity of about 30 W / (m · K) is formed on the back surface 1b of the semiconductor substrate 1 where the through electrode 2 is exposed. For this reason, the heat generated on the element formation surface (front surface 1a) of the semiconductor substrate 1 and transmitted to the back surface 1b via the through electrode 2 can be dissipated very efficiently. Even when applied, the heat dissipation efficiency can be sufficiently improved. Further, since the diamond-like carbon film 9 has an insulating property, it is possible to reliably prevent an electrical short circuit between the through electrode 2 and the semiconductor substrate 1 due to the diamond-like carbon film 9.
　また、第２の実施形態によると、貫通電極２の底部が半導体基板１の裏面１ｂから突き出ていると共に、当該突き出し部分の側壁にダイヤモンドライクカーボン膜９が接しているため、放熱効率をより一層向上させることができる。 In addition, according to the second embodiment, the bottom of the through electrode 2 protrudes from the back surface 1b of the semiconductor substrate 1, and the diamond-like carbon film 9 is in contact with the side wall of the protruding portion. Can be improved.
　尚、第２の実施形態において、半導体基板１の裏面１ｂからの貫通電極２の突き出し部分の高さが十分であれば、電極６を形成しなくてもよい。また、貫通電極２の底部を半導体基板１の裏面１ｂから突き出させなくてもよい。また、例えば図１０（ａ）に示すように、ダイヤモンドライクカーボン膜９と貫通電極２とが離間していてもよい。また、例えば図１０（ｂ）に示すように、半導体基板１の裏面１ｂに、貫通電極２の少なくとも端面（底面）を露出させる第１の凹部３を設けてもよい。このようにすると、半導体基板１の裏面１ｂの実質的な表面積を増大させることができるので、放熱効率をより一層向上させることができる。また、この場合、図１０（ｂ）に示すように、ダイヤモンドライクカーボン膜９が、第１の凹部３における貫通電極２の底面を除く内面を覆っていると、特に、第１の凹部３における貫通電極２の突き出し部分の側壁にダイヤモンドライクカーボン膜９が接していると、放熱効率をさらに向上させることができる。 In the second embodiment, the electrode 6 may not be formed if the height of the protruding portion of the through electrode 2 from the back surface 1b of the semiconductor substrate 1 is sufficient. Further, the bottom portion of the through electrode 2 may not protrude from the back surface 1 b of the semiconductor substrate 1. For example, as shown in FIG. 10A, the diamond-like carbon film 9 and the through electrode 2 may be separated from each other. For example, as illustrated in FIG. 10B, a first recess 3 that exposes at least an end surface (bottom surface) of the through electrode 2 may be provided on the back surface 1 b of the semiconductor substrate 1. In this way, since the substantial surface area of the back surface 1b of the semiconductor substrate 1 can be increased, the heat dissipation efficiency can be further improved. Further, in this case, as shown in FIG. 10B, when the diamond-like carbon film 9 covers the inner surface except the bottom surface of the through electrode 2 in the first recess 3, particularly in the first recess 3. When the diamond-like carbon film 9 is in contact with the side wall of the protruding portion of the through electrode 2, the heat dissipation efficiency can be further improved.
　また、本実施形態に係る半導体装置及びその製造方法は、チップ－チップ積層（ウェハダイシングにより得られたチップ状態の半導体装置同士の積層）、チップ－ウェーハ積層（チップ状態の半導体装置と、ダイシング前のウェーハ状態の半導体装置との積層）、又はウェーハ－ウェーハ積層（ウェーハ状態の半導体装置同士の積層）された半導体装置及びその製造方法のいずれにも適用可能である。 In addition, the semiconductor device and the manufacturing method thereof according to the present embodiment include chip-chip stacking (stacking of chip-state semiconductor devices obtained by wafer dicing), chip-wafer stacking (chip-state semiconductor device and pre-dicing semiconductor device). The semiconductor device can be applied to any of the semiconductor devices in which the wafer state semiconductor device is stacked) or the wafer-wafer stack (lamination of the semiconductor devices in the wafer state) and the manufacturing method thereof.
　以上に説明したように、本発明に係る半導体装置及びその製造方法は、貫通電極と半導体基板との電気的な短絡を防止しつつ、基板裏面に貫通電極と連結する放熱用凹部を設けることにより、又は、基板裏面上に貫通電極若しくはその近傍に達する絶縁性高放熱材料膜を設けることにより、放熱効率の高い放熱構造を実現するものであり、特に、チップ－チップ積層、チップ－ウェーハ積層又はウェーハ－ウェーハ積層された半導体装置及びその製造方法等において有用である。 As described above, the semiconductor device and the manufacturing method thereof according to the present invention are provided by providing a heat radiation recess connected to the through electrode on the back surface of the substrate while preventing an electrical short circuit between the through electrode and the semiconductor substrate. Alternatively, by providing an insulating high heat dissipation material film that reaches the through electrode or the vicinity thereof on the back surface of the substrate, a heat dissipation structure with high heat dissipation efficiency is realized. In particular, chip-chip stacking, chip-wafer stacking or This is useful in a wafer-wafer stacked semiconductor device, a manufacturing method thereof, and the like.
　　　１　　半導体基板
　　　１ａ　　半導体基板の表面
　　　１ｂ　　半導体基板の裏面
　　　２　　貫通電極
　　　３　　第１の凹部
　　　４　　第１の絶縁膜
　　　５　　導電膜
　　　５ａ　　放熱部
　　　６　　電極
　　　７　　第２の絶縁膜
　　　８　　第２の凹部
　　　９　　ダイヤモンドライクカーボン膜
　　１０　　レジスト
　　１１　　トランジスタ
　　１２　　配線層
　　１３　　絶縁膜
　　１４　　バリア膜
　　５０　　チップ領域 DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 1a The surface of a semiconductor substrate 1b The back surface of a semiconductor substrate 2 The penetration electrode 3 The 1st recessed part 4 The 1st insulating film 5 The electrically conductive film 5a The thermal radiation part 6 The electrode 7 The 2nd insulating film 8 The 2nd recessed part 9 Diamond-like carbon Film 10 Resist 11 Transistor 12 Wiring layer 13 Insulating film 14 Barrier film 50 Chip region

Claims (25)

  1. 　半導体基板と、
    　前記半導体基板を貫通する貫通電極とを備え、
    　前記半導体基板の素子形成面の反対面には、前記貫通電極の少なくとも端面を露出させる第１の凹部と、前記貫通電極を露出させない第２の凹部とが形成されており、
    　前記半導体基板の前記反対面上には、前記第１の凹部における前記貫通電極の前記端面を除く内面及び前記第２の凹部の内面を覆うように第１の絶縁膜が形成されており、
    　前記第１の絶縁膜上には、前記貫通電極の前記端面と接続し且つ前記第１の凹部の外側まで延びる導電膜が形成されていることを特徴とする半導体装置。     A semiconductor substrate;
    A through electrode penetrating the semiconductor substrate,
    A first recess that exposes at least an end surface of the through electrode and a second recess that does not expose the through electrode are formed on the surface opposite to the element formation surface of the semiconductor substrate.
    On the opposite surface of the semiconductor substrate, a first insulating film is formed so as to cover an inner surface of the first recess excluding the end surface of the through electrode and an inner surface of the second recess,
    A conductive film is formed on the first insulating film, the conductive film being connected to the end face of the through electrode and extending to the outside of the first recess.
  2. 　請求項１に記載の半導体装置において、
    　前記第１の凹部の外側に位置する部分の前記導電膜上に電極が形成されており、
    　前記第１の絶縁膜上及び前記導電膜上に、前記電極の少なくとも上面が露出するように第２の絶縁膜が形成されていることを特徴とする半導体装置。     The semiconductor device according to claim 1,
    An electrode is formed on the conductive film in a portion located outside the first recess,
    A semiconductor device, wherein a second insulating film is formed on the first insulating film and the conductive film so that at least an upper surface of the electrode is exposed.
  3. 　請求項１又は２に記載の半導体装置において、
    　前記第１の絶縁膜の熱伝導率は、シリコン酸化膜の熱導電率よりも高いことを特徴とする半導体装置。     The semiconductor device according to claim 1 or 2,
    The semiconductor device according to claim 1, wherein the thermal conductivity of the first insulating film is higher than the thermal conductivity of the silicon oxide film.
  4. 　請求項１～３のいずれか１項に記載の半導体装置において、
    　前記第１の絶縁膜の熱伝導率は、１．５Ｗ／（ｍ・Ｋ）以上であることを特徴とする半導体装置     The semiconductor device according to any one of claims 1 to 3,
    The semiconductor device characterized in that the thermal conductivity of the first insulating film is 1.5 W / (m · K) or more.
  5. 　請求項１～４のいずれか１項に記載の半導体装置において、
    　前記第１の絶縁膜はダイヤモンドライクカーボン膜からなることを特徴とする半導体装置。     The semiconductor device according to any one of claims 1 to 4,
    The semiconductor device according to claim 1, wherein the first insulating film is made of a diamond-like carbon film.
  6. 　請求項１～５のいずれか１項に記載の半導体装置において、
    　前記半導体基板の前記反対面に前記第２の凹部が形成されていないことを特徴とする半導体装置。     The semiconductor device according to any one of claims 1 to 5,
    2. The semiconductor device according to claim 1, wherein the second recess is not formed on the opposite surface of the semiconductor substrate.
  7. 　貫通電極が素子形成面の反対面に露出しないように埋設されている半導体基板を準備する工程（ａ）と、
    　前記半導体基板の前記反対面に、前記貫通電極の少なくとも端面を露出させる第１の凹部と、前記貫通電極を露出させない第２の凹部とを形成する工程（ｂ）と、
    　前記半導体基板の前記反対面上に、前記第１の凹部における前記貫通電極の前記端面を除く内面及び前記第２の凹部の内面を覆うように第１の絶縁膜を形成する工程（ｃ）と、
    　前記第１の絶縁膜上に、前記貫通電極の前記端面と接続し且つ前記第１の凹部の外側まで延びる導電膜を形成する工程（ｄ）とを備えていることを特徴とする半導体装置の製造方法。     A step (a) of preparing a semiconductor substrate embedded so that the through electrode is not exposed on the surface opposite to the element formation surface;
    Forming on the opposite surface of the semiconductor substrate a first recess that exposes at least an end surface of the through electrode and a second recess that does not expose the through electrode; and
    Forming a first insulating film on the opposite surface of the semiconductor substrate so as to cover an inner surface of the first recess excluding the end surface of the through electrode and an inner surface of the second recess; ,
    And (d) forming a conductive film connected to the end face of the through electrode and extending to the outside of the first recess on the first insulating film. Production method.
  8. 　請求項７に記載の半導体装置の製造方法において、
    　前記工程（ａ）と前記工程（ｂ）との間に、前記半導体基板を前記反対面側から研磨し、当該研磨後の前記反対面に前記貫通電極が露出しないように前記半導体基板を薄くする工程をさらに備えていることを特徴とする半導体装置の製造方法。     In the manufacturing method of the semiconductor device according to claim 7,
    Between the step (a) and the step (b), the semiconductor substrate is polished from the opposite surface side, and the semiconductor substrate is thinned so that the through electrode is not exposed on the opposite surface after the polishing. A method of manufacturing a semiconductor device, further comprising a step.
  9. 　請求項７又は８に記載の半導体装置の製造方法において、
    　前記工程（ｄ）よりも後に、前記第１の凹部の外側に位置する部分の前記導電膜上に電極を形成した後、前記第１の絶縁膜上及び前記導電膜上に、前記電極の少なくとも上面が露出するように第２の絶縁膜を形成する工程をさらに備えていることを特徴とする半導体装置の製造方法。     In the manufacturing method of the semiconductor device according to claim 7 or 8,
    After the step (d), an electrode is formed on the conductive film in a portion located outside the first recess, and then at least the electrode is formed on the first insulating film and the conductive film. A method of manufacturing a semiconductor device, further comprising the step of forming a second insulating film so that the upper surface is exposed.
  10. 　請求項７～９のいずれか１項に記載の半導体装置の製造方法において、
    　前記第１の絶縁膜の熱伝導率は、シリコン酸化膜の熱導電率よりも高いことを特徴とする半導体装置の製造方法。     The method for manufacturing a semiconductor device according to any one of claims 7 to 9,
    A method of manufacturing a semiconductor device, wherein the thermal conductivity of the first insulating film is higher than the thermal conductivity of a silicon oxide film.
  11. 　請求項７～１０のいずれか１項に記載の半導体装置の製造方法において、
    　前記第１の絶縁膜の熱伝導率は、１．５Ｗ／（ｍＫ）以上であることを特徴とする半導体装置の製造方法。     The method of manufacturing a semiconductor device according to any one of claims 7 to 10,
    The method of manufacturing a semiconductor device, wherein the first insulating film has a thermal conductivity of 1.5 W / (mK) or more.
  12. 　請求項７～１１のいずれか１項に記載の半導体装置の製造方法において、
    　前記第１の絶縁膜はダイヤモンドライクカーボン膜からなることを特徴とする半導体装置の製造方法。     The method for manufacturing a semiconductor device according to any one of claims 7 to 11,
    The method of manufacturing a semiconductor device, wherein the first insulating film is made of a diamond-like carbon film.
  13. 　請求項７～１２のいずれか１項に記載の半導体装置の製造方法において、
    　前記工程（ｂ）で、前記半導体基板の前記反対面に前記第２の凹部を形成しないことを特徴とする半導体装置の製造方法。     The method of manufacturing a semiconductor device according to any one of claims 7 to 12,
    In the step (b), the second recess is not formed on the opposite surface of the semiconductor substrate.
  14. 　半導体基板と、
    　前記半導体基板を貫通する貫通電極とを備え、
    　前記半導体基板の素子形成面の反対面上には、前記貫通電極の少なくとも端面が露出するようにダイヤモンドライクカーボン膜が形成されていることを特徴とする半導体装置。     A semiconductor substrate;
    A through electrode penetrating the semiconductor substrate,
    A diamond-like carbon film is formed on the surface of the semiconductor substrate opposite to the element formation surface so that at least the end surface of the through electrode is exposed.
  15. 　請求項１４に記載の半導体装置において、
    　前記貫通電極は、前記半導体基板の前記反対面から突き出ていることを特徴とする半導体装置。     The semiconductor device according to claim 14.
    The semiconductor device, wherein the through electrode protrudes from the opposite surface of the semiconductor substrate.
  16. 　請求項１４又は１５に記載の半導体装置において、
    　前記貫通電極の前記端面上に電極が形成されていることを特徴とする半導体装置。     The semiconductor device according to claim 14 or 15,
    An electrode is formed on the end face of the through electrode.
  17. 　請求項１４～１６のいずれか１項に記載の半導体装置において、
    　前記半導体基板の前記反対面には、前記貫通電極の少なくとも前記端面を露出させる凹部が形成されていることを特徴とする半導体装置。     The semiconductor device according to any one of claims 14 to 16,
    A recess is formed on the opposite surface of the semiconductor substrate to expose at least the end face of the through electrode.
  18. 　請求項１７に記載の半導体装置において、
    　前記ダイヤモンドライクカーボン膜は、前記凹部における前記貫通電極の前記端面を除く内面を覆っていることを特徴とする半導体装置。     The semiconductor device according to claim 17,
    The diamond-like carbon film covers an inner surface excluding the end face of the through electrode in the recess.
  19. 　請求項１４～１８のいずれか１項に記載の半導体装置において、
    　前記ダイヤモンドライクカーボン膜は、前記貫通電極から離間して形成されていることを特徴とする半導体装置。     The semiconductor device according to any one of claims 14 to 18,
    The semiconductor device, wherein the diamond-like carbon film is formed away from the through electrode.
  20. 　貫通電極が素子形成面の反対面に露出するように形成されている半導体基板を準備する工程（ａ）と、
    　前記半導体基板の素子形成面の反対面上に、前記貫通電極の少なくとも端面が露出するようにダイヤモンドライクカーボン膜を形成する工程（ｂ）とを備えていることを特徴とする半導体装置の製造方法。     A step (a) of preparing a semiconductor substrate formed so that the through electrode is exposed on the surface opposite to the element formation surface;
    And (b) forming a diamond-like carbon film on the surface opposite to the element formation surface of the semiconductor substrate so that at least the end surface of the through electrode is exposed. .
  21. 　請求項２０に記載の半導体装置の製造方法において、
    　前記工程（ａ）は、前記半導体基板の前記反対面に対して研磨及びエッチングを行うことにより、前記貫通電極を前記半導体基板の前記反対面から突き出させる工程を含むことを特徴とする半導体装置の製造方法。     In the manufacturing method of the semiconductor device according to claim 20,
    The step (a) includes a step of protruding the through electrode from the opposite surface of the semiconductor substrate by polishing and etching the opposite surface of the semiconductor substrate. Production method.
  22. 　請求項２０又は２１に記載の半導体装置の製造方法において、
    　前記工程（ｂ）よりも後に、前記貫通電極の前記端面上に電極を形成する工程をさらに備えていることを特徴とする半導体装置の製造方法。     In the manufacturing method of the semiconductor device according to claim 20 or 21,
    A method of manufacturing a semiconductor device, further comprising a step of forming an electrode on the end face of the through electrode after the step (b).
  23. 　請求項２０～２２のいずれか１項に記載の半導体装置の製造方法において、
    　前記工程（ａ）は、前記貫通電極が前記反対面に露出しないように埋設されている前記半導体基板を準備した後、前記半導体基板の前記反対面に、前記貫通電極の少なくとも前記端面を露出させる凹部を形成する工程を含むことを特徴とする半導体装置の製造方法。     The method for manufacturing a semiconductor device according to any one of claims 20 to 22,
    In the step (a), after preparing the semiconductor substrate embedded so that the through electrode is not exposed on the opposite surface, at least the end surface of the through electrode is exposed on the opposite surface of the semiconductor substrate. The manufacturing method of the semiconductor device characterized by including the process of forming a recessed part.
  24. 　請求項２３に記載の半導体装置の製造方法において、
    　前記工程（ｂ）は、前記ダイヤモンドライクカーボン膜を、前記凹部における前記貫通電極の前記端面を除く内面を覆うように形成する工程を含むことを特徴とする半導体装置の製造方法。     24. The method of manufacturing a semiconductor device according to claim 23.
    The step (b) includes a step of forming the diamond-like carbon film so as to cover an inner surface of the concave portion excluding the end face of the through electrode.
  25. 　請求項２０～２４のいずれか１項に記載の半導体装置の製造方法において、
    　前記工程（ｂ）は、前記ダイヤモンドライクカーボン膜を、前記貫通電極から離間して形成する工程を含むことを特徴とする半導体装置の製造方法。     The method for manufacturing a semiconductor device according to any one of claims 20 to 24,
    The step (b) includes a step of forming the diamond-like carbon film at a distance from the through electrode.
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