TW201620017A - 碳化矽半導體元件以及其製造方法 - Google Patents

碳化矽半導體元件以及其製造方法 Download PDF

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TW201620017A
TW201620017A TW103140001A TW103140001A TW201620017A TW 201620017 A TW201620017 A TW 201620017A TW 103140001 A TW103140001 A TW 103140001A TW 103140001 A TW103140001 A TW 103140001A TW 201620017 A TW201620017 A TW 201620017A
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layer
semiconductor device
semiconductor layer
doped region
carbide semiconductor
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TW103140001A
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TWI562207B (zh
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Cheng-Tyng Yen
Chien-Chung Hung
Yao-Feng Huang
Hsiang-Ting Hung
Chwan-Ying Lee
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Hestia Power Inc
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Priority to US14/612,782 priority patent/US9373713B2/en
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Abstract

一種碳化矽半導體元件以及其製造方法，藉由設置一通道控制區域，並令該通道控制區域具有一從一第一摻雜邊界開始遞增，並於該第一摻雜邊界與一第二摻雜邊界之間達到一最大值，而後朝該第二摻雜邊界遞減的雜質濃度分布，使得該碳化矽半導體元件，能夠在不犧牲臨界電壓的情況下，降低導通電阻，提升其汲極電流。

Description

碳化矽半導體元件以及其製造方法
本發明為有關一種半導體元件，尤指一種碳化矽半導體元件以及其製造方法。
半導體功率元件在特性上，要求在設計的耐壓 (blocking voltage)，應具備盡量小的導通電阻、低反向漏電流、以及較快的開關速度，以減少操作時的導通損耗(conduction loss)及切換損耗(switching loss)。而碳化矽(silicon carbide，SiC)由於具有寬能隙 (其中4H-SiC的 Eg 可達3.26eV)、高臨界崩潰電場強度(2.2MV/cm)及高熱導係數(4.9W/cm-K)等特性，被認為是功率開關元件的極佳材料。碳化矽也是唯一可藉由熱氧化形成氧化層的化合物半導體，因此可以適合用來製作MOSFET(metal oxide semiconductor field effect transistor)與IGBT(insulated gate bipolar transistor)等MOS控制開關元件(MOS controlled switches)。
不過當以熱氧化方式形成閘極氧化層時，未完全反應的碳殘留在閘極氧化層與碳化矽之間的介面，會形成Si空缺(silicon vacancy)、碳簇(carbon cluster) 或間隙碳(carbon interstitial) 等缺陷，而在能隙內的不同位置形成能態，最終成為受體陷阱 (acceptor traps) 或施體陷阱 (donor traps)。一般功率半導體用途的SiC MOSFET以n型通道MOSFET為主，當p型井反轉形成通道時，靠近導帶的受體陷阱一方面會補捉電子，減少了能夠用來傳導電流的電子密度，一方面填入了電子的受體陷阱又會形成負電荷，對電子的傳導造成嚴重的庫侖散射，而造成非常低的通道遷移率，大幅增加SiC MOSFET的導通電阻。改善通道遷移率以降低導通電阻的方式包括以nitric oxide (NO) 、nitrous oxide (N2 O)或POCl3 等氣體以氧化後退火(post-oxidation annealing)的方式鈍化介面陷阱等(提供非專利參考文獻如下：
[1] S. Salemi, N. Goldsman, D. P. Eittsserry, A. Akturk, A. Lelis, J. Appl. Phys. 113, 053703, 2013.
[2] H. Li, S. Dimitrijev, H. B. Harrison, D. Sweatman, Appl. Phys. Lett. 70 (15), 2028, 1997.
[3] D. Okamoto, H. Yano, T. Hatayama, T. Fuyuki, Mater. Sci. Forum, 645, 495, 2010.
[4] Y. K. Sharma, A. C. Ahyi, T. Issacs-Smith, X. Shen, S. T. Pantelides, X. Zhu, L. C. Feldman, J. Rozen, J. R. Williams, Solid-State Electronics, 68, 103, 2012.)。
然而，目前已知的各種改善降低導通電阻的方法，最常見的妥協(trade off)，就是同時也使得MOS元件的臨界電壓(threshold voltage)降低，使得元件在操作時有較高的誤開風險。
本發明的主要目的，在於降低導通電阻的同時，仍然可維持一定的臨界電壓，以避免元件在操作時產生誤開的風險。
為達上述目的，本發明提供一種碳化矽半導體元件，包含有一第一半導體層、一第二半導體層、一絕緣層、一閘電極、一第一摻雜區域、一第二摻雜區域、一第三摻雜區域。該第一半導體層具有一第一導電性；該第二半導體層設置於該第一半導體層上；該絕緣層設置於該第二半導體層上；該閘電極設置於該絕緣層上；該第一摻雜區域具有一相對該第一導電性的第二導電性，位於該第一半導體層內並沿著該第二半導體層，該第一摻雜區域具有一第一摻雜邊界；該第二摻雜區域具有一第一導電性，位於該第一摻雜區域內並沿著該第二半導體層，該第二摻雜區域具有一第二摻雜邊界；該第三摻雜區域具有一第二導電性，位於該第一半導體層內並沿著該第二半導體層，且該第三摻雜區域與該第二摻雜區域相鄰並與該第一摻雜區域部分重疊。
其中，該第一摻雜區域包含一通道控制區域，該通道控制區域沿著該第二半導體層並介於該第一摻雜邊界與該第二摻雜邊界之間。
其中，該通道控制區域具有一從該第一摻雜邊界開始遞增，並於該第一摻雜邊界與該第二摻雜邊界之間達到一最大值，而後朝該第二摻雜邊界遞減的雜質濃度分布。
為達上述目的，本發明還提供一種製造碳化矽半導體元件的方法，包含以下步驟：
步驟1：提供一具有一第一導電性的第一半導體層；
步驟2：提供一位於該第一半導體層上的第一遮罩；
步驟3：透過該第一遮罩利用一第一離子佈植於該第一半導體層形成一具有一第二導電性的第一摻雜區域，該第一摻雜區域具有一第一摻雜邊界；
步驟4：透過該第一遮罩利用一第二離子佈植於該第一摻雜區域形成一具有一第一導電性的第二摻雜區域，該第二摻雜區域具有一第二摻雜邊界；
步驟5：透過一第二遮罩利用一第三離子佈植於該第一半導體層形成一具有一第二導電性的第三摻雜區域；
步驟6：於該第一半導體層上形成一第二半導體層；
步驟7：於該第二半導體層上形成一絕緣層；
步驟8：於該絕緣層上形成一閘電極層；
其中，該第一離子佈植的一射入方向與該第一半導體的一法線之間形成一夾角，而形成一沿著該第二半導體層並介於該第一摻雜邊界與該第二摻雜邊界之間的通道控制區域，該通道控制區域具有一從該第一摻雜邊界開始遞增，並於該第一摻雜邊界與該第二摻雜邊界之間達到一最大值，而後朝該第二摻雜邊界遞減的雜質濃度分布。
如此一來，本發明藉由設置該通道控制區域具有從該第一摻雜邊界開始遞增，並於該第一摻雜邊界與該第二摻雜邊界之間達到該最大值，而後朝該第二摻雜邊界遞減的該雜質濃度分布，令該碳化矽半導體元件，不僅能改善其導通電阻，提升其汲極電流，且同時能夠不犧牲臨界電壓，避免元件在操作時產生誤開的風險。
有關本發明的詳細說明及技術內容，現就配合圖式說明如下：
請參閱『圖1』所示，為本發明第一實施例的結構示意圖，如圖所示，本發明為一種碳化矽半導體元件，包含有一第一半導體層10、一第二半導體層20、一絕緣層30、一閘電極40a、一第一摻雜區域11、一第二摻雜區域12、一第三摻雜區域13。該第一半導體層10具有一第一導電性，其材質可為碳化矽，該第一導電性例如可為n型。該第二半導體層20設置於該第一半導體層10上，其材質可為碳化矽，具有一介於0.01μm至0.5μm的厚度以及一介於1×1015 cm-3 至1×1018 cm-3 之間的雜質濃度。該絕緣層30設置於該第二半導體層20上，其材質可為二氧化矽、氮氧化矽、氮化矽、氧化鋁及氮化鋁…等。該閘電極40a設置於該絕緣層30上，其材質可為一高摻雜的n型多晶矽或一高摻雜的p型多晶矽。
該第一摻雜區域11具有一相對該第一導電性的第二導電性，例如為p型，該第一摻雜區域11位於該第一半導體層10內並沿著該第二半導體層20分佈，該第一摻雜區域11具有一介於1×1017 cm-3 至5×1018 cm-3 之間的雜質濃度，並具有一形成於該第一半導體層10內的第一摻雜邊界111。該第二摻雜區域12具有一第一導電性，例如為n型，位於該第一摻雜區域11內並沿著該第二半導體層20分佈，該第二摻雜區域12具有一介於5×1018 cm-3 至1×1020 cm-3 之間的雜質濃度，並具有一形成於該第一摻雜區域11內的第二摻雜邊界121。而該第三摻雜區域13具有一第二導電性，例如為p型，位於該第一半導體層10內並沿著該第二半導體層20分佈，且該第三摻雜區域13與該第二摻雜區域12相鄰並與該第一摻雜區域11部分重疊，該第三摻雜區域13具有一介於1×1018 cm-3 至5×1019 cm-3 之間的雜質濃度。
在本發明中，該第一摻雜區域11還包含一通道控制區域112，該通道控制區域112沿著該第二半導體層20並介於該第一摻雜邊界111與該第二摻雜邊界121之間，並且，該通道控制區域112具有一雜質濃度分布，該雜質濃度分布從該第一摻雜邊界111開始遞增，並於該第一摻雜邊界111與該第二摻雜邊界121之間達到一最大值X，而後朝該第二摻雜邊界121遞減，如『圖2』所示，為本發明第一實施例通道控制區域的雜質濃度分布示意圖，其中，橫軸的起點為該第一摻雜邊界111，橫軸的終點為該第二摻雜邊界121，縱軸則為雜質濃度NA(cm-3 )，於該第一摻雜邊界111與該第二摻雜邊界121之間，該雜質濃度分布具有該最大值X。在本發明中，該雜質濃度分布係指該第一摻雜區域11內之一平行於表面，且靠近該表面之平面區域(即『圖2』所指之該通道控制區域112)上，該雜質濃度自該第一摻雜邊界111至該第二摻雜邊界121之間的分布。
另外，在第一實施例中，該第二半導體層20的該雜質濃度於一厚度方向，還可形成一梯度分布，該梯度分布可具有一峰值Y，該峰值Y的位置靠近該第一半導體層10，如『圖3』所示，為本發明第一實施例第二半導體層20雜質濃度的梯度分佈示意圖，橫軸的起點為該第二半導體層20靠近該第一半導體層10的一下表面位置，橫軸的終點為該第二半導體層20靠近該絕緣層30的一上表面位置，縱軸則為雜質濃度ND(cm-3 )，該峰值Y靠近該第一半導體層10的該下表面位置。
請參閱『圖4』所示，為本發明第二實施例的結構示意圖，在第二實施例中，相較於第一實施例，其特徵在於該第二半導體層20還可包含複數個磊晶層21，該磊晶層21例如可包含一第一通道層211以及一第二通道層212，該第一通道層211設置於一第一半導體上，具有該第一導電性以及一第一雜質濃度，該第二通道層212設置於該第一通道層211上並具有一第二雜質濃度，該第一雜質濃度高於該第二雜質濃度，且該第二通道層212可具有該第一導電性或是該第二導電性而不限制。
再者，要說明的是，在本發明中，該碳化矽半導體元件，利用該第一半導體層10、該第二半導體層20、該絕緣層30、該閘電極40a、該第一摻雜區域11、該第二摻雜區域12以及該第三摻雜區域13之間的結構配置，則可進一步製作成一金屬-氧化物-半導體場效電晶體(MOSFET)或是一絕緣柵雙極型電晶體(IGBT)，請參閱『圖5』所示，為本發明製作成MOSFET該通道控制區域112使用不同條件的ID-VG模擬比較示意圖，由圖中可知，本發明的該通道控制區域112，於條件2轉換成條件1的過程中，經由調整該雜質濃度分布的設置，使得利用本發明所製作而成的MOSFET，可在提高汲極電流(ID)的同時提高臨界電壓(VG)，避免元件在操作時產生誤開的風險。
請參閱『圖6A』至『圖6I』所示，為本發明一實施例的製造流程示意圖，本發明還揭示一種製造碳化矽半導體元件的方法，包含以下步驟：
步驟1：如『圖6A』，提供具有該第一導電性的該第一半導體層10。
步驟2：提供一位於該第一半導體層10上的第一遮罩50，在此進一步說明如下，首先，如『圖6B』，可先提供一第一遮罩層51於該第一半導體層10上，接著再對該第一遮罩層51施以一微影製程形成複數個第一鏤空55，而於該第一半導體層10上形成該第一遮罩50，該第一遮罩50可具有如『圖7A』的斜側壁53a或『圖7B』的斜側壁53b，此處僅為舉例說明，本發明的該第一遮罩50尚可採用如『圖6B』之垂直側壁。該斜側壁53a與該斜側壁53b與該第一半導體層10的一法線N之間各形成一銳角a，該銳角a為介於2度至45度之間，其中該斜側壁53a具有一為正的斜率，該斜側壁53b具有一為負的斜率。又或者是如『圖7C』，於提供該第一遮罩層51後直接再提供一第二遮罩層52於該第一遮罩層51上，之後再對該第一遮罩層51與該第二遮罩層52施以該微影製程形成該第一鏤空55而形成該第一遮罩50，如此，即可於該第一遮罩50上選擇形成如『圖7C』的一階狀側壁54；該階狀側壁54令該第一遮罩50具有一下層部(第一遮罩層51)以及一寬於該下層部的上層部(第二遮罩層52)。
步驟3：如『圖6C』所示，透過該第一遮罩50利用一第一離子佈植於該第一半導體層10形成具有該第二導電性的該第一摻雜區域11，該第一摻雜區域11具有一第一摻雜邊界111；在本實施例中，該第一離子佈植所使用之摻質例如可為鋁(Aluminum)或硼(Boron)，該第一離子佈植的一射入方向與該第一半導體層10的該法線N形成一夾角θ，該夾角θ介於2度至45度之間，而透過該第一遮罩50植入該第一半導體層10。『圖6C』的該第一摻雜區域11僅為舉例示意，實際進行離子佈植時，係固定該第一離子佈植的該射入方向，並讓該第一半導體層10相對該射入方向旋轉，以形成該第一摻雜區域11。
步驟4：如『圖6D』所示，透過該第一遮罩50利用一第二離子佈植於該第一摻雜區域11形成具有該第一導電性的該第二摻雜區域12，該第二摻雜區域12具有一第二摻雜邊界121，在此實施例中，該第二離子佈植所使用之摻質可為磷(Phosphorus)或氮(Nitrogen)，該第二離子佈植的一射入方向與該第一半導體層10的該法線N呈平行，透過該第一遮罩50植入該第一摻雜區域11。
步驟5：如『圖6E』所示，透過一第二遮罩60利用一第三離子佈植於該第一半導體層10形成具有該第二導電性的該第三摻雜區域13；該第二遮罩60具有一第二鏤空61，該第三離子佈植所使用之摻質可為鋁(Aluminum)或硼(Boron)，透過該第二遮罩60植入該第一半導體層10形成該第三摻雜區域13，該第三摻雜區域13與該第二摻雜區域12相鄰並與該第一摻雜區域11部分重疊。
步驟6：如『圖6F』所示，於該第一半導體層10上形成該第二半導體層20，該第二半導體層20為利用一磊晶製程於大於1500°C之溫度下形成。
步驟7：如『圖6G』所示，於該第二半導體層20上形成該絕緣層30，該絕緣層30可為使用加熱反應或沉積方式，例如熱氧化、化學氣相沉積(chemical vapor deposition)或原子層沉積(atomic layer deposition，ALD) 形成的二氧化矽、氮氧化矽、氮化矽、氧化鋁及氮化鋁層，並選擇使用在含有氧化亞氮、一氧化氮、氮、氬、氨、氫、水、磷化氫或三氯氧磷的氣體環境下進行之氧化或沉積後之退火製程，而形成該絕緣層30。
步驟8：如『圖6G』所示，於該絕緣層30上形成一閘電極層40b；該閘電極層40b為先沉積一閘電極材料，例如為高摻雜濃度的n型多晶矽或高摻雜濃度的p型多晶矽，並對該閘電極材料施以一微影製程，再使該閘電極材料部分氧化而形成。
在本實施例中，要說明的是，由於該第一離子佈植的該射入方向與該第一半導體的該法線N之間形成該夾角θ，使得該第一離子於植入該第一半導體層10後，得以形成一沿著該第二半導體層20並介於該第一摻雜邊界111與該第二摻雜邊界121之間的通道控制區域112，令該通道控制區域112具有從該第一摻雜邊界111開始遞增，並於該第一摻雜邊界111與該第二摻雜邊界121之間達到該最大值X，而後朝該第二摻雜邊界121遞減的該雜質濃度分布，藉由最佳化該第二半導體層20之厚度與濃度梯度分布與該第一離子佈植之植入能量與劑量，可得到一最佳化之該通道控制區域112之該雜質濃度分布，而達到如『圖5』之所示在降低導通電阻的同時提高臨界電壓之效果。
並且，在本實施例中，製造碳化矽半導體元件的方法還可包含：
步驟9：提供一鈍化層70覆蓋該絕緣層30與該閘電極層40b，該鈍化層70材料可為四乙基矽氧烷、硼磷矽玻璃、磷矽玻璃、氮氧化矽、氮化矽及富矽氮等，作為金屬前介電層(PMD，Pre-Metal Dielectric)。
步驟10：形成一穿過該鈍化層70、該絕緣層30與該第二半導體層20的接觸窗80，用以形成具有良好歐姆接觸(Ohmic contact)特性之源極接觸(Source Contact)。
綜上所述，由於本發明藉由設置該通道控制區域具有從該第一摻雜邊界開始遞增，並於該第一摻雜邊界與該第二摻雜邊界之間達到該最大值，而後朝該第二摻雜邊界遞減的該雜質濃度分布，令該碳化矽半導體元件，不僅能改善其導通電阻，提升其汲極電流，且同時能夠不犧牲臨界電壓，避免元件在操作時產生誤開的風險，因此本發明極具進步性及符合申請發明專利的要件，爰依法提出申請，祈  鈞局早日賜准專利，實感德便。
以上已將本發明做一詳細說明，惟以上所述者，僅爲本發明的一較佳實施例而已，當不能限定本發明實施的範圍。即凡依本發明申請範圍所作的均等變化與修飾等，皆應仍屬本發明的專利涵蓋範圍內。
10‧‧‧第一半導體層
11‧‧‧第一摻雜區域
111‧‧‧第一摻雜邊界
112‧‧‧通道控制區域
12‧‧‧第二摻雜區域
121‧‧‧第二摻雜邊界
13‧‧‧第三摻雜區域
20‧‧‧第二半導體層
21‧‧‧磊晶層
211‧‧‧第一通道層
212‧‧‧第二通道層
30‧‧‧絕緣層
40a‧‧‧閘電極
40b‧‧‧閘電極層
50‧‧‧第一遮罩
51‧‧‧第一遮罩層
52‧‧‧第二遮罩層
53‧‧‧斜側壁
54‧‧‧階狀側壁
55‧‧‧第一鏤空
60‧‧‧第二遮罩
61‧‧‧第二鏤空
70‧‧‧鈍化層
80‧‧‧接觸窗
θ‧‧‧夾角
a‧‧‧銳角
N‧‧‧法線
X‧‧‧最大值
Y‧‧‧峰值
圖1，為本發明第一實施例的結構示意圖。 圖2，為本發明第一實施例通道控制區域的雜質濃度分布示意圖。 圖3，為本發明第一實施例第二半導體層雜質濃度的梯度分佈示意圖。 圖4，為本發明第二實施例的結構示意圖。 圖5，為本發明製作成MOSFET之通道控制區域使用不同條件的ID-VG模擬比較示意圖。 圖6A至圖6I，為本發明一實施例的製造流程示意圖。 圖7A至圖7C，分別為本發明一實施例的斜側壁與階狀側壁示意圖。
10‧‧‧第一半導體層
11‧‧‧第一摻雜區域
111‧‧‧第一摻雜邊界
112‧‧‧通道控制區域
12‧‧‧第二摻雜區域
121‧‧‧第二摻雜邊界
13‧‧‧第三摻雜區域
20‧‧‧第二半導體層
30‧‧‧絕緣層
40a‧‧‧閘電極

Claims (30)

  1. 一種碳化矽半導體元件，包含有： 一具有一第一導電性的第一半導體層； 一設置於該第一半導體層上的第二半導體層； 一設置於該第二半導體層上的絕緣層； 一設置於該絕緣層上的閘電極； 一具有一相對該第一導電性的第二導電性的第一摻雜區域，該第一摻雜區域位於該第一半導體層內並沿著該第二半導體層，該第一摻雜區域具有一第一摻雜邊界； 一具有一第一導電性的第二摻雜區域，該第二摻雜區域位於該第一摻雜區域內並沿著該第二半導體層，該第二摻雜區域具有一第二摻雜邊界； 一具有一第二導電性的第三摻雜區域，該第三摻雜區域位於該第一半導體層內並沿著該第二半導體層，且該第三摻雜區域與該第二摻雜區域相鄰並與該第一摻雜區域部分重疊； 其中，該第一摻雜區域包含一通道控制區域，該通道控制區域沿著該第二半導體層並介於該第一摻雜邊界與該第二摻雜邊界之間； 其中，該通道控制區域具有一從該第一摻雜邊界開始遞增，並於該第一摻雜邊界與該第二摻雜邊界之間達到一最大值，而後朝該第二摻雜邊界遞減的雜質濃度分布。
  2. 如申請專利範圍第1項所述的碳化矽半導體元件，其中該通道控制區域從該第一摻雜邊界沿著該第二半導體層至該第二摻雜邊界，具有一介於0.1μm至1μm之間的長度。
  3. 如申請專利範圍第1項所述的碳化矽半導體元件，其中該通道控制區域的該雜質濃度分布介於1×1017 cm-3 至1×1019 cm-3 之間。
  4. 如申請專利範圍第1項所述的碳化矽半導體元件，其中該第二半導體層具有一介於0.01μm至0.5μm的厚度。
  5. 如申請專利範圍第1項所述的碳化矽半導體元件，其中該第二半導體層具有一介於1×1015 cm-3 至1×1018 cm-3 之間的雜質濃度。
  6. 如申請專利範圍第5項所述的碳化矽半導體元件，其中該第二半導體層的該雜質濃度於一厚度方向形成一梯度分布。
  7. 如申請專利範圍第6項所述的碳化矽半導體元件，其中該梯度分布具有一峰值，該峰值的位置靠近該第一半導體層。
  8. 如申請專利範圍第1項所述的碳化矽半導體元件，其中該第二半導體層包含複數個磊晶層。
  9. 如申請專利範圍第8項所述的碳化矽半導體元件，其中該磊晶層包含一具有該第一導電性與一第一雜質濃度而設置於該第一半導體上的第一通道層以及一具有一第二雜質濃度而設置於該第一通道層上的第二通道層。
  10. 如申請專利範圍第9項所述的碳化矽半導體元件，其中該第一雜質濃度高於該第二雜質濃度。
  11. 如申請專利範圍第9項所述的碳化矽半導體元件，其中該第二通道層具有該第一導電性。
  12. 如申請專利範圍第9項所述的碳化矽半導體元件，其中該第二通道層具有該第二導電性。
  13. 如申請專利範圍第1項所述的碳化矽半導體元件，為配置成一金屬-氧化物-半導體場效電晶體(MOSFET)。
  14. 如申請專利範圍第1項所述的碳化矽半導體元件，為配置成一絕緣柵雙極性電晶體(IGBT)。
  15. 如申請專利範圍第1項所述的碳化矽半導體元件，其中該碳化矽半導體元件具有一大於1V的臨界電壓。
  16. 一種製造碳化矽半導體元件的方法，包含以下步驟： 步驟1：提供一具有一第一導電性的第一半導體層； 步驟2：提供一位於該第一半導體層上的第一遮罩； 步驟3：透過該第一遮罩利用一第一離子佈植於該第一半導體層形成一具有一第二導電性的第一摻雜區域，該第一摻雜區域具有一第一摻雜邊界； 步驟4：透過該第一遮罩利用一第二離子佈植於該第一摻雜區域形成一具有一第一導電性的第二摻雜區域，該第二摻雜區域具有一第二摻雜邊界； 步驟5：透過一第二遮罩利用一第三離子佈植於該第一半導體層形成一具有一第二導電性的第三摻雜區域； 步驟6：於該第一半導體層上形成一第二半導體層； 步驟7：於該第二半導體層上形成一絕緣層； 步驟8：於該絕緣層上形成一閘電極層； 其中，該第一離子佈植的一射入方向與該第一半導體層的一法線之間形成一夾角，而形成一沿著該第二半導體層並介於該第一摻雜邊界與該第二摻雜邊界之間的通道控制區域，該通道控制區域具有一從該第一摻雜邊界開始遞增，並於該第一摻雜邊界與該第二摻雜邊界之間達到一最大值，而後朝該第二摻雜邊界遞減的雜質濃度分布。
  17. 如申請專利範圍第16項所述的製造碳化矽半導體元件的方法，其中於步驟2中還包含： 步驟2A：提供一第一遮罩層於該第一半導體層上； 步驟2B：對該第一遮罩層施以一微影製程而於該第一半導體層上形成該第一遮罩。
  18. 如申請專利範圍第17項所述的製造碳化矽半導體元件的方法，其中於步驟2B中還包含： 步驟2a：提供一第二遮罩層於該第一遮罩層上； 步驟2b：對該第一遮罩層與該第二遮罩層施以該微影製程形成該第一遮罩。
  19. 如申請專利範圍第16項所述的製造碳化矽半導體元件的方法，其中該夾角介於2度至45度之間。
  20. 如申請專利範圍第16項所述的製造碳化矽半導體元件的方法，其中該第一遮罩於該第一半導體層上包含一斜側壁。
  21. 如申請專利範圍第20項所述的製造碳化矽半導體元件的方法，其中該斜側壁與該第一半導體層的該法線之間形成一介於2度至45度之間的銳角。
  22. 如申請專利範圍第20項所述的製造碳化矽半導體元件的方法，其中該斜側壁具有一為負的斜率。
  23. 如申請專利範圍第16項所述的製造碳化矽半導體元件的方法，其中該第一遮罩於該第一半導體層上包含一階狀側壁，令該第一遮罩具有一下層部以及一寬於該下層部的上層部。
  24. 如申請專利範圍第16項所述的製造碳化矽半導體元件的方法，其中於步驟6中利用一磊晶製程於大於1500°C之溫度下形成該第二半導體層。
  25. 如申請專利範圍第16項所述的製造碳化矽半導體元件的方法，其中該絕緣層的材料為選自二氧化矽、氮氧化矽、氮化矽、氧化鋁及氮化鋁所組成的群組。
  26. 如申請專利範圍第16項所述的製造碳化矽半導體元件的方法，其中於步驟7中更包含一於選自氧化亞氮、一氧化氮、氮、氬、氨、氫、水、磷化氫及三氯氧磷所組成的群組的氣體環境下進行之退火製程，而形成該絕緣層。
  27. 如申請專利範圍第16項所述的製造碳化矽半導體元件的方法，其中於步驟8中還包含： 步驟8A：沉積一閘電極材料； 步驟8B：對該閘電極材料施以一微影製程； 步驟8C：使該閘電極材料部分氧化。
  28. 如申請專利範圍第27項所述的製造碳化矽半導體元件的方法，其中該閘電極材料包含一高摻雜的n型多晶矽或一高摻雜的p型多晶矽。
  29. 如申請專利範圍第16項所述的製造碳化矽半導體元件的方法，其中更包含： 步驟9：提供一鈍化層覆蓋該絕緣層與該閘電極層； 步驟10：形成一穿過該鈍化層、該絕緣層與該第二半導體層的接觸窗。
  30. 如申請專利範圍第29項所述的製造碳化矽半導體元件的方法，其中該鈍化層材料為選自四乙基矽氧烷、硼磷矽玻璃、磷矽玻璃、氮氧化矽、氮化矽及富矽氮所組成的群組。
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