TW201603278A - 具有環繞式閘極電晶體的半導體元件及其製造方法 - Google Patents

具有環繞式閘極電晶體的半導體元件及其製造方法 Download PDF

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TW201603278A
TW201603278A TW104103357A TW104103357A TW201603278A TW 201603278 A TW201603278 A TW 201603278A TW 104103357 A TW104103357 A TW 104103357A TW 104103357 A TW104103357 A TW 104103357A TW 201603278 A TW201603278 A TW 201603278A
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layer pattern
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sacrificial layer
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TWI634667B (zh
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裵東一
徐康一
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三星電子股份有限公司
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Abstract

本發明提供一種半導體元件，其包含安置於基板上之鰭片結構、安置於鰭片結構上之犧牲層圖案、安置於犧牲層圖案上之主動層圖案以及延伸穿過犧牲層圖案且包圍主動層圖案之一部分的閘極介電層及閘電極層。

Description

具有環繞式閘極電晶體的半導體元件及其製造方法
本申請案主張2014年7月14日在USPTO申請之美國非臨時申請案第14/330,305號之優先權，其揭露內容以全文引用的方式併入本文中。
本發明概念之例示性實施例是關於具有環繞式閘極電晶體的半導體元件且關於製造具有環繞式閘極電晶體的半導體元件之方法。
最近，已開發出能夠高速操作以及高度整合之半導體元件。然而，諸如短通道效應、窄寬度效應、通道長度調變等特性可對這些高度整合之半導體元件之效能有負面影響。
本發明概念之例示性實施例提供具有環繞式閘極電晶 體的半導體元件以及製造具有環繞式閘極電晶體的半導體元件之方法。
在一例示性實施例中，半導體元件包含安置於基板上之鰭片結構、安置於鰭片結構上之犧牲層圖案、安置於犧牲層圖案上之主動層圖案以及延伸穿過犧牲層圖案且包圍主動層圖案之一部分的閘極介電層及閘電極層。
在一例示性實施例中，半導體元件更包含安置於閘電極層之側壁上之間隙壁以及安置於主動層圖案上之源極/汲極結構。 藉由間隙壁將源極/汲極結構與閘電極層分隔，且犧牲層圖案安置在源極/汲極結構下且不安置在閘電極層下。
在一例示性實施例中，源極/汲極結構覆蓋主動層圖案之上表面及側壁。
在一例示性實施例中，犧牲層圖案包含半導體材料。
在一例示性實施例中，半導體材料包含矽鍺(silicon germanium，SiGe)。
在一例示性實施例中，犧牲層圖案包含絕緣材料。
在一例示性實施例中，絕緣層包含氧化矽。
在一例示性實施例中，閘電極層包含金屬材料。
在一例示性實施例中，基板包含第一區域以及第二區域，鰭片結構包含安置於第一區域中之第一鰭片結構以及安置於第二區域中之第二鰭片結構，犧牲層圖案包含安置於第一鰭片結構上之第一犧牲層圖案以及安置於第二鰭片結構上之第二犧牲層圖案，主動層圖案包含安置於第一犧牲層圖案上之第一主動層圖案以及安置於第二犧牲層圖案上之第二主動層圖案，閘極介電層 包含第一閘極介電層以及第二閘極介電層，閘電極層包含第一閘電極層以及第二閘電極層，第一閘極介電層以及第一閘電極層延伸穿過第一犧牲層圖案且包圍第一主動層圖案的一部分，且第二閘極介電層以及第二閘電極層延伸穿過第二犧牲層圖案且包圍第二主動層圖案的一部分。
在一例示性實施例中，第一犧牲層圖案包含與第二犧牲層圖案不同之材料。
在一例示性實施例中，第一犧牲層圖案包含半導體材料且第二犧牲層圖案包含絕緣材料。
在一例示性實施例中，半導體材料包含矽鍺(SiGe)且絕緣材料包含氧化矽。
在一例示性實施例中，半導體元件包含具有第一鰭片結構、第一主動層圖案、第一閘極介電層以及第一閘電極層之第一環繞式閘極電晶體及具有第二鰭片結構、第二主動層圖案、第二閘極介電層以及第二閘電極層之第二環繞式閘極電晶體。第一環繞式閘極電晶體可包含PMOS電晶體且第二環繞式閘極電晶體可包含NMOS電晶體。
在一例示性實施例中，第一犧牲層圖案具有第一鍺濃度且第二犧牲層圖案具有第二鍺濃度。第一鍺濃度可低於第二鍺濃度。
在一例示性實施例中，半導體元件包含基板，所述基板包含第一區域以及第二區域；安置於第一區域中之第一環繞式閘極電晶體，第一環繞式閘極電晶體包含第一鰭片結構；安置於第一鰭片結構上之第一犧牲層圖案；安置於第一犧牲層圖案上之第 一主動層圖案以及延伸穿過第一犧牲層圖案且包圍第一主動層圖案之一部分的第一閘電極層；以及安置於第二區域中之第二環繞式閘極電晶體，第二環繞式閘極電晶體包含第二鰭片結構；安置於第二鰭片結構上之第二犧牲層圖案；安置於第二犧牲層圖案上之第二主動層圖案以及延伸穿過第二犧牲層圖案且包圍第二主動層圖案之第一部分的第二閘電極層。第一閘電極層可完全包圍第一主動層圖案之一部分且第二閘電極層可部分包圍第二主動層圖案之第一部分。
在一例示性實施例中，半導體元件包含安置在第二主動層圖案之第二部分下的絕緣層且第二主動層圖案之第二部分不與第二閘電極層重疊。
在一例示性實施例中，絕緣層包含氧化矽層。
在一例示性實施例中，第一犧牲層圖案以及第二犧牲層圖案包含半導體材料。
在一例示性實施例中，半導體材料包含矽鍺(SiGe)
在一例示性實施例中，第一區域對應於邏輯區域且第二區域對應於SRAM區域。
在一例示性實施例中，製造半導體元件之方法包含在基板上形成鰭片結構；在鰭片結構上形成犧牲層圖案，犧牲層圖案包含第一區域以及第二區域；在犧牲層圖案上形成主動層圖案，主動層圖案包含在犧牲層圖案之第一區域上形成之第一區域以及在犧牲層圖案之第二區域上形成之第二區域；形成橫越主動層圖案之第一區域之虛設閘極圖案；在虛設閘極圖案以及主動層圖案之第二部分上形成層間介電層；使層間介電層平坦化以暴露虛設 閘極圖案；移除虛設閘極圖案以暴露主動層圖案之第一區域以及犧牲層圖案之第一區域；移除犧牲層圖案之第一區域；在主動層圖案之第一區域上形成閘極介電層，閘極介電層包圍主動層圖案之第一區域；以及在閘極介電層上形成閘電極層，閘電極層包圍主動層圖案之第一區域。
在一例示性實施例中，使用磊晶生長製程形成犧牲層圖案以及主動層圖案。
在一例示性實施例中，方法更包含使用磊晶生長製程在主動層圖案之第二區域上形成源極/汲極結構。
在一例示性實施例中，可使用選擇性蝕刻製程進行移除犧牲層圖案之第一區域之方法。
在一例示性實施例中，選擇性蝕刻製程包含濕式蝕刻製程。
1‧‧‧半導體元件
2‧‧‧半導體元件
3‧‧‧半導體元件
4‧‧‧半導體元件
5‧‧‧半導體元件
6‧‧‧半導體元件
13‧‧‧半導體元件
14‧‧‧半導體元件
100‧‧‧基板
105‧‧‧絕緣體
110‧‧‧元件隔離結構
120‧‧‧第一犧牲層圖案
121‧‧‧第一區域
122‧‧‧第二區域
125‧‧‧第二犧牲層圖案
128‧‧‧通孔
130‧‧‧主動層圖案
131‧‧‧第一區域
132‧‧‧第二區域
140‧‧‧p型源極/汲極結構
145‧‧‧n型源極/汲極結構
150‧‧‧閘極介電層
152‧‧‧虛設閘極層
154‧‧‧層間介電層
160‧‧‧第一閘電極層
162‧‧‧第二閘電極層
165‧‧‧間隙壁
170‧‧‧絕緣層
210‧‧‧第一主動區域
220‧‧‧第二主動區域
230‧‧‧第三主動區域
240‧‧‧第四主動區域
250‧‧‧接觸孔
251‧‧‧第一閘電極
252‧‧‧第二閘電極
253‧‧‧第三閘電極
254‧‧‧第四閘電極
261‧‧‧第一共用接點
262‧‧‧第二共用接點
271‧‧‧第一互連線
272‧‧‧第二互連線
410‧‧‧邏輯區域
411‧‧‧第一電晶體
412‧‧‧第三電晶體
420‧‧‧靜態隨機存取記憶體(SRAM)區域
421‧‧‧第二電晶體
422‧‧‧第四電晶體
1000‧‧‧系統晶片
1001‧‧‧應用程式處理器
1010‧‧‧中央處理單元
1020‧‧‧多媒體系統
1030‧‧‧匯流排
1040‧‧‧記憶體系統
1050‧‧‧周邊電路
1060‧‧‧DRAM元件
1100‧‧‧電子系統
1110‧‧‧控制器
1120‧‧‧輸入/輸出元件
1130‧‧‧記憶體元件
1140‧‧‧介面
1150‧‧‧匯流排
1200‧‧‧平板電腦
1300‧‧‧筆記型電腦
1400‧‧‧智慧型電話
BL‧‧‧位元線
BLb‧‧‧位元線桿
F‧‧‧鰭片結構
I‧‧‧第一區域
II‧‧‧第二區域
INV1‧‧‧第一反相器
INV2‧‧‧第二反相器
PD1‧‧‧第一下拉電晶體
PD2‧‧‧第二下拉電晶體
PS1‧‧‧第一傳送電晶體
PS2‧‧‧第二傳送電晶體
PU1‧‧‧第一上拉電晶體
PU2‧‧‧第二上拉電晶體
TR1‧‧‧第一環繞式閘極電晶體
TR2‧‧‧第二環繞式閘極電晶體
TR3‧‧‧第三環繞式閘極電晶體
VCC‧‧‧電源節點
VSS‧‧‧接地節點
WL‧‧‧字線
本發明概念之以上及其他特徵將藉由參考附圖詳細描述其例示性實施例變得更顯而易見，在圖式中：圖1為說明根據本發明概念之例示性實施例之半導體元件的透視圖。
圖2為對應於圖1之線A-A的橫截面圖。
圖3為對應於圖1之線B-B的橫截面圖。
圖4為說明根據本發明概念之例示性實施例之半導體元件的透視圖。
圖5為對應於圖4之線C-C的橫截面圖。
圖6為說明根據本發明概念之例示性實施例之半導體元件的橫截面圖。
圖7為說明根據本發明概念之例示性實施例之半導體元件的透視圖。
圖8為說明根據本發明概念之例示性實施例之半導體元件的透視圖。
圖9為對應於圖8之線D-D的橫截面圖。
圖10為說明根據本發明概念之例示性實施例之半導體元件的電路圖。
圖11為顯示於圖10中之電路圖的等效佈局。
圖12及圖13為說明根據本發明概念之例示性實施例之半導體元件的方塊圖。
圖14為包含根據本發明概念之例示性實施例之半導體元件的系統晶片(system-on-chip，SoC)的系統方塊圖。
圖15為包含根據本發明概念之例示性實施例之半導體元件的電子系統的方塊圖。
圖16至圖18為包含根據本發明概念之例示性實施例之半導體元件的電子產品之實例。
圖19至圖24為說明製造根據本發明概念之例示性實施例之半導體元件的方法的透視圖。
參考附圖在下文中將更全面描述本發明概念之例示性實施例。類似圖式元件符號可指整個附圖中之類似元件。
應理解，當稱元件在另一元件「上」、「連接」或「耦接」至另一元件時，其可直接在另一元件上、連接或耦接至另一元件，或可存在介入元件。
應理解，儘管本文中可使用術語「第一」、「第二」等描述各種元件、組件、區域、層及/或區段，但這些元件、組件、區域、層及/或區段不應受這些術語限制。這些術語僅用以將一個元件、組件、區域、層或區段與另一元件、組件、區域、層或區段區別。因此，可在不脫離實例實施例之教示的情況下將下文論述之第一元件、組件、區域、層或區段稱為第二元件、組件、區域、層或區段。
亦應理解，當稱層或元件在另一層或基板「上」時，其可直接在另一層或基板上，或亦可存在介入層。另外，應理解，當稱層在另一層「下」時，其可直接在層下或亦可存在一個或多於一個介入層。此外，亦應理解，當稱層在兩個層「之間」時，其可為兩個層之間的唯一層，或亦可存在一個或多於一個介入層。
出於易於描述之目的，本文中可使用空間相對術語，例如「在……底下」、「在……下方」、「在……下部」、「在……上方」、「在……上部」等，以描述如圖式中所說明之一個元件或特徵與其他元件或特徵的關係。應理解在使用中，空間相對術語意欲涵蓋元件之不同定向。舉例而言，若將圖式中之元件翻轉，則描述為「在」其他元件或特徵「下方」或「底下」之元件隨後將定向「在」其他元件或特徵「上方」。因此，例示性術語「在……下方」可涵蓋在……上方以及在……下方之定向。元件可以其他方式定向(例如旋轉90度或在其他定向下)且本文中使用之空間相對描述詞相 應地進行解釋。
圖1為說明根據本發明概念之例示性實施例之半導體元件的透視圖。圖2及圖3分別為對應於圖1之線A-A及B-B的橫截面圖。
參看圖1至圖3，半導體元件1可包含第一環繞式閘極電晶體TR1。第一環繞式閘極電晶體TR1可包含基板100、鰭片結構F、犧牲層圖案120、主動層圖案130、源極/汲極結構140、閘極介電層150以及閘電極層160。第一環繞式閘極電晶體TR1可例如為場效電晶體(field effect transistor，FET)。
基板100可例如包含塊體矽基板或矽絕緣體(silicon-on-insulator，SOI)基板。基板100可例如由矽(Si)、鍺(Ge)、矽鍺(SiGe)、銻化銦(InSb)、碲化鉛(PbTe)、砷化銦(InAs)、磷化銦(InP)、砷化鎵(GaAs)及/或銻化鎵(GaSb)形成。
基板100亦可包含磊晶層。磊晶層可例如包含矽(Si)或鍺(Ge)。磊晶層亦可包含化合物半導體，諸如4-4族化合物半導體或3-5族化合物半導體。4-4族化合物半導體可為具有碳(C)、矽(Si)、鍺(Ge)以及錫(Sn)中之至少兩種材料的二元化合物或三元化合物，然而，4-4族化合物半導體不限於此。3-5族化合物半導體可為具有鋁(Al)、鎵(Ga)、銦(In)、磷(P)、砷(As)以及銻(Sb)中之至少兩種材料的二元化合物、三元化合物或四元化合物，然而，3-5族化合物半導體不限於此。
可在基板100上形成鰭片結構F。根據例示性實施例，鰭片結構F可由與基板100相同之材料形成或鰭片結構F可由與基板100不同之材料形成。
鰭片結構F可具有自基板100突出之形狀。根據例示性實施例，鰭片結構F可具有具較大底部寬度之楔形形狀或在頂部及底部具有實質上相同寬度之矩形形狀。在一例示性實施例中，鰭片結構F之頂部邊緣可具有圓形形狀。
可在基板100上形成元件隔離結構110且所述元件隔離結構110可覆蓋鰭片結構F之側壁。元件隔離結構110可由諸如氧化矽層、氮化矽層或氮氧化矽層之絕緣層形成。
可在鰭片結構F上形成犧牲層圖案120。犧牲層圖案120可包含半導體材料，諸如矽鍺(SiGe)。在犧牲層圖案120包含矽鍺(SiGe)之例示性實施例中，鍺(Ge)之比例可高於矽(Si)之比例。因此，可增加犧牲層圖案120與其他具有較低比例鍺(Ge)之層之間的蝕刻選擇性。
可在犧牲層圖案120上形成具有第一部分以及第二部分之主動層圖案130。主動層圖案130可例如包含矽層或可使用磊晶生長製程形成之3-5族化合物半導體。主動層圖案130可由實質上與鰭片結構F相同之材料形成。主動層圖案130之第一部分可用作第一環繞式閘極電晶體TR1之通道區域。
可在主動層圖案130上形成閘極介電層150。閘極介電層150可延伸穿過犧牲層圖案120且可包圍主動層圖案130之第一部分。在一例示性實施例中，如圖2中所示，閘極介電層150完全包圍主動層圖案130之第一部分。如圖1中所示，閘極介電層150之一部分可沿著間隙壁165之側壁向上延伸。間隙壁165可例如包含氧化矽層、氮化矽層或氮氧化矽層。
閘極介電層150可包含高k介電層，諸如氧化鉿層、氧 化鋁層、氧化鋯層或氧化鉭層。
在一例示性實施例中，可在閘極介電層150與主動層圖案130之間形成界面層。界面層可由例如介電常數約小於9之低k介電層形成。舉例而言，界面層可由氧化矽層、氮氧化矽層或其混合物形成。
可在閘極介電層150上形成閘電極層160且所述閘電極層160可橫越主動層圖案130之第一部分。閘電極層160亦可延伸穿過犧牲層圖案120且可包圍主動層圖案130之第一部分。在一例示性實施例中，如圖2中所示，閘電極層160完全包圍主動層圖案130之第一部分。閘電極層160可包含金屬，諸如鎢(W)、鋁(Al)或其混合物。在一例示性實施例中，閘電極層160可更包含功函數金屬層以控制第一環繞式閘極電晶體TR1之功函數。功函數金屬層可例如包含鈦(Ti)、鉭(Ta)、氮化鈦(TiN)或其混合物。
可在主動層圖案130之第二部分上以及在閘電極層160之兩側形成源極/汲極結構140。源極/汲極結構140對應於半導體元件1之源極或汲極。可藉由間隙壁165以及閘極介電層150將源極/汲極結構140與閘電極層160隔離或分隔。間隙壁165例如可具有圓形形狀、I形狀或L形狀。可使用選擇性磊晶生長製程形成源極/汲極結構140。源極/汲極結構140可覆蓋一部分主動層圖案130之側壁且可不在主動層圖案130下形成。因此，源極/汲極結構140之最低表面的高度(level)可高於或等於犧牲層圖案120之最上表面，然而，源極/汲極結構140不限於此。在一例示性實施例中，可在無磊晶層之情況下在主動層圖案130中藉由使用離 子植入製程將雜質注入其中形成源極/汲極結構140。舉例而言，當第一環繞式閘極電晶體TR1為PMOS電晶體時，源極/汲極結構140可包含p型雜質。
可在元件隔離結構110上形成層間介電層154(顯示於圖21中)。層間介電層154可覆蓋犧牲層圖案120及源極/汲極結構140。
根據本發明概念之例示性實施例，可在主動層圖案130上且亦可在主動層圖案130下形成閘電極層160。因此，可提高第一環繞式閘極電晶體TR1之工作電流值且可降低第一環繞式閘極電晶體TR1之漏電流值。因此，可改良半導體元件之可靠性及效能。
圖4為說明根據本發明概念之例示性實施例之半導體元件的透視圖。圖5為對應於圖4之線C-C的橫截面圖。
參看圖4及圖5，包含第二環繞式閘極電晶體TR2之半導體元件2可包含由與第一環繞式閘極電晶體TR1之犧牲層圖案120不同的材料形成的犧牲層圖案125。舉例而言，犧牲層圖案125可由氧化矽層形成。在第二環繞式閘極電晶體TR2為NMOS電晶體之例示性實施例中，第二環繞式閘極電晶體TR2可包含具有n型雜質之源極/汲極結構145。
形成鰭片結構F、主動層圖案130、閘極介電層150、閘電極層160等之製程可與上述製程類似。為方便解釋，可忽略先前所述之製程之描述。
圖6為說明根據本發明概念之例示性實施例之半導體元件的橫截面圖。為方便解釋，可忽略先前所述之元件之描述。
參看圖6，可在絕緣體105上形成半導體元件3之鰭片結構F。舉例而言，可在矽絕緣體(SOI)基板上形成半導體元件3。在此情況下，可藉由使磊晶層生長且將磊晶層圖案化形成鰭片結構F。
圖7為說明根據本發明概念之例示性實施例之半導體元件的透視圖。
參看圖7，半導體元件4可包含具有p型源極/汲極結構140之第一環繞式閘極電晶體TR1及具有n型源極/汲極結構145之第二環繞式閘極電晶體TR2。可在具有第一區域I及第二區域II之基板100上形成半導體元件4。可在第一區域I中形成第一環繞式閘極電晶體TR1且可在第二區域II中形成第二環繞式閘極電晶體TR2。
可在第一區域I中形成第一犧牲層圖案120且可在第二區域II中形成第二犧牲層圖案125。第一犧牲層圖案120及第二犧牲層圖案125可由互不相同之材料形成。舉例而言，第一犧牲層圖案120可包含半導體層且第二犧牲層圖案125可包含絕緣層。在一例示性實施例中，第一犧牲層圖案120可包含矽鍺(SiGe)層且第二犧牲層圖案125可包含氧化矽層。
在第一犧牲層圖案120包含矽鍺層之例示性實施例中，可在第一環繞式閘極電晶體TR1之通道區域中誘發壓縮應力。因此，在形成於一部分第一犧牲層圖案120中之通道區域中可增加p型載體移動性(motility)。在第二犧牲層圖案125包含氧化矽層之例示性實施例中，在第二環繞式閘極電晶體TR2之通道區域中可不誘發任何潛在壓縮應力。因此，在形成於一部分第二犧牲層圖 案125中之通道區域中可不減少n型載體移動性。
在一例示性實施例中，第一犧牲層圖案120以及第二犧牲層圖案125均可包含矽鍺層。第一犧牲層圖案120可具有第一鍺濃度且第二犧牲層圖案125可具有第二鍺濃度。第一鍺濃度與第二鍺濃度可互不相同。舉例而言，第一鍺濃度可大於第二鍺濃度。
在一例示性實施例中，第一環繞式閘極電晶體TR1為PMOS電晶體且第二環繞式閘極電晶體為NMOS電晶體。
圖8為說明根據本發明概念之例示性實施例之半導體元件的透視圖。圖9為對應於圖8之線D-D的橫截面圖。
參看圖8及圖9，半導體元件5可包含第一環繞式閘極電晶體TR1以及第三環繞式閘極電晶體TR3，其在基板100上形成且分別具有通道區域。基板100可具有第一區域I及第二區域II。可在第一區域I中形成第一環繞式閘極電晶體TR1且可在第二區域II中形成第三環繞式閘極電晶體TR3。
第一環繞式閘極電晶體TR1之第一閘電極層160可包圍一部分在第一區域I中形成之通道區域。在一例示性實施例中，第一閘電極層160可完全包圍一部分在第一區域I中形成之通道區域。舉例而言，在第一區域I中第一閘電極層160可包圍主動層圖案130之頂部、側壁及底部。
第三環繞式閘極電晶體TR3之第二閘電極層162可部分包圍一部分在第二區域II中形成之通道區域。舉例而言，在第二區域II中，第二閘電極層162可僅包圍主動層圖案130之頂部及側壁。
在第二區域II中，可在主動層圖案130下形成犧牲層圖案120及絕緣層170。舉例而言，在源極/汲極結構140形成於其上之區中，可在主動層圖案130之一部分下形成可包含矽鍺層之犧牲層圖案120，且在閘極介電層150及第二閘電極層162形成於其上之區中，可在主動層圖案130之另一部分下形成絕緣層170。
在一例示性實施例中，第一環繞式閘極電晶體TR1以及第三環繞式閘極電晶體TR3可為相同類型的電晶體。舉例而言，第一環繞式閘極電晶體TR1以及第三環繞式閘極電晶體TR3可為n型電晶體或p型電晶體。或者，第一環繞式閘極電晶體TR1可為p型電晶體且第三環繞式閘極電晶體TR3可為n型電晶體。
圖10為說明根據本發明概念之例示性實施例之半導體元件的電路圖。圖11為顯示於圖10中之電路圖的等效佈局。
參看圖10，半導體元件6可包含具有在電源節點VCC及接地節點VSS之間形成之第一反相器INV1及第二反相器INV2之靜態隨機存取記憶體(Static Random Access Memory，SRAM)元件。具有輸入節點及輸出節點之第一反相器INV1可具有第一上拉電晶體PU1及第一下拉電晶體PD1。具有輸入節點及輸出節點之第二反相器INV2可具有第二上拉電晶體PU2及第二下拉電晶體PD2。第一反相器INV1之輸入節點可與第一傳送電晶體PS1之源極/汲極區域以及第二反相器INV2之輸出節點連接。第二反相器INV2之輸入節點可與第二傳送電晶體PS2之源極/汲極區域以及第一反相器INV1之輸出節點連接。第一傳送電晶體PS1及第二傳送電晶體PS2之閘電極可與字線WL連接。位元線BL可與第一傳送電晶體PS1之源極/汲極區域連接。位元線桿BLb可與第二 傳送電晶體PS2之源極/汲極區域連接。半導體元件6可包含本文所述之根據本發明概念之例示性實施例之至少一種環繞式閘極電晶體。
參看圖11，第一主動區域至第四主動區域210、220、230及240可在第一方向上延伸。在一例示性實施例中，第二主動區域220及第三主動區域230之長度可小於第一主動區域210及第四主動區域240之長度。
第一閘電極251可橫越第一主動區域210及第二主動區域220以形成第一下拉電晶體PD1以及第一上拉電晶體PU1。第二閘電極252可橫越第一主動區域210以形成第一傳送電晶體PS1。第一閘電極251及第二閘電極252可實質上相互平行且相互隔開。第三閘電極253可橫越第三主動區域230及第四主動區域240以形成第二下拉電晶體PD2以及第二上拉電晶體PU2。第四閘電極254可橫越第四主動區域240以形成第二傳送電晶體PS2。第三閘電極253以及第四閘電極254可實質上相互平行且相互隔開。
可在第一傳送電晶體PS1及第二傳送電晶體PS2之閘電極上形成接觸孔250。可另外在上述電晶體之源極/汲極區域上形成其他接觸孔。
可在一部分第二主動區域220上形成第一共用接點261。第一共用接點261可使第一上拉電晶體PU1之源極/汲極與第二上拉電晶體PU2以及第二下拉電晶體PD2之閘電極連接。第一互連線271可使第一共用接點261與第一上拉電晶體PD1以及第一傳送電晶體PS1之源極/汲極區域連接。
可在第三主動區域230之一部分上形成第二共用接點262。第二共用接點262可使第二上拉電晶體PU2之源極/汲極與第一上拉電晶體PU1以及第一下拉電晶體PD1之閘電極連接。第二互連線272可使第二共用接點262與第二下拉電晶體PD2以及第二傳送電晶體PS2之源極/汲極區域連接。
圖12及圖13為說明根據本發明概念之例示性實施例之半導體元件的方塊圖。
參看圖12，半導體元件13可包含邏輯區域410以及SRAM區域420。可將第一電晶體411安置於邏輯區域410中且可將第二電晶體421安置於SRAM區域420中。第一電晶體411及第二電晶體421之類型可互不相同。舉例而言，在一例示性實施例中，第一電晶體411可為第一環繞式閘極電晶體TR1(顯示於圖7中)且第二電晶體421可為第二環繞式閘極電晶體TR2(顯示於圖7中)。或者，第一電晶體411及第二電晶體421之類型可為相同。在一例示性實施例中，第一電晶體411可為第一環繞式閘極電晶體TR1(顯示於圖8中)且第二電晶體421可為第三環繞式閘極電晶體TR3(顯示於圖8中)。
在例示性實施例中，可用DRAM區域、MRAM區域、RRAM區域或PRAM區域替換SRAM區域，或DRAM區域、MRAM區域、RRAM區域及PRAM區域中之至少一者可添加有SRAM區域及邏輯區域410。
參看圖13，半導體元件14可包含邏輯區域410、第三電晶體412以及第四電晶體422。在一例示性實施例中，第三電晶體412及第四電晶體422之類型可互不相同。舉例而言，第三電 晶體412可為第一環繞式閘極電晶體TR1(顯示於圖7)，且第四電晶體422可為第二環繞式閘極電晶體TR2(顯示於圖7中)。或者，第三電晶體412及第四電晶體422之類型可為相同。在一例示性實施例中，第三電晶體412可為第一環繞式閘極電晶體TR1(顯示於圖8中)且第四電晶體422可為第三環繞式閘極電晶體TR3(顯示於圖8中)。
圖14為包含根據本發明概念之例示性實施例之半導體元件的系統晶片(SoC)的系統方塊圖。
參看圖14，SoC可包含應用程式處理器1001及DRAM元件1060。應用程式處理器1001可包含中央處理單元1010、多媒體系統1020、匯流排(例如多級互連匯流排)1030、記憶體系統1040及周邊電路1050。
中央處理單元1010可進行驅動系統晶片1000之操作。多媒體系統1020可例如包含三維(three-dimensional，3D)引擎模組、視訊編碼解碼器、顯示系統、攝影系統及/或後處理器。中央處理單元1010、多媒體系統1020、記憶體系統1040及周邊電路1050可經由匯流排1030相互通信。匯流排1030可具有多層結構。舉例而言，匯流排1030可為多層先進高效能匯流排(advanced high-performance bus，AHB)或多層先進可擴展介面(advanced extensible interface，AXI)。
當應用程式處理器1001與外部元件連接時，記憶體系統1040可提供執行高速操作的環境。外部元件可例如為DRAM元件。周邊電路1050可提供其中系統晶片1000能夠與外部元件平穩連接的環境。在此情況下，外部元件可例如為主機板。可如圖 14中所示，將DRAM元件1060安置在1001外部。在一例示性實施例中，DRAM元件1060可與應用程式處理器1001一起封裝以形成疊層封裝(package-on-package，PoP)結構。
系統晶片1000之至少一個元件可包含本文所述之根據本發明概念之例示性實施例之半導體元件。
圖15為包含根據本發明概念之例示性實施例之半導體元件的電子系統的方塊圖。
參看圖15，電子系統1100可例如包含控制器1110、輸入/輸出元件1120、記憶體元件1130、介面1140以及匯流排1150。控制器1110、輸入/輸出元件1120、記憶體元件1130及介面1140可經由匯流排1150相互通信。
控制器1110可例如包含微處理器、數位信號處理器、微控制器或可控制執行程式之類似元件。輸入/輸出元件1120可例如包含小鍵盤、鍵盤或顯示器。記憶體元件1130可儲存用於執行控制器1110之代碼或資料且保存藉由控制器1110執行之資料。記憶體元件1130可例如包含根據本發明之例示性實施例之半導體元件。
系統1100可應用於諸如個人數位助理(personal digital assistant，PDA)、攜帶型電腦、平板電腦、無線電話、行動電話、數位音樂播放器、記憶卡等產品。
圖16至圖18為包含根據本發明之例示性實施例之半導體元件的電子產品之實例。圖16顯示平板電腦1200，圖17顯示筆記型電腦1300且圖18顯示智慧型電話1400。本文所述之根據本發明概念之至少一個例示性實施例之半導體元件可用於平板電 腦1200、筆記型電腦1300或智慧型電話1400。
圖19至圖24為說明製造根據本發明概念之例示性實施例之半導體元件的方法的透視圖。
參看圖19，可使用第一磊晶生長製程在基板100上形成第一磊晶層。第一磊晶層可例如包含矽鍺(SiGe)。可使用第二磊晶生長製程在第一磊晶層上形成第二磊晶層。第二磊晶層可例如包含矽(Si)。
可蝕刻第二磊晶層以形成主動層圖案130且可蝕刻第一磊晶層以形成犧牲層圖案120。可以某一深度蝕刻基板100以形成鰭片結構F。
在一例示性實施例中，可使用乾式蝕刻製程依序蝕刻第二磊晶層、第一磊晶層以及基板100。可在基板100上形成元件隔離結構110(顯示於圖1及圖4中)以覆蓋鰭片結構F。
主動層圖案130可具有第一區域131及第二區域132。可在如圖20A中所示之虛設閘極層152下形成主動層圖案130之第一區域131。主動層圖案130之第一區域131可為環繞式閘極電晶體之通道層。可在如圖20C中所示之源極/汲極結構140下形成主動層圖案130之第二區域132。
犧牲層圖案120亦可包含第一區域121及第二區域122。可在主動層圖案130之第一區域131下形成犧牲層圖案120之第一區域121。可在主動層圖案130之第二區域132下形成犧牲層圖案120之第二區域122。
根據本發明概念之例示性實施例，可在SOI基板上形成基板100。在此情況下，可使用磊晶生長製程形成基板100且基板 100可包含矽(Si)。可將犧牲層圖案120之第一區域121移除以形成如圖6中所示之環繞式閘極電晶體。
參看圖20A，可在主動層圖案130之第一區域131上形成橫越主動層圖案130之虛設閘極圖案152。虛設閘極圖案152可覆蓋犧牲層圖案120之第一區域121。虛設閘極圖案152可例如包含多晶矽層。
參看圖20B，可在虛設閘極圖案152之兩個側壁上形成間隙壁165。間隙壁165可例如包含氮化矽(SiN)或氮氧化矽(SiON)中之至少一者。
參看圖20C，可在虛設閘極圖案152之兩側形成源極/汲極結構140。可使用磊晶生長製程形成源極/汲極結構140。源極/汲極結構140之最低表面之高度可高於或約等於犧牲層圖案120之最上表面。可藉由間隙壁165將源極/汲極結構140與虛設閘極圖案152隔離或分隔。
可使用例如離子植入製程將雜質注入源極/汲極結構140中。亦可將雜質注入主動層圖案130之第二區域132中。
在一例示性實施例中，可在使主動層圖案130之第二區域132部分凹入(recessing)之後在主動層圖案130上形成源極/汲極結構140。
參看圖21，可在源極/汲極結構140上形成層間介電層154。在虛設閘極圖案152及源極/汲極結構140上形成層間介電層154之後，可使層間介電層154平坦化以暴露虛設閘極圖案152之上表面。層間介電層154可例如包含氧化矽層或氮氧化矽層。
參看圖22，可將虛設閘極圖案152移除以暴露主動層圖 案130之第一區域131以及犧牲層圖案120之第一區域121。參看犧牲層圖案120，在移除虛設閘極圖案152之後，僅可暴露第一區域121之側壁。可使用例如乾式蝕刻製程及濕式蝕刻製程中之至少一者移除虛設閘極圖案152。
參看圖23，可使用選擇性蝕刻製程移除犧牲層圖案120之經暴露之第一區域121。因此，可暴露主動層圖案130之第一區域131的底表面且可在第一區域131下形成通孔128。可使用例如包含氯化氫之濕式蝕刻劑(例如氫氯酸)進行選擇性蝕刻製程。
參看圖24，可在主動層圖案130之暴露表面上形成閘極介電層150。閘極介電層150可包圍主動層圖案130之第一區域131。在一例示性實施例中，閘極介電層150完全包圍主動層圖案130之第一區域131。可同時在主動層圖案130之第一區域131的上表面、側表面以及底表面上形成閘極介電層150。可沿著間隙壁165之內側壁形成閘極介電層150且使其向上延伸。
再次參看圖1至圖3，可在閘極介電層150上形成閘電極層160。閘電極層160可延伸穿過通孔128且包圍主動層圖案130之第一區域131。因此，閘電極層160可延伸穿過犧牲層圖案120之一部分。
在犧牲層圖案120包含諸如氧化矽層之絕緣層的例示性實施例中，可以與顯示於圖4至圖6中之第二環繞式閘極電晶體TR2類似的方式形成環繞式閘極電晶體。
在犧牲層圖案120之第一區域121經如圖9中所示之絕緣層170替代的例示性實施例中，可以與顯示於圖8及圖9中之第三環繞式閘極電晶體TR3類似的方式形成環繞式閘極電晶體。
儘管已參考本發明概念之例示性實施例特定顯示且描述本發明概念，但所屬技術領域中的一般技術者應理解，在不脫離由以下申請專利範圍界定之本發明精神以及範疇的情況下，可在其中進行形式以及細節之各種改變。
1‧‧‧半導體元件
100‧‧‧基板
110‧‧‧元件隔離結構
120‧‧‧犧牲層圖案
130‧‧‧主動層圖案
140‧‧‧源極/汲極結構
150‧‧‧閘極介電層
165‧‧‧間隙壁
F‧‧‧鰭片結構
TR1‧‧‧第一環繞式閘極電晶體

Claims (20)

  1. 一種半導體元件，包括：安置於基板上之鰭片結構；安置於所述鰭片結構上之犧牲層圖案；安置於所述犧牲層圖案上之主動層圖案；以及延伸穿過所述犧牲層圖案且包圍所述主動層圖案之一部分的閘極介電層及閘電極層。
  2. 如申請專利範圍第1項所述之半導體元件，更包括：安置於所述閘電極層之側壁上之間隙壁；以及安置於所述主動層圖案上之源極/汲極結構，其中所述源極/汲極結構藉由所述間隙壁與所述閘電極層分隔，其中所述犧牲層圖案安置在所述源極/汲極結構下且不安置在所述閘電極層下。
  3. 如申請專利範圍第2項所述之半導體元件，其中所述源極/汲極結構覆蓋所述主動層圖案之上表面以及所述主動層圖案之側壁。
  4. 如申請專利範圍第1項所述之半導體元件，其中所述犧牲層圖案包括半導體材料。
  5. 如申請專利範圍第4項所述之半導體元件，其中所述半導體材料包括矽鍺(silicon germanium，SiGe)。
  6. 如申請專利範圍第1項所述之半導體元件，其中所述犧牲層圖案包括絕緣材料。
  7. 如申請專利範圍第6項所述之半導體元件，其中所述絕緣 材料包括氧化矽。
  8. 如申請專利範圍第1項所述之半導體元件，其中所述閘電極層包括金屬。
  9. 如申請專利範圍第1項所述之半導體元件，其中所述基板包括矽絕緣體(silicon-on-insulator，SOI)基板。
  10. 如申請專利範圍第1項所述之半導體元件，其中所述基板包括第一區域以及第二區域，其中所述鰭片結構包括安置於所述第一區域中之第一鰭片結構以及安置於所述第二區域中之第二鰭片結構，其中所述犧牲層圖案包括安置於所述第一鰭片結構上之第一犧牲層圖案以及安置於所述第二鰭片結構上之第二犧牲層圖案，其中所述主動層圖案包括安置於所述第一犧牲層圖案上之第一主動層圖案以及安置於所述第二犧牲層圖案上之第二主動層圖案，其中所述閘極介電層包括第一閘極介電層以及第二閘極介電層，其中所述閘電極層包括第一閘電極層以及第二閘電極層，其中所述第一閘極介電層以及所述第一閘電極層延伸穿過所述第一犧牲層圖案且包圍所述第一主動層圖案之一部分，其中所述第二閘極介電層以及所述第二閘電極層延伸穿過所述第二犧牲層圖案且包圍所述第二主動層圖案之一部分。
  11. 如申請專利範圍第10項所述之半導體元件，其中所述第一犧牲層圖案包括半導體材料且所述第二犧牲層圖案包括絕緣材料。
  12. 如申請專利範圍第11項所述之半導體元件，其中所述半導體材料包括矽鍺(SiGe)且所述絕緣材料包括氧化矽。
  13. 如申請專利範圍第10項所述之半導體元件，更包括：包括所述第一鰭片結構、所述第一主動層圖案、所述第一閘極介電層以及所述第一閘電極層之第一環繞式閘極電晶體；以及包括所述第二鰭片結構、所述第二主動層圖案、所述第二閘極介電層以及所述第二閘電極層之第二環繞式閘極電晶體，其中所述第一環繞式閘極電晶體包括PMOS電晶體且所述第二環繞式閘極電晶體包括NMOS電晶體。
  14. 如申請專利範圍第10項所述之半導體元件，其中所述第一犧牲層圖案具有第一鍺濃度且所述第二犧牲層圖案具有第二鍺濃度，且所述第一鍺濃度小於所述第二鍺濃度。
  15. 一種半導體元件，包括：包括第一區域以及第二區域之基板；安置於所述第一區域中之第一環繞式閘極電晶體，其中所述第一環繞式閘極電晶體包括第一鰭片結構、安置於所述第一鰭片結構上之第一犧牲層圖案、安置於所述第一犧牲層圖案上之第一主動層圖案以及延伸穿過所述第一犧牲層圖案且包圍所述第一主動層圖案之一部分的第一閘電極層；以及安置於所述第二區域中之第二環繞式閘極電晶體，其中所述第二環繞式閘極電晶體包括第二鰭片結構、安置於所述第二鰭片結構上之第二犧牲層圖案、安置於所述第二犧牲層圖案上之第二主動層圖案以及延伸穿過所述第二犧牲層圖案且包圍所述第二主動層圖案之第一部分的第二閘電極層。
  16. 如申請專利範圍第15項所述之半導體元件，更包括：安置在所述第二主動層圖案之第二部分下的絕緣層，其中所述第二主動層圖案之所述第二部分不與所述第二閘電極層重疊。
  17. 如申請專利範圍第16項所述之半導體元件，其中所述絕緣層包括氧化矽層。
  18. 如申請專利範圍第15項所述之半導體元件，其中所述第一犧牲層圖案以及所述第二犧牲層圖案包括矽鍺(SiGe)。
  19. 一種製造半導體元件之方法，包括：在基板上形成鰭片結構；在所述鰭片結構上形成犧牲層圖案，其中所述犧牲層圖案包括第一區域以及第二區域；在所述犧牲層圖案上形成主動層圖案，其中所述主動層圖案包括形成於所述犧牲層圖案之所述第一區域上的第一區域以及形成於所述犧牲層圖案之所述第二區域上的第二區域；形成橫越所述主動層圖案之所述第一區域的虛設閘極圖案；在所述虛設閘極圖案上以及在所述主動層圖案之所述第二區域上形成層間介電層；使所述層間介電層平坦化以暴露所述虛設閘極圖案；移除所述虛設閘極圖案以暴露所述主動層圖案之所述第一區域以及所述犧牲層圖案之所述第一區域；移除所述犧牲層圖案之所述第一區域；在所述主動層圖案之所述第一區域上形成閘極介電層，其中所述閘極介電層包圍所述主動層圖案之所述第一區域；以及在所述閘極介電層上形成閘電極層，其中所述閘電極層包圍 所述主動層圖案之所述第一區域。
  20. 一種半導體元件，包括：基板；具有楔形形狀且自所述基板突出之鰭片結構；安置於所述鰭片結構上之犧牲層圖案，其中所述鰭片結構具有接近所述基板之第一寬度以及接近所述犧牲層圖案之第二寬度，且所述第一寬度大於所述第二寬度；安置於所述犧牲層圖案上之主動層圖案；延伸穿過所述犧牲層圖案且包圍所述主動層圖案之一部分的閘極介電層及閘電極層；以及安置於所述主動層圖案上之源極/汲極結構，其中所述源極/汲極結構覆蓋所述主動層圖案之上表面以及所述主動層圖案之側壁，其中所述犧牲層圖案安置在所述源極/汲極結構下且不安置在所述閘電極層下。
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US9653361B2 (en) 2017-05-16
US20160013309A1 (en) 2016-01-14
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US9443978B2 (en) 2016-09-13
KR20160008440A (ko) 2016-01-22

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