TW201539660A - 堆疊晶粒積體電路 - Google Patents

堆疊晶粒積體電路 Download PDF

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Publication number
TW201539660A
TW201539660A TW104108864A TW104108864A TW201539660A TW 201539660 A TW201539660 A TW 201539660A TW 104108864 A TW104108864 A TW 104108864A TW 104108864 A TW104108864 A TW 104108864A TW 201539660 A TW201539660 A TW 201539660A
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Taiwan
Prior art keywords
package substrate
via structures
die
package
interposer
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TW104108864A
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English (en)
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TWI573224B (zh
Inventor
Charles G Woychik
Cyprian Emeka Uzoh
Ron Zhang
Daniel Buckminster
Guilian Gao
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Invensas Corp
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Publication of TW201539660A publication Critical patent/TW201539660A/zh
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Publication of TWI573224B publication Critical patent/TWI573224B/zh

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Abstract

本發明為一種積體電路封裝的裝置。在此裝置中，封裝基板具有複數個第一通孔結構，其係從封裝基板之一下表面延伸至該封裝基板之一上表面。晶粒具有複數個第二通孔結構，其延伸至晶粒之一下表面。在積體電路封裝中，晶粒之下表面係面向封裝基板之上表面。封裝基板不包含一重新分配層。晶粒以及封裝基板係彼此耦接。

Description

堆疊晶粒積體電路
本發明係關於積體電路(IC)，特別關於一堆疊晶粒IC。
微電子組件通常包括至少一基體電路(IC)，例如至少一已封裝晶粒(晶片，chip)或至少一晶粒。此些IC中的至少一種係可安裝在一電路平台上，例如一晶圓，以形成例如晶圓級封裝(WLP)、一印刷板(PB)、印刷配線板(PWB)、印刷電路板(PCB)、印刷配線裝配(PWA)、封裝基板、中介層、或晶片載體。此外，一個IC可安裝在另一IC上。中介層可為一IC，且中介層可為一被動IC或一主動IC，其中後者包含至少一主動元件，例如電晶體；以及例如，前者不包括任何的主動元件。此外，中介層可形成類似PWB，亦即沒有任何電路元件，例如電容、電阻、或主動元件。此外，中介層係包含至少一基板通孔。
一IC可包括複數個導電元件，例如導電路徑、跡線、軌線、通孔、接觸部、墊體(例如接觸墊以及焊接墊)、插點、節點、或端部等等，其用於與一電路平台電性互連。此些元件之排列可有助於用以提供IC功能的電性連接。IC可藉由焊接耦接電路平台，例如將電路平台的跡線或端部 與IC的接腳、柱狀物或類似物之焊接墊或曝露端相焊接。此外，重新分配層(RDL)可為IC的一部分，以有助於覆晶配置、晶片堆疊以及更方便好使用的焊接墊。傳統上，在IC與另一IC之間相互連接、或是IC與電路平台之間相互連接在輸入/輸出互連件(I/O)之密度或是間距有相關的爭議，所以目前已經將晶粒堆疊以形成"3D IC"以提高I/O的數量。然而，對於形成3D IC仍有相關的問題，包含成本限制。
因此，目前亟欲解決的問題在於如何提供較低成本的“3D IC”。
本發明之裝置係有關於一積體電路封裝。裝置中，封裝基板具有複數個第一通孔結構，其從封裝基板之一下表面延伸至該封裝基板之一上表面。一晶粒具有複數個第二通孔結構，複數個第二通孔結構係延伸至晶粒之一下表面。在積體電路封裝件中，晶粒之下表面係面向封裝基板之上表面。封裝基板不包含一重新分配層。晶粒以及封裝基板係彼此耦接。
本發明之方法係有關於一積體電路封裝。在此方法中，取得具有複數個第一通孔結構的封裝基板，複數個第一通孔結構係從封裝基板之一下表面延伸至封裝基板之一上表面。取得具有複數個第二通孔結構的晶粒，複數個第二通孔結構係延伸至晶粒之一下表面。晶粒之下表面係位於面向封裝基板之上表面，以提供積體電路封裝。晶粒以及封裝基板係彼此耦接。封裝基板不包含一重新分配層。
ILD1、ILD2、ILD3、ILD4‧‧‧層間介電層
M1、M2、M3、M4、M5‧‧‧金屬化層
3‧‧‧FEOL結構
4‧‧‧前側
5‧‧‧後段製程(BEOL)結構
6‧‧‧背側
7‧‧‧淺溝渠隔離層(STI)
8‧‧‧電晶體閘極區
9‧‧‧接觸插部
10‧‧‧晶粒
10-1、10-2、10-3、10-4‧‧‧晶粒
11‧‧‧預金屬化介電區(PMD)
12‧‧‧基板
13‧‧‧鈍化層
14‧‧‧上表面
15‧‧‧襯墊層
16‧‧‧下表面
18‧‧‧通孔結構
20‧‧‧接觸面
21‧‧‧通孔導體
22‧‧‧接觸面
23‧‧‧接觸墊
24‧‧‧障蔽層
28‧‧‧鈍化層
29‧‧‧凸塊
31‧‧‧鈍化層
32‧‧‧金屬層
33‧‧‧球體
34‧‧‧貼合墊片
40‧‧‧中介層
41‧‧‧封裝基板
42‧‧‧散熱膏
43‧‧‧散熱片
44‧‧‧互連件
47‧‧‧線路
50‧‧‧封裝元件
52‧‧‧凸塊
53‧‧‧焊球
54‧‧‧填充劑
300‧‧‧IC封裝件
301‧‧‧晶粒
302‧‧‧晶粒
311‧‧‧上表面
312‧‧‧下表面
313‧‧‧下部分
322‧‧‧成型
323‧‧‧間距
340‧‧‧中介層
355‧‧‧厚度
401‧‧‧凸塊
402‧‧‧間距
411‧‧‧表面
412‧‧‧表面
418‧‧‧通孔結構
421‧‧‧端
422‧‧‧端
441‧‧‧封裝基板
442‧‧‧中間部
455‧‧‧厚度
501‧‧‧上方部分
502‧‧‧互連結構
521‧‧‧頂部
601‧‧‧厚度
602‧‧‧厚度
611‧‧‧填充劑層
622‧‧‧表面
633‧‧‧球體
634‧‧‧成型材料層
635‧‧‧線路
644‧‧‧虛
655‧‧‧電路板
656‧‧‧填充劑層
661‧‧‧可填充低模數材料
662‧‧‧凹槽
663‧‧‧凹槽
671‧‧‧通孔結構
672‧‧‧通孔結構
701‧‧‧晶粒
本發明之上述及其他特徵優點可藉由參照附圖實施例詳細說明而進一步了解，其中：第1A圖為本案較佳實施例之提供積體電路之在線晶圓的示例性部分的剖面示意圖。
第1B圖為本案較佳實施例之提供另一IC的在線晶圓的示例性部分的剖面示意圖。
第1C圖為第1A圖之IC之基板的下表面之化學機械研磨後的垂直覆晶的IC。
第1D圖為第1A圖之IC經背側蝕刻基板之下表面以露出通孔導體之下端接觸面之後垂直覆晶的IC。
第1E圖為第1D圖以及IC之下表面，其上形成鈍化層，且鈍化層可用至少一電介質層形成。
第2A圖為本案較佳實施例之具有通孔結構之例示性三維IC封裝元件的剖面方塊圖。
第2B圖為本案較佳實施例之具有通孔結構之另一例示性3D IC封裝元件的剖面方塊圖。
第3A圖至第3D圖為本案較佳實施例之3D IC封裝元件(IC封裝)的例示性製造流程的個別剖面方塊圖。
第4A圖至第4C圖為本案較佳實施例之用於IC封裝件之封裝基板的例示性製造過程的個別剖面方塊圖。
第5A圖至第5B圖為本案較佳實施例之用於IC封裝件之另一封裝基板的例示性製造過程的個別剖面方塊圖。
第6A-1圖、第6A-2圖、第6B圖、第6C圖、第6D-1圖、第6D-2圖、第6E圖、第6F-1圖、第6F-2圖、第6G圖分别為第3D圖之中介層之與第4B圖與第5B圖之封裝基板相互連接之後例示性IC封裝件之製造流程的個別剖面圖。
本文中，詞彙“與/或”包含一或多個相關條列項目之任何或所有組合。當“至少其一”之敘述前綴於一元件清單前時，係修飾整個清單元件而非修飾清單中之個別元件。
第1A圖為用於提供IC元件10的在線晶圓的示例性部分的剖面示意圖。IC 10包含半導體材料之基板12，而半導體材料例如為矽(Si)、砷化鎵(GaAs)、高分子材料、陶瓷、碳系基板(例如鑽石)、矽碳(SiC)、鍺(Ge)、Si1-xGex、或類似材料。雖然以下係描述在線晶圓所提供的半導體基板12，但是任何半導體材料或介電材料(例如陶瓷或玻璃)片或材料層，皆可作為基板。此外，即使所描述為IC 10，但本發明可使用含有至少一基板通孔結構的任何的微電子裝置。
基板12包含一上表面14以及一下表面16，其在側面方向上延伸且在基板12的厚度上彼此平行。在此所用的"上"、"下"或其他方向性用語係相對於圖示之參考框，並非有意限制其在其他組件或使用在各個系統潛在的替代方位。
上表面14可通常與被稱為在線晶圓之"前側(front side)" 4相關聯，以及下表面16可通常與被稱為在線晶圓的"背側(back side)" 6相關聯。在製程中，在線晶圓的前側4可用於形成被稱為前段製程(“FEOL”)結構3以及後段製程(BEOL)結構5。通常，FEOL結構3可包括淺溝渠隔離層(STI)7、電晶體閘極區8、電晶體源/汲極區(未顯示於圖中)、電晶體閘介電區(未顯示於圖中)、通孔蝕刻停止層(CESL，未顯示於圖中)、預金屬化介電區(PMD)11、以及接觸插部9，以及其他FEOL結構。PMD 11可由至少一層所構成。通常，BEOL結構5可包括至少一層間介電層(ILD)以及至少一金屬化層(M)。在此示例中，有四層ILD，即ILD1、ILD2、ILD3以及ILD4。然而，在其他實施例中可有較少或較多層ILD。此外，每一ILD可由至少一介電層所構成。在此例中，有五層金屬化層，即M1、M2、M3、M4以及M5。然而，在其他實施例中，可以有較少或較多金屬化層。此外，從金屬化層延伸出的金屬可延伸穿過至少一ILD，其為已知的技術。此外，每一金屬化層可由至少一金屬層所構成。鈍化層13可形成在前一金屬化層上。鈍化層13可包括至少一介電層，以及更進一步可包括一抗反射塗層(ARC)。此外，一重新分配層(RDL)可形成在鈍化層上。傳統上，RDL可包含：介電層，例如聚酰亞胺(polyimide)層；介電層上的另一金屬層，其連接至最後金屬化層之金屬層之焊墊；以及另一介電層，例如另一聚酰亞胺層，其位在RDL金屬層上方而其一暴露部分係移除以提供另一焊墊。一端開口可暴露此RDL金屬層之其他焊墊。接著，傳統上焊料凸塊或是焊線可耦接此焊墊。
作為FEOL或BEOL構造形成的一部分，複數個通孔結構 18可在延伸進基板12內之複數個開孔內延伸。通孔結構18通常為任何形狀的任何固體形式，其係填滿基板12之開口或是孔洞而形成。此固體的示例形狀通常包括圓柱形、圓錐形、錐台形、長方狀棱形、正方形或類似形狀。在申請號13/193,814而申請日為2011年7月29日的美國專利申請案，以及申請號12/842,717與12/842,651而申請日為2010年7月23日的兩件美國專利申請案，已經揭露針對通孔結構的開孔、通孔及其製程的示例。而這些專利的內容係在本發明中作為參考。
傳統上，通孔結構18可從上表面14朝下延伸至下表面16，而後在背側顯露出。通孔結構18可在表面14以及16之間延伸，基板12的厚度夠薄能使通孔結構18的下端表面顯露出，以下將有詳細說明。在表面14以及16之間分別延伸穿過基板12的通孔結構18，其可延伸穿過上下表面，可被稱為基板通孔。基板通常以矽形成，此基板通孔通常又被稱為TSV，其代表矽通孔(through-silicon-vias)。
在基板12上形成的複數個開孔可保形塗佈(conformally coated)、氧化或以襯墊或隔離層15做襯墊處理。傳統上，襯墊層15係為二氧化矽；然而，氧化矽、氮化矽或另一介電材料亦可用來將通孔結構18與基板12電性絕緣。通常，襯墊層15係為絕緣或介電材料，其位於通孔結構18的任何導電部以及基板12之間，使得一電性訊號、一接地、一供應電壓、或類似訊號可藉由通孔結構18傳遞而不會洩漏至基板12，若有洩漏會導致信號損耗或衰減、短路或其他電路錯誤。
障蔽層24可覆蓋襯墊15。通常，障蔽層24係對於填充至通孔結構18形成於其中的開孔之金屬材料提供擴散阻障。障蔽層24可由 至少一層所構成。此外，障蔽層24可對於後續的電鍍或是其他沉積處理提供晶種層，因此障蔽層24可被稱為障蔽/晶種層。而且，障蔽層24可提供黏著層以讓隨後的沉積金屬黏著。如此，障蔽層24可為障蔽/黏著層、障蔽/晶種層、或是障蔽/黏接/晶種層。可用於障蔽層24的材料，例如可包括鉭(Ta)、氮化鉭(TaN)、鈀(Pd)、氮化鈦(TiN)、鉭矽氮(TaSiN)、鉭化合物、鈦化合物、鎳化合物、銅化合物等等。
通孔結構18通常可由金屬或其他導電材料組成，通常在形成於基板12上的開孔的所剩空隙填入金屬或其他導電材料，以產生通孔導體21。在各個示例中，通孔結構18的通孔導體21可通常由銅或銅合金組成。然而，通孔導體21可額外或替代地包括至少一其他導電材料，例如鉭、鎳、鈦、鉬、鎢、鋁、金或銀，以及此些材料的合金或化合物，以及其他相似材料。通孔導體21可包含非金屬添加劑以控制通孔結構18之各種環境或是操作的參數。
每一個通孔結構18可包含一上端接觸面20以及一下端接觸面22，上端接觸面20係與基底12之上表面14同一水平面，而下端接觸面22係與背側暴露的基底12之下表面16同一水平面。端表面20以及22可用以與通孔結構18以及其他內部或是外部元件互連，以下將做詳細描述。
在此範例中，通孔導體21之上端接觸面20係透過一個別接觸墊23與M1互相連接。接觸墊23可形成在PMD 11中的個別開口中，M1係在PMD 11中延伸。然而，在其他實施例中，至少一通孔導體21可透過至少一ILD延伸到至少一其他更高的水平面的金屬化層。此外，通孔 結構18可稱為前側TSV，最初係以蝕刻基底12之前側來形成用於形成通孔結構18的開口。
然而，通孔結構可為背側TSV，如第1B圖所示，其顯示用於提供另一IC 10的在線晶圓之例示性部分的剖面示意圖。製造背側TSV之方法通常被稱為“後通孔方法"，而製造前側TSV之方法通常被稱為“前通孔方法"。
第1B圖之IC 10包含複數個通孔結構18，其為背側TSV。對於通孔結構18之背側TSV，襯墊層15可為在"環狀(donut)"矽溝槽蝕刻內的一沉積聚合物以及其沉積在下表面16上作為一鈍化層28，接著進行一中央矽溝槽蝕刻以移除“環狀"矽溝槽之內部部分，以及接著在圖案化與電鍍之前沉積一晶種層，以提供具有個別焊料凸塊墊或是座落凸塊29的通孔導體21。可選擇，在沉積以及圖案化聚合物隔離層以作為襯墊層15之前，可使用習知的異向性矽蝕刻。
為了清楚說明舉例之目的且非為限制，以下其將假設使用複數個前側TSV，其說明係同樣適用於背側TSV。
第1C圖為第1A圖以及基板12的下表面16之一化學機械研磨(“CMP”)後的IC 10。CMP可執行以暫時地露出下端接觸面22，如此可藉由CMP移除在下端接觸面22下面的襯墊層15以及障蔽層24之部分。如此，在此範例中，下端接觸面22可與下表面16共平面以及同一水平面。
第1D圖顯示第1A圖以及經背側蝕刻基板12之下表面16以暫時地露出通孔導體21之下端接觸面22之後的IC 10。在此範例中，下 端接觸面22可與下表面16共平面；然而，背側露出蝕刻之後，當通孔導體21以及障蔽層24(可選擇性)可從基板12突出，則在此範例中下端接觸面22沒有與下表面16同一水平面。為了清楚說明之目的且非為限制，將是進一步描述第1D圖之IC 10，而下列描述說明可同樣地應用於第1C圖之IC 10。
第1E圖顯示第1D圖之圖示以及基板12之下表面16，其上形成鈍化層31，且鈍化層31可用至少一電介質層形成。此外，鈍化層31可為一聚合物層。例如，鈍化層31可為苯並環丁烯(“BCB”)層、或是氮化矽層與BCB層之組合。在一些應用中，鈍化層31可稱為一晶間層。金屬層32，例如銅、銅合金或是先前描述過的其他金屬，可形成在鈍化層31上以及通孔導體21之下端接觸面22上。此金屬層32可為RDL金屬層。球體33可分别形成在貼合墊片34上，墊片可是形成在金屬層32上或是為金屬層32之一部分。球體33可用一焊接材料形成，例如焊料或是其他焊接材料。球體33可為微小凸塊、C4凸塊、球柵陣列(BGA)球體、或是其他晶粒互連結構。在一些應用中，金屬層32可稱為一座落墊。
最近，TSV已使用於提供三維(3D)IC。通常，可在一焊墊層上或在一晶片電性配線層(on-chip electrical wiring level)上，使用TSV將一晶粒與另一晶粒相附著。可從晶圓切成小塊成為單一IC，即晶粒10。如先前描述，單一晶粒可彼此黏合或是與一電路平台黏合。為了清楚說明之目的且非為限制，以下係假設一中介層使用於電路平台。
互連元件(例如中介層)可在各種用途的電子配裝中，其包含利於具有不同連接構造之元件之間的相互連接或是讓微電子配裝中的元件 之間相間隔。中介層可包含一半導體層，例如矽或其他相似物，以材料片、材料層或是具有導電元件之基板的形式，其中導電元件例如為在開口內延伸的導電孔，而開口係延伸穿過半導體材料層。導電孔可用於穿過中介層的訊號傳輸。在一些中介層中，通孔之複數端部可用作接觸墊，用以連接中介層至其他微電子元件。在其他範例中，至少一RDL可形成在其至少一側上的中介層之一部分，並與穿透孔之一端部或兩端部相連接。RDL可包含多條導電跡線，其在至少一電介質片或是電介質層上或是其內延伸。在單一介電層中，跡線可提供在同一水平面或是由RDL內介電材料所分隔的多個水平面上。RDL內可包含通孔，以相互連接在RDL中不同水平面上的跡線。
第2A圖為具有通孔結構18之例示性3D IC封裝元件50的剖面方塊圖。堆疊晶粒或是封裝層疊晶粒可包含TSV互連件，為了清楚說明舉例之目的，以下係描述3D IC封裝元件50使用通孔結構18之說明。在3D IC封裝元件50之範例中，有三個IC晶粒10，即IC晶粒10-1、10-2與10-3，其依序堆疊。在其他實施例，可堆疊少於三個或多於三個IC 10。IC 10可使用微小凸塊52或焊料焊料凸塊彼此黏合。可選擇，可使用從晶粒之背側延伸出的銅柱體。一些微小凸塊52可互相連接至通孔結構18。例如，銅/錫微小凸塊瞬時液相(TLP)黏合技術可用於將複數個IC彼此黏合。如此，互連層可形成於3D堆疊之IC 10之上側、下側、或是上下兩側。
3D堆疊的複數個IC中最底的IC10-3可選擇耦接一中介層40。中介層40可為主動晶粒或是被動晶粒。為了清楚說明之目的且非為限制，以下係假設中介層40為被動晶粒。IC 10-3可藉由微小凸塊52耦接 至中介層40。中介層40可耦接至一封裝基板41。封裝基板41可用薄層形成，又稱為多層結構或是層壓基板。多層結構可為有機或是無機。用於"硬的"封裝基板的材料範例包含環氧樹脂系層(例如FR4)、樹脂系層(例如雙馬來酰亞胺三嗪樹脂(BT))、陶瓷基板、玻璃基板、或是封裝基板之其他形式。用於覆晶黏著的底部填充劑54可密封用於耦接中介晶粒40以及封裝基板41的C4凸塊或是其他焊球53。撒佈機/散熱片43可黏著至封裝基板41，散熱片43以及基板封裝件41之組合可包裝此3D堆疊之複數個IC 10以及中介層40。散熱膏42可耦接3D堆疊頂部之IC 10-1之上表面至散熱片43之上部內表面。球柵陣列(BGA)球體或是其他陣列互連件44可用以耦接封裝基板41至電路平台，例如PCB。
第2B圖為一具有通孔結構18之另一例示性3D IC封裝元件50的剖面方塊圖。除了以下說明的差異之外，第2A圖以及第2B圖之3D IC封裝元件50的其他部分大致上相同。在第2B圖中，另一IC 10-4係分别地透過微小凸塊52耦接至中介層40，其中IC 10-4並無耦接於IC 10-1、10-2與10-3之堆疊中。此外，中介層40包含金屬以及通孔層，用於提供相互連接IC 10-3與10-4的線路47。此外，中介層40包含透過微小凸塊52耦接IC 10-4的通孔結構18。
3D晶圓級封裝(3D-WLP)可用於相互連接至少二個IC、或是將至少一IC連接至一中介層、或是其任何組合。而可使用通孔結構18來相互連接。可選擇，複數個IC可為晶粒對晶粒(D2D)的互相連接，或是晶片對晶片(C2C)的互相連接，而其可使用通孔結構18相互連接。可選擇，複數個IC可進一步為晶粒對晶圓(D2W)互相連接、或是晶片對晶 圓(C2W)互相連接，而其可使用通孔結構18相互連接。因此，可使用任何各種晶粒堆疊或是晶片堆疊方法來以提供3D堆疊IC(3D-SIC或是3D-IC)。
第3A圖至第3D圖為3D IC封裝元件(IC封裝)300的製程例示性流程的個別剖面方塊圖。IC封裝件300包含複數個IC晶粒(例如IC晶粒301與302)以及一中介層340。中介層340透過複數個互連元件與IC晶粒耦接，互連元件例如微小凸塊或是覆晶焊料凸塊52。複數個凸塊52之間可具有間距323，其實質上小於間距302。在第3B圖中，可沉積底部填充劑54使其設置在IC晶粒301與302之複數個下表面310與中介層340之RDL 332之上表面311之間，即中介層340之上表面。雖然在此說明性地繪示底部填充劑54，但是亦可使用成型材料、封裝材料、及/或底部填充劑材料以提供晶粒301與302以及中介層340之間的側面支撐，以利後續的處理。RDL 332可耦接中介層340之通孔結構18。中介層340可有單一RDL 332，而此RDL 332可設置在封裝基板所黏著之側的對面側上，即單一RDL 332可設置在中介層340之一側上，該側係用於黏著至少一IC晶粒。沿著傳輸線上，中介層340在封裝基板所黏著之側上沒有RDL，即沒有RDL沿著中介層340之下表面312。如此，不須任何訊號(電力或接地)通道，封裝基板之通孔結構可一對一對應透過RDL耦接中介層340之通孔結構18。此封裝基板可用於系統級封裝(SiP)之至少一晶粒或是中介層，即通常針對用於形成3D IC的D2D、W2D或是WLP互連線路的至少一晶粒。
中介層340之總厚度355係不大於0.05毫米(50μm)。為了清楚說明之目的且非為限制，以下係假設中介層340，如同IC晶粒301與 302，包含製造完成的多層結構(基板)，其通常已完成全部的BEOL以及FEOL處理操作，通常用於IC封裝件300。在被動晶粒構造中，例如被動中介層，其沒有任何FEOL處理操作。例如，如上所述，第1A圖之基板12係為一單層。然而，基板通常為一單層或是多層，用以形成被動元件或是主動元件。在製程中，半導體晶粒可作為一基板。
再次，為了清楚說明之目的而非為限制，本文係假設一BEOL層或是一RDL 332已經形成在中介層340上，而為在線IC封裝300之一部分。為了讓下列描述更容易理解，在封裝基板之前的至少一RDL係已有效地移動至RDL 332。如此，RDL 332可包含額外的電力、接地、及/或封裝之外的輸入以及輸出訊號的路徑選擇。沿著傳輸線，複數個導電性通孔結構18之間距302可等於封裝基板(例如IC封裝件300)中對應之通孔結構的間距。
在第3C圖中，成型材料或是密封劑材料或是化合物(成型)322可沉積在IC晶粒301與302上以及上表面311上，以密封IC晶粒301與302於中介層340。在第3D圖中，可在中介層340之下表面312上執行背側曝露處理。背側暴露處理可用於暴露通孔結構18之下部分313。通孔結構18有厚度602。
第4A圖至第4C圖為用於IC封裝件300之基板441的例示性製造處理過程的個別剖面方塊圖。封裝基板441可具有複數個導電性通孔結構418，其從封裝基板441之下表面412延伸至封裝基板441之上表面411。可選擇，封裝基板441一部分可沒有導電性通孔結構418，例如中間部442。封裝基板441可具有大約0.1毫米至0.5毫米之範圍內的總厚度 455，即100μm至500μm的範圍，其為中介層340之厚度355的整數倍數。上表面411上的通孔結構418之複數暴露端421係用於相互連接至中介層340。下表面412上的通孔結構418之複數暴露端422可用於與印刷電路板或是背板或是其他電路板相互連接，包含但非為限制，含有可撓式印刷電路或是高密度PCB。材料可為FR4、FR5、BT、陶瓷、堆積物、聚酰亞胺(polyimide)或是任何其他電路板材料。封裝基板441可用半導體材料形成，例如矽。然而，封裝基板441可用各種其他基板材料形成，而非限制於用半導體形成。例如，封裝基板441可用無機或是有機材料形成。可用於封裝基板441的其他基板材料之範例包含陶瓷、玻璃、複合材料或聚合物、或其組合，例如聚合物複合材料。通常，封裝基板材料可具有大約2ppm/℃至7ppm/℃之範圍內的熱膨脹(CTE)係數，及/或封裝基板材料之模數可在大約70GPa至140GPa之範圍內。因為封裝基板441之厚度足夠大以減緩大幅度的翹曲，模數及/或CTE數值可根據不同應用而變化。
在第4B圖中，用於複數個互連元件的複數個焊料凸塊401可分别沉積黏著於複數個導電性通孔結構418。焊料凸塊401可對應於通孔結構418之複數個暴露端421而沉積在封裝基板441之上表面411。複數個通孔結構之間可具有間距402，其等於或是至少非常接近間距302，以使封裝基板441之通孔結構418以及中介層340之通孔結構18之間能有一對一對應。
第4C圖為另一實施例，其中導電性通孔結構418設置遍及封裝基板441，包含中間部442。在製程中，“現貨”封裝基板441係使用於任何至少一晶粒，其中導電性通孔結構418之一間距402及/或多個間距 402係用於讓至少一晶粒與封裝基板441相互連接。此外，更完整分布的導電性通孔結構418可改進其可製造性，且可對耦接提供更均勻的表面。另外，封裝基板441可製造散售提供給封裝公司或是IC封裝件製造商，而且提供商可有效地提供客製或是專用的商品化封裝基板441。而且，一片封裝基板441實質上可大於中介層，以及根據使用者的選擇，可切成小塊成複數個封裝件基板441以耦接對應的中介層及/或其他至少一晶粒。如此，一片封裝基板441可用於IC封裝件之各種構造。然而，為了清楚說明示例之目的且非為限制，本文係假設中間部442並未用於封裝基板441之導電性通孔結構418，即使封裝基板441之中間部442有導電性通孔結構418但中間部442的至少一導電性通孔結構418沒有連接。即使導電性通孔結構418不是90°度，但封裝基板441沒有側面的導電性通孔結構418，即低於45°度。
第5A圖至第5B圖為用於IC封裝件300之另一封裝基板441的例示性製造過程的個別剖面方塊圖。封裝基板441可具有複數個導電性通孔結構418，其從封裝基板441之下表面412延伸至封裝基板441之上表面411。可蝕刻以暴露上表面411上對應複數端421的上方部分501，以進一步暴露通孔結構418之複數個暴露端。然而，對於第4A圖以及第5A圖之封裝基板，通孔結構418如同暴露的上方部分501一樣，可用電鍍或是其他低成本金屬化層形成。如此，通孔結構418以及選擇性暴露的上方部分501，可有效地預製作為封裝基板441之一部分。沿著傳輸線上，藉由使用無機封裝基板441，相較於使用有機封裝基板441，可進一步減少成本。
複數端421以及上方部分501可相互連接至中介層340。在 下表面412上通孔結構418之複數個暴露端可與印刷電路板、背板或是其他電路板相互連接。
在第5B圖中，上方部分501可用以提供複數個凸起的互連結構502，例如Tessera of San Jose,California所開發的微小接腳互連層(μPLIR)。凸起的互連結構502可與上方部分501之無電及/或電解質電鍍形成。通常，μPLIR平台係利用圓錐形的凸起互連結構502，例如鍍有鎳/銅的固體銅接觸件。在製程中，應理解的是無電鎳電鍍(EN)係為一自動催化沉積。μPLIR技術可用於任何、多種型態的互連線路，其含有例如IC至封裝基板的互連線路、中介層至封裝基板的互連線路、封裝件至PCB的互連線路、及/或PoP互連線路。複數個凸起的互連結構502可透過沒有底部填充劑的構造作連接。另外，當封裝基板441為無機材料形成的被動元件時，相比於底部填充劑，異向性導電膜(ACF)可用於與凸起的互連結構502相互連接。可選擇，複數個凸起的特徵可加強流通性，底部填充劑可與凸起的互連結構502一起使用。
焊料凸塊401，例如複數個凸起的互連結構502，可分别沉積以耦接至導電性通孔結構418。焊料凸塊401可沿著封裝基板441之上表面411沉積，其係對應於凸起的互連結構502之暴露頂部521。複數個通孔結構之間可具有間距402，其等於或是至少非常接近間距302，以使封裝基板441之通孔結構418以及中介層340之通孔結構18之間能有一對一對應。
第6A-1圖、第6A-2圖、第6B圖、第6C圖、第6D-1圖、第6D-2圖、第6E圖、第6F-1圖、第6F-2圖、第6G圖分别為第3D圖之 中介層之與第4B圖與第5B圖340之封裝基板相互連接300之後的例示性IC封裝件441之製造流程的個別剖面圖。在製程中，第6A-1圖與6A-2圖分别繪示第3D圖之中介層之第4B圖與第5B圖之封裝基板441相互連接之後的IC封裝件300的個別剖面圖。此種相互連接可用回流形成。然而，不需要使用焊料。例如，可使用金屬對金屬直接貼合，金屬間黏著或是其他冶金黏著、或導電性環氧樹脂、或是ACF。通常，封裝基板之上表面面積可近似中介層340之下表面面積。換句話說，因為有通孔結構18以及418之間的一對一對應，封裝基板441不需要任何RDL且實質上有比習知技術較小的表面面積。額外參考第3A圖至第3D圖、第4A圖、第4B圖、第5A圖以及第5B圖，以進一步同時描述第6A-1圖以及第6A-2圖。
對於露出的背側，第3D圖內的成型可用以保護薄中介層340，以附著至封裝基板441。然而，一旦附著至中介層340，封裝基板441可作為中介層340的加固物。在製程中，用以提供封裝基板441之至少一電介質層的團塊材料之熱膨脹(CTE)係數係與提供中介層340之至少一電介質層的團塊材料大致相似或是相等，以控制翘曲。用於封裝基板441之材料範例包含矽、玻璃、陶瓷(例如氧化鋁或是矽碳)、或是複合材料(例如碳纖維、環氧樹脂或是聚酰亞胺(polyimide))。為了清楚說明之目的且非為限制，以下係假設封裝基板441為玻璃加固物。
如上所述，中介層340可透過複數個互連元件耦接至封裝基板441之上表面411。因為複數個通孔結構18以及418之間的共同間距，所以封裝基板441之複數個互連元件以及中介層340之複數個互連元件之間有一對一對應關係。應該理解的是封裝基板441不包含任何重新分配層。 通常，封裝基板441不具有用於相互連接其通孔結構418以及中介層340之通孔結構18的重新分配層，以提供所耦接平台之通孔結構之間的一對一對應關係。
通孔結構418有厚度601，而通孔結構18有厚度602。厚度601可至少是第3D圖之厚度602的整數倍數。在傳輸線中，通孔結構418可代表穿過封裝基板441之最短距離或是最短傳遞延遲。如此，在穿過封裝基板441的訊號傳遞，封裝基板441對於每一通孔結構418可具有最小的訊號路徑延遲。此外，由於有較厚的導體，可藉由降低電阻值以強化導電性。雖然通孔結構418有比通孔結構18更低的電阻值，通孔結構418之長度可顯著地大於通孔結構18。因此，藉由比具有RDL的傳統封裝基板有更少的傳遞延遲以及電阻值，本發明之封裝基板441可提高電力以及接地之傳輸，且針對輸入以及輸出通訊至IC封裝件300附著之電路板提供強化效能。
第4B圖以及第5B圖之間的間距402，係對應互連元件之間的間距，例如複數個凸起的互連結構502或是通孔結構418之複數端421。同樣地，複數個互連元件之間的間距係對應間距402，例如通孔結構18之下部分313。每一間距302以及402是0.6毫米或是較小間距，而間距323可為0.45毫米或是更少，而對於更小的間距，間距323可為10μm或是較小間距。沿著傳輸線上，球柵陣列(BGA)可用於中介層340之通孔結構18以及封裝基板之通孔結構之間的相互連接。然而，BGA會增加成本。相反地，對於相對大的範圍，使用大的產品片可用電鍍以形成具有電鍍之通孔結構418的封裝基板441，如同可選擇電鍍凸起的互連結構502，以降低 成本。在製程中，在第4A圖以及第5A圖，取得用於提供封裝基板441的材料片。在用於封裝基板441之通孔結構418的材料片中形成開口。使用電鍍溶液以及電性陽極接觸材料片之一或是兩表面電鍍材料片中的開口全部的體積。一些時間之後材料片可切成小塊以提供作為複數個含有封裝基板441的封裝基板。
為了清楚說明之目的且非為限制，以下係描述第6A-1圖之IC封裝件300之後續的處理，此些描述說明也可同樣地應用於第6A-2圖之IC封裝件300。第6B圖係第6A-1圖在底部填充劑層611加入中介層340以及封裝基板441之間後的圖式。第6C圖係第6C圖從成型322之頂部研磨到IC晶粒301與302之上表面622之圖式。
第6D-1圖為第6C圖在球體633(例如焊球)黏著至先前的沿著封裝基板441之下表面412的通孔結構418之暴露端422。第6D-2圖係第6C圖在球體633(例如焊球)耦合著至先前的沿著封裝基板441之下表面412的通孔結構418之暴露端422。線路635之焊接通孔陣列(BVA)，例如Tessera所提供者，可耦接至複數端422以及對應的球體633之間。BVA線路635可密封於沉積在下表面412上的密封或成型材料層634，以及BVA線路635之複數端部或是尖端可暴露以黏著對應的球體633。BVA線路635對於將IC封裝件300黏著至電路板可更有彈性。此彈性可用以補償IC封裝件300(特別是封裝基板441)以及電路板之間CTE不匹配，封裝件300係附著在電路板上。
為了清楚說明之目的且非為限制，以下係描述將參考第6D-1圖之IC封裝件300之後續的分離處理，此些描述說明也可同樣地應用 於第6D-2圖之IC封裝件300。第6E圖係第6D-1圖之圖式旋轉90度，虛線644係指示IC封裝件300可切成小塊或者從晶圓其他產品片分離出。
第6F-1圖係第6D-1圖之圖式單片之後的結果。IC封裝件300係黏著至電路板655。底部填充劑層656可選擇沉積在IC封裝件300之下表面412以及電路板655之上表面之間。
第6F-2圖為第6D-2圖之圖式單片之後的結果。IC封裝件300係黏著至電路板655。在此構造中，為了提升彈性使IC封裝件300更能與電路板655搭配，不需要使用底部填充劑層656。
因此，對於第6F-1圖以及第6F-2圖之任一或是兩者的IC封裝件300、以及通孔結構18以及418，用於耦合中介層340以及封裝基板441的通孔結構18以及418之間的相互連接，如同耦合封裝基板441以及電路板655一樣，可專為電力、接地以及封裝至電路板輸入/輸出通訊之用。
第6G圖為第6F-1圖之圖式中沒有底部填充劑層656以及具有各種可選擇的封裝基板441構造的圖式。因為封裝基板441實質上可為堅硬的，所以可形成鄰近通孔結構之間的複數個凹部或是凹槽662。凹槽662可被填充，或者不填充。
在製程中，凹部或是凹槽662係形成於封裝基板441中鄰近通孔結構418之間。凹槽662係延伸至鄰近通孔結構418之間的全部寬度，即接壤每一相鄰的通孔結構418。然而，凹槽662係僅延伸至封裝基板441之厚度之一部分。凹槽662可填充低模數材料661，例如軟矽樹脂或是撓性環氧樹脂樹脂。在凹部或是凹槽之另一構造中，凹槽663不接壤相鄰 的通孔結構418，但是相反的，一些封裝基板441材料係設置在每一相鄰的通孔結構418以及凹槽663之間。
此外，通孔結構418不需要完全地填滿。例如，通孔結構671係由沿著孔洞之內側壁以共形沉積所形成，而電鍍之後穿透孔可從上表面延伸至下表面。針對另一範例，通孔結構672係由沿著孔洞之內側壁以共形沉積所形成，然後電鍍以密封孔洞之上方部分。如此，可提供橋接性，即提供從通孔結構671以及672之末端對末端的導電性。因此，通孔結構671或是672之電洞之兩端可被塞住，例如藉由在兩端陽極使用濕化學的電鍍技術用以在兩端同時電鍍。複數個通孔結構18(例如TSV)之高度可為實質上矮的，例如高度低於大約10μm。如此，封裝基板441中的通孔結構之電流密度多少都會受通孔結構18限制。
因此，可避免不欲得之封裝件翹曲，藉由可減少封裝基板尺寸以及減少成本。此外，不需要使用傳統環氧樹脂系黏著劑處理晶圓材料，且可使用加固型材料。當使用無機材料，此方式可允許更高的背側處理溫度，例如是鈍化處理。當直接穿透的通孔結構係用於穿透封裝基板441之導電性時，可避免在封裝基板上使用昂貴堆焊層。而且，以更短的路徑長度穿透封裝基板可改進互連可靠性且減少傳遞延遲。在電鍍之前，被動元件可耦接至封裝基板441，而複數個被動元件可藉由電鍍相耦接。被動元件形成作為用於封裝基板的無機材料的熱積存，可有助於形成高品質被動元件。另外，封裝基板可形成於產品片之大體積製造，例如大量低成本電鍍以及大規模回流。因為通孔結構18以及418之間的一對一對應關係，可強化IC封裝件裝配良率且黏著處理可用於大規模回流裝配。
另外，即使提到中介層340，但是在另一實施例中IC晶粒301與302可直接耦接封裝基板441而不須中介層340，如第7圖。第7圖為第6F-2圖之沒有中介層340的方塊圖。在此IC封裝件300之構造中，第4C圖之封裝基板441具有IC晶粒301與302，其直接耦接至封裝基板441而沒有任何用於直接耦接封裝基板441的RDL層。微小凸塊52可具有封裝基板441之導電性通孔結構418之間距402或是整數倍間距402，可直接耦接IC晶粒301與302至對應的封裝基板441之通孔結構418。此外，IC晶粒301與302可比中介層340厚，如此較不容易受影響而翹曲。雖然說明性地繪示IC晶粒301與302之單層，但是IC晶粒301或是302之任一或是兩者可為晶粒堆疊，例如可選擇的至少一額外的晶粒701堆疊在IC晶粒301。另外，微小凸塊52之複數交替列或是行可用於導電性通孔結構418之對應的複數列或是複數行之間的相互連接。再次，不需要使用全部的封裝基板441之導電性通孔結構418，一些導電性通孔結構之可不使用，如說明性地繪示。
在較佳實施例之詳細說明中所提出之具體實施例僅用以方便說明本發明之技術內容，而非將本發明狹義地限制於上述實施例，在不超出本發明之精神及以下申請專利範圍之情況，所做之種種變化實施，皆屬於本發明之範圍。
ILD1、ILD2、ILD3、ILD4‧‧‧層間介電層
M1、M2、M3、M4、M5‧‧‧金屬化層
3‧‧‧FEOL結構
4‧‧‧前側
5‧‧‧後段製程(BEOL)結構
6‧‧‧背側
7‧‧‧淺溝渠隔離層(STI)
8‧‧‧電晶體閘極區
9‧‧‧接觸插部
10‧‧‧晶粒
10-1、10-2、10-3、10-4‧‧‧晶粒
11‧‧‧預金屬化介電區(PMD)
12‧‧‧基板
13‧‧‧鈍化層
14‧‧‧上表面
15‧‧‧襯墊層
16‧‧‧下表面
18‧‧‧通孔結構
20‧‧‧接觸面
21‧‧‧通孔導體
22‧‧‧接觸面
23‧‧‧接觸墊
24‧‧‧障蔽層

Claims (20)

  1. 一種裝置，包含：一封裝基板，具有一複數個第一通孔結構，其從該封裝基板之一下表面延伸至該封裝基板之一上表面；一晶粒，係具有一複數個第二通孔結構，該複數個第二通孔結構係延伸至該晶粒之一下表面；其中在一積體電路封裝件中，該晶粒之該下表面係面向該封裝基板之該上表面；其中封裝基板不包含一重新分配層；以及其中該晶粒以及該封裝基板係彼此耦接。
  2. 如申請專利範圍第1項所述之裝置，其中為了使該複數個第一通孔結構以及該複數個第二通孔結構之間可一對一對應，該封裝基板之該複數個第一通孔結構係分别耦接該晶粒之該複數個第二通孔結構。
  3. 如申請專利範圍第1項所述之裝置，其中該複數個第一通孔結構係直接耦接該複數個第二通孔結構。
  4. 如申請專利範圍第1項所述之裝置，其中透過對應的複數個互連元件(Interconnects)，該複數個第一通孔結構係分别直接耦接該複數個第二通孔結構。
  5. 如申請專利範圍第1項所述之裝置，其中該複數個第一通孔結構之一第一間距，係等於該複數個第二通孔結構之一第二間距。
  6. 如申請專利範圍第5項所述之裝置，其中該晶粒包含沿著該晶粒之一上表面設置的該重新分配層；該晶粒係為一中介層；以及該中介層之該重新分配層係耦接該中介層之該複數個第二通孔結構。
  7. 如申請專利範圍第6項所述之裝置，更包含：複數個晶粒，係耦接該中介層之該上表面與複數個第二互連元件。
  8. 如申請專利範圍第7項所述之裝置，其中該複數個第二互連件之第三間距之密度係大於該第一間距以及該第二間距。
  9. 如申請專利範圍第8項所述之裝置，其中該第三間距係為不大於0.45毫米。
  10. 如申請專利範圍第9項所述之裝置，其中該複數個第一通孔結構以及該複數個第二通孔結構為專用於電力、接地、以及封裝至電路板輸入/輸出通訊。
  11. 如申請專利範圍第1項所述之裝置，其中該封裝基板係實質上比該晶粒厚。
  12. 如申請專利範圍第11項所述之裝置，其中對於穿透該封裝基板之訊號傳遞之每一該複數個第一通孔結構而言，該封裝基板具有一最短訊號路徑延遲。
  13. 一種方法，包含：取得具有複數個第一通孔結構的一封裝基板，該複數個第一通孔結構係從該封裝基板之一下表面延伸至該封裝基板之一上表面；取得具有複數個第二通孔結構的一晶粒，該複數個第二通孔結構係延伸至該晶粒之一下表面；將該晶粒之該下表面定位面向該封裝基板之該上表面，以提供一積體電路封裝；以及將該晶粒以及該封裝基板彼此耦接； 其中該封裝基板不包含一重新分配層。
  14. 如申請專利範圍第13項所述之方法，其中該複數個第一通孔結構以及該複數個第二通孔結構之間係一對一對應，且該封裝基板之該複數個第一通孔結構係分别耦接該晶粒之該複數個第二通孔結構。
  15. 如申請專利範圍第13項所述之方法，其中該複數個第一通孔結構係直接耦接該複數個第二通孔結構。
  16. 如申請專利範圍第15項所述之方法，其中透過對應的複數個互連元件，該複數個第一通孔結構係分别直接耦接該複數個第二通孔結構。
  17. 如申請專利範圍第13項所述之方法，其中取得之該封裝基板之步驟包含：取得用於該封裝基板的一材料片；針對該封裝基板之該複數個第一通孔結構，在該材料片上形成複數個開口；在該材料片之該複數個開口中沉積導電材料，以提供該複數個第一通孔結構之導體；以及切割該材料片以提供含有該封裝基板之複數個封裝基板。
  18. 如申請專利範圍第17項所述之方法，更包含：沿著該封裝基板之該下表面，形成附著至該複數個第一通孔結構之複數端的線路，以提供一焊接通孔陣列；以及在該焊接通孔陣列上，沿著該封裝基板之該下表面沉積一成型化合物。
  19. 如申請專利範圍第17項所述之方法，其中該封裝基板係由一無機材料形成。
  20. 如申請專利範圍第17項所述之方法，其中形成該封裝基板之一材料，係由矽、玻璃、聚合物以及其複合材料所組成的群組中所選出。
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