TW201526185A - Semiconductor device - Google Patents

Abstract

The present invention provides a semiconductor device developed toward miniaturization and high density for connecting internal leads. The semiconductor device of embodiments of this invention comprises: a plurality of leads including internal leads and external leads; semiconductor chips arranged on a plurality of leads; spacers disposed between the semiconductor chips and a plurality of leads, a gap being formed between the back of the semiconductor chips and a plurality of leads; conducting wires formed at the gaps for electrically connecting the internal leads below the rear side of the semiconductor chips; and a first insulation layers disposed between the semiconductor chips and the leads.

Description

Semiconductor device

[Related application]

This application claims priority from Japanese Patent Application No. 2013-269434 (Application Date: December 26, 2013) as a basic application. This application contains the entire contents of the basic application by reference to the basic application.

The present invention relates to a semiconductor device.

As the speed of semiconductor devices increases, it is susceptible to fluctuations in potential of the power supply (Vcc) or ground (Vss). In particular, the I/O (Input/Output) signal of the data is affected by the potential fluctuation of the power supply, the ground, or both, and the variation in the rising/falling portion of the I/O signal becomes large. Therefore, in order to stabilize (enhance) the potential of the power supply or the ground or to lower the inductance between the power supply and the ground, an operation of electrically connecting the lead wires of the power supply or the ground for the ground by the metal wires is performed. Further, in order to improve the versatility of the semiconductor device, an operation of changing the order of arrangement of the inner leads such as the control signal or the I/O signal and the arrangement order of the outer leads is performed. In this case, in the package body, the leads are connected to each other by a metal wire for relaying, thereby changing the order of arrangement of the electrode pads and the order of arrangement of the outer leads, and the metal wires for relaying are located between the leads The way of the lead is set.

Moreover, in recent years, the size and density of semiconductor devices have been increasing. For example, there is a semiconductor device in which a semiconductor wafer is laminated in a package or a semiconductor device in which a semiconductor wafer is enlarged. However, in such a semiconductor device, semiconductor wafers occupy According to the area becoming larger (widening), it is difficult to ensure a space for the metal wires to be placed in the package. Moreover, if it is desired to secure a space for the metal wires in the package body, the package body becomes large.

As described above, a semiconductor device having a miniaturization and high density development has been sought which can connect the inner leads.

The present invention provides a miniaturized, high-density semiconductor device that can connect internal leads.

The semiconductor device of the embodiment includes: a plurality of leads including an inner lead and an outer lead; a semiconductor wafer disposed on the plurality of leads; and a spacer interposed between the semiconductor wafer and the plurality of leads on the back of the semiconductor wafer A gap is formed between the plurality of leads; the wires are disposed in the gap, and the inner leads are electrically connected under the back surface of the semiconductor wafer; and the first insulating layer is disposed between the semiconductor wafer and the wires.

100‧‧‧Semiconductor device

110‧‧‧ lead substrate

111‧‧‧ lead

111A‧‧‧ inner lead

111B‧‧‧External lead

111C‧‧‧ recess

121~124‧‧‧Semiconductor wafer

121P~124P‧‧‧electrode pad

121R~124R‧‧‧Back

130‧‧‧ spacers

131‧‧‧Adhesive layer

132‧‧‧Insulation (2nd insulation)

134‧‧‧ conductor layer

140‧‧‧Wire

150‧‧‧ sealing resin

D1‧‧‧ Height

D2, D3‧‧‧ distance

E‧‧‧Electrical conductor

F1‧‧‧Insulation (1st insulation layer)

F2, F3, F4‧‧‧ insulation

S‧‧‧ gap

S1, S2, S3‧‧‧ upper surface

S101~S107‧‧‧Steps

W‧‧‧Metal wire

Fig. 1 is a plan view showing a semiconductor device according to a first embodiment.

Fig. 2 is an enlarged cross-sectional view showing the semiconductor device of the first embodiment.

Fig. 3 is a partial plan view showing a semiconductor device of the embodiment.

Figure 4 is a cross-sectional view taken along line X-X.

Fig. 5 is a flow chart showing a method of manufacturing a semiconductor device according to an embodiment.

(First embodiment)

1 is a plan view of a semiconductor device 100 of an embodiment. Fig. 2 is a partially enlarged cross-sectional view showing the semiconductor device 100 of the embodiment. In the present embodiment, the semiconductor device 100 is a TSOP (Thin Small Outline Package) type semiconductor device.

As shown in FIGS. 1 and 2, the semiconductor device 100 includes a lead substrate 110, semiconductor wafers 121 to 124, a spacer 130, a wire 140, a sealing resin 150, and insulating layers F1 to F4. Further, in FIG. 1, the semiconductor wafers 121 to 124, the spacer 130, and the wires 140 sealed by the sealing resin 150 are described by solid lines instead of chain lines.

The lead substrate 110 has a plurality of leads 111. For each of the leads 111, a metal material having excellent conductivity, for example, copper (Cu), iron (Fe), or nickel (Ni) is used. Each of the leads 111 has an inner lead 111A sealed in the sealing resin 150, and an outer lead 111B exposed from the sealing resin 150. The inner lead 111A mainly functions as a connection portion with the electrode pads of the semiconductor wafers 121 to 124. The outer lead 111B functions as an external connection terminal. Further, the plurality of leads 111 are fixed by an insulating fixing tape (for example, Polyimide) so that the position is not shifted.

Each of the leads 111 includes a plurality of leads including a power supply (Vcc) lead, a ground (Vss) lead, a control signal lead, and an input/output (I/O) lead. Here, the control signal lead includes a wafer enable (CE), a write enable (WE), a lead enable (RE), an instruction lock enable (CLE), an address latch enable (ALE), Leads for write protection (WP), ready/busy (R/B), data strobe signal (DQS), etc.

In addition, the order of arrangement of the respective leads differs depending on the specifications of the package board on which the semiconductor device 100 is mounted.

The semiconductor wafers 121 to 124 are, for example, memory elements such as NAND (NOT-AND) type flash memories and controller elements thereof. A plurality of electrode pads 121P to 124P are formed on one side of the semiconductor wafers 121 to 124 so as to be arranged along one side thereof. Each of the semiconductor wafers 121 to 124 is laminated on the lead substrate 110 in a stepped manner so as to be exposed along the electrode pads 121P to 124P formed on one side.

Insulating layers F1 to F4 are disposed on the back surfaces 121R to 124R of the semiconductor wafers 121 to 124. The insulating layers F1 to F4 also serve as an adhesive layer, and the insulating layers F1 to F4 are, for example, die attach films (adhesive films). As a specific material of the insulating layers F1 to F4, an example For example, a thermosetting or photocurable material containing a polyimine resin, an epoxy resin, an acrylic resin or the like as a main component is used. Each of the semiconductor wafers 122 to 124 is connected to each of the semiconductor wafers 121 to 123 via the insulating layers F1 to F3.

The insulating layer F1 (first insulating layer) is disposed on the back surface 121R of the semiconductor wafer 121 and covers the entire back surface 121R of the semiconductor wafer 121. That is, the insulating layer F1 is located between the back surface 121R of the semiconductor wafer 121 and the wire 140, so that the semiconductor wafer 121 is insulated from the spacer 130 and the wire 140. Thereby, it is possible to prevent the semiconductor wafer 121 from coming into contact with the wires 140 during operation to cause an electrical short circuit.

Furthermore, in Fig. 2, four semiconductor wafers are laminated. However, the number of laminated semiconductor wafers is not limited to four. The number of semiconductor wafers may be one or more. The electrode pads 121P to 124P of the semiconductor wafers 121 to 124 exposed by the stepped layers are electrically connected to the inner leads 111A of the leads 111 by metal wires W such as Au wires or Cu wires.

The spacer 130 is interposed between the lead substrate 110 and the back surface 121R of the lowermost semiconductor wafer 121. The spacer 130 is formed between the lead substrate 110 and the back surface 121R of the lowermost semiconductor wafer 121 to form a gap S. The height D1 of the gap S is preferably 70 μm or more. Furthermore, if the height D1 of the gap S is too high, the semiconductor device 100 becomes thick. Therefore, the height D1 of the gap S is preferably 100 μm or less.

The spacer 130 includes an adhesive layer 131 and an insulating layer (second insulating layer) 132. As the adhesive layer 131, for example, a thermosetting or photocurable material mainly composed of a polyimide resin, an epoxy resin, an acrylic resin or the like is used. Further, the insulating layer 132 is made of an insulating material such as a polyimide resin.

Furthermore, in FIG. 1, six spacers 130 are present between the back surface 121R of the semiconductor wafer 121 and the lead substrate 110. However, the spacer 130 may be provided as long as it can secure the space of the wire 140 described below. Therefore, the position at which the spacer 130 is disposed is not limited to the position shown in FIG. For example, the spacer 130 may be disposed on the back surface 121R of the semiconductor wafer 121. angle.

The wire 140 is, for example, a metal wire using gold (Au), copper (Cu), aluminum (Al) or the like which is excellent in electrical conductivity. The wire 140 electrically connects the inner leads 111A. In the present embodiment, the wire 140 is attached to the back surface 121R of the lowermost semiconductor wafer 121, and between the inner lead 111A of the power supply (Vcc) lead, the inner lead 111A of the ground (Vss) lead, and the control signal lead. At least one or more inner leads 111A between the leads 111A are electrically connected to each other.

The sealing resin 150 seals the lead substrate 110, the semiconductor wafers 121 to 124, the spacer 130, the wires 140, and the insulating layers F1 to F4. Further, the lead wires 111B outside the lead wires 111 are sealed with the sealing resin 150 in a state where they are exposed.

Next, the connection between the leads 111A of the wires 140 of the semiconductor device 100 will be described in more detail. 3 is a partial plan view of the semiconductor device 100. Figure 4 is a cross-sectional view taken along line X-X of Figure 3. 3 and 4 show an example in which the wires 140 are electrically connected between the inner leads 111A of the power supply (Vcc) leads and the inner leads 111A of the ground (Vss) leads. In addition, in FIG. 3, illustration of the semiconductor wafer 121-124, the sealing resin 150, and the insulating layers F1 - F4 is abbreviate|omitted. Further, the metal wire W is indicated by a chain line until halfway. In FIG. 4, the illustration of the spacer 130 and the sealing resin 150 is omitted.

As shown in FIG. 3, the wire 140 is electrically connected between the inner lead 111A of the power supply (Vcc) lead and the inner lead 111A of the ground (Vss) lead in a state of crossing the other inner lead 111A. Furthermore, in the example shown in FIG. 3, the wire 140 spans the lead for input/output (I/O). In the vicinity of the input/output (I/O) leads, it is susceptible to the potential of the power supply (Vcc) or ground (Vss). Therefore, as shown in FIG. 3, it is preferable to electrically connect the power supply (Vcc) lead disposed around the lead wire for input/output (I/O) and the inner lead 111A of the ground (Vss) lead. However, the wire 140 can also span other leads, such as control signal leads.

Further, as shown in FIG. 3, the input/output (I/O) leads are sandwiched between the power supply (Vcc) lead electrically connected by the wire 140 and the inner lead 111A of the ground (Vss) lead. The lead wire 111A is formed with a concave portion 111C. Further, as shown in FIG. 3, in the semiconductor device 100, a concave portion 111C is formed in a region where the wire 140 is crossed.

Therefore, as shown in FIG. 4, the distance D2 between the upper surface S1, S2 of the inner lead 111A and the back surface 121R of the semiconductor wafer 121 connected to the power supply (Vcc) lead of the wire 140 and the ground (Vss) lead is shorter than The upper surface S3 of the inner lead 111A and the back surface 121R of the semiconductor wafer 121 of the input/output (I/O) lead wire for the input/output (I/O) of the power supply (Vcc) lead and the inner lead (111) of the grounding (Vss) lead are connected. Distance D3. Furthermore, the distance D2 is the same distance as the distance D1.

That is, by forming the concave portion 111C, the position of the upper surface of the inner lead 111A sandwiched by the inner lead 111A connected by the wire 140 is lower than the upper surface of the inner lead 111A connected by the wire 140. Therefore, it is possible to reduce the contact of the wire 140 with the inner lead 111A other than the inner lead 111A as the connection target. Further, by forming the concave portion 111C, the distance between the upper surface of the inner lead 111A and the rear surface 121R of the semiconductor wafer 121 becomes longer. Therefore, the parasitic capacitance of the semiconductor wafer 121 and the inner lead 111A in which the concave portion 111C is formed can be reduced.

Furthermore, the recess 111C of the inner lead 111A can be formed by dry etching or wet etching. Further, it is also possible to apply pressure to the inner lead 111A and to flatten it in the up and down direction. By flattening, the thickness of the inner lead 111A is reduced to form the concave portion 111C (imprint processing). Further, the inner lead 111A may be bent downward by the press working to form the concave portion 111C. The imprint process or the press process can suppress the reduction in the cross-sectional area of the inner lead 111A. Therefore, the increase in the resistance of the inner lead 111A in which the concave portion 111C is formed can be suppressed.

Further, in the examples shown in FIGS. 3 and 4, in order to stabilize (enhance) the potential of the power supply (Vcc) and the ground (Vss) or to reduce the inductance between the power supply and the ground, the power supply is used by the wire 140. The inner leads 111A of the (Vcc) leads and the inner leads 111A of the ground (Vss) leads are electrically connected. However, in order to change the order of arrangement of the inner leads 111A and the order of the outer leads 111B, it is also possible to electrically connect the control signal leads and/or the inner leads 111A of the input/output (I/O) leads by the wires 140. Sexual connection.

(Manufacture of Semiconductor Device 100)

FIG. 5 is a flow chart showing a method of manufacturing the semiconductor device 100. Hereinafter, a method of manufacturing the semiconductor device 100 will be described with reference to FIGS. 1 to 5 .

The spacer 130 is mounted at a specific position of the lead substrate 110 (step S101). The mounting of the spacer 130 may be performed in the middle of the manufacturing process of the lead substrate 110 before the press working or the imprinting process and the cutting process of the leading end of the lead.

Next, the inner leads 111A of the desired leads 111 in the leads 111 of the lead substrate 110 are electrically connected by the wires 140 (step S102). For the connection of the wires 140, an existing wire bonding device is used.

Next, the insulating layers F1 to F4 are disposed on the back surfaces 121R to 124R of the semiconductor wafers 121 to 124 (step S103). For the insulating layers F1 to F4, an adhesive film such as a die attach film is used.

Next, the semiconductor wafers 121 to 124 and the insulating layers F1 to F4 are stacked in a stepwise manner on the spacer 130 (step S104).

Next, the electrode pads 121P to 124P of the stacked semiconductor wafers 121 to 124 and the inner leads 111A of the lead substrate 110 are electrically connected by a metal wire W (step S105). Further, for the connection of the metal wires W, an existing wire bonding device is used.

Next, the lead substrate 110, the semiconductor wafers 121 to 124, the spacer 130, the wires 140, the metal wires W, and the like are sealed by the sealing resin 150 (step S106).

Next, bending processing, cutting processing, and the like of the lead wire 111B exposed from the self-sealing resin 150 are performed (step S107). Further, after the spacer 130 is attached to the back surface of the semiconductor wafer 121, the semiconductor wafer 121 may be mounted on the lead substrate 110.

As described above, the semiconductor device 100 includes the spacer 130 that forms the gap S between the back surface 121R of the semiconductor wafer 121 and the plurality of leads 111. Further, in the gap S, the inner leads 111A are electrically connected to each other by the wires 140.

Therefore, there is no setting for the outside of the area where the semiconductor wafers 121 to 124 are packaged. In the case of the space of the wires 140, the inner leads 111A may be electrically connected by the wires 140.

Further, the position of the upper surface of the inner lead 111A sandwiched by the inner lead 111A connected by the lead wire 140 is lower than the upper surface of the inner lead 111A connected by the lead wire 140. Therefore, it is possible to reduce the contact of the wire 140 with the inner lead 111A other than the inner lead 111A as the connection target. Further, by forming the concave portion 111C, the distance between the upper surface of the inner lead 111A and the rear surface 121R of the semiconductor wafer 121 is increased, and the insulating layer F1 is provided between the back surface 121R of the semiconductor wafer 121 and the inner lead 111A. Therefore, the parasitic capacitance of the semiconductor wafer 121 and the inner lead 111A in which the concave portion 111C is formed can be reduced.

Further, when the concave portion 111C of the inner lead 111A is formed by imprinting or pressing, the reduction in the cross-sectional area of the inner lead 111A can be suppressed. Therefore, the increase in the resistance of the inner lead 111A in which the concave portion 111C is formed can be suppressed.

The embodiments of the present invention have been described, but the embodiments are presented as examples and are not intended to limit the scope of the invention. The present invention can be implemented in various other forms, and various omissions, substitutions and changes can be made without departing from the scope of the invention. The embodiments and variations thereof are included in the scope of the invention and the scope of the invention as set forth in the appended claims.

100‧‧‧Semiconductor device

110‧‧‧ lead substrate

111A‧‧‧ inner lead

111B‧‧‧External lead

121~124‧‧‧Semiconductor wafer

121P‧‧‧electrode pad

130‧‧‧ spacers

140‧‧‧Wire

150‧‧‧ sealing resin

W‧‧‧Metal wire

Claims (6)

A semiconductor device comprising: a plurality of leads including an inner lead and an outer lead; a semiconductor wafer disposed on the plurality of leads; a spacer interposed between a portion of the back surface of the semiconductor wafer and the plurality of leads Forming a gap between the back surface of the semiconductor wafer and the plurality of leads; the wire is disposed in the gap, and adjacent to the I/O signal among the plurality of leads under the back surface of the semiconductor wafer At least one or more inner leads between the leads of the power supply lead of the lead, the inner lead of the ground lead, and the inner lead of the control signal lead are electrically connected across the other inner leads; and the first insulation a layer disposed between the back surface of the semiconductor wafer and the conductive line; and a distance between an upper surface of the inner lead connected to the conductive line and a back surface of the semiconductor wafer is shorter than an inner lead connected to the conductive line The distance between the upper surface of the lead and the back side of the semiconductor wafer. A semiconductor device comprising: a plurality of leads including an inner lead and an outer lead; a semiconductor wafer disposed on the plurality of leads; a spacer interposed between the semiconductor wafer and the plurality of leads, a gap is formed between the back surface of the semiconductor wafer and the plurality of leads; the wires are disposed in the gap, and the inner leads are electrically connected under the back surface of the semiconductor wafer; and the first insulating layer is disposed on the semiconductor Between the wafer and the above conductor. The semiconductor device according to claim 2, wherein the wire is at least one of a lead between a power supply lead in the plurality of leads, an inner lead of the ground lead, and an inner lead of the control signal lead. Electrical connection between leads. The semiconductor device of claim 2 or 3, wherein said wire is electrically connected between said inner leads across other inner leads. The semiconductor device of claim 2 or 3, wherein a distance between an upper surface of the inner lead to which the lead is connected and a rear surface of the semiconductor wafer is shorter than an upper surface of the inner lead sandwiched by the inner lead to which the lead is connected The distance from the back side of the semiconductor wafer. The semiconductor device of claim 2 or 3, wherein the spacer comprises a second insulating layer and is disposed on a portion of the back surface of the semiconductor wafer.