JP2015126102A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device capable of connecting inner leads while miniaturization and density increase of semiconductor devices is advanced.SOLUTION: A semiconductor device comprises: a plurality of leads including an inner lead 111A and an outer lead 111B; a semiconductor chip 121 provided on the plurality of leads; a spacer 130 which exists between the semiconductor chip 121 and the plurality of leads and forms a space between a back surface of the semiconductor chip 121 and the plurality of leads 111; a wire 140 provided in the space and electrically connecting the inner leads 111A under the back surface of the semiconductor chip 121; and a first insulation layer provided between the semiconductor chip 121 and the wire 140.

Description

  The present invention relates to a semiconductor device.

  Along with the increase in the speed of semiconductor devices, it is easily affected by fluctuations in the potential of the power supply (Vcc) and ground (Vss). In particular, the I / O signal of data is affected by potential fluctuations of the power supply, the ground, or both, and variation at the rising / falling portions of the I / O signal is large. Therefore, for the purpose of stabilizing (strengthening) the potential of the power supply or ground or reducing the inductance between the power supply and the ground, the power supply leads or the ground (grounding) leads may be electrically connected by metal wires. It has been broken. In order to improve the versatility of the semiconductor device, the arrangement order of inner leads and the arrangement order of outer leads such as control signals and I / O signals are changed. In this case, the arrangement order of the electrode pads and the arrangement order of the outer leads are changed by connecting the leads with a relay metal wire provided so as to straddle the leads between them in the package.

  In recent years, semiconductor devices have been reduced in size and density. For example, there are a semiconductor device in which semiconductor chips are stacked in a package and a semiconductor device in which a semiconductor chip is enlarged. However, in such a semiconductor device, since the area occupied by the semiconductor chip is large (wide), it is difficult to secure a space for providing the metal wire in the package. Moreover, if it is going to secure the space which provides a metal wire in a package, a package will become large.

  As described above, there is a demand for a semiconductor device that can connect inner leads in a semiconductor device that is becoming smaller and higher in density.

US Patent Application Publication No. 2011/210432

  The problem to be solved by the present invention is to provide a semiconductor device capable of connecting inner leads in a semiconductor device that is becoming smaller and higher in density.

  In order to solve the above-described problems, a semiconductor device according to an embodiment includes a plurality of leads having inner leads and outer leads, a semiconductor chip provided on the plurality of leads, and the semiconductor chip and the plurality of leads. A spacer that forms a gap between the back surface of the semiconductor chip and the plurality of leads; a wire that is provided in the gap and electrically connects the inner leads under the back surface of the semiconductor chip; and the semiconductor chip and the wire And a first insulating layer provided therebetween.

1 is a plan view showing a semiconductor device according to a first embodiment. FIG. 3 is an enlarged cross-sectional view showing the semiconductor device according to the first embodiment. 1 is a partial plan view of a semiconductor device according to an embodiment. Sectional drawing in line segment XX. 5 is a flowchart showing a method for manufacturing a semiconductor device according to the embodiment.

(First embodiment)
FIG. 1 is a plan view of a semiconductor device 100 according to the embodiment. FIG. 2 is a partially enlarged cross-sectional view of the semiconductor device 100 according to the embodiment. In this embodiment, the semiconductor device 100 is a TSOP (Thin Small Outline Package) type semiconductor device.

  As shown in FIGS. 1 and 2, the semiconductor device 100 includes a lead substrate 110, semiconductor chips 121 to 124, a spacer 130, a wire 140, a sealing resin 150, and insulating layers F <b> 1 to F <b> 4. In FIG. 1, the semiconductor chips 121 to 124, the spacers 130, and the wires 140 that are sealed with the sealing resin 150 are indicated by solid lines instead of chain lines.

  The lead substrate 110 has a plurality of leads 111. For each lead 111, a metal material having excellent conductivity, for example, copper (Cu), iron (Fe), or nickel (Ni) is used. Each lead 111 includes an inner lead 111 </ b> A sealed in the sealing resin 150 and an outer lead 111 </ b> B exposed from the sealing resin 150. The inner lead 111 </ b> A mainly functions as a connection portion with the electrode pads of the semiconductor chips 121 to 124. The outer lead 111B functions as an external connection terminal. The plurality of leads 111 are fixed by an insulating fixing tape (for example, polyimide) so that the positions are not displaced.

  Each lead 111 includes a plurality of leads including a power supply (Vcc) lead, a ground (Vss) lead, a control signal lead, and an input / output (I / O) lead. The control signal read includes chip enable (CE), write enable (WE), read enable (RE), command latch enable (CLE), address latch enable (ALE), write protect (WP), ready / Reads such as busy (R / B) and data strobe signal (DQS) are included.

  Note that the arrangement order of the leads differs depending on the specifications of the mounting board on which the semiconductor device 100 is mounted.

  The semiconductor chips 121 to 124 are, for example, a storage element such as a NAND flash memory and its controller element. On one side of the semiconductor chips 121 to 124, a plurality of electrode pads 121P to 124P are formed so as to be aligned along the one side. Each of the semiconductor chips 121 to 124 is stacked on the lead substrate 110 in a stepped manner so that the electrode pads 121P to 124P formed along one side are exposed.

  Insulating layers F1 to F4 are disposed on the rear surfaces 121R to 124R of the semiconductor chips 121 to 124, respectively. The insulating layers F1 to F4 also serve as adhesive layers, and the insulating layers F1 to F4 are, for example, die attach films (adhesive films). As a specific material of the insulating layers F1 to F4, for example, a thermosetting or photocurable material mainly composed of polyimide resin, epoxy resin, acrylic resin, or the like is used. The semiconductor chips 122 to 124 are bonded on the semiconductor chips 121 to 123 by insulating layers F1 to F3.

  The insulating layer F1 (first insulating layer) is disposed on the back surface 121R of the semiconductor chip 121 and covers the entire back surface 121R of the semiconductor chip 121. That is, since the insulating layer F <b> 1 is located between the back surface 121 </ b> R of the semiconductor chip 121 and the wire 140, the insulating layer F <b> 1 is insulated from the semiconductor chip 121, the spacer 130, and the wire 140. Thereby, it is possible to prevent the semiconductor chip 121 and the wire 140 from being touched and electrically short-circuited during operation.

  In FIG. 2, four semiconductor chips are stacked. However, the number of stacked semiconductor chips is not limited to four. The number of semiconductor chips may be one or more. The electrode pads 121P to 124P of the semiconductor chips 121 to 124 exposed by stacking in a staircase shape are electrically connected to the inner leads 111A of the leads 111 by metal wires W such as Au wires and Cu wires.

  The spacer 130 is interposed between the lead substrate 110 and the back surface 121 </ b> R of the lowermost semiconductor chip 121. The spacer 130 forms a gap S between the lead substrate 110 and the back surface 121 </ b> R of the lowermost semiconductor chip 121. The height D1 of the gap S is preferably 70 μm or more. If the height D1 of the gap S is too high, the semiconductor device 100 becomes thick. For this reason, the height D1 of the gap S is preferably 100 μm or less.

  The spacer 130 includes an adhesive layer 131 and an insulating layer (second insulating layer) 132. For the adhesive layer 131, for example, a thermosetting or photo-curing material whose main component is polyimide resin, epoxy resin, acrylic resin, or the like is used. The insulating layer 132 is made of an insulating material such as polyimide resin.

  In FIG. 1, six spacers 130 exist between the back surface 121 </ b> R of the semiconductor chip 121 and the lead substrate 110. However, the spacer 130 only needs to secure a space for providing a wire 140 described later. For this reason, the position where the spacer 130 is provided is not limited to the position shown in FIG. For example, the spacers 130 may be arranged at the four corners of the back surface 121R of the semiconductor chip 121.

  The wire 140 is, for example, a metal wire using gold (Au), copper (Cu), aluminum (Al), or an alloy thereof having excellent conductivity. The wire 140 electrically connects the inner leads 111A. In this embodiment, the wires 140 are provided between the inner leads 111A of the power supply (Vcc) leads, between the inner leads 111A of the ground (Vss) leads, and between the inner leads 111A of the ground (Vss) leads, under the back surface 121R of the lowermost semiconductor chip 121. At least one inner lead 111A is electrically connected between at least one inner lead 111A.

  The sealing resin 150 seals the lead substrate 110, the semiconductor chips 121 to 124, the spacer 130, the wire 140, and the insulating layers F1 to F4. The outer leads 111B of each lead 111 are sealed with a sealing resin 150 in an exposed state.

  Next, the connection between the inner leads 111A by the wires 140 of the semiconductor device 100 will be described in more detail. FIG. 3 is a partial plan view of the semiconductor device 100. 4 is a cross-sectional view taken along line XX in FIG. 3 and 4 show an example in which the inner leads 111A of the power supply (Vcc) leads and the inner leads 111A of the ground (Vss) leads are electrically connected by the wires 140. FIG. 3, illustration of the semiconductor chips 121 to 124, the sealing resin 150, and the insulating layers F1 to F4 is omitted. Further, the metal wire W is shown halfway with a chain line. In FIG. 4, illustration of the spacer 130 and the sealing resin 150 is omitted.

  As shown in FIG. 3, the wires 140 are electrically connected between the inner leads 111A of the power supply (Vcc) leads and between the inner leads 111A of the ground (Vss) leads in a state of straddling the other inner leads 111A. doing. In the example shown in FIG. 3, the wire 140 straddles the input / output (I / O) lead. In the vicinity of the input / output (I / O) lead, it is easily affected by the potential of the power supply (Vcc) or the ground (Vss). For this reason, as shown in FIG. 3, the inner leads 111A of the power supply (Vcc) lead and the ground (Vss) lead arranged around the input / output (I / O) lead are electrically connected. It is preferable to do. However, the wire 140 may straddle another lead, for example, a control signal lead.

  Further, as shown in FIG. 3, an input / output (I / O) lead sandwiched between inner leads 111A of a power supply (Vcc) lead and a ground (Vss) lead electrically connected by a wire 140 is used. A recess 111C is formed in the inner lead 111A. As shown in FIG. 3, in the semiconductor device 100, a recess 111 </ b> C is formed in a region where the wire 140 straddles.

  Therefore, as shown in FIG. 4, the distance D2 between the upper surfaces S1 and S2 of the inner leads 111A of the power supply (Vcc) lead and the ground (Vss) lead to which the wire 140 is connected and the rear surface 121R of the semiconductor chip 121. The upper surface S3 of the inner lead 111A of the input / output (I / O) lead sandwiched between the inner lead 111A of the power supply (Vcc) lead and the ground (Vss) lead to which the wire 140 is connected and the semiconductor chip It is shorter than the distance D3 with the back surface 121R of 121. The distance D2 is the same distance as the distance D1.

  That is, by forming the recess 111C, the position of the upper surface of the inner lead 111A sandwiched between the inner leads 111A connected by the wire 140 is made lower than the upper surface of the inner lead 111A connected by the wire 140. For this reason, the possibility that the wire 140 may come into contact with the inner lead 111A other than the inner lead 111A to be connected can be reduced. Further, by forming the recess 111C, the distance between the upper surface of the inner lead 111A and the rear surface 121R of the semiconductor chip 121 is increased. For this reason, it is possible to reduce the parasitic capacitance between the semiconductor chip 121 and the inner lead 111A in which the recess 111C is formed.

  The recess 111C of the inner lead 111A can be formed by dry etching or wet etching. Alternatively, pressure may be applied to the inner lead 111A to crush it in the vertical direction. By crushing, the thickness of the inner lead 111A can be reduced and the recess 111C can be formed (coining process). Alternatively, the recess 111C may be formed by bending the inner lead 111A downward by pressing. The coining process and the depress process can suppress a decrease in the cross-sectional area of the inner lead 111A. For this reason, it can suppress that the electrical resistance of 111 A of inner leads in which the recessed part 111C was formed increases.

  In the example shown in FIG. 3 and FIG. 4, in order to stabilize (strengthen) the potential of the power supply (Vcc) and ground (Vss) or reduce the inductance between the power supply and the ground, the inner power supply (Vcc) lead Wires 140 are electrically connected between the leads 111A and the inner leads 111A of the ground (Vss) lead. However, for the purpose of changing the arrangement order of the inner leads 111A and the arrangement order of the outer leads 111B, the inner leads 111A of the control signal leads and / or the input / output (I / O) leads are electrically connected by the wires 140. You may make it do.

(Manufacture of semiconductor device 100)
FIG. 5 is a flowchart showing a method for manufacturing the semiconductor device 100. Hereinafter, a method for manufacturing the semiconductor device 100 will be described with reference to FIGS.

  A spacer 130 is attached to a predetermined position of the lead substrate 110 (step S101). The spacer 130 may be attached during the manufacturing process of the lead substrate 110, before pressing, coining, or cutting the lead tip.

  Next, among the leads 111 of the lead substrate 110, the inner leads 111A of the desired leads 111 are electrically connected by the wires 140 (step S102). An existing wire bonding apparatus is used to connect the wires 140.

  Next, insulating layers F1 to F4 are disposed on the rear surfaces 121R to 124R of the semiconductor chips 121 to 124 (step S103). An adhesive film such as a die attach film is used for the insulating layers F1 to F4.

  Next, the semiconductor chips 121 to 124 and the insulating layers F1 to F4 are stacked stepwise on the spacer 130 (step S104).

  Next, the electrode pads 121P to 124P of the stacked semiconductor chips 121 to 124 and the inner leads 111A of the lead substrate 110 are electrically connected by the metal wires W (step S105). For the connection of the metal wire W, an existing wire bonding apparatus is used.

  Next, the lead substrate 110, the semiconductor chips 121 to 124, the spacer 130, the wire 140, the metal wire W, and the like are sealed with the sealing resin 150 (step S106).

  Next, the outer lead 111B exposed from the sealing resin 150 is bent or cut (step S107). Note that the semiconductor chip 121 may be attached onto the lead substrate 110 after the spacer 130 is attached to the back surface of the semiconductor chip 121.

  As described above, the semiconductor device 100 includes the spacer 130 that forms the gap S between the back surface 121 </ b> R of the semiconductor chip 121 and the plurality of leads 111. In the gap S, the inner leads 111 </ b> A are electrically connected by wires 140.

  Therefore, even when there is no space for the wire 140 outside the region where the semiconductor chips 121 to 124 are mounted, the inner leads 111A can be electrically connected by the wire 140.

  Further, the position of the upper surface of the inner lead 111A sandwiched between the inner leads 111A connected by the wire 140 is set lower than the upper surface of the inner lead 111A connected by the wire 140. For this reason, the possibility that the wire 140 may come into contact with the inner lead 111A other than the inner lead 111A to be connected can be reduced. Further, by forming the recess 111C, the distance between the upper surface of the inner lead 111A and the back surface 121R of the semiconductor chip 121 is increased, and the insulating layer F1 is provided between the back surface 121R of the semiconductor chip 121 and the inner lead 111A. For this reason, it is possible to reduce the parasitic capacitance between the semiconductor chip 121 and the inner lead 111A in which the recess 111C is formed.

  Furthermore, when the recess 111C of the inner lead 111A is formed by coining or pressing, it is possible to suppress a decrease in the cross-sectional area of the inner lead 111A. For this reason, it can suppress that the electrical resistance of 111 A of inner leads in which the recessed part 111C was formed increases.

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

100 Semiconductor device 110 Lead substrate 111 Lead 111A Inner lead 111B Outer lead 121-124 Semiconductor chip 121P-124P Electrode pad 121R-124R Back surface 130 Spacer 131 Adhesive layer 132 Insulating layer (second insulating layer)
134 Conductor layer 140 Wire 150 Sealing resin E Conductor F1 Insulating layer (first insulating layer)
F2 Insulating layer F3 Insulating layer F4 Insulating layer S Gaps S1, S2, S3 Upper surface W Metal wire

Claims (6)

A plurality of leads having inner leads and outer leads;
A semiconductor chip provided on the plurality of leads;
A spacer interposed between a part of the back surface of the semiconductor chip and the plurality of leads, and forming a gap between the back surface of the semiconductor chip and the plurality of leads;
Among the plurality of leads provided between the inner leads of the power supply leads adjacent to the I / O signal leads, between the inner leads of the ground leads, and the control signal leads, provided in the gap and below the back surface of the semiconductor chip. A wire for electrically connecting at least one inner lead between the inner leads across the other inner leads;
A first insulating layer provided between the back surface of the semiconductor chip and the wire;
With
The distance between the upper surface of the inner lead to which the wire is connected and the back surface of the semiconductor chip is determined by the distance between the upper surface of the inner lead sandwiched between the inner leads to which the wire is connected and the back surface of the semiconductor chip. Even a short semiconductor device. A plurality of leads having inner leads and outer leads;
A semiconductor chip provided on the plurality of leads;
A spacer interposed between the semiconductor chip and the plurality of leads, and forming a gap between the back surface of the semiconductor chip and the plurality of leads;
A wire provided in the gap and electrically connecting the inner leads under the back surface of the semiconductor chip;
A first insulating layer provided between the semiconductor chip and the wire;
A semiconductor device comprising: The wire is
3. The at least one inner lead among the plurality of leads is electrically connected between the inner leads of the power supply lead, between the inner leads of the ground lead, and between the inner leads of the control signal lead. Semiconductor device.   The semiconductor device according to claim 2, wherein the wire straddles another inner lead and electrically connects the inner leads.   The distance between the upper surface of the inner lead to which the wire is connected and the back surface of the semiconductor chip is based on the distance between the upper surface of the inner lead sandwiched between the inner leads to which the wire is connected and the back surface of the semiconductor chip. The semiconductor device according to claim 2, wherein the semiconductor device is shorter. The spacer includes a second insulating layer,
The semiconductor device according to claim 2, wherein the semiconductor device is provided on a part of a back surface of the semiconductor chip.

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