TWI529918B - Semiconductor memory card - Google Patents

Description

Semiconductor memory card [Related application]

The present application has priority in the application based on Japanese Patent Application No. 2012-43680 (filing date: February 29, 2012). This application contains the entire contents of the basic application by reference to the basic application.

Embodiments of the present invention relate to a semiconductor memory card.

In a memory card (semiconductor memory card) in which a nonvolatile semiconductor memory chip such as a NAND (Not-AND) type flash memory is incorporated, in order to increase the capacity, speed, and manufacturing cost, The application of the structure is as follows: a semiconductor memory device of a SiP (System in Package) structure in which a memory chip or a controller chip is sealed in one package is housed in a cartridge. The semiconductor memory device of the SiP structure includes, for example, a wiring board provided with external connection terminals, a memory chip and a controller wafer mounted on a surface opposite to a terminal forming surface of the wiring substrate, and a sealing resin layer. The wafer mounting surface of the wiring substrate is formed by sealing the memory chip and the controller wafer.

In the semiconductor memory device of the SiP structure, a wiring board is generally used in which a wiring layer formed by patterning a copper foil is provided on both surfaces of an insulating resin substrate, and wiring layers on both sides are electrically connected by via holes. A gold plating layer serving as an external connection terminal is formed in one of the copper wiring layers provided on the terminal forming surface of the wiring board. In the semiconductor memory device of the prior SiP structure, there are the following disadvantages: from performing electrical connection with an external device The length of the wiring from the connection terminal to the controller chip tends to be long. Therefore, the signal transmission speed is lowered, and the substrate area is liable to increase due to a decrease in the wiring density. In this case, in order to increase the signal transmission speed in the memory card or to miniaturize the wiring board constituting the SiP structure, it is preferable to shorten the wiring length from the external connection terminal to the controller chip.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor memory card capable of shortening the wiring length from an external connection terminal to a controller chip.

A semiconductor memory card according to an embodiment includes a semiconductor memory device including a wiring board including a first surface including a plurality of external connection terminals and a first wiring layer, and a second wafer including a wafer mounting region and a second wiring layer And a via hole electrically connecting the first wiring layer and the second wiring layer; the memory chip is disposed on the wafer mounting region of the wiring substrate, and includes at least one first electrode pad arranged along the outer shape; The wafer is laminated on the memory chip and includes at least one second electrode pad arranged along the outer shape; the first metal wire electrically connecting the first electrode pad of the memory chip and the second wiring of the wiring substrate a second metal wire electrically connected to the second electrode pad of the controller wafer and the second wiring layer of the wiring substrate; and a sealing resin layer for connecting the memory chip and the controller wafer together with the first and second metals The wire is sealed together on the second surface of the wiring board. The plurality of external connection terminals are arranged along the first outer shape so as to be located in the vicinity of the first outer edge of the wiring board. The second electrode wafer of the controller chip The electrode pad electrically connected to the external connection terminal is located in the region on the second surface corresponding to the formation region of the plurality of external connection terminals on the first surface of the wiring substrate or in the vicinity of the region. The plurality of external connection terminals are arranged in parallel to each other and are arranged outside the controller wafer on the first outer side of the wiring substrate.

Hereinafter, a semiconductor memory card according to an embodiment will be described with reference to the drawings. Fig. 1 is a plan view showing a semiconductor memory card of an embodiment. The semiconductor memory card 1 shown in FIG. 1 is used, for example, as an SD (Secure Digital) ^TM memory card (SD ^TM card), including a pair of upper and lower cartridges 2, and a semiconductor housed in the cartridge 2. Memory device 3. The semiconductor memory device 3 is composed of a semiconductor device of a SiP structure. Hereinafter, the specific structure of the semiconductor memory device 3 will be described in detail.

(First embodiment)

A semiconductor memory device of the SiP structure according to the first embodiment will be described with reference to Figs. 3 to 6 . 3 is a perspective view showing the upper surface of the semiconductor memory device of the first embodiment, FIG. 4 is a cross-sectional view taken along line AA of FIG. 3, and FIG. 5 is a perspective view of the upper surface (molding surface) of the semiconductor memory device. FIG. 6 is a perspective view showing a terminal forming surface of a wiring substrate in the semiconductor memory device shown in FIG. Perspective of the face. The semiconductor memory device 11 (3) shown in the drawings includes a wiring substrate 12 which also serves as a substrate for forming an external connection terminal and a substrate for mounting a semiconductor wafer. The wiring board 12 has the first surface 12a which is a forming surface of the external connection terminal, and becomes The second surface 12b of the mounting surface of the memory chip or controller chip.

As shown in FIG. 4, the wiring board 12 includes a resin base material 13 including an epoxy resin or a BT (Bismaleimide Triazine) resin (a bismaleimide triazine resin), and the like, and a first wiring layer 14 provided on the first wiring layer 14 The first surface 12a side of the resin substrate 13; the second wiring layer 15 is provided on the second surface 12b side of the resin substrate 13, and the through hole 16 electrically connects the first wiring layer 14 and the second wiring layer 15. The first and second wiring layers 14 and 15 are formed by, for example, patterning copper foil laminated on both surfaces of the resin substrate 13 in accordance with a wiring pattern. The surfaces of the first and second wiring layers 14 and 15 are covered with the solder resists 17 and 18 for insulation protection.

The first wiring layer 14 has an external connection terminal 19. In the portion of the first interconnect layer 14 that becomes the external connection terminal 19, an opening pattern is formed on the solder resist 17, and the gold plating layer 20 is formed on the first wiring layer 14 via the opening pattern. The external connection terminal 19 is composed of a first wiring layer 14 and a gold plating layer 20 as a surface layer. The second wiring layer 15 has connection pads 21 (21A, 21B). In the portion of the second wiring layer 15 that serves as the connection pad 21, an opening pattern is formed on the solder resist 18, and the gold plating layer 22 is formed on the second wiring layer 15 via the opening patterns. The connection pad 21 is composed of a second wiring layer 15 and a gold plating layer 22 as a surface layer. The gold plating layers 20, 22 are formed, for example, by electroplating.

As shown in FIGS. 4 and 5, the first surface 12a of the wiring board 12 has a first wiring layer 14 and a plurality of external connection terminals 19. The plurality of external connection terminals 19 are arranged along the first outer side S1 so as to be located in the vicinity of the first outer side S1 of the wiring board 12. As shown in FIGS. 3, 4, and 6, the second surface 12b of the wiring board 12 has the second wiring layer 15 and the wafer mounting region 23. The second wiring layer 15 has connection pads 21A and 21B. The connection pad 21A is disposed and disposed in the wafer mounting area The connection portion of the electrode pad of the memory chip of the domain 23, the connection pad 21B serves as a connection portion with the electrode pad of the controller wafer laminated on the memory chip.

The memory chip 24 is disposed in the wafer mounting region 23 of the wiring substrate 12. As the memory chip 24, for example, a semiconductor memory wafer such as a NAND type flash memory is used. FIG. 3 and FIG. 4 show a state in which eight memory chips 24 are stacked and placed in the wafer mounting region 23. The number of mounting of the memory chip 24 with respect to the wiring substrate 12 is not limited to this. The number of the memory chips 24 to be mounted may be one, or two or four, or nine or more. The number of the memory chips 24 to be mounted on the wiring substrate 12 may be one or plural.

In FIGS. 3 and 4, a plurality of memory chips 24 have the same shape in a rectangular shape, and each has an electrode pad 25. The electrode pads 25 are located on the second outer side S2 side opposite to the first outer side S1 of the wiring board 12, and are arranged side by side along the second outer side S2 side of the memory chip 24. The plurality of memory chips 24 constitute a memory chip group 26, and are further divided into two wafer groups 26A and 26B. The first wafer group 26A is composed of four memory chips 24 arranged in a state of being laminated on the wafer mounting region 23 of the wiring substrate 12. The second wafer group 26B is composed of four memory chips 24 arranged in a state of being laminated on the first wafer group 26A.

The four memory chips 24 constituting the first wafer group 26A are stacked in a stepped manner such that the electrode pads 25 are placed on the second outer side S2 side of the wiring substrate 12, and the electrode pads 25 are exposed. The electrode pads 25 of the four memory chips 24 are sequentially connected via the metal wires 27. In the first wafer group 26A, the electrode pads 25 of the memory chip 24 located at the lowermost layer are connected via the metal wires 27 The connection pads 21A of the wiring substrate 12 are electrically connected. In the first wafer group 26A, the second wafer group 26B is disposed by interposing the spacer layer 28 made of a resin.

The four memory chips 24 constituting the second wafer group 26B are stacked in a stepped manner such that the electrode pads 25 are placed on the second outer side S2 side of the wiring substrate 12, and the electrode pads 25 are exposed. The electrode pads 25 of the four memory chips 24 are sequentially connected via the metal wires 27. In the second wafer group 26B, the electrode pads 25 of the memory chip 24 located at the lowermost layer are electrically connected to the connection pads 21A of the wiring substrate 12 via the metal wires 27. In the first wafer group 26A, the metal wires 27 connected to the electrode pads 25 of the uppermost memory chip 24 are embedded in the insulating resin spacer layer 28, thereby preventing the second wafer group 26B from being located most. The lower layer of memory wafer 24 is in contact.

A controller wafer 29 is laminated on the memory chip group 26. The controller chip 29 selects a wafer from which data is written or read from a plurality of memory chips 24 to perform writing to the selected memory chip 24 and to the selected memory chip 24. Reading of the memorized data, etc. The controller wafer 29 has an L-shaped pad structure and includes an electrode pad 30A arranged along the long side 29a and an electrode pad 30B arranged along the short side 29b. The controller wafer 29 is disposed such that the long side 29a is located on the first outer side S1 side of the wiring board 12, that is, on the side of the first outer side S1 on which the plurality of external connection terminals 19 are arranged, and is parallel to the first outer side S1.

The electrode pads 30 (30A, 30B) of the controller wafer 29 are electrically connected to the connection pads 21B of the wiring substrate 12 via the metal wires 31. The electrode pad 30A arranged along the long side 29a of the controller wafer 29 is connected to the pad disposed in the pad region 32A provided on the first outer side S1 side of the wiring substrate 12 via the metal wire 31. 21B is electrically connected. The electrode pads 30B arranged along the short sides 29b of the controller wafer 29 are electrically connected to the connection pads 21B disposed in the pad regions 32B provided on the third outer side S3 side of the wiring substrate 12 via the metal wires 31.

A sealing resin layer 33 containing, for example, an epoxy resin is molded on the second surface 12b of the wiring substrate 12 on which the memory chip 24 or the controller wafer 29 is mounted. The memory chip 24 or the controller wafer 29 is integrally sealed with the metal wires 27, 31 and the like by the sealing resin layer 33. The semiconductor memory device 11 (3) of the SiP structure is constructed by these. As described above, the semiconductor memory card 1 is constructed by accommodating the semiconductor memory device 11 of the SiP structure into the cartridge 2. As shown in FIG. 1, the cartridge 2 has an opening 4 for exposing the external connection terminal 19.

However, the above-described memory card SD ^TM card requires memory capacity is further increased. Therefore, the practical use of a memory card having a memory capacity of 64 GB or more has been continuously promoted. In addition to the increase in memory capacity, such a memory card is also expected to increase the transmission speed of the digital signal. Therefore, the practical use of a memory card in which the theoretical maximum transmission speed of a digital signal is 50 MB/sec or more is continuously advanced. That is, the memory card with the maximum specification value of the data read/write speed between the memory card and the external device (host) is 50 MB/sec or more. Here, the memory card having the above-described signal transmission speed is referred to as a high-speed operation type (high-speed transmission type) memory card.

In the high-speed operation type memory card as described above, in order to improve the characteristics of the interface (IF, Interface) signal between the external device and the memory card, the transmission speed of the digital signal as described above is satisfied, and it is desired to shorten the self-operation. External connection terminal for electrical connection of external machine to electrode pad of controller chip Wiring length (signal wiring length for IF). Therefore, in the semiconductor memory card 1 of the embodiment, the electrode pads (IF electrode pads) 301 electrically connected to the external connection terminals 19 in the electrode pads 30 of the controller wafer 29 are disposed on the wiring substrate 12 In the region (terminal corresponding region) X1 on the second surface 12b corresponding to the formation region of the external connection terminal 19 on the first surface 12a. Further, the IF electrode pad 301 may be disposed in the vicinity of the terminal corresponding region X1.

When the IF electrode pad 301 is disposed in the terminal corresponding region X1, the controller wafer 29 is laminated on the memory chip 24 (memory wafer group 26) as follows: the long side 29a and the first of the wiring substrate 12 The outer side S1 is parallel, the first outer side S1 of the wiring board 12 is parallel to the arrangement direction of the external connection terminals 19, and the long side 29a is located on the first outer side S1 side of the wiring board 12. The IF electrode pad 301 is disposed along the long side 29a of the controller wafer 29. The IF electrode pad 301 is electrically connected to the connection pad 21B provided in the pad region 32A on the first outer side S1 side of the wiring substrate 12 via the metal wire 31.

Further, in order to arrange the IF electrode pad 301 in the vicinity of the center of the terminal corresponding region X1 on the second surface 12b of the wiring board 12, the IF electrode pad 301 is disposed on the long side 29a of the controller wafer 29 close to the terminal. Corresponds to the position of the center of the area X1. That is, the position of the IF electrode pad 301 on the long side 29a of the controller wafer 29 is set such that the IF electrode pad 301 is closer to the other electrode pads 30 of the controller wafer 29 other than the IF electrode pad 301. In the center of the terminal corresponding area X1.

By applying the arrangement position of the IF electrode pad 301 as described above, the signal wiring length from the external connection terminal 19 to the IF electrode pad 301 of the controller wafer 29 can be shortened. That is, configured with the short side 29b along the controller chip 29. In the case of the IF electrode pad 301 or the controller wafer 29 on the second surface 12b of the wiring substrate 12 (for example, the side of the memory chip 24 of FIG. 3 and the side of the wiring board 12 outside the side S3) In contrast, since the distance from the IF electrode pad 301 to the plurality of external connection terminals 19 is shortened, the length of the IF signal wiring can be shortened.

In the semiconductor memory device 11 shown in FIG. 3, since the controller wafer 29 having the L-type pad structure is applied, the electrode pads 30B arranged along the short side 29b of the controller wafer 29 are bonded to the connection pads 21B ( Wire Bonding), and the position of the IF electrode pad 301 is limited. As shown in FIG. 7, when the controller wafer 29 having the long-side one-side pad structure is applied, the IF electrode pad 301 can be disposed closer to the center of the terminal corresponding region X1. In either case, the length of the signal wiring from the external connection terminal 19 to the IF electrode pad 301 can be shortened by arranging the IF electrode pad 301 along the long side 29a of the controller wafer 29.

In order to shorten the wiring length from the external connection terminal 19 provided on the first surface 12a of the wiring board 12 to the connection pad 21B (the connection pad 21B disposed in the pad region 32A) provided on the second surface 12b, the wiring is shortened. One of the through holes 16 of the first wiring layer 14 and the second wiring layer 15 is connected between the plurality of external connection terminals 19. In FIGS. 5 and 6, the through hole 161 is a through hole for signal wiring, and is provided between a plurality of external connection terminals 19. By applying such a signal wiring via hole 161, the signal wiring length from the external connection terminal 19 to the IF electrode pad 301 of the controller wafer 29 can be further shortened. In addition, in FIG. 5, illustration of one part of wiring (wiring from the connection pad 21A to the connection pad 21B, etc.) is abbreviate|omitted.

As described above, the IF electrode pad 301 from the external connection terminal 19 to the controller wafer 29 is shortened based on the arrangement position of the IF electrode pad 301 or the electrical connection structure between the first wiring layer 14 and the second wiring layer 15. The signal wiring length is thereby increased the electrical characteristics of the IF signal between the external device and the semiconductor memory card 1. Therefore, the transmission speed of the digital signal can be improved. Furthermore, the capacitive load of the memory card also affects the characteristics of the IF signal. Therefore, in the semiconductor memory card 1, a region X2 in which the second wiring layer 15 is not provided is set in one of the terminal corresponding regions X1 on the second surface 12b of the wiring substrate 12. Thereby, the capacitive load when the semiconductor memory card 1 is connected to an external device can be reduced.

Here, when the region X2 in which the second interconnect layer 15 is not provided is set in a portion of the terminal corresponding region X1, if the region X2 is a blank region (a region where no component is provided), the following is true: the memory is mounted. The warpage of the wiring substrate 12 when the wafer 24 or the controller wafer 29 is formed or when the sealing resin layer 33 is formed becomes remarkable. On the other hand, in the region X2, the metal layer (Cu layer) 34 constituting the second wiring layer 15 is partially provided in a state of being electrically independent from the second wiring layer 15. Fig. 6 shows a state in which the Cu layer 34 having a dot pattern (dot pattern) is formed in the region X2. Such a dummy pattern of the Cu layer 34 can suppress not only the warpage of the wiring substrate 12 but also the capacitive load of the semiconductor memory card 1.

Furthermore, the plated leads also have an effect on the capacitive loading of the memory card. That is, the second wiring layer 15 has a plating lead 35 for forming a surface layer (gold plating layer) 20 of the external connection terminal 19 by plating. If the plating lead 35 becomes long, the capacitive load when the semiconductor memory card 1 is connected to an external device may become Big. In this case, the plating lead 35 provided on the second surface 12b of the wiring board 12 is provided in the wiring board 12 via a through hole (a through hole for plating) 162 provided between the plurality of external connection terminals 19 The external connection terminal 19 of the first surface 12a is electrically connected to the first outer side S1 of the wiring substrate 12. Thereby, the length of the plating lead 35 of the gold plating layer 20 which forms the external connection terminal 19 by electroplating can be drastically shortened.

As described above, the signal wiring length from the external connection terminal 19 to the IF electrode pad 301 of the controller wafer 29 is shortened, and the semiconductor memory card 1 is lowered by forming a dummy pattern of the Cu layer 34 or shortening the plating lead 35. The capacitive load, thereby improving the electrical characteristics of the IF signal between the external device and the semiconductor memory card 1. Therefore, the transmission speed of the digital signal between the external device and the semiconductor memory card 1 can be improved. That is, the semiconductor memory card 1 capable of realizing the theoretical maximum transmission speed of a digital signal of 50 MB/sec or more can be provided. As described above, the semiconductor memory card 1 of the first embodiment is suitable for a high-speed operation type memory card.

In the semiconductor memory card 1 of the first embodiment, one of the first wiring layer 14 electrically connected to the wiring board 12 and the through hole 16 of the second wiring layer 15 is provided between the plurality of external connection terminals 19. Therefore, the second wiring layer 15 can be formed in the terminal formation region X1 of the second surface 12b of the wiring substrate 12. As described above, by increasing the formation density of the second wiring layer 15, the size of the wiring substrate 12 can be reduced. As shown in FIG. 4, the memory wafer 24 can be stacked in a plurality of stages to increase the memory capacity, and the wiring board 12 can be miniaturized.

Moreover, by increasing the formation density of the second wiring layer 15, the connection pads 21A connected to the memory chip 24 can be collectively disposed on the second outside of the wiring substrate 12. On the side of the side S2, the connection pad 21B connected to the controller wafer 29 is disposed on the first outer side S1 side of the wiring substrate 12. Thereby, the size of the wiring board 12 can also be reduced. Moreover, the wiring shape or the arrangement structure of the connection pads as described above can be realized without increasing the number of wiring layers of the wiring board 12. By these, the manufacturing cost of the semiconductor memory device 11 of the SiP structure can be reduced, and the manufacturing cost of the semiconductor memory card 1 can be reduced.

Further, as shown in FIG. 4, the first wafer group 26A and the second wafer group 26B are laminated so that the pad arrays of the memory chips 24 constituting the first wafer group 26A are aligned in the same direction, whereby the memory wafer 24 can be connected. The metal wires 27 of the wiring substrate 12 are wired in the same direction. Thereby, the mounting area of the memory chip 24 with respect to the wiring board 12 or the number of wiring layers of the wiring board 12 can be reduced. Therefore, when the area of the wiring board 12 is made the same, a larger memory chip 24 can be mounted, so that the memory capacity can be increased by the semiconductor memory device 11 having the same outer shape. Further, when the area of the memory chip 24 is the same, the wiring board 12 and the semiconductor memory device 11 can be miniaturized.

(Second embodiment)

Next, a semiconductor memory device of the SiP structure according to the second embodiment will be described with reference to Figs. 8 to 11 . 8 is a perspective view showing the upper surface of the semiconductor memory device of the second embodiment, FIG. 9 is a cross-sectional view taken along line AA of FIG. 8, and FIG. 10 is a perspective view of the upper surface (molding surface) of the semiconductor memory device. The perspective view of the terminal forming surface of the wiring substrate in the semiconductor memory device shown, and FIG. 11 is a perspective view of the wafer mounting of the wiring substrate in the semiconductor memory device shown in FIG. 8 from the upper surface (molding surface) of the semiconductor memory device. Perspective of the face. Furthermore, the same part as the first embodiment is labeled The same reference numerals are omitted and a part of the description is omitted.

The semiconductor memory device 41 (3) shown in FIGS. 8 to 11 includes the wiring board 12 in the same manner as in the first embodiment. Similarly to the first embodiment, the wiring board 12 includes a first wiring layer 14 provided on the first surface 12a side of the resin substrate 13, and a second wiring layer 15 provided on the second resin substrate 13. The surface of the surface 12b and the through hole 16 are electrically connected to the first wiring layer 14 and the second wiring layer 15. The first wiring layer 14 has an external connection terminal 19. The second wiring layer 15 has connection pads 21 (21A, 21B).

As shown in FIGS. 9 and 10, the first surface 12a of the wiring board 12 includes a first wiring layer 14 and a plurality of external connection terminals 19. The plurality of external connection terminals 19 are arranged along the first outer side S1 so as to be located in the vicinity of the first outer side S1 of the wiring board 12. As shown in FIGS. 8 , 9 , and 11 , the second surface 12 b of the wiring board 12 includes the second wiring layer 15 and the wafer mounting region 23 . The memory chip 24 and the controller wafer 29 are arranged in parallel in the wafer mounting region 23 of the wiring substrate 12. The number of the memory chips 24 to be mounted is not limited to one, and may be two, four, eight or more.

The memory chip 24 has an electrode pad 25. The electrode pads 25 are located on the second outer side S2 side of the wiring substrate 12, and are arranged side by side along the second outer side S2 side of the memory wafer 24. The electrode pads 25 of the memory wafer 24 are electrically connected to the connection pads 21A of the wiring substrate 12 via the metal wires 27. The controller wafer 29 has a long-side one-sided pad structure and has electrode pads 30 arranged along the long sides. The electrode pads 30 of the controller wafer 29 are electrically connected to the connection pads 21B of the wiring substrate 12 via the metal wires 31.

Electrically connecting one of the first wiring layer 14 and the through hole 16 of the second wiring layer 15 It is disposed between a plurality of external connection terminals 19. The through hole 161 provided in the through hole 16 between the external connection terminals 19 is a signal wiring through hole, and is formed as a part of the signal wiring electrically connecting the external connection terminal 19 and the electrode pad 30 of the controller wafer 29. In other words, at least a part of the plurality of external connection terminals 19 is electrically connected to the electrode pads 30 of the controller wafer 29 via the signal wiring vias 161. Thereby, the signal wiring length from the external connection terminal 19 to the electrode pad 30 of the controller wafer 29 can be shortened.

Further, the through hole 162 provided in the through hole 16 between the external connection terminals 19 is a through hole for plating leads, and is formed as a part of a wiring electrically connecting the external connection terminal 19 and the plating lead 35. In other words, at least a part of the plurality of external connection terminals 19 is electrically connected to the plating leads 35 via the plating lead vias 162, and the plating leads 35 are led out to the first outer side S1 of the wiring substrate 12. By this, the length of the plating lead 35 of the gold plating layer 20 which forms the external connection terminal 19 by electroplating can be drastically shortened.

A sealing resin layer 33 containing, for example, an epoxy resin is molded on the second surface 12b of the wiring substrate 12 on which the memory chip 24 or the controller wafer 29 is mounted. The memory chip 24 or the controller wafer 29 is integrally sealed with the metal wires 27, 31 and the like by the sealing resin layer 33. The semiconductor memory device 41 (3) of the SiP structure is constructed by these. As described above, the semiconductor memory card 1 is constructed by accommodating the semiconductor memory device 11 of the SiP structure into the cartridge 2. As shown in FIG. 1, the cartridge 2 has an opening 4 for exposing the external connection terminal 19.

As described above, by providing a portion (161, 162) of the through hole 16 between the plurality of external connection terminals 19, the external connection terminal 19 can be shortened The signal wiring length of the controller wafer 29 or the length of the plating lead 35. Moreover, a region (terminal corresponding region) on the second surface 12b corresponding to the formation region of the external connection terminal 19 on the first surface 12a of the wiring substrate 12 can be used as the wiring region. By this, the wiring density per unit area of the wiring board 12 can be increased, so that the size of the wiring board 12 can be reduced. Thereby, the manufacturing cost of the semiconductor memory device 11 of the SiP structure can be reduced, and the manufacturing cost of the semiconductor memory card 1 can be reduced.

Further, by shortening the signal wiring length from the external connection terminal 19 to the controller chip 29, the signal transmission speed with the external device is increased. By shortening the length of the plating lead 35, the capacitive load when the semiconductor memory card 1 is connected to an external device is reduced. With these, it is possible to cope with the high-speed operation of the semiconductor memory card 1. Furthermore, since the through holes 161 and 162 provided between the plurality of external connection terminals 19 are housed in the cartridge 2 when the semiconductor memory device 41 is housed in the cartridge 2, they are hidden under the barrier wall 5 between the openings 4, so It is seen from the appearance of the memory card 1, and it does not adversely affect the operation of the memory card 1.

Furthermore, the embodiments of the present invention have been described, but the embodiments are presented as examples and are not intended to limit the scope of the invention. The embodiments can be implemented in various other forms, and various omissions, substitutions and changes can be made without departing from the scope of the invention. The invention or its modifications are intended to be included within the scope and spirit of the invention, and are included in the scope of the invention as described in the appended claims.

1‧‧‧Semiconductor memory card

2‧‧‧Carton

3‧‧‧Semiconductor memory device

11‧‧‧Semiconductor memory device

12‧‧‧Wiring substrate

12a‧‧‧1st

12b‧‧‧2nd

14‧‧‧1st wiring layer

15‧‧‧2nd wiring layer

16‧‧‧through hole

19‧‧‧External connection terminal

20‧‧‧ gold plating

21‧‧‧Connecting mat

21A‧‧‧Connecting mat

21B‧‧‧Connecting mat

22‧‧‧ gold plating

23‧‧‧ wafer loading area

24‧‧‧ memory chip

25‧‧‧electrode pads

27‧‧‧Metal wire

29‧‧‧ Controller chip

29a‧‧‧Longside

29b‧‧‧Short side

30‧‧‧electrode pads

30A‧‧‧electrode pad

30B‧‧‧electrode pad 31 metal wire

32A‧‧‧Mat area

32B‧‧‧Mat area

33‧‧‧ sealing resin layer

34‧‧‧metal layer (Cu layer)

35‧‧‧ plating lead

41‧‧‧Semiconductor memory device

161‧‧‧through hole

162‧‧‧through hole

301‧‧‧ IF electrode pads

S1‧‧‧1st side

S2‧‧‧2nd side

S3‧‧‧3rd side

X1‧‧‧ terminal corresponding area

Fig. 1 is a plan view showing a semiconductor memory card of an embodiment.

Fig. 2 is a plan view showing a semiconductor memory device housed in the semiconductor memory card shown in Fig. 1.

Fig. 3 is a perspective view showing the upper surface of the semiconductor memory device of the first embodiment;

Figure 4 is a cross-sectional view taken along line A-A of Figure 3.

Fig. 5 is a perspective view showing a terminal forming surface of a wiring substrate in the semiconductor memory device shown in Fig. 3 as seen from the upper surface of the semiconductor memory device.

Fig. 6 is a perspective view showing the wafer mounting surface of the wiring substrate in the semiconductor memory device shown in Fig. 3 as seen from the upper surface of the semiconductor memory device.

Fig. 7 is a top perspective view showing a modification of the semiconductor memory device of the first embodiment.

Fig. 8 is a perspective view showing the upper surface of the semiconductor memory device of the second embodiment.

Figure 9 is a cross-sectional view taken along line A-A of Figure 8.

Fig. 10 is a perspective view showing a terminal forming surface of a wiring substrate in the semiconductor memory device shown in Fig. 8 as seen from the upper surface of the semiconductor memory device.

Fig. 11 is a perspective view showing the wafer mounting surface of the wiring substrate in the semiconductor memory device shown in Fig. 8 as seen from the upper surface of the semiconductor memory device.

3‧‧‧Semiconductor memory device

11‧‧‧Semiconductor memory device

12‧‧‧Wiring substrate

12b‧‧‧2nd

21A‧‧‧Connecting mat

21B‧‧‧Connecting mat

23‧‧‧ wafer loading area

24‧‧‧ memory chip

25‧‧‧electrode pads

27‧‧‧Metal wire

29‧‧‧ Controller chip

29a‧‧‧Longside

29b‧‧‧Short side

30A‧‧‧electrode pad

30B‧‧‧electrode pad

31‧‧‧Metal wire

32A‧‧‧Mat area

32B‧‧‧Mat area

301‧‧‧ IF electrode pads

S1‧‧‧1st side

S2‧‧‧2nd side

S3‧‧‧3rd side

Y1‧‧‧ terminal corresponding area

Claims (4)

A semiconductor memory card comprising: a semiconductor memory device comprising: a wiring substrate including a first surface including a plurality of external connection terminals and a first wiring layer; and a wafer mounting region and a second wiring layer a second surface, and a through hole electrically connecting the first wiring layer and the second wiring layer; and the memory wafer is disposed on the wafer mounting region of the wiring substrate, and includes at least one of the outer edges a first electrode pad; a controller wafer laminated on the memory chip and including at least one second electrode pad arranged along the outer shape; and a first metal wire electrically connected to the first electrode of the memory chip An electrode pad and the second wiring layer of the wiring substrate; a second metal wire electrically connecting the second electrode pad of the controller wafer and the second wiring layer of the wiring substrate; and a sealing resin layer Forming the memory chip and the controller wafer together with the first and second metal wires on the second surface of the wiring substrate; and the plurality of The external connection terminals are arranged along the first outer shape so as to be located adjacent to the first outer edge of the wiring substrate, and the second electrode pads of the controller wafer are electrically connected to the external connection terminals. The electrode pad is located in a region on the second surface corresponding to a formation region of the plurality of external connection terminals on the first surface of the wiring substrate or in the vicinity of the region The plurality of external connection terminals are arranged in parallel, and are arranged outside the controller wafer on the first outer side of the wiring substrate; and the terminal corresponding region on the second surface of the wiring substrate is not provided a region of the second interconnect layer is partially provided with a metal layer constituting the second interconnect layer in a region where the second interconnect layer is not provided, and is not electrically connected to the second interconnect layer; At least a part of the hole is disposed between the plurality of external connection terminals, and at least a part of the plurality of external connection terminals is connected to the second of the controller chip via the through hole provided between the plurality of external connection terminals The electrode pads are electrically connected; each of the plurality of external connection terminals includes a plating layer as a surface layer, and the second wiring layer of the wiring substrate includes a plating lead forming the plating layer, and at least a part of the plating lead is disposed through The through holes between the plurality of external connection terminals are electrically connected to the external connection terminals. A semiconductor memory card comprising: a semiconductor memory device comprising: a wiring substrate including a first surface including a plurality of external connection terminals and a first wiring layer; and a wafer mounting region and a second wiring layer a second surface, and a through hole electrically connecting the first wiring layer and the second wiring layer; and the memory wafer is disposed on the wafer mounting region of the wiring substrate, and includes at least one of the outer edges First electrode pad; a controller wafer laminated on the memory chip and including at least one second electrode pad arranged along the outer shape; and a first metal wire electrically connecting the first electrode pad of the memory chip and the wiring a second wiring layer of the substrate; a second metal wire electrically connected to the second electrode pad of the controller wafer and the second wiring layer of the wiring substrate; and a sealing resin layer for the memory chip And the controller chip is formed on the second surface of the wiring board together with the first and second metal wires, and the plurality of external connection terminals are located on the first outer side of the wiring substrate In the vicinity of the first outer shape, the electrode pads electrically connected to the external connection terminals of the second electrode pads of the controller wafer are located on the first surface of the wiring substrate Arranging along the plurality of external connection terminals in a region of the second surface corresponding to the formation region of the plurality of external connection terminals or in the vicinity of the region The controller wafers are arranged in parallel with each other on the first outer side of the wiring board, and the terminal corresponding region on the second surface of the wiring substrate includes an area in which the second wiring layer is not provided. Further, in a region where the second wiring layer is not provided, a metal layer constituting the second wiring layer is partially provided in a state where the second wiring layer is not electrically connected. A semiconductor memory card comprising a semiconductor memory device, the semiconductor memory device comprising: The wiring board includes a first surface including a plurality of external connection terminals and a first wiring layer, a second surface including the wafer mounting region and the second wiring layer, and electrically connected to the first wiring layer and the second wiring layer The memory chip is disposed on the wafer mounting region of the wiring substrate, and includes at least one first electrode pad arranged along the outer shape, and a controller chip disposed on the wafer of the wiring substrate a second electrode pad arranged on the memory chip in the region or on the memory chip; the first metal wire electrically connecting the first electrode pad of the memory chip and the wiring substrate a wiring layer; the second metal wire electrically connecting the second electrode pad of the controller chip and the second wiring layer of the wiring substrate; and a sealing resin layer for connecting the memory chip and the controller The wafer is formed on the second surface of the wiring board together with the first and second metal wires, and at least a part of the through hole is provided in the plurality of external connections At least a part of the plurality of external connection terminals is electrically connected to the second electrode pad of the controller chip via the through hole provided between the plurality of external connection terminals. The semiconductor memory card of claim 3, wherein each of the plurality of external connection terminals includes a plating layer as a surface layer, and the second wiring layer of the wiring substrate includes a plating lead forming the plating layer; At least a part of the plating lead is electrically connected to the external connection terminal via the through hole provided between the plurality of external connection terminals.